Revision 175:af195413fb11, committed 2017-10-11

Comitter:

AnnaBridge

Date:

Wed Oct 11 12:45:49 2017 +0100

Parent:

174:b96e65c34a4d

Child:

176:447f873cad2f

Commit message:

This updates the lib to the mbed lib v 153

Changed in this revision

--- a/drivers/CAN.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/CAN.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,11 @@
 
 CAN::~CAN() {
     // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
     can_irq_free(&_can);
     can_free(&_can);
 }

--- a/drivers/InterruptIn.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/InterruptIn.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -19,17 +19,12 @@
 
 namespace mbed {
 
-static void donothing() {}
-
 InterruptIn::InterruptIn(PinName pin) : gpio(),
                                         gpio_irq(),
-                                        _rise(),
-                                        _fall() {
+                                        _rise(NULL),
+                                        _fall(NULL) {
     // No lock needed in the constructor
 
-    _rise = donothing;
-    _fall = donothing;
-
     gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
     gpio_init_in(&gpio, pin);
 }
@@ -56,7 +51,7 @@
         _rise = func;
         gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
     } else {
-        _rise = donothing;
+        _rise = NULL;
         gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
     }
     core_util_critical_section_exit();
@@ -68,7 +63,7 @@
         _fall = func;
         gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
     } else {
-        _fall = donothing;
+        _fall = NULL;
         gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
     }
     core_util_critical_section_exit();
@@ -77,8 +72,16 @@
 void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
     InterruptIn *handler = (InterruptIn*)id;
     switch (event) {
-        case IRQ_RISE: handler->_rise(); break;
-        case IRQ_FALL: handler->_fall(); break;
+        case IRQ_RISE: 
+            if (handler->_rise) {
+                handler->_rise();
+            }
+            break;
+        case IRQ_FALL: 
+            if (handler->_fall) {
+                handler->_fall(); 
+            }
+            break;
         case IRQ_NONE: break;
     }
 }

--- a/drivers/PwmOut.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/PwmOut.h	Wed Oct 11 12:45:49 2017 +0100
@@ -21,6 +21,7 @@
 #if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
 #include "hal/pwmout_api.h"
 #include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
 
 namespace mbed {
 /** \addtogroup drivers */
@@ -56,12 +57,18 @@
      *
      *  @param pin PwmOut pin to connect to
      */
-    PwmOut(PinName pin) {
+    PwmOut(PinName pin) : _deep_sleep_locked(false) {
         core_util_critical_section_enter();
         pwmout_init(&_pwm, pin);
         core_util_critical_section_exit();
     }
 
+    ~PwmOut() {
+        core_util_critical_section_enter();
+        unlock_deep_sleep();
+        core_util_critical_section_exit();
+    }
+
     /** Set the ouput duty-cycle, specified as a percentage (float)
      *
      *  @param value A floating-point value representing the output duty-cycle,
@@ -71,6 +78,7 @@
      */
     void write(float value) {
         core_util_critical_section_enter();
+        lock_deep_sleep();
         pwmout_write(&_pwm, value);
         core_util_critical_section_exit();
     }
@@ -177,7 +185,24 @@
     }
 
 protected:
+    /** Lock deep sleep only if it is not yet locked */
+    void lock_deep_sleep() {
+        if (_deep_sleep_locked == false) {
+            sleep_manager_lock_deep_sleep();
+            _deep_sleep_locked = true;
+        }
+    }
+
+    /** Unlock deep sleep in case it is locked */
+    void unlock_deep_sleep() {
+        if (_deep_sleep_locked == true) {
+            sleep_manager_unlock_deep_sleep();
+            _deep_sleep_locked = false;
+        }
+    }
+
     pwmout_t _pwm;
+    bool _deep_sleep_locked;
 };
 
 } // namespace mbed

--- a/drivers/SerialBase.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/SerialBase.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -133,6 +133,16 @@
     // Stub
 }
 
+SerialBase::~SerialBase()
+{
+    // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
+}
+
 #if DEVICE_SERIAL_FC
 void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
     lock();

--- a/drivers/SerialBase.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/SerialBase.h	Wed Oct 11 12:45:49 2017 +0100
@@ -241,8 +241,7 @@
 
 protected:
     SerialBase(PinName tx, PinName rx, int baud);
-    virtual ~SerialBase() {
-    }
+    virtual ~SerialBase();
 
     int _base_getc();
     int _base_putc(int c);

--- a/drivers/Ticker.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/Ticker.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -25,10 +25,11 @@
 void Ticker::detach() {
     core_util_critical_section_enter();
     remove();
-    // unlocked only if we were attached (we locked it)
-    if (_function) {
+    // unlocked only if we were attached (we locked it) and this is not low power ticker
+    if(_function && _lock_deepsleep) {
         sleep_manager_unlock_deep_sleep();
     }
+
     _function = 0;
     core_util_critical_section_exit();
 }

--- a/drivers/Ticker.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/Ticker.h	Wed Oct 11 12:45:49 2017 +0100
@@ -21,13 +21,15 @@
 #include "platform/mbed_toolchain.h"
 #include "platform/NonCopyable.h"
 #include "platform/mbed_sleep.h"
+#include "hal/lp_ticker_api.h"
+#include "platform/mbed_critical.h"
 
 namespace mbed {
 /** \addtogroup drivers */
 
 /** A Ticker is used to call a function at a recurring interval
  *
- *  You can use as many seperate Ticker objects as you require.
+ *  You can use as many separate Ticker objects as you require.
  *
  * @note Synchronization level: Interrupt safe
  *
@@ -64,14 +66,18 @@
 class Ticker : public TimerEvent, private NonCopyable<Ticker> {
 
 public:
-    Ticker() : TimerEvent(), _function(0) {
+    Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true) {
     }
 
-    Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0) {
+    // When low power ticker is in use, then do not disable deep-sleep.
+    Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)  {
         data->interface->init();
+#if DEVICE_LOWPOWERTIMER
+        _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
     }
 
-    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+    /** Attach a function to be called by the Ticker, specifying the interval in seconds
      *
      *  @param func pointer to the function to be called
      *  @param t the time between calls in seconds
@@ -80,7 +86,7 @@
         attach_us(func, t * 1000000.0f);
     }
 
-    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+    /** Attach a member function to be called by the Ticker, specifying the interval in seconds
      *
      *  @param obj pointer to the object to call the member function on
      *  @param method pointer to the member function to be called
@@ -97,21 +103,28 @@
         attach(callback(obj, method), t);
     }
 
-    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+    /** Attach a function to be called by the Ticker, specifying the interval in micro-seconds
      *
      *  @param func pointer to the function to be called
      *  @param t the time between calls in micro-seconds
+     *
+     *  @note setting @a t to a value shorter that it takes to process the ticker callback
+     *  will cause the system to hang. Ticker callback will be called constantly with no time
+     *  for threads scheduling.
+     *
      */
     void attach_us(Callback<void()> func, us_timestamp_t t) {
-        // lock only for the initial callback setup
-        if (!_function) {
+        core_util_critical_section_enter();
+        // lock only for the initial callback setup and this is not low power ticker
+        if(!_function && _lock_deepsleep) {
             sleep_manager_lock_deep_sleep();
         }
         _function = func;
         setup(t);
+        core_util_critical_section_exit();
     }
 
-    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+    /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds
      *
      *  @param obj pointer to the object to call the member function on
      *  @param method pointer to the member function to be called
@@ -143,6 +156,7 @@
 protected:
     us_timestamp_t         _delay;  /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
     Callback<void()>    _function;  /**< Callback. */
+    bool          _lock_deepsleep;  /**< Flag which indicates if deep-sleep should be disabled. */
 };
 
 } // namespace mbed

--- a/drivers/Timer.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/Timer.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -17,21 +17,38 @@
 #include "hal/ticker_api.h"
 #include "hal/us_ticker_api.h"
 #include "platform/mbed_critical.h"
+#include "hal/lp_ticker_api.h"
 
 namespace mbed {
 
-Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()), _lock_deepsleep(true) {
     reset();
 }
 
-Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data), _lock_deepsleep(true) {
     reset();
+#if DEVICE_LOWPOWERTIMER
+    _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+}
+
+Timer::~Timer() {
+    core_util_critical_section_enter();
+    if (_running) {
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
+    }
+    _running = 0;
+    core_util_critical_section_exit();
 }
 
 void Timer::start() {
     core_util_critical_section_enter();
     if (!_running) {
-        sleep_manager_lock_deep_sleep();
+        if(_lock_deepsleep) {
+            sleep_manager_lock_deep_sleep();
+        }
         _start = ticker_read_us(_ticker_data);
         _running = 1;
     }
@@ -42,7 +59,9 @@
     core_util_critical_section_enter();
     _time += slicetime();
     if (_running) {
-        sleep_manager_unlock_deep_sleep();
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
     }
     _running = 0;
     core_util_critical_section_exit();

--- a/drivers/Timer.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/Timer.h	Wed Oct 11 12:45:49 2017 +0100
@@ -53,6 +53,7 @@
 public:
     Timer();
     Timer(const ticker_data_t *data);
+    ~Timer();
 
     /** Start the timer
      */
@@ -100,6 +101,7 @@
     us_timestamp_t _start;   // the start time of the latest slice
     us_timestamp_t _time;    // any accumulated time from previous slices
     const ticker_data_t *_ticker_data;
+    bool _lock_deepsleep;    // flag which indicates if deep-sleep should be disabled
 };
 
 } // namespace mbed

--- a/drivers/UARTSerial.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/drivers/UARTSerial.h	Wed Oct 11 12:45:49 2017 +0100
@@ -56,6 +56,12 @@
      */
     virtual short poll(short events) const;
 
+    /* Resolve ambiguities versus our private SerialBase
+     * (for writable, spelling differs, but just in case)
+     */
+    using FileHandle::readable;
+    using FileHandle::writable;
+
     /** Write the contents of a buffer to a file
      *
      *  @param buffer   The buffer to write from

--- a/hal/mbed_ticker_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/hal/mbed_ticker_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -263,6 +263,7 @@
 
 us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
 {
+    initialize(ticker);
     update_present_time(ticker);
     return ticker->queue->present_time;
 }

--- a/mbed.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/mbed.h	Wed Oct 11 12:45:49 2017 +0100
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 152
+#define MBED_LIBRARY_VERSION 153
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
 #define MBED_MINOR_VERSION 6
-#define MBED_PATCH_VERSION 1
+#define MBED_PATCH_VERSION 2
 
 #else
 // mbed 2

--- a/platform/Callback.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/Callback.h	Wed Oct 11 12:45:49 2017 +0100
@@ -77,7 +77,7 @@
      */
     Callback(R (*func)() = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -590,6 +590,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -651,7 +652,7 @@
      */
     Callback(R (*func)(A0) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -1165,6 +1166,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -1226,7 +1228,7 @@
      */
     Callback(R (*func)(A0, A1) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -1741,6 +1743,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -1802,7 +1805,7 @@
      */
     Callback(R (*func)(A0, A1, A2) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -2318,6 +2321,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -2379,7 +2383,7 @@
      */
     Callback(R (*func)(A0, A1, A2, A3) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -2896,6 +2900,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -2957,7 +2962,7 @@
      */
     Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -3475,6 +3480,7 @@
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }

--- a/platform/DeepSleepLock.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/DeepSleepLock.h	Wed Oct 11 12:45:49 2017 +0100
@@ -16,7 +16,9 @@
 #ifndef MBED_DEEPSLEEPLOCK_H
 #define MBED_DEEPSLEEPLOCK_H
 
+#include <limits.h>
 #include "platform/mbed_sleep.h"
+#include "platform/mbed_critical.h"
 
 namespace mbed {
 
@@ -36,29 +38,47 @@
   * @endcode
   */
 class DeepSleepLock {
+private:
+    uint16_t _lock_count;
+
 public:
-    DeepSleepLock()
+    DeepSleepLock(): _lock_count(1)
     {
         sleep_manager_lock_deep_sleep();
     }
 
     ~DeepSleepLock()
     {
-        sleep_manager_unlock_deep_sleep();
+        if (_lock_count) {
+            sleep_manager_unlock_deep_sleep();
+        }
     }
 
     /** Mark the start of a locked deep sleep section
      */
     void lock()
     {
-        sleep_manager_lock_deep_sleep();
+        uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1);
+        if (1 == count) {
+            sleep_manager_lock_deep_sleep();
+        }
+        if (0 == count) {
+            error("DeepSleepLock overflow (> USHRT_MAX)");
+        }
     }
 
     /** Mark the end of a locked deep sleep section
      */
     void unlock()
     {
-        sleep_manager_unlock_deep_sleep();
+        uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1);
+        if (count == 0) {
+            sleep_manager_unlock_deep_sleep();
+        }
+        if (count == USHRT_MAX) {
+            core_util_critical_section_exit();
+            error("DeepSleepLock underflow (< 0)");
+        }
     }
 };
 

--- a/platform/mbed_retarget.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/mbed_retarget.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -13,9 +13,11 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#include <time.h>
 #include "platform/platform.h"
 #include "platform/FilePath.h"
 #include "hal/serial_api.h"
+#include "hal/us_ticker_api.h"
 #include "platform/mbed_toolchain.h"
 #include "platform/mbed_semihost_api.h"
 #include "platform/mbed_interface.h"
@@ -24,6 +26,7 @@
 #include "platform/mbed_error.h"
 #include "platform/mbed_stats.h"
 #include "platform/mbed_critical.h"
+#include "platform/PlatformMutex.h"
 #include <stdlib.h>
 #include <string.h>
 #include <limits.h>
@@ -33,6 +36,8 @@
 #include <errno.h>
 #include "platform/mbed_retarget.h"
 
+static SingletonPtr<PlatformMutex> _mutex;
+
 #if defined(__ARMCC_VERSION)
 #   if __ARMCC_VERSION >= 6010050
 #      include <arm_compat.h>
@@ -446,6 +451,7 @@
 #if defined(__ARMCC_VERSION)
     int whence = SEEK_SET;
 #endif
+
     if (fh < 3) {
         errno = ESPIPE;
         return -1;
@@ -536,13 +542,21 @@
 
 
 #if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
-extern "C" int _fstat(int fd, struct stat *st) {
-    if (fd < 3) {
+extern "C" int _fstat(int fh, struct stat *st) {
+    if (fh < 3) {
         st->st_mode = S_IFCHR;
         return  0;
     }
-    errno = EBADF;
-    return -1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    st->st_mode = fhc->isatty() ? S_IFCHR : S_IFREG;
+    st->st_size = fhc->size();
+    return 0;
 }
 #endif
 
@@ -1008,6 +1022,16 @@
     return buffer;
 }
 
+void *operator new(std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
 void operator delete(void *ptr)
 {
     if (ptr != NULL) {
@@ -1020,3 +1044,22 @@
         free(ptr);
     }
 }
+
+/* @brief   standard c library clock() function.
+ *
+ * This function returns the number of clock ticks elapsed since the start of the program.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @return
+ *  the number of clock ticks elapsed since the start of the program.
+ *
+ * */
+extern "C" clock_t clock()
+{
+    _mutex->lock();
+    clock_t t = ticker_read(get_us_ticker_data());
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    _mutex->unlock();
+    return t;
+}

--- a/platform/mbed_retarget.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/mbed_retarget.h	Wed Oct 11 12:45:49 2017 +0100
@@ -29,23 +29,33 @@
  * need to define the types ourselves for the other compilers that normally
  * target embedded systems */
 #if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;    ///< Signed size type, usually encodes negative errors
-typedef long off_t;     ///< Offset in a data stream
-typedef int mode_t;     ///< Mode for opening files
+typedef signed   int  ssize_t;  ///< Signed size type, usually encodes negative errors
+typedef signed   long off_t;    ///< Offset in a data stream
+typedef unsigned int  mode_t;   ///< Mode for opening files
+typedef unsigned int  dev_t;    ///< Device ID type
+typedef unsigned long ino_t;    ///< File serial number
+typedef unsigned int  nlink_t;  ///< Number of links to a file
+typedef unsigned int  uid_t;    ///< User ID
+typedef unsigned int  gid_t;    ///< Group ID
 
-#define O_RDONLY 0
-#define O_WRONLY 1
-#define O_RDWR   2
-#define O_CREAT  0x0200
-#define O_TRUNC  0x0400
-#define O_APPEND 0x0008
+#define O_RDONLY 0      ///< Open for reading
+#define O_WRONLY 1      ///< Open for writing
+#define O_RDWR   2      ///< Open for reading and writing
+#define O_CREAT  0x0200 ///< Create file if it does not exist
+#define O_TRUNC  0x0400 ///< Truncate file to zero length
+#define O_EXCL   0x0800 ///< Fail if file exists
+#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
 
 #define NAME_MAX 255    ///< Maximum size of a name in a file path
 
+#include <time.h>
+
 #else
+
 #include <sys/fcntl.h>
 #include <sys/types.h>
 #include <sys/syslimits.h>
+
 #endif
 
 
@@ -83,107 +93,349 @@
  * symbol definitions used by the POSIX filesystem API to return errno codes.
  * Note also that ARMCC errno.h defines some symbol values differently from
  * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
- * this and future changes by changing the symbol definition as shown below. */
-#undef ENOENT
-#define ENOENT      2       /* No such file or directory. */
-
-#undef EIO
-#define EIO         5       /* I/O error */
-
-#undef ENXIO
-#define ENXIO       6       /* No such device or address */
-
-#undef ENOEXEC
-#define ENOEXEC     8       /* Exec format error */
-
-#undef EBADF
-#define EBADF       9       /* Bad file number */
-
-#undef EAGAIN
-#define EAGAIN      11      /* Resource unavailable, try again */
-
-#undef EWOULDBLOCK
-#define EWOULDBLOCK EAGAIN  /* Operation would block */
-
-#undef ENOMEM
-#define ENOMEM      12      /* Not enough space */
-
-#undef EACCES
-#define EACCES      13      /* Permission denied */
+ * this and future changes by changing the symbol definition as shown below.
+ */
+#undef  EPERM
+#define EPERM           1       /* Operation not permitted */
+#undef  ENOENT
+#define ENOENT          2       /* No such file or directory */
+#undef  ESRCH
+#define ESRCH           3       /* No such process */
+#undef  EINTR
+#define EINTR           4       /* Interrupted system call */
+#undef  EIO
+#define EIO             5       /* I/O error */
+#undef  ENXIO
+#define ENXIO           6       /* No such device or address */
+#undef  E2BIG
+#define E2BIG           7       /* Argument list too long */
+#undef  ENOEXEC
+#define ENOEXEC         8       /* Exec format error */
+#undef  EBADF
+#define EBADF           9       /* Bad file number */
+#undef  ECHILD
+#define ECHILD          10      /* No child processes */
+#undef  EAGAIN
+#define EAGAIN          11      /* Try again */
+#undef  ENOMEM
+#define ENOMEM          12      /* Out of memory */
+#undef  EACCES
+#define EACCES          13      /* Permission denied */
+#undef  EFAULT
+#define EFAULT          14      /* Bad address */
+#undef  ENOTBLK
+#define ENOTBLK         15      /* Block device required */
+#undef  EBUSY
+#define EBUSY           16      /* Device or resource busy */
+#undef  EEXIST
+#define EEXIST          17      /* File exists */
+#undef  EXDEV
+#define EXDEV           18      /* Cross-device link */
+#undef  ENODEV
+#define ENODEV          19      /* No such device */
+#undef  ENOTDIR
+#define ENOTDIR         20      /* Not a directory */
+#undef  EISDIR
+#define EISDIR          21      /* Is a directory */
+#undef  EINVAL
+#define EINVAL          22      /* Invalid argument */
+#undef  ENFILE
+#define ENFILE          23      /* File table overflow */
+#undef  EMFILE
+#define EMFILE          24      /* Too many open files */
+#undef  ENOTTY
+#define ENOTTY          25      /* Not a typewriter */
+#undef  ETXTBSY
+#define ETXTBSY         26      /* Text file busy */
+#undef  EFBIG
+#define EFBIG           27      /* File too large */
+#undef  ENOSPC
+#define ENOSPC          28      /* No space left on device */
+#undef  ESPIPE
+#define ESPIPE          29      /* Illegal seek */
+#undef  EROFS
+#define EROFS           30      /* Read-only file system */
+#undef  EMLINK
+#define EMLINK          31      /* Too many links */
+#undef  EPIPE
+#define EPIPE           32      /* Broken pipe */
+#undef  EDOM
+#define EDOM            33      /* Math argument out of domain of func */
+#undef  ERANGE
+#define ERANGE          34      /* Math result not representable */
+#undef  EDEADLK
+#define EDEADLK         35      /* Resource deadlock would occur */
+#undef  ENAMETOOLONG
+#define ENAMETOOLONG    36      /* File name too long */
+#undef  ENOLCK
+#define ENOLCK          37      /* No record locks available */
+#undef  ENOSYS
+#define ENOSYS          38      /* Function not implemented */
+#undef  ENOTEMPTY
+#define ENOTEMPTY       39      /* Directory not empty */
+#undef  ELOOP
+#define ELOOP           40      /* Too many symbolic links encountered */
+#undef  EWOULDBLOCK
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#undef  ENOMSG
+#define ENOMSG          42      /* No message of desired type */
+#undef  EIDRM
+#define EIDRM           43      /* Identifier removed */
+#undef  ECHRNG
+#define ECHRNG          44      /* Channel number out of range */
+#undef  EL2NSYNC
+#define EL2NSYNC        45      /* Level 2 not synchronized */
+#undef  EL3HLT
+#define EL3HLT          46      /* Level 3 halted */
+#undef  EL3RST
+#define EL3RST          47      /* Level 3 reset */
+#undef  ELNRNG
+#define ELNRNG          48      /* Link number out of range */
+#undef  EUNATCH
+#define EUNATCH         49      /* Protocol driver not attached */
+#undef  ENOCSI
+#define ENOCSI          50      /* No CSI structure available */
+#undef  EL2HLT
+#define EL2HLT          51      /* Level 2 halted */
+#undef  EBADE
+#define EBADE           52      /* Invalid exchange */
+#undef  EBADR
+#define EBADR           53      /* Invalid request descriptor */
+#undef  EXFULL
+#define EXFULL          54      /* Exchange full */
+#undef  ENOANO
+#define ENOANO          55      /* No anode */
+#undef  EBADRQC
+#define EBADRQC         56      /* Invalid request code */
+#undef  EBADSLT
+#define EBADSLT         57      /* Invalid slot */
+#undef  EDEADLOCK
+#define EDEADLOCK       EDEADLK /* Resource deadlock would occur */
+#undef  EBFONT
+#define EBFONT          59      /* Bad font file format */
+#undef  ENOSTR
+#define ENOSTR          60      /* Device not a stream */
+#undef  ENODATA
+#define ENODATA         61      /* No data available */
+#undef  ETIME
+#define ETIME           62      /* Timer expired */
+#undef  ENOSR
+#define ENOSR           63      /* Out of streams resources */
+#undef  ENONET
+#define ENONET          64      /* Machine is not on the network */
+#undef  ENOPKG
+#define ENOPKG          65      /* Package not installed */
+#undef  EREMOTE
+#define EREMOTE         66      /* Object is remote */
+#undef  ENOLINK
+#define ENOLINK         67      /* Link has been severed */
+#undef  EADV
+#define EADV            68      /* Advertise error */
+#undef  ESRMNT
+#define ESRMNT          69      /* Srmount error */
+#undef  ECOMM
+#define ECOMM           70      /* Communication error on send */
+#undef  EPROTO
+#define EPROTO          71      /* Protocol error */
+#undef  EMULTIHOP
+#define EMULTIHOP       72      /* Multihop attempted */
+#undef  EDOTDOT
+#define EDOTDOT         73      /* RFS specific error */
+#undef  EBADMSG
+#define EBADMSG         74      /* Not a data message */
+#undef  EOVERFLOW
+#define EOVERFLOW       75      /* Value too large for defined data type */
+#undef  ENOTUNIQ
+#define ENOTUNIQ        76      /* Name not unique on network */
+#undef  EBADFD
+#define EBADFD          77      /* File descriptor in bad state */
+#undef  EREMCHG
+#define EREMCHG         78      /* Remote address changed */
+#undef  ELIBACC
+#define ELIBACC         79      /* Can not access a needed shared library */
+#undef  ELIBBAD
+#define ELIBBAD         80      /* Accessing a corrupted shared library */
+#undef  ELIBSCN
+#define ELIBSCN         81      /* .lib section in a.out corrupted */
+#undef  ELIBMAX
+#define ELIBMAX         82      /* Attempting to link in too many shared libraries */
+#undef  ELIBEXEC
+#define ELIBEXEC        83      /* Cannot exec a shared library directly */
+#undef  EILSEQ
+#define EILSEQ          84      /* Illegal byte sequence */
+#undef  ERESTART
+#define ERESTART        85      /* Interrupted system call should be restarted */
+#undef  ESTRPIPE
+#define ESTRPIPE        86      /* Streams pipe error */
+#undef  EUSERS
+#define EUSERS          87      /* Too many users */
+#undef  ENOTSOCK
+#define ENOTSOCK        88      /* Socket operation on non-socket */
+#undef  EDESTADDRREQ
+#define EDESTADDRREQ    89      /* Destination address required */
+#undef  EMSGSIZE
+#define EMSGSIZE        90      /* Message too long */
+#undef  EPROTOTYPE
+#define EPROTOTYPE      91      /* Protocol wrong type for socket */
+#undef  ENOPROTOOPT
+#define ENOPROTOOPT     92      /* Protocol not available */
+#undef  EPROTONOSUPPORT
+#define EPROTONOSUPPORT 93      /* Protocol not supported */
+#undef  ESOCKTNOSUPPORT
+#define ESOCKTNOSUPPORT 94      /* Socket type not supported */
+#undef  EOPNOTSUPP
+#define EOPNOTSUPP      95      /* Operation not supported on transport endpoint */
+#undef  EPFNOSUPPORT
+#define EPFNOSUPPORT    96      /* Protocol family not supported */
+#undef  EAFNOSUPPORT
+#define EAFNOSUPPORT    97      /* Address family not supported by protocol */
+#undef  EADDRINUSE
+#define EADDRINUSE      98      /* Address already in use */
+#undef  EADDRNOTAVAIL
+#define EADDRNOTAVAIL   99      /* Cannot assign requested address */
+#undef  ENETDOWN
+#define ENETDOWN        100     /* Network is down */
+#undef  ENETUNREACH
+#define ENETUNREACH     101     /* Network is unreachable */
+#undef  ENETRESET
+#define ENETRESET       102     /* Network dropped connection because of reset */
+#undef  ECONNABORTED
+#define ECONNABORTED    103     /* Software caused connection abort */
+#undef  ECONNRESET
+#define ECONNRESET      104     /* Connection reset by peer */
+#undef  ENOBUFS
+#define ENOBUFS         105     /* No buffer space available */
+#undef  EISCONN
+#define EISCONN         106     /* Transport endpoint is already connected */
+#undef  ENOTCONN
+#define ENOTCONN        107     /* Transport endpoint is not connected */
+#undef  ESHUTDOWN
+#define ESHUTDOWN       108     /* Cannot send after transport endpoint shutdown */
+#undef  ETOOMANYREFS
+#define ETOOMANYREFS    109     /* Too many references: cannot splice */
+#undef  ETIMEDOUT
+#define ETIMEDOUT       110     /* Connection timed out */
+#undef  ECONNREFUSED
+#define ECONNREFUSED    111     /* Connection refused */
+#undef  EHOSTDOWN
+#define EHOSTDOWN       112     /* Host is down */
+#undef  EHOSTUNREACH
+#define EHOSTUNREACH    113     /* No route to host */
+#undef  EALREADY
+#define EALREADY        114     /* Operation already in progress */
+#undef  EINPROGRESS
+#define EINPROGRESS     115     /* Operation now in progress */
+#undef  ESTALE
+#define ESTALE          116     /* Stale NFS file handle */
+#undef  EUCLEAN
+#define EUCLEAN         117     /* Structure needs cleaning */
+#undef  ENOTNAM
+#define ENOTNAM         118     /* Not a XENIX named type file */
+#undef  ENAVAIL
+#define ENAVAIL         119     /* No XENIX semaphores available */
+#undef  EISNAM
+#define EISNAM          120     /* Is a named type file */
+#undef  EREMOTEIO
+#define EREMOTEIO       121     /* Remote I/O error */
+#undef  EDQUOT
+#define EDQUOT          122     /* Quota exceeded */
+#undef  ENOMEDIUM
+#define ENOMEDIUM       123     /* No medium found */
+#undef  EMEDIUMTYPE
+#define EMEDIUMTYPE     124     /* Wrong medium type */
+#undef  ECANCELED
+#define ECANCELED       125     /* Operation Canceled */
+#undef  ENOKEY
+#define ENOKEY          126     /* Required key not available */
+#undef  EKEYEXPIRED
+#define EKEYEXPIRED     127     /* Key has expired */
+#undef  EKEYREVOKED
+#define EKEYREVOKED     128     /* Key has been revoked */
+#undef  EKEYREJECTED
+#define EKEYREJECTED    129     /* Key was rejected by service */
+#undef  EOWNERDEAD
+#define EOWNERDEAD      130     /* Owner died */
+#undef  ENOTRECOVERABLE
+#define ENOTRECOVERABLE 131     /* State not recoverable */
+#endif
 
-#undef EFAULT
-#define EFAULT      14      /* Bad address */
-
-#undef EEXIST
-#define EEXIST      17      /* File exists */
-
-#undef EXDEV
-#define EXDEV       18      /* Cross-device link */
-
-#undef ENODEV
-#define ENODEV      19
-
-#undef EINVAL
-#define EINVAL      22      /* Invalid argument */
-
-#undef ENFILE
-#define ENFILE      23      /* Too many open files in system */
-
-#undef EMFILE
-#define EMFILE      24      /* File descriptor value too large */
-
-#undef ESPIPE
-#define ESPIPE      29      /* Invalid seek */
-
-#undef ENOSYS
-#define ENOSYS      38      /* Function not implemented */
-
-#undef EOVERFLOW
-#define EOVERFLOW   75      /* Value too large to be stored in data type */
-
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
 /* Missing stat.h defines.
  * The following are sys/stat.h definitions not currently present in the ARMCC
  * errno.h. Note, ARMCC errno.h defines some symbol values differing from
  * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
- * changes by changing the symbol definition for filesystem use. */
-#define     _IFDIR  0040000 /* directory */
-#define     _IFREG  0100000 /* regular */
+ * changes by changing the symbol definition for filesystem use.
+ */
+#define     _IFMT   0170000 //< type of file
+#define     _IFSOCK 0140000 //< socket
+#define     _IFLNK  0120000 //< symbolic link
+#define     _IFREG  0100000 //< regular
+#define     _IFBLK  0060000 //< block special
+#define     _IFDIR  0040000 //< directory
+#define     _IFCHR  0020000 //< character special
+#define     _IFIFO  0010000 //< fifo special
 
-#define S_IFDIR     _IFDIR
-#define S_IFREG     _IFREG
+#define S_IFMT      _IFMT   //< type of file
+#define S_IFSOCK    _IFSOCK //< socket
+#define S_IFLNK     _IFLNK  //< symbolic link
+#define S_IFREG     _IFREG  //< regular
+#define S_IFBLK     _IFBLK  //< block special
+#define S_IFDIR     _IFDIR  //< directory
+#define S_IFCHR     _IFCHR  //< character special
+#define S_IFIFO     _IFIFO  //< fifo special
 
 #define S_IRWXU     (S_IRUSR | S_IWUSR | S_IXUSR)
-#define     S_IRUSR 0000400 /* read permission, owner */
-#define     S_IWUSR 0000200 /* write permission, owner */
-#define     S_IXUSR 0000100/* execute/search permission, owner */
+#define     S_IRUSR 0000400 ///< read permission, owner
+#define     S_IWUSR 0000200 ///< write permission, owner
+#define     S_IXUSR 0000100 ///< execute/search permission, owner
 #define S_IRWXG     (S_IRGRP | S_IWGRP | S_IXGRP)
-#define     S_IRGRP 0000040 /* read permission, group */
-#define     S_IWGRP 0000020 /* write permission, grougroup */
-#define     S_IXGRP 0000010/* execute/search permission, group */
+#define     S_IRGRP 0000040 ///< read permission, group
+#define     S_IWGRP 0000020 ///< write permission, grougroup
+#define     S_IXGRP 0000010 ///< execute/search permission, group
 #define S_IRWXO     (S_IROTH | S_IWOTH | S_IXOTH)
-#define     S_IROTH 0000004 /* read permission, other */
-#define     S_IWOTH 0000002 /* write permission, other */
-#define     S_IXOTH 0000001/* execute/search permission, other */
+#define     S_IROTH 0000004 ///< read permission, other
+#define     S_IWOTH 0000002 ///< write permission, other
+#define     S_IXOTH 0000001 ///< execute/search permission, other
+
+/* Refer to sys/stat standard
+ * Note: Not all fields may be supported by the underlying filesystem
+ */
+struct stat {
+    dev_t     st_dev;     ///< Device ID containing file
+    ino_t     st_ino;     ///< File serial number
+    mode_t    st_mode;    ///< Mode of file
+    nlink_t   st_nlink;   ///< Number of links to file
+
+    uid_t     st_uid;     ///< User ID
+    gid_t     st_gid;     ///< Group ID
+
+    off_t     st_size;    ///< Size of file in bytes
+
+    time_t    st_atime;   ///< Time of last access
+    time_t    st_mtime;   ///< Time of last data modification
+    time_t    st_ctime;   ///< Time of last status change
+};
 
 #endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */
 
 
 /* The following are dirent.h definitions are declared here to garuntee
- * consistency where structure may be different with different toolchains */
+ * consistency where structure may be different with different toolchains
+ */
 struct dirent {
-    char d_name[NAME_MAX+1];
-    uint8_t d_type;
+    char d_name[NAME_MAX+1]; ///< Name of file
+    uint8_t d_type;          ///< Type of file
 };
 
 enum {
-    DT_UNKNOWN, // The file type could not be determined.
-    DT_FIFO,    // This is a named pipe (FIFO).
-    DT_CHR,     // This is a character device.
-    DT_DIR,     // This is a directory.
-    DT_BLK,     // This is a block device.
-    DT_REG,     // This is a regular file.
-    DT_LNK,     // This is a symbolic link.
-    DT_SOCK,    // This is a UNIX domain socket.
+    DT_UNKNOWN, ///< The file type could not be determined.
+    DT_FIFO,    ///< This is a named pipe (FIFO).
+    DT_CHR,     ///< This is a character device.
+    DT_DIR,     ///< This is a directory.
+    DT_BLK,     ///< This is a block device.
+    DT_REG,     ///< This is a regular file.
+    DT_LNK,     ///< This is a symbolic link.
+    DT_SOCK,    ///< This is a UNIX domain socket.
 };
 
 #endif /* RETARGET_H */

--- a/platform/mbed_rtc_time.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/mbed_rtc_time.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -15,10 +15,8 @@
  */
 #include "hal/rtc_api.h"
 
-#include <time.h>
 #include "platform/mbed_critical.h"
 #include "platform/mbed_rtc_time.h"
-#include "hal/us_ticker_api.h"
 #include "platform/SingletonPtr.h"
 #include "platform/PlatformMutex.h"
 
@@ -76,14 +74,6 @@
     _mutex->unlock();
 }
 
-clock_t clock() {
-    _mutex->lock();
-    clock_t t = us_ticker_read();
-    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
-    _mutex->unlock();
-    return t;
-}
-
 void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
     _mutex->lock();
     _rtc_read = read_rtc;

--- a/platform/mbed_wait_api_no_rtos.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/mbed_wait_api_no_rtos.c	Wed Oct 11 12:45:49 2017 +0100
@@ -30,8 +30,9 @@
 }
 
 void wait_us(int us) {
-    uint32_t start = us_ticker_read();
-    while ((us_ticker_read() - start) < (uint32_t)us);
+    const ticker_data_t *const ticker = get_us_ticker_data();
+    uint32_t start = ticker_read(ticker);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
 }
 
 #endif // #ifndef MBED_CONF_RTOS_PRESENT

--- a/platform/mbed_wait_api_rtos.cpp	Mon Oct 02 15:33:19 2017 +0100
+++ b/platform/mbed_wait_api_rtos.cpp	Wed Oct 11 12:45:49 2017 +0100
@@ -22,6 +22,7 @@
 #include "hal/us_ticker_api.h"
 #include "rtos/rtos.h"
 #include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
 
 void wait(float s) {
     wait_us(s * 1000000.0f);
@@ -32,15 +33,19 @@
 }
 
 void wait_us(int us) {
-    uint32_t start = us_ticker_read();
+    const ticker_data_t *const ticker = get_us_ticker_data();
+
+    uint32_t start = ticker_read(ticker);
     // Use the RTOS to wait for millisecond delays if possible
     int ms = us / 1000;
     if ((ms > 0) && core_util_are_interrupts_enabled()) {
+        sleep_manager_lock_deep_sleep();
         Thread::wait((uint32_t)ms);
+        sleep_manager_unlock_deep_sleep();
     }
     // Use busy waiting for sub-millisecond delays, or for the whole
     // interval if interrupts are not enabled
-    while ((us_ticker_read() - start) < (uint32_t)us);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
 }
 
 #endif // #if MBED_CONF_RTOS_PRESENT

--- a/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -29,14 +29,14 @@
 
 void rtc_init(void) {
     init();
-    
+
     // Enable the oscillator
 #if defined (TARGET_K20D50M)
     RTC->CR |= RTC_CR_OSCE_MASK;
 #else
     // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator
     /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */
-    RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK; 
+    RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK;
 #endif
 
     //Configure the TSR. default value: 1
@@ -78,11 +78,6 @@
     // disable counter
     RTC->SR &= ~RTC_SR_TCE_MASK;
 
-    // we do not write 0 into TSR
-    // to avoid invalid time
-    if (t == 0)
-        t = 1;
-
     // write seconds
     RTC->TSR = t;
 

--- a/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -26,7 +26,7 @@
 
     // select RTC clock source
     SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
-    
+
     // Enable external crystal source if clock source is 32KHz
     if (extosc_frequency()==32768) {
         SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
@@ -104,11 +104,6 @@
     // disable counter
     RTC->SR &= ~RTC_SR_TCE_MASK;
 
-    // we do not write 0 into TSR
-    // to avoid invalid time
-    if (t == 0)
-        t = 1;
-
     // write seconds
     RTC->TSR = t;
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -28,154 +28,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
-#include "fsl_smc.h"
-#include "fsl_clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief Clock configuration structure. */
-typedef struct _clock_config
-{
-    mcg_config_t mcgConfig;       /*!< MCG configuration.      */
-    sim_clock_config_t simConfig; /*!< SIM configuration.      */
-    osc_config_t oscConfig;       /*!< OSC configuration.      */
-    uint32_t coreClock;           /*!< core clock frequency.   */
-} clock_config_t;
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/* Configuration for enter VLPR mode. Core clock = 4MHz. */
-const clock_config_t g_defaultClockConfigVlpr = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModeBLPI,            /* Work in BLPI mode. */
-            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable.   */
-            .ircs = kMCG_IrcFast,                /* Select IRC4M.      */
-            .fcrdiv = 0U,                        /* FCRDIV is 0.*/
-
-            .frdiv = 0U,
-            .drs = kMCG_DrsLow,         /* Low frequency range */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, /* Don't enable PLL. */
-                    .prdiv = 0U,
-                    .vdiv = 0U,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
-            .pllFllDiv = 0U,
-            .pllFllFrac = 0U,
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0U,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 4000000U, /* Core clock frequency */
-};
-
-/* Configuration for enter RUN mode. Core clock = 120MHz. */
-const clock_config_t g_defaultClockConfigRun = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModePEE,             /* Work in PEE mode. */
-            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
-            .ircs = kMCG_IrcSlow,                /* Select IRC32k. */
-            .fcrdiv = 0U,                        /* FCRDIV is 0. */
-
-            .frdiv = 4U,
-            .drs = kMCG_DrsLow,         /* Low frequency range */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x04U,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
-            .pllFllDiv = 0U,
-            .pllFllFrac = 0U,
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 120000000U, /* Core clock frequency */
-};
-
-/* Configuration for HSRUN mode. Core clock = 180MHz. */
-const clock_config_t g_defaultClockConfigHsrun = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModePEE,                   /* Work in PEE mode. */
-            .irclkEnableMode = kMCG_IrclkEnableInStop, /* MCGIRCLK enable. */
-            .ircs = kMCG_IrcSlow,                      /* Select IRC32k.*/
-            .fcrdiv = 0U,                              /* FCRDIV is 0. */
-
-            .frdiv = 4U,
-            .drs = kMCG_DrsLow,         /* Low frequency range. */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC. */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x0EU,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x02260000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 180000000U, /* Core clock frequency */
-};
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
 /*
  * How to setup clock using clock driver functions:
  *
@@ -204,62 +56,389 @@
  * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
  */
 
-void BOARD_BootClockVLPR(void)
-{
-    CLOCK_SetSimSafeDivs();
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: MK66FN2M0xxx18
+package_id: MK66FN2M0VMD18
+mcu_data: ksdk2_0
+processor_version: 1.0.1
+board: FRDM-K66F
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
-                         g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
+#include "fsl_smc.h"
+#include "fsl_clock_config.h"
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
-
-    SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_RTC32KCLK_CLK                       2U  /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+#define SIM_PLLFLLSEL_IRC48MCLK_CLK                       3U  /*!< PLLFLL select: IRC48MCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
 
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    SMC_SetPowerModeVlpr(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
 }
 
-void BOARD_BootClockRUN(void)
-{
-    CLOCK_SetSimSafeDivs();
-
-    CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
-    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: Core_clock.outFreq, value: 180 MHz, locked: true, accuracy: '0.001'}
+- {id: Flash_clock.outFreq, value: 180/7 MHz}
+- {id: FlexBus_clock.outFreq, value: 60 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 375 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 12 MHz}
+- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+- {id: PLLFLLCLK.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: powerMode, value: HSRUN}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLLCS}
+- {id: MCG.VDIV.scale, value: '30'}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C1_IREFSTEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV2.scale, value: '3', locked: true}
+- {id: SIM.OUTDIV3.scale, value: '3', locked: true}
+- {id: SIM.OUTDIV4.scale, value: '7', locked: true}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+- {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT}
+- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLDIV}
+- {id: SIM.TRACECLKSEL.sel, value: SIM.TRACEDIV}
+- {id: SIM.TRACEDIV.scale, value: '2'}
+- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+- {id: USBPHY.DIV.scale, value: '40'}
+- {id: USBPHY.PFD_CLK_SEL.sel, value: USBPHY.PFD_CLK_DIV2}
+- {id: USBPHY.PFD_FRAC_DIV.scale, value: '24', locked: true}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
-                        &g_defaultClockConfigRun.mcgConfig.pll0Config);
-
-    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
-                                  g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable | kMCG_IrclkEnableInStop,/* MCGIRCLK enabled as well as in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0xeU,                     /* VCO divider: multiplied by 30 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x2260000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /3, OUTDIV3: /3, OUTDIV4: /7 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockHSRUN =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
-
-    SystemCoreClock = g_defaultClockConfigRun.coreClock;
-}
-
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
 void BOARD_BootClockHSRUN(void)
 {
+    /* Set HSRUN power mode */
     SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
     SMC_SetPowerModeHsrun(SMC);
     while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
     {
     }
-
+    /* Set the system clock dividers in SIM to safe value. */
     CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockHSRUN.ircs,
+                                  mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
+                        mcgConfig_BOARD_BootClockHSRUN.pllcs,
+                        &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+}
 
-    CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
-    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 4 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV3.scale, value: '1'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 16 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
-    CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
-                        &g_defaultClockConfigHsrun.mcgConfig.pll0Config);
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockVLPR);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockVLPR.freq);
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Select the MCG external reference clock. */
+    CLOCK_SetExternalRefClkConfig(mcgConfig_BOARD_BootClockVLPR.oscsel);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
 
-    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
-                                  g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: Core_clock.outFreq, value: 120 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: FlexBus_clock.outFreq, value: 60 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 375 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 12 MHz}
+- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+- {id: PLLFLLCLK.outFreq, value: 120 MHz}
+- {id: System_clock.outFreq, value: 120 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLLCS}
+- {id: MCG.PRDIV.scale, value: '1', locked: true}
+- {id: MCG.VDIV.scale, value: '20', locked: true}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x4U,                     /* VCO divider: multiplied by 20 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x1140000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
-    SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
+                        mcgConfig_BOARD_BootClockRUN.pllcs,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
 }
+

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -27,28 +27,121 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
+
 #ifndef _CLOCK_CONFIG_H_
 #define _CLOCK_CONFIG_H_
 
+#include "fsl_common.h"
+
 /*******************************************************************************
- * DEFINITION
+ * Definitions
  ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ 12000000U
-#define BOARD_XTAL32K_CLK_HZ 32768U
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
 
 /*******************************************************************************
- * API
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK           180000000U  /*!< Core clock frequency: 180000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
+/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
+/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockHSRUN configuration
  ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus*/
 
-void BOARD_BootClockVLPR(void);
-void BOARD_BootClockRUN(void);
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
 void BOARD_BootClockHSRUN(void);
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus*/
 
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             120000000U  /*!< Core clock frequency: 120000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
 #endif /* _CLOCK_CONFIG_H_ */
+

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_phy.h"
 
@@ -53,8 +53,10 @@
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to enet clocks for each instance. */
 extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -64,14 +66,30 @@
 {
     uint32_t bssReg;
     uint32_t counter = PHY_TIMEOUT_COUNT;
+    uint32_t idReg = 0;
     status_t result = kStatus_Success;
     uint32_t instance = ENET_GetInstance(base);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Set SMI first. */
     CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     ENET_SetSMI(base, srcClock_Hz, false);
 
+    /* Initialization after PHY stars to work. */
+    while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
+    {
+        PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+        counter --;       
+    }
+
+    if (!counter)
+    {
+        return kStatus_Fail;
+    }
+
     /* Reset PHY. */
+    counter = PHY_TIMEOUT_COUNT;
     result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
     if (result == kStatus_Success)
     {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h	Wed Oct 11 12:45:49 2017 +0100
@@ -9,17 +9,17 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151218
+**     Build:               b170112
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MK66F18
 **
-**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -30,7 +30,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -45,8 +45,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -5218,7 +5218,7 @@
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
 /** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS                             { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn }
+#define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
 #define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
 
 /*!
@@ -6182,6 +6182,9 @@
 #define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
 #define ENET_Error_IRQS                          { ENET_Error_IRQn }
 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+/* ENET Buffer Descriptor and Buffer Address Alignment. */
+#define ENET_BUFF_ALIGNMENT                      (16U)
+
 
 /*!
  * @}
@@ -7731,30 +7734,30 @@
 
 
 /* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE                                 (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA                                      ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE                                 (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB                                      ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE                                 (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC                                      ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE                                 (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD                                      ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE                                 (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE                                      ((GPIO_Type *)PTE_BASE)
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
 /** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
 /** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
 
 /*!
  * @}
@@ -9828,252 +9831,6 @@
 
 
 /* ----------------------------------------------------------------------------
-   -- MPU Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
- * @{
- */
-
-/** MPU - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
-       uint8_t RESERVED_0[12];
-  struct {                                         /* offset: 0x10, array step: 0x8 */
-    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
-    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
-  } SP[5];
-       uint8_t RESERVED_1[968];
-  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
-       uint8_t RESERVED_2[832];
-  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} MPU_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MPU Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Masks MPU Register Masks
- * @{
- */
-
-/*! @name CESR - Control/Error Status Register */
-#define MPU_CESR_VLD_MASK                        (0x1U)
-#define MPU_CESR_VLD_SHIFT                       (0U)
-#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
-#define MPU_CESR_NRGD_MASK                       (0xF00U)
-#define MPU_CESR_NRGD_SHIFT                      (8U)
-#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
-#define MPU_CESR_NSP_MASK                        (0xF000U)
-#define MPU_CESR_NSP_SHIFT                       (12U)
-#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
-#define MPU_CESR_HRL_MASK                        (0xF0000U)
-#define MPU_CESR_HRL_SHIFT                       (16U)
-#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
-#define MPU_CESR_SPERR_MASK                      (0xF8000000U)
-#define MPU_CESR_SPERR_SHIFT                     (27U)
-#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
-
-/*! @name EAR - Error Address Register, slave port n */
-#define MPU_EAR_EADDR_MASK                       (0xFFFFFFFFU)
-#define MPU_EAR_EADDR_SHIFT                      (0U)
-#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
-
-/* The count of MPU_EAR */
-#define MPU_EAR_COUNT                            (5U)
-
-/*! @name EDR - Error Detail Register, slave port n */
-#define MPU_EDR_ERW_MASK                         (0x1U)
-#define MPU_EDR_ERW_SHIFT                        (0U)
-#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
-#define MPU_EDR_EATTR_MASK                       (0xEU)
-#define MPU_EDR_EATTR_SHIFT                      (1U)
-#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
-#define MPU_EDR_EMN_MASK                         (0xF0U)
-#define MPU_EDR_EMN_SHIFT                        (4U)
-#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
-#define MPU_EDR_EPID_MASK                        (0xFF00U)
-#define MPU_EDR_EPID_SHIFT                       (8U)
-#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
-#define MPU_EDR_EACD_MASK                        (0xFFFF0000U)
-#define MPU_EDR_EACD_SHIFT                       (16U)
-#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
-
-/* The count of MPU_EDR */
-#define MPU_EDR_COUNT                            (5U)
-
-/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
-#define MPU_WORD_VLD_MASK                        (0x1U)
-#define MPU_WORD_VLD_SHIFT                       (0U)
-#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
-#define MPU_WORD_M0UM_MASK                       (0x7U)
-#define MPU_WORD_M0UM_SHIFT                      (0U)
-#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
-#define MPU_WORD_M0SM_MASK                       (0x18U)
-#define MPU_WORD_M0SM_SHIFT                      (3U)
-#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
-#define MPU_WORD_M0PE_MASK                       (0x20U)
-#define MPU_WORD_M0PE_SHIFT                      (5U)
-#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
-#define MPU_WORD_ENDADDR_MASK                    (0xFFFFFFE0U)
-#define MPU_WORD_ENDADDR_SHIFT                   (5U)
-#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
-#define MPU_WORD_SRTADDR_MASK                    (0xFFFFFFE0U)
-#define MPU_WORD_SRTADDR_SHIFT                   (5U)
-#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
-#define MPU_WORD_M1UM_MASK                       (0x1C0U)
-#define MPU_WORD_M1UM_SHIFT                      (6U)
-#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
-#define MPU_WORD_M1SM_MASK                       (0x600U)
-#define MPU_WORD_M1SM_SHIFT                      (9U)
-#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
-#define MPU_WORD_M1PE_MASK                       (0x800U)
-#define MPU_WORD_M1PE_SHIFT                      (11U)
-#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
-#define MPU_WORD_M2UM_MASK                       (0x7000U)
-#define MPU_WORD_M2UM_SHIFT                      (12U)
-#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
-#define MPU_WORD_M2SM_MASK                       (0x18000U)
-#define MPU_WORD_M2SM_SHIFT                      (15U)
-#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
-#define MPU_WORD_PIDMASK_MASK                    (0xFF0000U)
-#define MPU_WORD_PIDMASK_SHIFT                   (16U)
-#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
-#define MPU_WORD_M2PE_MASK                       (0x20000U)
-#define MPU_WORD_M2PE_SHIFT                      (17U)
-#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
-#define MPU_WORD_M3UM_MASK                       (0x1C0000U)
-#define MPU_WORD_M3UM_SHIFT                      (18U)
-#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
-#define MPU_WORD_M3SM_MASK                       (0x600000U)
-#define MPU_WORD_M3SM_SHIFT                      (21U)
-#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
-#define MPU_WORD_M3PE_MASK                       (0x800000U)
-#define MPU_WORD_M3PE_SHIFT                      (23U)
-#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
-#define MPU_WORD_PID_MASK                        (0xFF000000U)
-#define MPU_WORD_PID_SHIFT                       (24U)
-#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
-#define MPU_WORD_M4WE_MASK                       (0x1000000U)
-#define MPU_WORD_M4WE_SHIFT                      (24U)
-#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
-#define MPU_WORD_M4RE_MASK                       (0x2000000U)
-#define MPU_WORD_M4RE_SHIFT                      (25U)
-#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
-#define MPU_WORD_M5WE_MASK                       (0x4000000U)
-#define MPU_WORD_M5WE_SHIFT                      (26U)
-#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
-#define MPU_WORD_M5RE_MASK                       (0x8000000U)
-#define MPU_WORD_M5RE_SHIFT                      (27U)
-#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
-#define MPU_WORD_M6WE_MASK                       (0x10000000U)
-#define MPU_WORD_M6WE_SHIFT                      (28U)
-#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
-#define MPU_WORD_M6RE_MASK                       (0x20000000U)
-#define MPU_WORD_M6RE_SHIFT                      (29U)
-#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
-#define MPU_WORD_M7WE_MASK                       (0x40000000U)
-#define MPU_WORD_M7WE_SHIFT                      (30U)
-#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
-#define MPU_WORD_M7RE_MASK                       (0x80000000U)
-#define MPU_WORD_M7RE_SHIFT                      (31U)
-#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
-
-/* The count of MPU_WORD */
-#define MPU_WORD_COUNT                           (12U)
-
-/* The count of MPU_WORD */
-#define MPU_WORD_COUNT2                          (4U)
-
-/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
-#define MPU_RGDAAC_M0UM_MASK                     (0x7U)
-#define MPU_RGDAAC_M0UM_SHIFT                    (0U)
-#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
-#define MPU_RGDAAC_M0SM_MASK                     (0x18U)
-#define MPU_RGDAAC_M0SM_SHIFT                    (3U)
-#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
-#define MPU_RGDAAC_M0PE_MASK                     (0x20U)
-#define MPU_RGDAAC_M0PE_SHIFT                    (5U)
-#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
-#define MPU_RGDAAC_M1UM_MASK                     (0x1C0U)
-#define MPU_RGDAAC_M1UM_SHIFT                    (6U)
-#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
-#define MPU_RGDAAC_M1SM_MASK                     (0x600U)
-#define MPU_RGDAAC_M1SM_SHIFT                    (9U)
-#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
-#define MPU_RGDAAC_M1PE_MASK                     (0x800U)
-#define MPU_RGDAAC_M1PE_SHIFT                    (11U)
-#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
-#define MPU_RGDAAC_M2UM_MASK                     (0x7000U)
-#define MPU_RGDAAC_M2UM_SHIFT                    (12U)
-#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
-#define MPU_RGDAAC_M2SM_MASK                     (0x18000U)
-#define MPU_RGDAAC_M2SM_SHIFT                    (15U)
-#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
-#define MPU_RGDAAC_M2PE_MASK                     (0x20000U)
-#define MPU_RGDAAC_M2PE_SHIFT                    (17U)
-#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
-#define MPU_RGDAAC_M3UM_MASK                     (0x1C0000U)
-#define MPU_RGDAAC_M3UM_SHIFT                    (18U)
-#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
-#define MPU_RGDAAC_M3SM_MASK                     (0x600000U)
-#define MPU_RGDAAC_M3SM_SHIFT                    (21U)
-#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
-#define MPU_RGDAAC_M3PE_MASK                     (0x800000U)
-#define MPU_RGDAAC_M3PE_SHIFT                    (23U)
-#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
-#define MPU_RGDAAC_M4WE_MASK                     (0x1000000U)
-#define MPU_RGDAAC_M4WE_SHIFT                    (24U)
-#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
-#define MPU_RGDAAC_M4RE_MASK                     (0x2000000U)
-#define MPU_RGDAAC_M4RE_SHIFT                    (25U)
-#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
-#define MPU_RGDAAC_M5WE_MASK                     (0x4000000U)
-#define MPU_RGDAAC_M5WE_SHIFT                    (26U)
-#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
-#define MPU_RGDAAC_M5RE_MASK                     (0x8000000U)
-#define MPU_RGDAAC_M5RE_SHIFT                    (27U)
-#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
-#define MPU_RGDAAC_M6WE_MASK                     (0x10000000U)
-#define MPU_RGDAAC_M6WE_SHIFT                    (28U)
-#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
-#define MPU_RGDAAC_M6RE_MASK                     (0x20000000U)
-#define MPU_RGDAAC_M6RE_SHIFT                    (29U)
-#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
-#define MPU_RGDAAC_M7WE_MASK                     (0x40000000U)
-#define MPU_RGDAAC_M7WE_SHIFT                    (30U)
-#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
-#define MPU_RGDAAC_M7RE_MASK                     (0x80000000U)
-#define MPU_RGDAAC_M7RE_SHIFT                    (31U)
-#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
-
-/* The count of MPU_RGDAAC */
-#define MPU_RGDAAC_COUNT                         (12U)
-
-
-/*!
- * @}
- */ /* end of group MPU_Register_Masks */
-
-
-/* MPU - Peripheral instance base addresses */
-/** Peripheral MPU base address */
-#define MPU_BASE                                 (0x4000D000u)
-/** Peripheral MPU base pointer */
-#define MPU                                      ((MPU_Type *)MPU_BASE)
-/** Array initializer of MPU peripheral base addresses */
-#define MPU_BASE_ADDRS                           { MPU_BASE }
-/** Array initializer of MPU peripheral base pointers */
-#define MPU_BASE_PTRS                            { MPU }
-
-/*!
- * @}
- */ /* end of group MPU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
    -- NV Peripheral Access Layer
    ---------------------------------------------------------------------------- */
 
@@ -10590,7 +10347,7 @@
 /** Array initializer of PIT peripheral base pointers */
 #define PIT_BASE_PTRS                            { PIT }
 /** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+#define PIT_IRQS                                 { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
 
 /*!
  * @}
@@ -13237,6 +12994,252 @@
 
 
 /* ----------------------------------------------------------------------------
+   -- SYSMPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
+ * @{
+ */
+
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define SYSMPU_CESR_VLD_MASK                     (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT                    (0U)
+#define SYSMPU_CESR_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK                    (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT                   (8U)
+#define SYSMPU_CESR_NRGD(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK                     (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT                    (12U)
+#define SYSMPU_CESR_NSP(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK                     (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT                    (16U)
+#define SYSMPU_CESR_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK                   (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT                  (27U)
+#define SYSMPU_CESR_SPERR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define SYSMPU_EAR_EADDR_MASK                    (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT                   (0U)
+#define SYSMPU_EAR_EADDR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT                         (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define SYSMPU_EDR_ERW_MASK                      (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT                     (0U)
+#define SYSMPU_EDR_ERW(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK                    (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT                   (1U)
+#define SYSMPU_EDR_EATTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK                      (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT                     (4U)
+#define SYSMPU_EDR_EMN(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EPID_MASK                     (0xFF00U)
+#define SYSMPU_EDR_EPID_SHIFT                    (8U)
+#define SYSMPU_EDR_EPID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EACD_MASK                     (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT                    (16U)
+#define SYSMPU_EDR_EACD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT                         (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define SYSMPU_WORD_VLD_MASK                     (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT                    (0U)
+#define SYSMPU_WORD_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0UM_MASK                    (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT                   (0U)
+#define SYSMPU_WORD_M0UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0SM_MASK                    (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT                   (3U)
+#define SYSMPU_WORD_M0SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0PE_MASK                    (0x20U)
+#define SYSMPU_WORD_M0PE_SHIFT                   (5U)
+#define SYSMPU_WORD_M0PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT                (5U)
+#define SYSMPU_WORD_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT                (5U)
+#define SYSMPU_WORD_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK                    (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT                   (6U)
+#define SYSMPU_WORD_M1UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK                    (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT                   (9U)
+#define SYSMPU_WORD_M1SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1PE_MASK                    (0x800U)
+#define SYSMPU_WORD_M1PE_SHIFT                   (11U)
+#define SYSMPU_WORD_M1PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M2UM_MASK                    (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT                   (12U)
+#define SYSMPU_WORD_M2UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK                    (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT                   (15U)
+#define SYSMPU_WORD_M2SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_PIDMASK_MASK                 (0xFF0000U)
+#define SYSMPU_WORD_PIDMASK_SHIFT                (16U)
+#define SYSMPU_WORD_PIDMASK(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_M2PE_MASK                    (0x20000U)
+#define SYSMPU_WORD_M2PE_SHIFT                   (17U)
+#define SYSMPU_WORD_M2PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M3UM_MASK                    (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT                   (18U)
+#define SYSMPU_WORD_M3UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK                    (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT                   (21U)
+#define SYSMPU_WORD_M3SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3PE_MASK                    (0x800000U)
+#define SYSMPU_WORD_M3PE_SHIFT                   (23U)
+#define SYSMPU_WORD_M3PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_PID_MASK                     (0xFF000000U)
+#define SYSMPU_WORD_PID_SHIFT                    (24U)
+#define SYSMPU_WORD_PID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_M4WE_MASK                    (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT                   (24U)
+#define SYSMPU_WORD_M4WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4RE_MASK                    (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT                   (25U)
+#define SYSMPU_WORD_M4RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK                    (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT                   (26U)
+#define SYSMPU_WORD_M5WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK                    (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT                   (27U)
+#define SYSMPU_WORD_M5RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK                    (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT                   (28U)
+#define SYSMPU_WORD_M6WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK                    (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT                   (29U)
+#define SYSMPU_WORD_M6RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK                    (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT                   (30U)
+#define SYSMPU_WORD_M7WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK                    (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT                   (31U)
+#define SYSMPU_WORD_M7RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT                        (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2                       (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define SYSMPU_RGDAAC_M0UM_MASK                  (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT                 (0U)
+#define SYSMPU_RGDAAC_M0UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK                  (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT                 (3U)
+#define SYSMPU_RGDAAC_M0SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0PE_MASK                  (0x20U)
+#define SYSMPU_RGDAAC_M0PE_SHIFT                 (5U)
+#define SYSMPU_RGDAAC_M0PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK                  (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT                 (6U)
+#define SYSMPU_RGDAAC_M1UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK                  (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT                 (9U)
+#define SYSMPU_RGDAAC_M1SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1PE_MASK                  (0x800U)
+#define SYSMPU_RGDAAC_M1PE_SHIFT                 (11U)
+#define SYSMPU_RGDAAC_M1PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK                  (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT                 (12U)
+#define SYSMPU_RGDAAC_M2UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK                  (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT                 (15U)
+#define SYSMPU_RGDAAC_M2SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2PE_MASK                  (0x20000U)
+#define SYSMPU_RGDAAC_M2PE_SHIFT                 (17U)
+#define SYSMPU_RGDAAC_M2PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK                  (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT                 (18U)
+#define SYSMPU_RGDAAC_M3UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK                  (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT                 (21U)
+#define SYSMPU_RGDAAC_M3SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3PE_MASK                  (0x800000U)
+#define SYSMPU_RGDAAC_M3PE_SHIFT                 (23U)
+#define SYSMPU_RGDAAC_M3PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK                  (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT                 (24U)
+#define SYSMPU_RGDAAC_M4WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK                  (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT                 (25U)
+#define SYSMPU_RGDAAC_M4RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK                  (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT                 (26U)
+#define SYSMPU_RGDAAC_M5WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK                  (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT                 (27U)
+#define SYSMPU_RGDAAC_M5RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK                  (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT                 (28U)
+#define SYSMPU_RGDAAC_M6WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK                  (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT                 (29U)
+#define SYSMPU_RGDAAC_M6RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK                  (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT                 (30U)
+#define SYSMPU_RGDAAC_M7WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK                  (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT                 (31U)
+#define SYSMPU_RGDAAC_M7RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT                      (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE                              (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU                                   ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS                        { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS                         { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
    -- TPM Peripheral Access Layer
    ---------------------------------------------------------------------------- */
 
@@ -17250,6 +17253,43 @@
 
 
 /* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
    -- SDK Compatibility
    ---------------------------------------------------------------------------- */
 
@@ -17498,16 +17538,16 @@
 #define DSPI2                                    SPI2
 #define FLEXCAN0                                 CAN0
 #define FLEXCAN1                                 CAN1
-#define GPIOA_BASE                               PTA_BASE
-#define GPIOA                                    PTA
-#define GPIOB_BASE                               PTB_BASE
-#define GPIOB                                    PTB
-#define GPIOC_BASE                               PTC_BASE
-#define GPIOC                                    PTC
-#define GPIOD_BASE                               PTD_BASE
-#define GPIOD                                    PTD
-#define GPIOE_BASE                               PTE_BASE
-#define GPIOE                                    PTE
+#define PTA_BASE                                 GPIOA_BASE
+#define PTA                                      GPIOA
+#define PTB_BASE                                 GPIOB_BASE
+#define PTB                                      GPIOB
+#define PTC_BASE                                 GPIOC_BASE
+#define PTC                                      GPIOC
+#define PTD_BASE                                 GPIOD_BASE
+#define PTD                                      GPIOD
+#define PTE_BASE                                 GPIOE_BASE
+#define PTE                                      GPIOE
 #define Watchdog_IRQn                            WDOG_EWM_IRQn
 #define Watchdog_IRQHandler                      WDOG_EWM_IRQHandler
 #define LPTimer_IRQn                             LPTMR0_IRQn

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,14 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 2.9, 2015-06-08
-**     Build:               b151217
+**     Build:               b170228
 **
 **     Abstract:
 **         Chip specific module features.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -19,7 +18,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -34,8 +33,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -212,8 +211,8 @@
 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
 /* @brief MMDVSQ availability on the SoC. */
 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
-/* @brief MPU availability on the SoC. */
-#define FSL_FEATURE_SOC_MPU_COUNT (1)
+/* @brief SYSMPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
 /* @brief MSCAN availability on the SoC. */
 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
 /* @brief MSCM availability on the SoC. */
@@ -304,6 +303,8 @@
 #define FSL_FEATURE_SOC_USB_COUNT (1)
 /* @brief USBDCD availability on the SoC. */
 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+/* @brief USBHS availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHS_COUNT (1)
 /* @brief USBHSDCD availability on the SoC. */
 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
 /* @brief USBPHY availability on the SoC. */
@@ -376,6 +377,8 @@
 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
 /* @brief Number of interrupt vectors. */
 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
 
 /* CMP module features */
 
@@ -437,7 +440,7 @@
 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
 /* @brief Total number of DMA channels on all modules. */
 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
-/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
 
 /* ENET module features */
@@ -485,6 +488,10 @@
     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
     /* @brief Has flash cache control in MCM module. */
     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
     /* @brief P-Flash start address. */
     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
     /* @brief P-Flash block count. */
@@ -499,6 +506,8 @@
     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
     /* @brief P-Flash block swap feature. */
     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
     /* @brief Has FlexNVM memory. */
     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
@@ -551,6 +560,10 @@
     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
     /* @brief Has 0x80 Program Partition command. */
     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
     /* @brief Has 0x81 Set FlexRAM Function command. */
@@ -662,6 +675,10 @@
     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
     /* @brief Has flash cache control in MCM module. */
     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
     /* @brief P-Flash start address. */
     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
     /* @brief P-Flash block count. */
@@ -676,6 +693,8 @@
     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
     /* @brief P-Flash block swap feature. */
     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16)
     /* @brief Has FlexNVM memory. */
     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
@@ -728,6 +747,10 @@
     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
     /* @brief Has 0x80 Program Partition command. */
     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
     /* @brief Has 0x81 Set FlexRAM Function command. */
@@ -830,6 +853,8 @@
     ((x) == FTM3 ? (8) : (-1)))))
 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has extended deadtime value. */
+#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
 /* @brief Enable pwm output for the module. */
 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
 /* @brief Has half-cycle reload for the module. */
@@ -839,6 +864,15 @@
 /* @brief Has reload initialization trigger. */
 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
 
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
 /* I2C module features */
 
 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
@@ -861,6 +895,8 @@
 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 /* @brief Has double buffering support (register S2). */
 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
 
 /* SAI module features */
 
@@ -899,12 +935,14 @@
 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
 /* @brief Number of digital filters. */
 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
-/* @brief Has MF5 register. */
+/* @brief Has MF register. */
 #define FSL_FEATURE_LLWU_HAS_MF (1)
 /* @brief Has PF register. */
 #define FSL_FEATURE_LLWU_HAS_PF (1)
 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
 /* @brief Has external pin 0 connected to LLWU device. */
 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
 /* @brief Index of port of external pin. */
@@ -1126,14 +1164,24 @@
 
 /* @brief Has process identifier support. */
 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
+/* @brief L1 ICACHE line size in byte. */
+#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16)
+/* @brief L1 DCACHE line size in byte. */
+#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16)
 
 /* LPTMR module features */
 
 /* @brief Has shared interrupt handler with another LPTMR module. */
 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
 
 /* LPUART module features */
 
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
@@ -1150,8 +1198,10 @@
 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
 /* @brief 2 bits long stop bit is available. */
 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
-/* @brief Maximal data width without parity bit. */
+/* @brief If 10-bit mode is supported. */
 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
@@ -1184,12 +1234,14 @@
 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
-/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
-#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
 /* @brief Has separate DMA RX and TX requests. */
 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
 /* @brief Has LPAURT_PARAM. */
 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
 /* @brief Has LPUART_VERID. */
@@ -1239,7 +1291,7 @@
 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 /* @brief TBD */
 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
-/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
 #define FSL_FEATURE_MCG_HAS_PLL (1)
 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
@@ -1270,29 +1322,6 @@
 /* @brief Reset clock mode is BLPI. */
 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
 
-/* MPU module features */
-
-/* @brief Specifies number of descriptors available. */
-#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
-/* @brief Has process identifier support. */
-#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
-/* @brief Has master 0. */
-#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
-/* @brief Has master 1. */
-#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
-/* @brief Has master 2. */
-#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
-/* @brief Has master 3. */
-#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
-/* @brief Has master 4. */
-#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
-/* @brief Has master 5. */
-#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
-/* @brief Has master 6. */
-#define FSL_FEATURE_MPU_HAS_MASTER6 (1)
-/* @brief Has master 7. */
-#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
-
 /* interrupt module features */
 
 /* @brief Lowest interrupt request number. */
@@ -1390,20 +1419,13 @@
 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
 /* @brief Has dedicated interrupt vector. */
 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
 
-/* GPIO module features */
-
-/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
-#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
-/* @brief Has port input disable register (PIDR). */
-#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
-/* @brief Has dedicated interrupt vector. */
-#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
-
 /* RCM module features */
 
 /* @brief Has Loss-of-Lock Reset support. */
@@ -1746,6 +1768,12 @@
 #define FSL_FEATURE_SMC_HAS_PARAM (0)
 /* @brief Has SMC_VERID. */
 #define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
 
 /* DSPI module features */
 
@@ -1769,6 +1797,17 @@
 /* @brief Has separate DMA RX and TX requests. */
 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
 
+/* SYSMPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Total number of MPU slave. */
+#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
+/* @brief Total number of MPU master. */
+#define FSL_FEATURE_SYSMPU_MASTER_COUNT (7)
+
 /* SysTick module features */
 
 /* @brief Systick has external reference clock. */
@@ -1796,12 +1835,20 @@
 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
 /* @brief Has external trigger selection. */
 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
-/* @brief Has TPM_COMBINE. */
+/* @brief Has TPM_COMBINE register. */
 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
-/* @brief Has TPM_FILTER. */
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
 #define FSL_FEATURE_TPM_HAS_FILTER (1)
-/* @brief Has TPM_QDCTRL. */
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_QDCTRL register. */
 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
 
 /* TSI module features */
 
@@ -1828,8 +1875,8 @@
 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
 /* @brief 2 bits long stop bit is available. */
 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
-/* @brief Maximal data width without parity bit. */
-#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
@@ -1881,6 +1928,8 @@
 
 /* USB module features */
 
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
 /* @brief HOST mode enabled */
 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
 /* @brief OTG mode enabled */
@@ -1900,6 +1949,8 @@
 
 /* USBHS module features */
 
+/* @brief EHCI module instance count */
+#define FSL_FEATURE_USBHS_EHCI_COUNT (1)
 /* @brief Number of endpoints supported */
 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
 
@@ -1909,7 +1960,7 @@
 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
-/* @brief Describes the set of SC[MODE_LV] bitfield values */
+/* @brief If high/low buffer mode supported */
 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
 /* @brief Module has also low reference (registers VREFL/VREFH) */
 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct	Wed Oct 11 12:45:49 2017 +0100
@@ -7,14 +7,13 @@
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b160406
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -25,7 +24,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -40,8 +39,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S	Wed Oct 11 12:45:49 2017 +0100
@@ -4,12 +4,11 @@
 ; *            MK66F18
 ; *  @version: 3.0
 ; *  @date:    2015-3-25
-; *  @build:   b151210
+; *  @build:   b170112
 ; * ---------------------------------------------------------------------------------------
 ; *
-; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
-; * All rights reserved.
-; *
+; * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
+; * Copyright 2016 - 2017 NXP
 ; * Redistribution and use in source and binary forms, with or without modification,
 ; * are permitted provided that the following conditions are met:
 ; *
@@ -20,7 +19,7 @@
 ; *   list of conditions and the following disclaimer in the documentation and/or
 ; *   other materials provided with the distribution.
 ; *
-; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; * o Neither the name of the copyright holder nor the names of its
 ; *   contributors may be used to endorse or promote products derived from this
 ; *   software without specific prior written permission.
 ; *
@@ -483,6 +482,8 @@
                 LDR     R0, =0xE000ED08
                 LDR     R1, =__Vectors
                 STR     R1, [R0]
+                LDR     R2, [R1]
+                MSR     MSP, R2
                 LDR     R0, =SystemInit
                 BLX     R0
                 CPSIE   i               ; Unmask interrupts

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld	Wed Oct 11 12:45:49 2017 +0100
@@ -6,14 +6,13 @@
 **     Compiler:            GNU C Compiler
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151217
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -24,7 +23,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -39,8 +38,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */
@@ -212,7 +211,6 @@
   text_end = ORIGIN(m_text) + LENGTH(m_text);
   ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
 
-  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;
   /* Uninitialized data section */
   .bss :
   {
@@ -222,9 +220,6 @@
     __bss_start__ = .;
     *(.bss)
     *(.bss*)
-    . = ALIGN(512);
-    USB_RAM_START = .;
-    . += USB_RAM_GAP;
     *(COMMON)
     . = ALIGN(4);
     __bss_end__ = .;
@@ -248,17 +243,6 @@
     . += STACK_SIZE;
   } > m_data_2
 
-  m_usb_bdt USB_RAM_START (NOLOAD) :
-  {
-    *(m_usb_bdt)
-    USB_RAM_BDT_END = .;
-  }
-
-  m_usb_global USB_RAM_BDT_END (NOLOAD) :
-  {
-    *(m_usb_global)
-  }
-
   /* Initializes stack on the end of block */
   __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
   __StackLimit = __StackTop - STACK_SIZE;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S	Wed Oct 11 12:45:49 2017 +0100
@@ -4,12 +4,11 @@
 /*            MK66F18                                                                     */
 /*  @version: 3.0                                                                         */
 /*  @date:    2015-3-25                                                                   */
-/*  @build:   b151210                                                                     */
+/*  @build:   b170112                                                                     */
 /* ---------------------------------------------------------------------------------------*/
 /*                                                                                        */
-/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
-/* All rights reserved.                                                                   */
-/*                                                                                        */
+/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.                               */
+/* Copyright 2016 - 2017 NXP                                                              */
 /* Redistribution and use in source and binary forms, with or without modification,       */
 /* are permitted provided that the following conditions are met:                          */
 /*                                                                                        */
@@ -20,7 +19,7 @@
 /*   list of conditions and the following disclaimer in the documentation and/or          */
 /*   other materials provided with the distribution.                                      */
 /*                                                                                        */
-/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/* o Neither the name of the copyright holder nor the names of its                        */
 /*   contributors may be used to endorse or promote products derived from this            */
 /*   software without specific prior written permission.                                  */
 /*                                                                                        */
@@ -328,6 +327,8 @@
     ldr     r0, =VTOR
     ldr     r1, =__isr_vector
     str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
 #ifndef __NO_SYSTEM_INIT
     ldr   r0,=SystemInit
     blx   r0

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf	Wed Oct 11 12:45:49 2017 +0100
@@ -6,14 +6,13 @@
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151009
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -24,7 +23,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -39,8 +38,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S	Wed Oct 11 12:45:49 2017 +0100
@@ -4,12 +4,11 @@
 ;            MK66F18
 ;  @version: 3.0
 ;  @date:    2015-3-25
-;  @build:   b151210
+;  @build:   b170112
 ; ---------------------------------------------------------------------------------------
 ;
-; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
-; All rights reserved.
-;
+; Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
+; Copyright 2016 - 2017 NXP
 ; Redistribution and use in source and binary forms, with or without modification,
 ; are permitted provided that the following conditions are met:
 ;
@@ -20,7 +19,7 @@
 ;   list of conditions and the following disclaimer in the documentation and/or
 ;   other materials provided with the distribution.
 ;
-; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; o Neither the name of the copyright holder nor the names of its
 ;   contributors may be used to endorse or promote products derived from this
 ;   software without specific prior written permission.
 ;
@@ -355,6 +354,8 @@
         LDR     R0, =0xE000ED08
         LDR     R1, =__vector_table
         STR     R1, [R0]
+        LDR     R2, [R1]
+        MSR     MSP, R2
         LDR     R0, =SystemInit
         BLX     R0
         CPSIE   I               ; Unmask interrupts

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,7 +1,6 @@
 /*
- * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
+ * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
@@ -12,7 +11,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -26,6 +25,7 @@
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 
 #ifndef __FSL_DEVICE_REGISTERS_H__
@@ -36,7 +36,7 @@
  *
  * The CPU macro should be declared in the project or makefile.
  */
-#if (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+#if (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VLQ18) || \
     defined(CPU_MK66FX1M0VMD18))
 
 #define K66F18_SERIES

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c	Wed Oct 11 12:45:49 2017 +0100
@@ -9,19 +9,19 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151216
+**     Build:               b170112
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -32,7 +32,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -47,8 +47,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -213,7 +213,6 @@
             Divider *= 0x04U;
           } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
             Divider *= 0x02U;
-          } else {
           }
           MCGOUTClock = (uint32_t)(480000000 / Divider);
           MCGOUTClock *= 18;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h	Wed Oct 11 12:45:49 2017 +0100
@@ -9,19 +9,19 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151216
+**     Build:               b170112
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -32,7 +32,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -47,8 +47,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -46,8 +46,10 @@
 /*! @brief Pointers to ADC16 bases for each instance. */
 static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC16 clocks for each instance. */
-const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -57,7 +59,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++)
     {
         if (s_adc16Bases[instance] == base)
         {
@@ -65,7 +67,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
+    assert(instance < ARRAY_SIZE(s_adc16Bases));
 
     return instance;
 }
@@ -76,8 +78,10 @@
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* ADCx_CFG1. */
     tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
@@ -126,8 +130,10 @@
 
 void ADC16_Deinit(ADC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void ADC16_GetDefaultConfig(adc16_config_t *config)
@@ -149,7 +155,7 @@
 status_t ADC16_DoAutoCalibration(ADC_Type *base)
 {
     bool bHWTrigger = false;
-    uint32_t tmp32;
+    volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */
     status_t status = kStatus_Success;
 
     /* The calibration would be failed when in hardwar mode.
@@ -171,6 +177,7 @@
             break;
         }
     }
+    tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */
 
     /* Restore the hardware trigger setting if it was enabled before. */
     if (bHWTrigger)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -74,7 +73,7 @@
  * @brief Channel multiplexer mode for each channel.
  *
  * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
- * are the different channels but share the same channel number.
+ * are the different channels that share the same channel number.
  */
 typedef enum _adc_channel_mux_mode
 {
@@ -104,7 +103,7 @@
     kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
     kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
 
-    /* This group of enumeration is for public user. */
+    /* This group of enumeration is for a public user. */
     kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit,    /*!< Single End 8-bit. */
     kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
     kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
@@ -203,7 +202,7 @@
 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
 
 /*!
- * @brief ADC16 converter configuration .
+ * @brief ADC16 converter configuration.
  */
 typedef struct _adc16_config
 {
@@ -219,7 +218,7 @@
 } adc16_config_t;
 
 /*!
- * @brief ADC16 Hardware compare configuration.
+ * @brief ADC16 Hardware comparison configuration.
  */
 typedef struct _adc16_hardware_compare_config
 {
@@ -237,7 +236,7 @@
     uint32_t channelNumber;                    /*!< Setting the conversion channel number. The available range is 0-31.
                                                     See channel connection information for each chip in Reference
                                                     Manual document. */
-    bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */
+    bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
     bool enableDifferentialConversion; /*!< Using Differential sample mode. */
 #endif                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
@@ -296,9 +295,9 @@
 void ADC16_Deinit(ADC_Type *base);
 
 /*!
- * @brief Gets an available pre-defined settings for converter's configuration.
+ * @brief Gets an available pre-defined settings for the converter's configuration.
  *
- * This function initializes the converter configuration structure with an available settings. The default values are:
+ * This function initializes the converter configuration structure with available settings. The default values are as follows.
  * @code
  *   config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
  *   config->clockSource                = kADC16_ClockSourceAsynchronousClock;
@@ -310,7 +309,7 @@
  *   config->enableLowPower             = false;
  *   config->enableContinuousConversion = false;
  * @endcode
- * @param config Pointer to configuration structure.
+ * @param config Pointer to the configuration structure.
  */
 void ADC16_GetDefaultConfig(adc16_config_t *config);
 
@@ -318,15 +317,15 @@
 /*!
  * @brief  Automates the hardware calibration.
  *
- * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation.
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
  * Execute the calibration before using the converter. Note that the hardware trigger should be used
- * during calibration.
+ * during the calibration.
  *
  * @param  base ADC16 peripheral base address.
  *
  * @return                 Execution status.
  * @retval kStatus_Success Calibration is done successfully.
- * @retval kStatus_Fail    Calibration is failed.
+ * @retval kStatus_Fail    Calibration has failed.
  */
 status_t ADC16_DoAutoCalibration(ADC_Type *base);
 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
@@ -350,16 +349,16 @@
 /* @} */
 
 /*!
- * @name Advanced Feature
+ * @name Advanced Features
  * @{
  */
 
 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
 /*!
- * @brief Enables generating the DMA trigger when conversion is completed.
+ * @brief Enables generating the DMA trigger when the conversion is complete.
  *
  * @param base   ADC16 peripheral base address.
- * @param enable Switcher of DMA feature. "true" means to enable, "false" means not.
+ * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
  */
 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
 {
@@ -378,7 +377,7 @@
  * @brief Enables the hardware trigger mode.
  *
  * @param base   ADC16 peripheral base address.
- * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not.
+ * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
  */
 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
 {
@@ -408,13 +407,12 @@
 /*!
  * @brief Configures the hardware compare mode.
  *
- * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result
- * in
- * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference
- * manual document for more detailed information.
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result
+ * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference
+ * manual for more information.
  *
  * @param base     ADC16 peripheral base address.
- * @param config   Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature.
+ * @param config   Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
  */
 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
 
@@ -422,21 +420,21 @@
 /*!
  * @brief Sets the hardware average mode.
  *
- * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple
- * conversion results are accumulated and averaged internally. This aids  reading results.
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
  *
  * @param base  ADC16 peripheral base address.
- * @param mode  Setting hardware average mode. See "adc16_hardware_average_mode_t".
+ * @param mode  Setting the hardware average mode. See "adc16_hardware_average_mode_t".
  */
 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
 
 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
 /*!
- * @brief Configures the PGA for converter's front end.
+ * @brief Configures the PGA for the converter's front end.
  *
  * @param base    ADC16 peripheral base address.
- * @param config  Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature.
+ * @param config  Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
  */
 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
@@ -468,26 +466,26 @@
 /*!
  * @brief Configures the conversion channel.
  *
- * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
  * configures the channel while the external trigger source helps to trigger the conversion.
  *
  * Note that the "Channel Group" has a detailed description.
- * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one
- * group of status and control register, one for each conversion. The channel group parameter indicates which group of
- * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers.  The
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
  * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
- * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware
- * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for
- * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the
- * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
- * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion.
- * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware
+ * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the
+ * number of SC1n registers (channel groups) specific to this device.  Channel group 1 or greater are not used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
  * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
  * conversion aborts the current conversion.
  *
  * @param base          ADC16 peripheral base address.
  * @param channelGroup  Channel group index.
- * @param config        Pointer to "adc16_channel_config_t" structure for conversion channel.
+ * @param config        Pointer to the "adc16_channel_config_t" structure for the conversion channel.
  */
 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -12,7 +13,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -28,7 +29,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
 #include "fsl_clock.h"
 
 /*******************************************************************************
@@ -124,7 +124,6 @@
 
 /* External XTAL0 (OSC0) clock frequency. */
 uint32_t g_xtal0Freq;
-
 /* External XTAL32K clock frequency. */
 uint32_t g_xtal32Freq;
 
@@ -195,17 +194,36 @@
  */
 static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
 
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
 /*!
  * @brief Delay function to wait FLL stable.
  *
  * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
  * 1ms. Every time changes FLL setting, should wait this time for FLL stable.
  */
-static void CLOCK_FllStableDelay(void);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
+void CLOCK_FllStableDelay(void)
+{
+    /*
+       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
+       at most, so this function could obtain the 1ms delay.
+     */
+    volatile uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+#else  /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */
+/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to
+ * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this
+ * file would call the CLOCK_FllStableDelay() regardness how it is defined.
+ */
+extern void CLOCK_FllStableDelay(void);
+#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
 
 static uint32_t CLOCK_GetMcgExtClkFreq(void)
 {
@@ -342,19 +360,6 @@
     return range;
 }
 
-static void CLOCK_FllStableDelay(void)
-{
-    /*
-       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
-       at most, so this function could obtain the 1ms delay.
-     */
-    volatile uint32_t i = 30000U;
-    while (i--)
-    {
-        __NOP();
-    }
-}
-
 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void)
 {
     if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
@@ -419,6 +424,9 @@
         case 1U: /* PLL. */
             freq = CLOCK_GetPll0Freq();
             break;
+        case 2U: /* USB1 PFD */
+            freq = CLOCK_GetExtPllFreq();
+            break;
         case 3U: /* MCG IRC48M. */
             freq = MCG_INTERNAL_IRC_48M;
             break;
@@ -573,7 +581,30 @@
 
 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 {
+    /* Source and freq are not used for USB HS. */
+    src = src;
+    freq = freq;
+
+    SIM->SCGC3 |= SIM_SCGC3_USBHS_MASK;
+
+    SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
+                      | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
+
+    USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PLL */
+
+    return true;
+}
+
+void CLOCK_DisableUsbhs0Clock(void)
+{
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY PLL */
+    SIM->SCGC3 &= ~SIM_SCGC3_USBHS_MASK;
+}
+
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
+{
     volatile uint32_t i;
+    uint32_t phyPllDiv = 0U;
 
     /*
      * In order to bring up the internal 480MHz USB PLL clock, should make sure:
@@ -584,12 +615,28 @@
     assert(!(MCG->C2 & MCG_C2_IRCS_MASK));
     assert(OSC0->CR & OSC_CR_ERCLKEN_MASK);
 
+    if (24000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+    }
+    else if (16000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+    }
+    else if (12000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+    }
+    else
+    {
+        return false;
+    }
+
     /* Source and freq are not used for USB HS. */
     src = src;
-    freq = freq;
 
+    SIM->SCGC3 |= SIM_SCGC3_USBHSPHY_MASK;
     SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK;
-    SIM->SCGC3 |= (SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
 
     i = 500000U;
     while (i--)
@@ -597,12 +644,66 @@
         __NOP();
     }
 
-    SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
-                      | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
+    USBPHY->TRIM_OVERRIDE_EN = 0x01U;                 /* Override the trim. */
+    USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
+    USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
+    USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv;
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */
+    USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;          /* Clear to 0U to run clocks */
+
+    /* Wait for lock. */
+    while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
+    {
+    }
 
     return true;
 }
 
+void CLOCK_DisableUsbhs0PhyPllClock(void)
+{
+    USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */
+    SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
+    SIM->SCGC3 &= ~SIM_SCGC3_USBHSPHY_MASK;
+}
+
+void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src)
+{
+    assert((frac <= 35U) && (frac >= 18U));
+    uint32_t fracFreq = (480000U * 18U / frac) * 1000U;
+
+    USBPHY->ANACTRL = (USBPHY->ANACTRL & ~(USBPHY_ANACTRL_PFD_FRAC_MASK | USBPHY_ANACTRL_PFD_CLK_SEL_MASK)) |
+                      (USBPHY_ANACTRL_PFD_FRAC(frac) | USBPHY_ANACTRL_PFD_CLK_SEL(src));
+
+    USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+    while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
+    {
+    }
+
+    if (kCLOCK_UsbPfdSrcExt == src)
+    {
+        s_extPllFreq = g_xtal0Freq;
+    }
+    else if (kCLOCK_UsbPfdSrcFracDivBy4 == src)
+    {
+        s_extPllFreq = fracFreq / 4U;
+    }
+    else if (kCLOCK_UsbPfdSrcFracDivBy2 == src)
+    {
+        s_extPllFreq = fracFreq / 2U;
+    }
+    else
+    {
+        s_extPllFreq = fracFreq;
+    }
+}
+
+void CLOCK_DisableUsbhs0PfdClock(void)
+{
+    USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+    s_extPllFreq = 0U;
+}
+
 uint32_t CLOCK_GetOutClkFreq(void)
 {
     uint32_t mcgoutclk;
@@ -705,6 +806,12 @@
 
     mcgpll0clk = CLOCK_GetPll0RefFreq();
 
+    /*
+     * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock.
+     * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock.
+     */
+    assert(mcgpll0clk);
+
     mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL);
     mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL);
 
@@ -746,16 +853,6 @@
     }
 
     MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
-    if (kMCG_OscselOsc == oscsel)
-    {
-        if (MCG->C2 & MCG_C2_EREFS_MASK)
-        {
-            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
-            {
-            }
-        }
-    }
-
     if (needDelay)
     {
         /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
@@ -936,6 +1033,14 @@
     }
 }
 
+void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs)
+{
+    MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs);
+    while (pllcs != MCG_S2_PLLCST_VAL)
+    {
+    }
+}
+
 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
 {
     /* Clear the previous flag, MCG_SC[LOCS0]. */
@@ -1279,7 +1384,7 @@
     return mode;
 }
 
-status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
     uint8_t mcg_c4;
     bool change_drs = false;
@@ -1323,7 +1428,7 @@
     }
 
     /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
-    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs));
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
 
     /* Check MCG_S[CLKST] */
     while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
@@ -1372,6 +1477,17 @@
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait and check status. */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1406,7 +1522,7 @@
     return kStatus_Success;
 }
 
-status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
     uint8_t mcg_c4;
     bool change_drs = false;
@@ -1459,7 +1575,7 @@
     {
     }
 
-    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs));
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
 
     /* Wait for FLL stable time. */
     if (fllStableDelay)
@@ -1514,6 +1630,17 @@
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV = frdiv */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for Reference clock Status bit to clear */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1574,6 +1701,12 @@
 
 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
 {
+    /* If external PLL is used, then the config could be NULL. */
+    if (kMCG_PllClkSelExtPll != pllcs)
+    {
+        assert(config);
+    }
+
     /*
        This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
        but with this workflow, the source mode could be all modes except PEI/PBI.
@@ -1601,13 +1734,15 @@
         CLOCK_EnablePll0(config);
     }
 
+    /* Change to PLL mode. */
+    MCG->C6 |= MCG_C6_PLLS_MASK;
+
     MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs);
     while (pllcs != MCG_S2_PLLCST_VAL)
     {
     }
 
-    /* Change to PLL mode. */
-    MCG->C6 |= MCG_C6_PLLS_MASK;
+    /* Wait for PLL mode changed. */
     while (!(MCG->S & MCG_S_PLLST_MASK))
     {
     }
@@ -1682,9 +1817,9 @@
     return kStatus_Success;
 }
 
-status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
-    return CLOCK_SetFeiMode(drs, fllStableDelay);
+    return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
 }
 
 status_t CLOCK_BootToFeeMode(
@@ -1721,6 +1856,17 @@
         ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal)    /* CLKS = 2 */
                                                                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
     while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
            (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
@@ -1735,7 +1881,11 @@
 
 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
 {
-    assert(config);
+    /* If external PLL is used, then the config could be NULL. */
+    if (kMCG_PllClkSelExtPll != pllcs)
+    {
+        assert(config);
+    }
 
     CLOCK_SetExternalRefClkConfig(oscsel);
 
@@ -1793,7 +1943,7 @@
         if (!(MCG->S & MCG_S_IRCST_MASK))
         {
             CLOCK_ExternalModeToFbeModeQuick();
-            CLOCK_SetFeiMode(config->drs, (void (*)(void))0);
+            CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
         }
 
         CLOCK_SetExternalRefClkConfig(config->oscsel);
@@ -1805,7 +1955,7 @@
         MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
 
         {
-            CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay);
+            CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
         }
     }
 
@@ -1821,13 +1971,13 @@
         switch (next_mode)
         {
             case kMCG_ModeFEI:
-                status = CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay);
+                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
                 break;
             case kMCG_ModeFEE:
                 status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
                 break;
             case kMCG_ModeFBI:
-                status = CLOCK_SetFbiMode(config->drs, (void (*)(void))0);
+                status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
                 break;
             case kMCG_ModeFBE:
                 status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -12,7 +13,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -31,45 +32,83 @@
 #ifndef _FSL_CLOCK_H_
 #define _FSL_CLOCK_H_
 
-#include "fsl_device_registers.h"
-#include <stdint.h>
-#include <stdbool.h>
-#include <assert.h>
+#include "fsl_common.h"
 
 /*! @addtogroup clock */
 /*! @{ */
 
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configures whether to check a parameter in a function.
+ *
+ * Some MCG settings must be changed with conditions, for example:
+ *  1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
+ *     MCGIRCLK is used as a system clock source.
+ *  2. MCG_C7[OSCSEL] should not be changed  when the external reference clock is used
+ *     as a system clock source. For example, in FBE/BLPE/PBE modes.
+ *  3. The users should only switch between the supported clock modes.
+ *
+ * MCG functions check the parameter and MCG status before setting, if not allowed
+ * to change, the functions return error. The parameter checking increases code size,
+ * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
+ * disable parameter checking.
+ */
+#ifndef MCG_CONFIG_CHECK_PARAM
+#define MCG_CONFIG_CHECK_PARAM 0U
+#endif
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could contol the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
-/*! @brief Clock driver version. */
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.2.2. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*@}*/
 
 /*! @brief External XTAL0 (OSC0) clock frequency.
  *
- * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the
- * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example,
- * if XTAL0 is 8MHz,
+ * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
+ * if XTAL0 is 8 MHz:
  * @code
- * CLOCK_InitOsc0(...); // Setup the OSC0
- * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver.
+ * CLOCK_InitOsc0(...); // Set up the OSC0
+ * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
  * @endcode
  *
- * This is important for the multicore platforms, only one core needs to setup
- * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq
- * to get valid clock frequency.
+ * This is important for the multicore platforms where only one core needs to set up the
+ * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
+ * to get a valid clock frequency.
  */
 extern uint32_t g_xtal0Freq;
 
 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
  *
- * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the
- * function CLOCK_SetXtal32Freq to set the value in to clock driver.
+ * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal32Freq to set the value in the clock driver.
  *
- * This is important for the multicore platforms, only one core needs to setup
- * the clock, all other cores need to call CLOCK_SetXtal32Freq
- * to get valid clock frequency.
+ * This is important for the multicore platforms where only one core needs to set up
+ * the clock. All other cores need to call the CLOCK_SetXtal32Freq
+ * to get a valid clock frequency.
  */
 extern uint32_t g_xtal32Freq;
 
@@ -194,16 +233,10 @@
         kCLOCK_Sdramc0 \
     }
 
-/*! @brief Clock ip name array for MMCAU. */
-#define MMCAU_CLOCKS  \
-    {                 \
-        kCLOCK_Mmcau0 \
-    }
-
 /*! @brief Clock ip name array for MPU. */
-#define MPU_CLOCKS  \
-    {               \
-        kCLOCK_Mpu0 \
+#define SYSMPU_CLOCKS  \
+    {                  \
+        kCLOCK_Sysmpu0 \
     }
 
 /*! @brief Clock ip name array for VREF. */
@@ -242,12 +275,6 @@
         kCLOCK_Crc0 \
     }
 
-/*! @brief Clock ip name array for LMEM. */
-#define LMEM_CLOCKS  \
-    {                \
-        kCLOCK_Lmem0 \
-    }
-
 /*! @brief Clock ip name array for I2C. */
 #define I2C_CLOCKS                                         \
     {                                                      \
@@ -267,9 +294,9 @@
     }
 
 /*! @brief Clock ip name array for CMP. */
-#define CMP_CLOCKS                            \
-    {                                         \
-        kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
+#define CMP_CLOCKS                                         \
+    {                                                      \
+        kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
     }
 
 /*!
@@ -334,9 +361,26 @@
     kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U),   /*!< Use PLL0.      */
     kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
     kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M.    */
-    kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U)                               /*!< Use USB_CLKIN. */
+    kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U),                              /*!< Use USB_CLKIN. */
+    kCLOCK_UsbSrcUnused = 0xFFFFFFFFU,                                    /*!< Used when the function does not
+                                                                               care the clock source. */
 } clock_usb_src_t;
 
+/*! @brief Source of the USB HS PHY. */
+typedef enum _clock_usb_phy_src
+{
+    kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
+} clock_usb_phy_src_t;
+
+/*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
+typedef enum _clock_usb_pfd_src
+{
+    kCLOCK_UsbPfdSrcExt = 0U,        /*!< Use external crystal. */
+    kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
+    kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
+    kCLOCK_UsbPfdSrcFrac = 3U,       /*!< Use PFD_FRAC output. */
+} clock_usb_pfd_src_t;
+
 /*------------------------------------------------------------------------------
 
  clock_gate_t definition:
@@ -402,6 +446,7 @@
     kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
+    kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
 
     kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
@@ -430,7 +475,7 @@
 
     kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
     kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
-    kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
+    kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
     kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
 } clock_ip_name_t;
 
@@ -447,7 +492,7 @@
 /*! @brief OSC work mode. */
 typedef enum _osc_mode
 {
-    kOSC_ModeExt = 0U, /*!< Use external clock.   */
+    kOSC_ModeExt = 0U, /*!< Use an external clock.   */
 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
     kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
 #else
@@ -498,8 +543,8 @@
  * @brief OSC Initialization Configuration Structure
  *
  * Defines the configuration data structure to initialize the OSC.
- * When porting to a new board, please set the following members
- * according to board setting:
+ * When porting to a new board, set the following members
+ * according to the board setting:
  * 1. freq: The external frequency.
  * 2. workMode: The OSC module mode.
  */
@@ -575,7 +620,7 @@
 typedef enum _mcg_pll_clk_select
 {
     kMCG_PllClkSelPll0,  /*!< PLL0 output clock is selected  */
-    kMCG_PllClkSelExtPll /* External PLL clock is selected   */
+    kMCG_PllClkSelExtPll /* The external PLL clock is selected   */
 } mcg_pll_clk_select_t;
 
 /*! @brief MCG clock monitor mode. */
@@ -596,8 +641,8 @@
     kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
     kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4),            /*!< IRC is used when using ATM. */
     kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5),       /*!< Hardware fail occurs during ATM. */
-    kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)             /*!< Could not change clock source because
-                                                                               it is used currently. */
+    kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)             /*!< Can't change the clock source because
+                                                                               it is in use. */
 };
 
 /*! @brief MCG status flags. */
@@ -621,11 +666,11 @@
 /*! @brief MCG PLL clock enable mode definition. */
 enum _mcg_pll_enable_mode
 {
-    kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of
-                                                           MCG clock mode. Generally, PLL
+    kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
+                                                           MCG clock mode. Generally, the PLL
                                                            is disabled in FLL modes
-                                                           (FEI/FBI/FEE/FBE), set PLL clock
-                                                           enable independent will enable
+                                                           (FEI/FBI/FEE/FBE). Setting the PLL clock
+                                                           enable independent, enables the
                                                            PLL in the FLL modes.          */
     kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK        /*!< MCGPLLCLK enable in STOP mode. */
 };
@@ -652,16 +697,16 @@
     uint8_t vdiv;       /*!< VCO divider VDIV.           */
 } mcg_pll_config_t;
 
-/*! @brief MCG configure structure for mode change.
+/*! @brief MCG mode change configuration structure
  *
- * When porting to a new board, please set the following members
- * according to board setting:
- * 1. frdiv: If FLL uses the external reference clock, please set this
- *    value to make sure external reference clock divided by frdiv is
- *    in the range 31.25kHz to 39.0625kHz.
+ * When porting to a new board, set the following members
+ * according to the board setting:
+ * 1. frdiv: If the FLL uses the external reference clock, set this
+ *    value to ensure that the external reference clock divided by frdiv is
+ *    in the 31.25 kHz to 39.0625 kHz range.
  * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
- *    PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to
- *    FSL_FEATURE_MCG_PLL_REF_MAX.
+ *    PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
+ *    FSL_FEATURE_MCG_PLL_REF_MAX range.
  */
 typedef struct _mcg_config
 {
@@ -694,26 +739,6 @@
 #endif /* __cplusplus */
 
 /*!
- * @brief Set the XTAL0 frequency based on board setting.
- *
- * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
- */
-static inline void CLOCK_SetXtal0Freq(uint32_t freq)
-{
-    g_xtal0Freq = freq;
-}
-
-/*!
- * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting.
- *
- * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
- */
-static inline void CLOCK_SetXtal32Freq(uint32_t freq)
-{
-    g_xtal32Freq = freq;
-}
-
-/*!
  * @brief Enable the clock for specific IP.
  *
  * @param name  Which clock to enable, see \ref clock_ip_name_t.
@@ -839,8 +864,12 @@
 
 /*! @brief Enable USB HS clock.
  *
- * @param src  USB HS clock source.
- * @param freq The frequency specified by src.
+ * This function only enables the access to USB HS prepheral, upper layer
+ * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
+ * clock to use USB HS.
+ *
+ * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
+ * @param freq USB HS does not care about the clock source, so this parameter is ignored.
  * @retval true The clock is set successfully.
  * @retval false The clock source is invalid to get proper USB HS clock.
  */
@@ -848,13 +877,49 @@
 
 /*! @brief Disable USB HS clock.
  *
- * Disable USB HS clock.
+ * Disable USB HS clock, this function should not be called after
+ * @ref CLOCK_DisableUsbhs0PhyPllClock.
+ */
+void CLOCK_DisableUsbhs0Clock(void);
+
+/*! @brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables the internal 480MHz USB PHY PLL clock.
+ *
+ * @param src  USB HS PHY PLL clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB HS clock.
+ */
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
+
+/*! @brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
  */
-static inline void CLOCK_DisableUsbhs0Clock(void)
-{
-    SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
-    SIM->SCGC3 &= ~(SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
-}
+void CLOCK_DisableUsbhs0PhyPllClock(void);
+
+/*! @brief Enable USB HS PFD clock.
+ *
+ * This function enables USB HS PFD clock. It should be called after function
+ * @ref CLOCK_EnableUsbhs0PhyPllClock.
+ * The PFD output clock is selected by the parameter @p src. When the @p src is
+ * @ref kCLOCK_UsbPfdSrcExt, then the PFD outout is from external crystal
+ * directly, in this case, the @p frac is not used. In other cases, the PFD_FRAC
+ * output clock frequency is 480MHz*18/frac, the PFD output frequency is based
+ * on the PFD_FRAC output.
+ *
+ * @param frac The value set to PFD_FRAC, it must be in the range of 18 to 35.
+ * @param src Source of the USB HS PFD clock (USB1PFDCLK).
+ */
+void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
+
+/*! @brief Disable USB HS PFD clock.
+ *
+ * This function disables USB HS PFD clock. It should be called before function
+ * @ref CLOCK_DisableUsbhs0PhyPllClock.
+ */
+void CLOCK_DisableUsbhs0PfdClock(void);
 
 /*! @brief Enable USB FS clock.
  *
@@ -997,9 +1062,9 @@
 /*@{*/
 
 /*!
- * @brief Get the MCG output clock(MCGOUTCLK) frequency.
+ * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
  *
- * This function gets the MCG output clock frequency (Hz) based on current MCG
+ * This function gets the MCG output clock frequency in Hz based on the current MCG
  * register value.
  *
  * @return The frequency of MCGOUTCLK.
@@ -1007,40 +1072,40 @@
 uint32_t CLOCK_GetOutClkFreq(void);
 
 /*!
- * @brief Get the MCG FLL clock(MCGFLLCLK) frequency.
+ * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
  *
- * This function gets the MCG FLL clock frequency (Hz) based on current MCG
- * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other
- * modes, FLL is disabled in low power state.
+ * This function gets the MCG FLL clock frequency in Hz based on the current MCG
+ * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
+ * disabled in low power state in other modes.
  *
  * @return The frequency of MCGFLLCLK.
  */
 uint32_t CLOCK_GetFllFreq(void);
 
 /*!
- * @brief Get the MCG internal reference clock(MCGIRCLK) frequency.
+ * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
  *
- * This function gets the MCG internal reference clock frequency (Hz) based
- * on current MCG register value.
+ * This function gets the MCG internal reference clock frequency in Hz based
+ * on the current MCG register value.
  *
  * @return The frequency of MCGIRCLK.
  */
 uint32_t CLOCK_GetInternalRefClkFreq(void);
 
 /*!
- * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency.
+ * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
  *
- * This function gets the MCG fixed frequency clock frequency (Hz) based
- * on current MCG register value.
+ * This function gets the MCG fixed frequency clock frequency in Hz based
+ * on the current MCG register value.
  *
  * @return The frequency of MCGFFCLK.
  */
 uint32_t CLOCK_GetFixedFreqClkFreq(void);
 
 /*!
- * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency.
+ * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
  *
- * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG
+ * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
  * register value.
  *
  * @return The frequency of MCGPLL0CLK.
@@ -1048,21 +1113,21 @@
 uint32_t CLOCK_GetPll0Freq(void);
 
 /*!
- * @brief Get the MCG external PLL frequency.
+ * @brief Gets the MCG external PLL frequency.
  *
- * This function gets the MCG external PLL frequency (Hz).
+ * This function gets the MCG external PLL frequency in Hz.
  *
- * @return The frequency of MCG external PLL.
+ * @return The frequency of the MCG external PLL.
  */
 uint32_t CLOCK_GetExtPllFreq(void);
 
 /*!
- * @brief Set the MCG external PLL frequency.
+ * @brief Sets the MCG external PLL frequency.
  *
- * This function sets the MCG external PLL frequency (Hz), the MCG external PLL
- * frequency is passed in to MCG driver through this function. Please call this
- * function after the external PLL frequency is changed, otherwise the APIs for
- * get frequency may returns wrong value.
+ * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
+ * frequency is passed to the MCG driver using this function. Call this
+ * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
+ * the frequency, may return an incorrect value.
  *
  * @param The frequency of MCG external PLL.
  */
@@ -1074,12 +1139,12 @@
 /*@{*/
 
 /*!
- * @brief Enable or disable MCG low power.
+ * @brief Enables or disables the MCG low power.
  *
- * Enable MCG low power will disable the PLL and FLL in bypass modes. That is,
- * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and
- * PBI mode, enable low power will set MCG to BLPI mode.
- * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting.
+ * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
+ * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
+ * PBI modes, enabling low power sets the MCG to BLPI mode.
+ * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
  *
  * @param enable True to enable MCG low power, false to disable MCG low power.
  */
@@ -1096,42 +1161,56 @@
 }
 
 /*!
- * @brief Configure the Internal Reference clock (MCGIRCLK)
+ * @brief Configures the Internal Reference clock (MCGIRCLK).
  *
- * This function setups the \c MCGIRCLK base on parameters. It selects the IRC
- * source, if fast IRC is used, this function also sets the fast IRC divider.
- * This function also sets whether enable \c MCGIRCLK in stop mode.
- * Calling this function in FBI/PBI/BLPI modes may change the system clock, so
- * it is not allowed to use this in these modes.
+ * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
+ * source. If the fast IRC is used, this function sets the fast IRC divider.
+ * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
+ * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
+ * using the function in these modes it is not allowed.
  *
  * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
  * @param ircs       MCGIRCLK clock source, choose fast or slow.
  * @param fcrdiv     Fast IRC divider setting (\c FCRDIV).
- * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK.
+ * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
  * @retval kStatus_Success MCGIRCLK configuration finished successfully.
  */
 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
 
 /*!
- * @brief Select the MCG external reference clock.
+ * @brief Selects the MCG external reference clock.
  *
- * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL]
- * and wait for the clock source stable. Should not change external reference
- * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes.
+ * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
+ * and waits for the clock source to be stable. Because the external reference
+ * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
  *
  * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
- * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change.
+ * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
  * @retval kStatus_Success External reference clock set successfully.
  */
 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
 
 /*!
+ * @brief Set the FLL external reference clock divider value.
+ *
+ * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
+ *
+ * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
+ */
+static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv);
+}
+
+/*!
  * @brief Enables the PLL0 in FLL mode.
  *
- * This function setups the PLL0 in FLL mode, make sure the PLL reference
- * clock is enabled before calling this function. This function reconfigures
- * the PLL0, make sure the PLL0 is not used as a clock source while calling
- * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL
+ * This function sets us the PLL0 in FLL mode and reconfigures
+ * the PLL0. Ensure that the PLL reference
+ * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
+ * The function CLOCK_CalcPllDiv gets the correct PLL
  * divider values.
  *
  * @param config Pointer to the configuration structure.
@@ -1141,7 +1220,7 @@
 /*!
  * @brief Disables the PLL0 in FLL mode.
  *
- * This function disables the PLL0 in FLL mode, it should be used together with
+ * This function disables the PLL0 in FLL mode. It should be used together with the
  * @ref CLOCK_EnablePll0.
  */
 static inline void CLOCK_DisablePll0(void)
@@ -1150,70 +1229,80 @@
 }
 
 /*!
- * @brief Calculates the PLL divider setting for desired output frequency.
+ * @brief Calculates the PLL divider setting for a desired output frequency.
  *
- * This function calculates the proper reference clock divider (\c PRDIV) and
- * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the
- * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are
- * returned from parameters. If desired frequency is not valid, this function
+ * This function calculates the correct reference clock divider (\c PRDIV) and
+ * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
+ * closest frequency match with the corresponding \c PRDIV/VDIV
+ * returned from parameters. If a desired frequency is not valid, this function
  * returns 0.
  *
  * @param refFreq    PLL reference clock frequency.
  * @param desireFreq Desired PLL output frequency.
  * @param prdiv      PRDIV value to generate desired PLL frequency.
  * @param vdiv       VDIV value to generate desired PLL frequency.
- * @return Closest frequency PLL could generate.
+ * @return Closest frequency match that the PLL was able generate.
  */
 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
 
+/*!
+ * @brief Set the PLL selection.
+ *
+ * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
+ * change finished.
+ *
+ * @param pllcs The PLL to select.
+ */
+void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
+
 /*@}*/
 
 /*! @name MCG clock lock monitor functions. */
 /*@{*/
 
 /*!
- * @brief Set the OSC0 clock monitor mode.
+ * @brief Sets the OSC0 clock monitor mode.
  *
- * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the RTC OSC clock monitor mode.
+ * @brief Sets the RTC OSC clock monitor mode.
  *
- * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the PLL0 clock monitor mode.
+ * @brief Sets the PLL0 clock monitor mode.
  *
- * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the external PLL clock monitor mode.
+ * @brief Sets the external PLL clock monitor mode.
  *
- * Set the external PLL clock monitor mode, see @ref mcg_monitor_mode_t
+ * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
  * for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Get the MCG status flags.
+ * @brief Gets the MCG status flags.
  *
- * This function gets the MCG clock status flags, all the status flags are
+ * This function gets the MCG clock status flags. All status flags are
  * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
- * check specific flags, compare the return value with the flags.
+ * check a specific flag, compare the return value with the flag.
  *
  * Example:
  * @code
@@ -1239,8 +1328,8 @@
 /*!
  * @brief Clears the MCG status flags.
  *
- * This function clears the MCG clock lock lost status. The parameter is logical
- * OR value of the flags to clear, see @ref _mcg_status_flags_t.
+ * This function clears the MCG clock lock lost status. The parameter is a logical
+ * OR value of the flags to clear. See @ref _mcg_status_flags_t.
  *
  * Example:
  * @code
@@ -1265,8 +1354,8 @@
  * @brief Configures the OSC external reference clock (OSCERCLK).
  *
  * This function configures the OSC external reference clock (OSCERCLK).
- * For example, to enable the OSCERCLK in normal mode and stop mode, and also set
- * the output divider to 1, as follows:
+ * This is an example to enable the OSCERCLK in normal and stop modes and also set
+ * the output divider to 1:
  *
    @code
    oscer_config_t config =
@@ -1320,45 +1409,71 @@
 }
 
 /*!
- * @brief Initialize OSC0.
+ * @brief Initializes the OSC0.
  *
- * This function initializes OSC0 according to board configuration.
+ * This function initializes the OSC0 according to the board configuration.
  *
  * @param  config Pointer to the OSC0 configuration structure.
  */
 void CLOCK_InitOsc0(osc_config_t const *config);
 
 /*!
- * @brief Deinitialize OSC0.
+ * @brief Deinitializes the OSC0.
  *
- * This function deinitializes OSC0.
+ * This function deinitializes the OSC0.
  */
 void CLOCK_DeinitOsc0(void);
 
 /* @} */
 
 /*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Sets the XTAL0 frequency based on board settings.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+    g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
+ *
+ * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+    g_xtal32Freq = freq;
+}
+/* @} */
+
+/*!
  * @name MCG auto-trim machine.
  * @{
  */
 
 /*!
- * @brief Auto trim the internal reference clock.
+ * @brief Auto trims the internal reference clock.
  *
- * This function trims the internal reference clock using external clock. If
+ * This function trims the internal reference clock by using the external clock. If
  * successful, it returns the kStatus_Success and the frequency after
  * trimming is received in the parameter @p actualFreq. If an error occurs,
  * the error code is returned.
  *
- * @param extFreq      External clock frequency, should be bus clock.
- * @param desireFreq   Frequency want to trim to.
- * @param actualFreq   Actual frequency after trim.
+ * @param extFreq      External clock frequency, which should be a bus clock.
+ * @param desireFreq   Frequency to trim to.
+ * @param actualFreq   Actual frequency after trimming.
  * @param atms         Trim fast or slow internal reference clock.
  * @retval kStatus_Success ATM success.
- * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM.
+ * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
  * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
- * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source.
- * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim.
+ * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
+ * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
  */
 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
 /* @} */
@@ -1369,260 +1484,265 @@
 /*!
  * @brief Gets the current MCG mode.
  *
- * This function checks the MCG registers and determine current MCG mode.
+ * This function checks the MCG registers and determines the current MCG mode.
  *
- * @return Current MCG mode or error code, see @ref mcg_mode_t.
+ * @return Current MCG mode or error code; See @ref mcg_mode_t.
  */
 mcg_mode_t CLOCK_GetMode(void);
 
 /*!
- * @brief Set MCG to FEI mode.
+ * @brief Sets the MCG to FEI mode.
  *
- * This function sets MCG to FEI mode. If could not set to FEI mode directly
- * from current mode, this function returns error. @ref kMCG_Dmx32Default is used in this
- * mode because using kMCG_Dmx32Fine with internal reference clock source
- * might damage hardware.
+ * This function sets the MCG to FEI mode. If setting to FEI mode fails
+ * from the current mode, this function returns an error.
  *
+ * @param       dmx32  DMX32 in FEI mode.
  * @param       drs The DCO range selection.
- * @param       fllStableDelay Delay function to make sure FLL is stable, if pass
- *              in NULL, then does not delay.
+ * @param       fllStableDelay Delay function to  ensure that the FLL is stable. Passing
+ *              NULL does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to a frequency above 32768 Hz.
  */
-status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FEE mode.
+ * @brief Sets the MCG to FEE mode.
  *
- * This function sets MCG to FEE mode. If could not set to FEE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FEE mode. If setting to FEE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FEE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable, if pass
- *          in NULL, then does not delay.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. Passing
+ *          NULL does not cause a delay.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FBI mode.
+ * @brief Sets the MCG to FBI mode.
  *
- * This function sets MCG to FBI mode. If could not set to FBI mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FBI mode. If setting to FBI mode fails
+ * from the current mode, this function returns an error.
  *
+ * @param  dmx32  DMX32 in FBI mode.
  * @param  drs  The DCO range selection.
- * @param  fllStableDelay Delay function to make sure FLL is stable. If FLL
- *         is not used in FBI mode, this parameter could be NULL. Pass in
- *         NULL does not delay.
+ * @param  fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *         is not used in FBI mode, this parameter can be NULL. Passing
+ *         NULL does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
  */
-status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FBE mode.
+ * @brief Sets the MCG to FBE mode.
  *
- * This function sets MCG to FBE mode. If could not set to FBE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FBE mode. If setting to FBE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FBE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable. If FLL
- *          is not used in FBE mode, this parameter could be NULL. Pass in NULL
- *          does not delay.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *          is not used in FBE mode, this parameter can be NULL. Passing NULL
+ *          does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to BLPI mode.
+ * @brief Sets the MCG to BLPI mode.
  *
- * This function sets MCG to BLPI mode. If could not set to BLPI mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
+ * from the current mode, this function returns an error.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetBlpiMode(void);
 
 /*!
- * @brief Set MCG to BLPE mode.
+ * @brief Sets the MCG to BLPE mode.
  *
- * This function sets MCG to BLPE mode. If could not set to BLPE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
+ * from the current mode, this function returns an error.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetBlpeMode(void);
 
 /*!
- * @brief Set MCG to PBE mode.
+ * @brief Sets the MCG to PBE mode.
  *
- * This function sets MCG to PBE mode. If could not set to PBE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to PBE mode. If setting to PBE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   pllcs  The PLL selection, PLLCS.
  * @param   config Pointer to the PLL configuration.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  *
  * @note
- * 1. The parameter \c pllcs selects the PLL, for some platforms, there is
- * only one PLL, the parameter pllcs is kept for interface compatible.
- * 2. The parameter \c config is the PLL configuration structure, on some
- * platforms, could choose the external PLL directly. This means that the
- * configuration structure is not necessary, pass in NULL for this case.
+ * 1. The parameter \c pllcs selects the PLL. For platforms with
+ * only one PLL, the parameter pllcs is kept for interface compatibility.
+ * 2. The parameter \c config is the PLL configuration structure. On some
+ * platforms,  it is possible to choose the external PLL directly, which renders the
+ * configuration structure not necessary. In this case, pass in NULL.
  * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
  */
 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
 
 /*!
- * @brief Set MCG to PEE mode.
+ * @brief Sets the MCG to PEE mode.
  *
- * This function sets MCG to PEE mode.
+ * This function sets the MCG to PEE mode.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  *
- * @note This function only change CLKS to use PLL/FLL output. If the
- *       PRDIV/VDIV are different from PBE mode, please setup these
- *       settings in PBE mode and wait for stable then switch to PEE mode.
+ * @note This function only changes the CLKS to use the PLL/FLL output. If the
+ *       PRDIV/VDIV are different than in the PBE mode, set them up
+ *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
  */
 status_t CLOCK_SetPeeMode(void);
 
 /*!
- * @brief Switch MCG to FBE mode quickly from external mode.
+ * @brief Switches the MCG to FBE mode from the external mode.
  *
- * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly.
- * It only changes to use external clock as the system clock souce and disable PLL, but does not
- * configure FLL settings. This is a lite function with small code size, it is useful
- * during mode switch. For example, to switch from PEE mode to FEI mode:
+ * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
+ * The external clock is used as the system clock souce and PLL is disabled. However,
+ * the FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEE mode to FEI mode:
  *
  * @code
  * CLOCK_ExternalModeToFbeModeQuick();
  * CLOCK_SetFeiMode(...);
  * @endcode
  *
- * @retval kStatus_Success Change successfully.
- * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function.
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
  */
 status_t CLOCK_ExternalModeToFbeModeQuick(void);
 
 /*!
- * @brief Switch MCG to FBI mode quickly from internal modes.
+ * @brief Switches the MCG to FBI mode from internal modes.
  *
- * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly.
- * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not
- * configure FLL settings. This is a lite function with small code size, it is useful
- * during mode switch. For example, to switch from PEI mode to FEE mode:
+ * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
+ * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
+ * FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEI mode to FEE mode:
  *
  * @code
  * CLOCK_InternalModeToFbiModeQuick();
  * CLOCK_SetFeeMode(...);
  * @endcode
  *
- * @retval kStatus_Success Change successfully.
- * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function.
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
  */
 status_t CLOCK_InternalModeToFbiModeQuick(void);
 
 /*!
- * @brief Set MCG to FEI mode during system boot up.
+ * @brief Sets the MCG to FEI mode during system boot up.
  *
- * This function sets MCG to FEI mode from reset mode, it could be used to
- * set up MCG during system boot up. @ref kMCG_Dmx32Default is used in this
- * mode because using kMCG_Dmx32Fine with internal reference clock source
- * might damage hardware.
+ * This function sets the MCG to FEI mode from the reset mode. It can also be used to
+ * set up MCG during system boot up.
  *
+ * @param  dmx32  DMX32 in FEI mode.
  * @param  drs The DCO range selection.
- * @param  fllStableDelay Delay function to make sure FLL is stable.
+ * @param  fllStableDelay Delay function to ensure that the FLL is stable.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
  */
-status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FEE mode during system bootup.
+ * @brief Sets the MCG to FEE mode during system bootup.
  *
- * This function sets MCG to FEE mode from reset mode, it could be used to
- * set up MCG during system boot up.
+ * This function sets MCG to FEE mode from the reset mode. It can also be used to
+ * set up the MCG during system boot up.
  *
  * @param   oscsel OSC clock select, OSCSEL.
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FEE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable.
+ * @param   fllStableDelay Delay function to ensure that the FLL is stable.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToFeeMode(
     mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to BLPI mode during system boot up.
+ * @brief Sets the MCG to BLPI mode during system boot up.
  *
- * This function sets MCG to BLPI mode from reset mode, it could be used to
- * setup MCG during sytem boot up.
+ * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
  *
  * @param  fcrdiv Fast IRC divider, FCRDIV.
  * @param  ircs   The internal reference clock to select, IRCS.
  * @param  ircEnableMode  The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
  *
  * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
 
 /*!
- * @brief Set MCG to BLPE mode during sytem boot up.
+ * @brief Sets the MCG to BLPE mode during sytem boot up.
  *
- * This function sets MCG to BLPE mode from reset mode, it could be used to
- * setup MCG during sytem boot up.
+ * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
  *
  * @param  oscsel OSC clock select, MCG_C7[OSCSEL].
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
 
 /*!
- * @brief Set MCG to PEE mode during system boot up.
+ * @brief Sets the MCG to PEE mode during system boot up.
  *
- * This function sets MCG to PEE mode from reset mode, it could be used to
- * setup MCG during system boot up.
+ * This function sets the MCG to PEE mode from reset mode. It can also be used to
+ * set up the MCG during system boot up.
  *
  * @param   oscsel OSC clock select, MCG_C7[OSCSEL].
  * @param   pllcs  The PLL selection, PLLCS.
  * @param   config Pointer to the PLL configuration.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
 
 /*!
- * @brief Set MCG to some target mode.
+ * @brief Sets the MCG to a target mode.
  *
- * This function sets MCG to some target mode defined by the configure
- * structure, if cannot switch to target mode directly, this function will
- * choose the proper path.
+ * This function sets MCG to a target mode defined by the configuration
+ * structure. If switching to the target mode fails, this function
+ * chooses the correct path.
  *
  * @param  config Pointer to the target MCG mode configuration structure.
- * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status.
+ * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
  *
- * @note If external clock is used in the target mode, please make sure it is
- * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before
- * this funciton.
+ * @note If the external clock is used in the target mode, ensure that it is
+ * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
+ * function.
  */
 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@
  ******************************************************************************/
 /*! @brief Pointers to CMP bases for each instance. */
 static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to CMP clocks for each instance. */
-const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
     {
         if (s_cmpBases[instance] == base)
         {
@@ -64,7 +66,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_CMP_COUNT);
+    assert(instance < ARRAY_SIZE(s_cmpBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@
 
     uint8_t tmp8;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     CMP_Enable(base, false); /* Disable the CMP module during configuring. */
@@ -123,8 +127,10 @@
     /* Disable the CMP module. */
     CMP_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void CMP_GetDefaultConfig(cmp_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -64,8 +63,8 @@
  */
 enum _cmp_status_flags
 {
-    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on compare output has occurred. */
-    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */
+    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
+    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
     kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
 };
 
@@ -85,20 +84,20 @@
  */
 typedef enum _cmp_reference_voltage_source
 {
-    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */
-    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */
 } cmp_reference_voltage_source_t;
 
 /*!
- * @brief Configure the comparator.
+ * @brief Configures the comparator.
  */
 typedef struct _cmp_config
 {
     bool enableCmp;                       /*!< Enable the CMP module. */
     cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
-    bool enableHighSpeed;                 /*!< Enable High Speed (HS) comparison mode. */
-    bool enableInvertOutput;              /*!< Enable inverted comparator output. */
-    bool useUnfilteredOutput;             /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */
+    bool enableHighSpeed;                 /*!< Enable High-speed (HS) comparison mode. */
+    bool enableInvertOutput;              /*!< Enable the inverted comparator output. */
+    bool useUnfilteredOutput;             /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */
     bool enablePinOut;                    /*!< The comparator output is available on the associated pin. */
 #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
     bool enableTriggerMode; /*!< Enable the trigger mode. */
@@ -106,24 +105,24 @@
 } cmp_config_t;
 
 /*!
- * @brief Configure the filter.
+ * @brief Configures the filter.
  */
 typedef struct _cmp_filter_config
 {
 #if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
-    bool enableSample;    /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */
+    bool enableSample;    /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */
 #endif                    /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
-    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/
-    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */
+    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/
+    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */
 } cmp_filter_config_t;
 
 /*!
- * @brief Configure the internal DAC.
+ * @brief Configures the internal DAC.
  */
 typedef struct _cmp_dac_config
 {
     cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
-    uint8_t DACValue;                                      /*!< Value for DAC Output Voltage. Available range is 0-63.*/
+    uint8_t DACValue;                                      /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
 } cmp_dac_config_t;
 
 #if defined(__cplusplus)
@@ -142,28 +141,28 @@
 /*!
  * @brief Initializes the CMP.
  *
- * This function initializes the CMP module. The operations included are:
+ * This function initializes the CMP module. The operations included are as follows.
  * - Enabling the clock for CMP module.
  * - Configuring the comparator.
  * - Enabling the CMP module.
- * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for
- * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
  *
  * @param base   CMP peripheral base address.
- * @param config Pointer to configuration structure.
+ * @param config Pointer to the configuration structure.
  */
 void CMP_Init(CMP_Type *base, const cmp_config_t *config);
 
 /*!
  * @brief De-initializes the CMP module.
  *
- * This function de-initializes the CMP module. The operations included are:
+ * This function de-initializes the CMP module. The operations included are as follows.
  * - Disabling the CMP module.
  * - Disabling the clock for CMP module.
  *
  * This function disables the clock for the CMP.
- * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the
- * clock for the CMP,  ensure that all the CMP instances are not used.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
  *
  * @param base CMP peripheral base address.
  */
@@ -173,7 +172,7 @@
  * @brief Enables/disables the CMP module.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the module or not.
+ * @param enable Enables or disables the module.
  */
 static inline void CMP_Enable(CMP_Type *base, bool enable)
 {
@@ -190,7 +189,7 @@
 /*!
 * @brief Initializes the CMP user configuration structure.
 *
-* This function initializes the user configure structure to these default values:
+* This function initializes the user configuration structure to these default values.
 * @code
 *   config->enableCmp           = true;
 *   config->hysteresisMode      = kCMP_HysteresisLevel0;
@@ -208,7 +207,7 @@
  * @brief  Sets the input channels for the comparator.
  *
  * This function sets the input channels for the comparator.
- * Note that two input channels cannot be set as same in the application. When the user selects the same input
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
  * from the analog mux to the positive and negative port, the comparator is disabled automatically.
  *
  * @param  base            CMP peripheral base address.
@@ -229,13 +228,11 @@
  * @brief Enables/disables the DMA request for rising/falling events.
  *
  * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
- * the DMA
- * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
- * if the
- * DMA is disabled.
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
+ * if the DMA is disabled.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 void CMP_EnableDMA(CMP_Type *base, bool enable);
 #endif /* FSL_FEATURE_CMP_HAS_DMA */
@@ -245,7 +242,7 @@
  * @brief Enables/disables the window mode.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
 {
@@ -265,7 +262,7 @@
  * @brief Enables/disables the pass through mode.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
 {
@@ -284,7 +281,7 @@
  * @brief  Configures the filter.
  *
  * @param  base   CMP peripheral base address.
- * @param  config Pointer to configuration structure.
+ * @param  config Pointer to the configuration structure.
  */
 void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
 
@@ -292,7 +289,7 @@
  * @brief Configures the internal DAC.
  *
  * @param base   CMP peripheral base address.
- * @param config Pointer to configuration structure. "NULL" is for disabling the feature.
+ * @param config Pointer to the configuration structure. "NULL" disables the feature.
  */
 void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -46,8 +46,6 @@
 #define CMT_CMTDIV_FOUR (4)
 /* CMT diver 8. */
 #define CMT_CMTDIV_EIGHT (8)
-/* CMT mode bit mask. */
-#define CMT_MODE_BIT_MASK (CMT_MSC_MCGEN_MASK | CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK)
 
 /*******************************************************************************
  * Prototypes
@@ -64,14 +62,16 @@
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to cmt clocks for each instance. */
-const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
+static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to cmt bases for each instance. */
 static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
 
 /*! @brief Pointers to cmt IRQ number for each instance. */
-const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
+static const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
 
 /*******************************************************************************
  * Codes
@@ -82,7 +82,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++)
     {
         if (s_cmtBases[instance] == base)
         {
@@ -90,7 +90,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_CMT_COUNT);
+    assert(instance < ARRAY_SIZE(s_cmtBases));
 
     return instance;
 }
@@ -113,8 +113,10 @@
 
     uint8_t divider;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock. */
     CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Sets clock divider. The divider set in pps should be set
        to make sycClock_Hz/divder = 8MHz */
@@ -144,15 +146,17 @@
     CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
     DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the clock. */
     CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
 {
-    uint8_t mscReg;
+    uint8_t mscReg = base->MSC;
 
-    /* Set the mode. */
+    /* Judge the mode. */
     if (mode != kCMT_DirectIROCtl)
     {
         assert(modulateConfig);
@@ -166,13 +170,14 @@
 
         /* Set carrier modulator. */
         CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
+        mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK);
+        mscReg |= mode;
     }
-
+    else
+    {
+        mscReg &= ~CMT_MSC_MCGEN_MASK;
+    }
     /* Set the CMT mode. */
-    mscReg = base->MSC;
-    mscReg &= ~CMT_MODE_BIT_MASK;
-    mscReg |= mode;
-
     base->MSC = mscReg;
 }
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CMT driver version 2.0.0. */
-#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CMT driver version 2.0.1. */
+#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -128,15 +127,15 @@
 };
 
 /*!
- * @brief CMT carrier generator and modulator configure structure
+ * @brief CMT carrier generator and modulator configuration structure
  *
  */
 typedef struct _cmt_modulate_config
 {
-    uint8_t highCount1;  /*!< The high time for carrier generator first register. */
-    uint8_t lowCount1;   /*!< The low time for carrier generator first register. */
-    uint8_t highCount2;  /*!< The high time for carrier generator second register for FSK mode. */
-    uint8_t lowCount2;   /*!< The low time for carrier generator second register for FSK mode. */
+    uint8_t highCount1;  /*!< The high-time for carrier generator first register. */
+    uint8_t lowCount1;   /*!< The low-time for carrier generator first register. */
+    uint8_t highCount2;  /*!< The high-time for carrier generator second register for FSK mode. */
+    uint8_t lowCount2;   /*!< The low-time for carrier generator second register for FSK mode. */
     uint16_t markCount;  /*!< The mark time for the modulator gate. */
     uint16_t spaceCount; /*!< The space time for the modulator gate. */
 } cmt_modulate_config_t;
@@ -164,10 +163,10 @@
  */
 
 /*!
- * @brief Gets the CMT default configuration structure. The purpose
- * of this API is to get the default configuration structure for the CMT_Init().
- * Use the initialized structure unchanged in CMT_Init(), or modify
- * some fields of the structure before calling the CMT_Init().
+ * @brief Gets the CMT default configuration structure. This API
+ * gets the default configuration structure for the CMT_Init().
+ * Use the initialized structure unchanged in CMT_Init() or modify
+ * fields of the structure before calling the CMT_Init().
  *
  * @param config The CMT configuration structure pointer.
  */
@@ -216,7 +215,7 @@
  *
  * @param base   CMT peripheral base address.
  * @return The CMT mode.
- *     kCMT_DirectIROCtl     Carrier modulator is disabled, the IRO signal is directly in software control.
+ *     kCMT_DirectIROCtl     Carrier modulator is disabled; the IRO signal is directly in software control.
  *     kCMT_TimeMode         Carrier modulator is enabled in time mode.
  *     kCMT_FSKMode          Carrier modulator is enabled in FSK mode.
  *     kCMT_BasebandMode     Carrier modulator is enabled in baseband mode.
@@ -235,11 +234,11 @@
 /*!
  * @brief Sets the primary data set for the CMT carrier generator counter.
  *
- * This function sets the high time and low time of the primary data set for the
+ * This function sets the high-time and low-time of the primary data set for the
  * CMT carrier generator counter to control the period and the duty cycle of the
  * output carrier signal.
- * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
- * (highCount + lowCount) * Tcmt. The duty cycle equals  highCount / (highCount + lowCount).
+ * If the CMT clock period is Tcmt, the period of the carrier generator signal equals
+ * (highCount + lowCount) * Tcmt. The duty cycle equals to highCount / (highCount + lowCount).
  *
  * @param base      CMT peripheral base address.
  * @param highCount The number of CMT clocks for carrier generator signal high time,
@@ -261,10 +260,10 @@
 /*!
  * @brief Sets the secondary data set for the CMT carrier generator counter.
  *
- * This function is used for FSK mode setting the high time and low time of the secondary
+ * This function is used for FSK mode setting the high-time and low-time of the secondary
  * data set CMT carrier generator counter to control the period and the duty cycle
  * of the output carrier signal.
- * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
+ * If the CMT clock period is Tcmt, the period of the carrier generator signal equals
  * (highCount + lowCount) * Tcmt. The duty cycle equals  highCount / (highCount + lowCount).
  *
  * @param base      CMT peripheral base address.
@@ -325,7 +324,7 @@
 }
 
 /*!
- * @brief Sets IRO - infrared output signal state.
+ * @brief Sets the IRO (infrared output) signal state.
  *
  * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set
  * and the IRO signal is enabled.
@@ -338,12 +337,12 @@
 /*!
  * @brief Enables the CMT interrupt.
  *
- * This function enables the CMT interrupts according to the provided maskIf enabled.
+ * This function enables the CMT interrupts according to the provided mask if enabled.
  * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end
  * of the modulator cycle. This interrupt provides a means for the user
  * to reload the new mark/space values into the CMT modulator data registers
  * and verify the modulator mark and space.
- * For example, to enable the end of cycle, do the following:
+ * For example, to enable the end of cycle, do the following.
  * @code
  *     CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
  * @endcode
@@ -360,7 +359,7 @@
  *
  * This function disables the CMT interrupts according to the provided maskIf enabled.
  * The CMT only has the end of the cycle interrupt.
- * For example, to disable the end of cycle, do the following:
+ * For example, to disable the end of cycle, do the following.
  * @code
  *     CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
  * @endcode

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,8 +34,12 @@
 #include <assert.h>
 #include <stdbool.h>
 #include <stdint.h>
+#include <string.h>
+
+#if defined(__ICCARM__)
 #include <stddef.h>
-#include <string.h>
+#endif
+
 #include "fsl_device_registers.h"
 
 /*!
@@ -43,8 +47,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -56,11 +58,13 @@
 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
 
 /* Debug console type definition. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U   /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U   /*!< Debug console base on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U  /*!< Debug console base on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -87,6 +91,11 @@
     kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
     kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
     kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
     kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
     kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
     kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
@@ -101,6 +110,18 @@
     kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
     kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
     kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
     kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
     kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
     kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
@@ -127,6 +148,14 @@
  */
 #include "fsl_clock.h"
 
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
 /*! @name Min/max macros */
 /* @{ */
 #if !defined(MIN)
@@ -182,11 +211,20 @@
  */
 static inline void EnableIRQ(IRQn_Type interrupt)
 {
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
 #if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
     if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
 #endif
     {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
         NVIC_EnableIRQ(interrupt);
+#endif
     }
 }
 
@@ -199,11 +237,20 @@
  */
 static inline void DisableIRQ(IRQn_Type interrupt)
 {
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
 #if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
     if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
 #endif
     {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
         NVIC_DisableIRQ(interrupt);
+#endif
     }
 }
 
@@ -217,11 +264,19 @@
  */
 static inline uint32_t DisableGlobalIRQ(void)
 {
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
     uint32_t regPrimask = __get_PRIMASK();
 
     __disable_irq();
 
     return regPrimask;
+#endif
 }
 
 /*!
@@ -236,7 +291,11 @@
  */
 static inline void EnableGlobalIRQ(uint32_t primask)
 {
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
     __set_PRIMASK(primask);
+#endif
 }
 
 /*!
@@ -244,9 +303,42 @@
  *
  * @param irq IRQ number
  * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
  */
 void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
 
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
 #if defined(__cplusplus)
 }
 #endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -32,6 +32,11 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+/*! @internal @brief Has data register with name CRC. */
+#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
+#define DATA CRC
+#define DATALL CRCLL
+#endif
 
 #if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
 /* @brief Default user configuration structure for CRC-16-CCITT */
@@ -87,7 +92,7 @@
  *
  * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
  */
-static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable)
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable)
 {
     return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
 }
@@ -99,7 +104,7 @@
  *
  * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
  */
-static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable)
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable)
 {
     return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
 }
@@ -113,7 +118,7 @@
  * @param base CRC peripheral address.
  * @param config Pointer to protocol configuration structure.
  */
-static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
+static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
 {
     uint32_t crcControl;
 
@@ -148,18 +153,18 @@
  * @param base CRC peripheral address.
  * @param protocolConfig Pointer to protocol configuration structure.
  */
-static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
 {
     crc_module_config_t moduleConfig;
     /* convert protocol to CRC peripheral module configuration, prepare for final checksum */
     moduleConfig.polynomial = protocolConfig->polynomial;
     moduleConfig.seed = protocolConfig->seed;
-    moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
-    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
+    moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
     moduleConfig.complementChecksum = protocolConfig->complementChecksum;
     moduleConfig.crcBits = protocolConfig->crcBits;
 
-    crc_ConfigureAndStart(base, &moduleConfig);
+    CRC_ConfigureAndStart(base, &moduleConfig);
 }
 
 /*!
@@ -172,7 +177,7 @@
  * @param base CRC peripheral address.
  * @param protocolConfig Pointer to protocol configuration structure.
  */
-static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
 {
     crc_module_config_t moduleConfig;
     /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
@@ -180,25 +185,27 @@
     moduleConfig.seed = protocolConfig->seed;
     moduleConfig.readTranspose =
         kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
-    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
     moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
     moduleConfig.crcBits = protocolConfig->crcBits;
 
-    crc_ConfigureAndStart(base, &moduleConfig);
+    CRC_ConfigureAndStart(base, &moduleConfig);
 }
 
 void CRC_Init(CRC_Type *base, const crc_config_t *config)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* ungate clock */
     CLOCK_EnableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* configure CRC module and write the seed */
     if (config->crcResult == kCrcFinalChecksum)
     {
-        crc_SetProtocolConfig(base, config);
+        CRC_SetProtocolConfig(base, config);
     }
     else
     {
-        crc_SetRawProtocolConfig(base, config);
+        CRC_SetRawProtocolConfig(base, config);
     }
 }
 
@@ -246,6 +253,11 @@
     }
 }
 
+uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->DATA;
+}
+
 uint16_t CRC_Get16bitResult(CRC_Type *base)
 {
     uint32_t retval;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,28 +34,27 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup crc_driver
+ * @addtogroup crc
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CRC driver version. Version 2.0.0. */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CRC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.1
+ *   - move DATA and DATALL macro definition from header file to source file
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-/*! @internal @brief Has data register with name CRC. */
-#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
-#define DATA CRC
-#define DATALL CRCLL
-#endif
-
 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
 /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
 #define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
@@ -108,31 +107,33 @@
 /*!
  * @brief Enables and configures the CRC peripheral module.
  *
- * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral.
- * It also configures the CRC module and starts checksum computation by writing the seed.
+ * This function enables the clock gate in the SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts a checksum computation by writing the seed.
  *
  * @param base CRC peripheral address.
- * @param config CRC module configuration structure
+ * @param config CRC module configuration structure.
  */
 void CRC_Init(CRC_Type *base, const crc_config_t *config);
 
 /*!
  * @brief Disables the CRC peripheral module.
  *
- * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ * This function disables the clock gate in the SIM module for the CRC peripheral.
  *
  * @param base CRC peripheral address.
  */
 static inline void CRC_Deinit(CRC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* gate clock */
     CLOCK_DisableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!
- * @brief Loads default values to CRC protocol configuration structure.
+ * @brief Loads default values to the CRC protocol configuration structure.
  *
- * Loads default values to CRC protocol configuration structure. The default values are:
+ * Loads default values to the CRC protocol configuration structure. The default values are as follows.
  * @code
  *   config->polynomial = 0x1021;
  *   config->seed = 0xFFFF;
@@ -143,14 +144,14 @@
  *   config->crcResult = kCrcFinalChecksum;
  * @endcode
  *
- * @param config CRC protocol configuration structure
+ * @param config CRC protocol configuration structure.
  */
 void CRC_GetDefaultConfig(crc_config_t *config);
 
 /*!
  * @brief Writes data to the CRC module.
  *
- * Writes input data buffer bytes to CRC data register.
+ * Writes input data buffer bytes to the CRC data register.
  * The configured type of transpose is applied.
  *
  * @param base CRC peripheral address.
@@ -160,27 +161,24 @@
 void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
 
 /*!
- * @brief Reads 32-bit checksum from the CRC module.
+ * @brief Reads the 32-bit checksum from the CRC module.
  *
- * Reads CRC data register (intermediate or final checksum).
- * The configured type of transpose and complement are applied.
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
  *
  * @param base CRC peripheral address.
- * @return intermediate or final 32-bit checksum, after configured transpose and complement operations.
+ * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
  */
-static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
-{
-    return base->DATA;
-}
+uint32_t CRC_Get32bitResult(CRC_Type *base);
 
 /*!
- * @brief Reads 16-bit checksum from the CRC module.
+ * @brief Reads a 16-bit checksum from the CRC module.
  *
- * Reads CRC data register (intermediate or final checksum).
- * The configured type of transpose and complement are applied.
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
  *
  * @param base CRC peripheral address.
- * @return intermediate or final 16-bit checksum, after configured transpose and complement operations.
+ * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
  */
 uint16_t CRC_Get16bitResult(CRC_Type *base);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@
  ******************************************************************************/
 /*! @brief Pointers to DAC bases for each instance. */
 static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to DAC clocks for each instance. */
-const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
     {
         if (s_dacBases[instance] == base)
         {
@@ -64,7 +66,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DAC_COUNT);
+    assert(instance < ARRAY_SIZE(s_dacBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@
 
     uint8_t tmp8;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     /* DACx_C0. */
@@ -91,15 +95,18 @@
     }
     base->C0 = tmp8;
 
-    DAC_Enable(base, true);
+    /* DAC_Enable(base, true); */
+    /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
 }
 
 void DAC_Deinit(DAC_Type *base)
 {
     DAC_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void DAC_GetDefaultConfig(dac_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,8 +45,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DAC driver version 2.0.0. */
-#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief DAC driver version 2.0.1. */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -104,15 +103,15 @@
 #if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD
     kDAC_BufferWatermark1Word = 0U, /*!< 1 word  away from the upper limit. */
 #endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS
     kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS
     kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS
     kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */
 } dac_buffer_watermark_t;
 #endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
 
@@ -137,7 +136,7 @@
 typedef struct _dac_config
 {
     dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */
-    bool enableLowPowerMode;                               /*!< Enable the low power mode. */
+    bool enableLowPowerMode;                               /*!< Enable the low-power mode. */
 } dac_config_t;
 
 /*!
@@ -150,8 +149,8 @@
     dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */
 #endif                                /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
     dac_buffer_work_mode_t workMode;  /*!< Select the buffer's work mode. */
-    uint8_t upperLimit;               /*!< Set the upper limit for buffer index.
-                                           Normally, 0-15 is available for buffer with 16 item. */
+    uint8_t upperLimit;               /*!< Set the upper limit for the buffer index.
+                                           Normally, 0-15 is available for a buffer with 16 items. */
 } dac_buffer_config_t;
 
 /*******************************************************************************
@@ -169,7 +168,7 @@
 /*!
  * @brief Initializes the DAC module.
  *
- * This function initializes the DAC module, including:
+ * This function initializes the DAC module including the following operations.
  *  - Enabling the clock for DAC module.
  *  - Configuring the DAC converter with a user configuration.
  *  - Enabling the DAC module.
@@ -182,7 +181,7 @@
 /*!
  * @brief De-initializes the DAC module.
  *
- * This function de-initializes the DAC module, including:
+ * This function de-initializes the DAC module including the following operations.
  *  - Disabling the DAC module.
  *  - Disabling the clock for the DAC module.
  *
@@ -193,7 +192,7 @@
 /*!
  * @brief Initializes the DAC user configuration structure.
  *
- * This function initializes the user configuration structure to a default value. The default values are:
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
  * @code
  *   config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
  *   config->enableLowPowerMode = false;
@@ -206,7 +205,7 @@
  * @brief Enables the DAC module.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_Enable(DAC_Type *base, bool enable)
 {
@@ -231,7 +230,7 @@
  * @brief Enables the DAC buffer.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_EnableBuffer(DAC_Type *base, bool enable)
 {
@@ -256,7 +255,7 @@
 /*!
  * @brief Initializes the DAC buffer configuration structure.
  *
- * This function initializes the DAC buffer configuration structure to a default value. The default values are:
+ * This function initializes the DAC buffer configuration structure to default values. The default values are as follows.
  * @code
  *   config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
  *   config->watermark   = kDAC_BufferWatermark1Word;
@@ -271,7 +270,7 @@
  * @brief Enables the DMA for DAC buffer.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
 {
@@ -289,15 +288,15 @@
  * @brief Sets the value for  items in the buffer.
  *
  * @param base  DAC peripheral base address.
- * @param index Setting index for items in the buffer. The available index should not exceed the size of the DAC buffer.
- * @param value Setting value for items in the buffer. 12-bits are available.
+ * @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC buffer.
+ * @param value Setting the value for items in the buffer. 12-bits are available.
  */
 void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value);
 
 /*!
- * @brief Triggers the buffer by software and updates the read pointer of the DAC buffer.
+ * @brief Triggers the buffer using software and updates the read pointer of the DAC buffer.
  *
- * This function triggers the function by software. The read pointer of the DAC buffer is updated with one step
+ * This function triggers the function using software. The read pointer of the DAC buffer is updated with one step
  * after this function is called. Changing the read pointer depends on the buffer's work mode.
  *
  * @param base DAC peripheral base address.
@@ -311,12 +310,12 @@
  * @brief Gets the current read pointer of the DAC buffer.
  *
  * This function gets the current read pointer of the DAC buffer.
- * The current output value depends on the item indexed by the read pointer. It is updated
- * by software trigger or hardware trigger.
+ * The current output value depends on the item indexed by the read pointer. It is updated either
+ * by a software trigger or a hardware trigger.
  *
  * @param  base DAC peripheral base address.
  *
- * @return      Current read pointer of DAC buffer.
+ * @return      The current read pointer of the DAC buffer.
  */
 static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
 {
@@ -327,11 +326,11 @@
  * @brief Sets the current read pointer of the DAC buffer.
  *
  * This function sets the current read pointer of the DAC buffer.
- * The current output value depends on the item indexed by the read pointer. It is updated by
- * software trigger or hardware trigger. After the read pointer changes, the DAC output value also changes.
+ * The current output value depends on the item indexed by the read pointer. It is updated either by a
+ * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
  *
  * @param base  DAC peripheral base address.
- * @param index Setting index value for the pointer.
+ * @param index Setting an index value for the pointer.
  */
 void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -52,8 +52,10 @@
 /*! @brief Array to map DMAMUX instance number to base pointer. */
 static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map DMAMUX instance number to clock name. */
 static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -63,7 +65,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
     {
         if (s_dmamuxBases[instance] == base)
         {
@@ -71,17 +73,21 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT);
+    assert(instance < ARRAY_SIZE(s_dmamuxBases));
 
     return instance;
 }
 
 void DMAMUX_Init(DMAMUX_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void DMAMUX_Deinit(DMAMUX_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,8 +45,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DMAMUX driver version 2.0.0. */
-#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief DMAMUX driver version 2.0.2. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*******************************************************************************
@@ -59,14 +58,14 @@
 #endif /* __cplusplus */
 
 /*!
- * @name DMAMUX Initialize and De-initialize
+ * @name DMAMUX Initialization and de-initialization
  * @{
  */
 
 /*!
- * @brief Initializes DMAMUX peripheral.
+ * @brief Initializes the DMAMUX peripheral.
  *
- * This function ungate the DMAMUX clock.
+ * This function ungates the DMAMUX clock.
  *
  * @param base DMAMUX peripheral base address.
  *
@@ -74,9 +73,9 @@
 void DMAMUX_Init(DMAMUX_Type *base);
 
 /*!
- * @brief Deinitializes DMAMUX peripheral.
+ * @brief Deinitializes the DMAMUX peripheral.
  *
- * This function gate the DMAMUX clock.
+ * This function gates the DMAMUX clock.
  *
  * @param base DMAMUX peripheral base address.
  */
@@ -89,9 +88,9 @@
  */
 
 /*!
- * @brief Enable DMAMUX channel.
+ * @brief Enables the DMAMUX channel.
  *
- * This function enable DMAMUX channel to work.
+ * This function enables the DMAMUX channel.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -104,11 +103,11 @@
 }
 
 /*!
- * @brief Disable DMAMUX channel.
+ * @brief Disables the DMAMUX channel.
  *
- * This function disable DMAMUX channel.
+ * This function disables the DMAMUX channel.
  *
- * @note User must disable DMAMUX channel before configure it.
+ * @note The user must disable the DMAMUX channel before configuring it.
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
  */
@@ -120,13 +119,13 @@
 }
 
 /*!
- * @brief Configure DMAMUX channel source.
+ * @brief Configures the DMAMUX channel source.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
- * @param source Channel source which is used to trigger DMA transfer.
+ * @param source Channel source, which is used to trigger the DMA transfer.
  */
-static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
+static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
 {
     assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
@@ -135,9 +134,9 @@
 
 #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
 /*!
- * @brief Enable DMAMUX period trigger.
+ * @brief Enables the DMAMUX period trigger.
  *
- * This function enable DMAMUX period trigger feature.
+ * This function enables the DMAMUX period trigger feature.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -150,9 +149,9 @@
 }
 
 /*!
- * @brief Disable DMAMUX period trigger.
+ * @brief Disables the DMAMUX period trigger.
  *
- * This function disable DMAMUX period trigger.
+ * This function disables the DMAMUX period trigger.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -165,6 +164,31 @@
 }
 #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
 
+#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
+/*!
+ * @brief Enables the DMA channel to be always ON.
+ *
+ * This function enables the DMAMUX channel always ON feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
+ */
+static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    if (enable)
+    {
+        base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
+    }
+    else
+    {
+        base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
+    }
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
+
 /* @} */
 
 #if defined(__cplusplus)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi.h"
 
@@ -65,27 +65,27 @@
 
 /*!
  * @brief Master fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Master finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Slave fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle);
 
 /*!
  * @brief Slave finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle);
 
@@ -100,7 +100,7 @@
 /*!
  * @brief Master prepare the transfer.
  * Basically it set up dspi_master_handle .
- * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
 
@@ -123,11 +123,13 @@
 /*! @brief Pointers to dspi IRQ number for each instance. */
 static IRQn_Type const s_dspiIRQ[] = SPI_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to dspi clocks for each instance. */
 static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to dspi handles for each instance. */
-static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)];
 
 /*! @brief Pointer to master IRQ handler for each instance. */
 static dspi_master_isr_t s_dspiMasterIsr;
@@ -135,6 +137,8 @@
 /*! @brief Pointer to slave IRQ handler for each instance. */
 static dspi_slave_isr_t s_dspiSlaveIsr;
 
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t s_dummyData[ARRAY_SIZE(s_dspiBases)] = {0};
 /**********************************************************************************************************************
 * Code
 *********************************************************************************************************************/
@@ -143,7 +147,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++)
     {
         if (s_dspiBases[instance] == base)
         {
@@ -151,16 +155,26 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DSPI_COUNT);
+    assert(instance < ARRAY_SIZE(s_dspiBases));
 
     return instance;
 }
 
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+    uint32_t instance = DSPI_GetInstance(base);
+    s_dummyData[instance] = dummyData;
+}
+
 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
+    assert(masterConfig);
+
     uint32_t temp;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* enable DSPI clock */
     CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     DSPI_Enable(base, true);
     DSPI_StopTransfer(base);
@@ -196,11 +210,14 @@
     DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz,
                              masterConfig->ctarConfig.betweenTransferDelayInNanoSec);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
     DSPI_StartTransfer(base);
 }
 
 void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)
 {
+    assert(masterConfig);
+
     masterConfig->whichCtar = kDSPI_Ctar0;
     masterConfig->ctarConfig.baudRate = 500000;
     masterConfig->ctarConfig.bitsPerFrame = 8;
@@ -223,10 +240,14 @@
 
 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
 {
+    assert(slaveConfig);
+
     uint32_t temp = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* enable DSPI clock */
     CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     DSPI_Enable(base, true);
     DSPI_StopTransfer(base);
@@ -250,11 +271,15 @@
                                          SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) |
                                          SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
+
     DSPI_StartTransfer(base);
 }
 
 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig)
 {
+    assert(slaveConfig);
+
     slaveConfig->whichCtar = kDSPI_Ctar0;
     slaveConfig->ctarConfig.bitsPerFrame = 8;
     slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
@@ -271,8 +296,10 @@
     DSPI_StopTransfer(base);
     DSPI_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* disable DSPI clock */
     CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh)
@@ -457,6 +484,8 @@
 
 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command)
 {
+    assert(command);
+
     command->isPcsContinuous = false;
     command->whichCtar = kDSPI_Ctar0;
     command->whichPcs = kDSPI_Pcs0;
@@ -466,6 +495,8 @@
 
 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
 {
+    assert(command);
+
     /* First, clear Transmit Complete Flag (TCF) */
     DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag);
 
@@ -562,7 +593,7 @@
 
     uint16_t wordToSend = 0;
     uint16_t wordReceived = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
     uint8_t bitsPerFrame;
 
     uint32_t command;
@@ -598,6 +629,7 @@
 
     command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -626,25 +658,6 @@
         {
             if (remainingSendByteCount == 1)
             {
-                while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize)
-                {
-                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
-                    {
-                        if (rxData != NULL)
-                        {
-                            *(rxData) = DSPI_ReadData(base);
-                            rxData++;
-                        }
-                        else
-                        {
-                            DSPI_ReadData(base);
-                        }
-                        remainingReceiveByteCount--;
-
-                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
-                    }
-                }
-
                 while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
                 {
                     DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
@@ -702,20 +715,23 @@
 
                 DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
 
-                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize)
                 {
-                    if (rxData != NULL)
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
                     {
-                        *(rxData) = DSPI_ReadData(base);
-                        rxData++;
+                        if (rxData != NULL)
+                        {
+                            *(rxData) = DSPI_ReadData(base);
+                            rxData++;
+                        }
+                        else
+                        {
+                            DSPI_ReadData(base);
+                        }
+                        remainingReceiveByteCount--;
+
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
                     }
-                    else
-                    {
-                        DSPI_ReadData(base);
-                    }
-                    remainingReceiveByteCount--;
-
-                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
                 }
             }
         }
@@ -726,25 +742,6 @@
         {
             if (remainingSendByteCount <= 2)
             {
-                while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize)
-                {
-                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
-                    {
-                        wordReceived = DSPI_ReadData(base);
-
-                        if (rxData != NULL)
-                        {
-                            *rxData = wordReceived;
-                            ++rxData;
-                            *rxData = wordReceived >> 8;
-                            ++rxData;
-                        }
-                        remainingReceiveByteCount -= 2;
-
-                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
-                    }
-                }
-
                 while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
                 {
                     DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
@@ -825,20 +822,23 @@
 
                 DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
 
-                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize)
                 {
-                    wordReceived = DSPI_ReadData(base);
-
-                    if (rxData != NULL)
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
                     {
-                        *rxData = wordReceived;
-                        ++rxData;
-                        *rxData = wordReceived >> 8;
-                        ++rxData;
+                        wordReceived = DSPI_ReadData(base);
+
+                        if (rxData != NULL)
+                        {
+                            *rxData = wordReceived;
+                            ++rxData;
+                            *rxData = wordReceived >> 8;
+                            ++rxData;
+                        }
+                        remainingReceiveByteCount -= 2;
+
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
                     }
-                    remainingReceiveByteCount -= 2;
-
-                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
                 }
             }
         }
@@ -849,6 +849,9 @@
 
 static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
 {
+    assert(handle);
+    assert(transfer);
+
     dspi_command_data_config_t commandStruct;
 
     DSPI_StopTransfer(base);
@@ -864,6 +867,7 @@
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
     handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -886,7 +890,8 @@
 
 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If the transfer count is zero, then return immediately.*/
     if (transfer->dataSize == 0)
@@ -903,13 +908,10 @@
     handle->state = kDSPI_Busy;
 
     DSPI_MasterTransferPrepare(base, handle, transfer);
-    DSPI_StartTransfer(base);
 
     /* Enable the NVIC for DSPI peripheral. */
     EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
 
-    DSPI_MasterTransferFillUpTxFifo(base, handle);
-
     /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
     * Since SPI is a synchronous interface, we only need to enable the RX interrupt.
     * The IRQ handler will get the status of RX and TX interrupt flags.
@@ -917,7 +919,10 @@
     s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ;
 
     DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+    DSPI_StartTransfer(base);
 
+    /* Fill up the Tx FIFO to trigger the transfer. */
+    DSPI_MasterTransferFillUpTxFifo(base, handle);
     return kStatus_Success;
 }
 
@@ -943,6 +948,8 @@
 
 static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     /* Disable interrupt requests*/
     DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable);
 
@@ -956,19 +963,20 @@
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    /* The transfer is complete.*/
-    handle->state = kDSPI_Idle;
 }
 
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
 
     /* If bits/frame is greater than one byte */
     if (handle->bitsPerFrame > 8)
@@ -1081,6 +1089,8 @@
 
 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     /* Disable interrupt requests*/
@@ -1091,6 +1101,8 @@
 
 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */
     if (handle->remainingReceiveByteCount)
     {
@@ -1212,7 +1224,8 @@
 
 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If receive length is zero */
     if (transfer->dataSize == 0)
@@ -1254,11 +1267,6 @@
     DSPI_FlushFifo(base, true, true);
     DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
 
-    DSPI_StartTransfer(base);
-
-    /* Prepare data to transmit */
-    DSPI_SlaveTransferFillUpTxFifo(base, handle);
-
     s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ;
 
     /* Enable RX FIFO drain request, the slave only use this interrupt */
@@ -1275,6 +1283,11 @@
         DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable);
     }
 
+    DSPI_StartTransfer(base);
+
+    /* Prepare data to transmit */
+    DSPI_SlaveTransferFillUpTxFifo(base, handle);
+
     return kStatus_Success;
 }
 
@@ -1300,8 +1313,10 @@
 
 static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     uint16_t transmitData = 0;
-    uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA;
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
 
     /* Service the transmitter, if transmit buffer provided, transmit the data,
     * else transmit dummy pattern
@@ -1386,6 +1401,8 @@
 
 static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     /* Disable interrupt requests */
     DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable |
                                      kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable);
@@ -1406,16 +1423,18 @@
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     /* Disable interrupt requests */
@@ -1429,7 +1448,9 @@
 
 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle)
 {
-    uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA;
+    assert(handle);
+
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
     uint32_t dataReceived;
     uint32_t dataSend = 0;
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,27 +33,24 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup dspi
+ * @addtogroup dspi_driver
  * @{
  */
 
-/*! @file */
-
 /**********************************************************************************************************************
  * Definitions
  *********************************************************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DSPI driver version 2.1.0. */
-#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief DSPI driver version 2.2.0. */
+#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
-/*! @name Dummy data */
-/*@{*/
-#define DSPI_MASTER_DUMMY_DATA (0x00U) /*!< Master dummy data used for tx if there is not txData. */
-#define DSPI_SLAVE_DUMMY_DATA (0x00U)  /*!< Slave dummy data used for tx if there is not txData. */
-/*@}*/
+#ifndef DSPI_DUMMY_DATA
+/*! @brief DSPI dummy data if there is no Tx data.*/
+#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */
+#endif
 
 /*! @brief Status for the DSPI driver.*/
 enum _dspi_status
@@ -61,7 +58,7 @@
     kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0),      /*!< DSPI transfer is busy.*/
     kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1),     /*!< DSPI driver error. */
     kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2),      /*!< DSPI is idle.*/
-    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */
+    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */
 };
 
 /*! @brief DSPI status flags in SPIx_SR register.*/
@@ -75,7 +72,7 @@
     kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
     kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK,     /*!< The module is in Stopped/Running state.*/
     kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
-                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/
+                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/
 };
 
 /*! @brief DSPI interrupt source.*/
@@ -109,8 +106,9 @@
 } dspi_master_slave_mode_t;
 
 /*!
- * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid
- * only when CPHA bit in CTAR register is 0.
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is
+ * valid
+ * only when the CPHA bit in the CTAR register is 0.
  */
 typedef enum _dspi_master_sample_point
 {
@@ -169,36 +167,37 @@
 typedef enum _dspi_shift_direction
 {
     kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
-    kDSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.*/
+    kDSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.
+                              Shifting out of LSB is not supported for slave */
 } dspi_shift_direction_t;
 
 /*! @brief DSPI delay type selection.*/
 typedef enum _dspi_delay_type
 {
     kDSPI_PcsToSck = 1U,  /*!< Pcs-to-SCK delay. */
-    kDSPI_LastSckToPcs,   /*!< Last SCK edge to Pcs delay. */
+    kDSPI_LastSckToPcs,   /*!< The last SCK edge to Pcs delay. */
     kDSPI_BetweenTransfer /*!< Delay between transfers. */
 } dspi_delay_type_t;
 
 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
 typedef enum _dspi_ctar_selection
 {
-    kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the
+    kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the
                          same register address. */
     kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
-    kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */
-    kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */
-    kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */
-    kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */
-    kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */
-    kDSPI_Ctar7 = 7U  /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */
+    kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */
+    kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */
+    kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */
+    kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */
+    kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */
+    kDSPI_Ctar7 = 7U  /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */
 } dspi_ctar_selection_t;
 
-#define DSPI_MASTER_CTAR_SHIFT (0U)   /*!< DSPI master CTAR shift macro , internal used. */
-#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */
-#define DSPI_MASTER_PCS_SHIFT (4U)    /*!< DSPI master PCS shift macro , internal used. */
-#define DSPI_MASTER_PCS_MASK (0xF0U)  /*!< DSPI master PCS mask macro , internal used. */
-/*! @brief Can use this enumeration for DSPI master transfer configFlags. */
+#define DSPI_MASTER_CTAR_SHIFT (0U)   /*!< DSPI master CTAR shift macro; used internally. */
+#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */
+#define DSPI_MASTER_PCS_SHIFT (4U)    /*!< DSPI master PCS shift macro; used internally. */
+#define DSPI_MASTER_PCS_MASK (0xF0U)  /*!< DSPI master PCS mask macro; used internally. */
+/*! @brief Use this enumeration for the DSPI master transfer configFlags. */
 enum _dspi_transfer_config_flag_for_master
 {
     kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
@@ -217,20 +216,21 @@
     kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
     kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
 
-    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Is PCS signal continuous. */
-    kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/
+    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Indicates whether the PCS signal is continuous. */
+    kDSPI_MasterActiveAfterTransfer =
+        1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
 };
 
-#define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro , internal used. */
-#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */
-/*! @brief Can use this enum for DSPI slave transfer configFlags. */
+#define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro; used internally. */
+#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */
+/*! @brief Use this enumeration for the DSPI slave transfer configFlags. */
 enum _dspi_transfer_config_flag_for_slave
 {
     kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */
                                                     /*!< DSPI slave can only use PCS0. */
 };
 
-/*! @brief DSPI transfer state, which is used for DSPI transactional APIs' state machine. */
+/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
 enum _dspi_transfer_state
 {
     kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
@@ -238,15 +238,15 @@
     kDSPI_Error        /*!< Transfer error. */
 };
 
-/*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/
+/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
 typedef struct _dspi_command_data_config
 {
-    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of chip select between transfers.*/
+    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of the chip select between transfers.*/
     dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
                                           Register (CTAR) to use for CTAS.*/
     dspi_which_pcs_t whichPcs;       /*!< The desired PCS signal to use for the data transfer.*/
     bool isEndOfQueue;               /*!< Signals that the current transfer is the last in the queue.*/
-    bool clearTransferCount;         /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
+    bool clearTransferCount;         /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
 } dspi_command_data_config_t;
 
 /*! @brief DSPI master ctar configuration structure.*/
@@ -258,33 +258,33 @@
     dspi_clock_phase_t cpha;          /*!< Clock phase. */
     dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
 
-    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum
-                                               delay. It sets the boundary value if out of range that can be set.*/
-    uint32_t lastSckToPcsDelayInNanoSec;    /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the
-                                               minimum delay.It sets the boundary value if out of range that can be
-                                               set.*/
-    uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum
-                                             delay.It sets the boundary value if out of range that can be set.*/
+    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
+                                               delay. It also sets the boundary value if out of range.*/
+    uint32_t lastSckToPcsDelayInNanoSec;    /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
+                                               minimum delay. It also sets the boundary value if out of range.*/
+
+    uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
+                                             delay. It also sets the boundary value if out of range.*/
 } dspi_master_ctar_config_t;
 
 /*! @brief DSPI master configuration structure.*/
 typedef struct _dspi_master_config
 {
-    dspi_ctar_selection_t whichCtar;      /*!< Desired CTAR to use. */
+    dspi_ctar_selection_t whichCtar;      /*!< The desired CTAR to use. */
     dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
 
-    dspi_which_pcs_t whichPcs;                     /*!< Desired Peripheral Chip Select (pcs). */
-    dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */
+    dspi_which_pcs_t whichPcs;                     /*!< The desired Peripheral Chip Select (pcs). */
+    dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */
 
-    bool enableContinuousSCK;   /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only
+    bool enableContinuousSCK;   /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
                                      supported for CPHA = 1.*/
-    bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
-                                     data is ignored, the data from the transfer that generated the overflow
-                                     is either ignored. ROOE = 1, the incoming data is shifted in to the
-                                     shift to the shift register. */
+    bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
+                                     data is ignored and the data from the transfer that generated the overflow
+                                     is also ignored. If ROOE = 1, the incoming data is shifted to the
+                                     shift register. */
 
-    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
-    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
                                                  Format. It's valid only when CPHA=0. */
 } dspi_master_config_t;
 
@@ -294,23 +294,23 @@
     uint32_t bitsPerFrame;      /*!< Bits per frame, minimum 4, maximum 16.*/
     dspi_clock_polarity_t cpol; /*!< Clock polarity. */
     dspi_clock_phase_t cpha;    /*!< Clock phase. */
-                                /*!< Slave only supports MSB , does not support LSB.*/
+                                /*!< Slave only supports MSB and does not support LSB.*/
 } dspi_slave_ctar_config_t;
 
 /*! @brief DSPI slave configuration structure.*/
 typedef struct _dspi_slave_config
 {
-    dspi_ctar_selection_t whichCtar;     /*!< Desired CTAR to use. */
+    dspi_ctar_selection_t whichCtar;     /*!< The desired CTAR to use. */
     dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
 
-    bool enableContinuousSCK;               /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only
+    bool enableContinuousSCK;               /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
                                                  supported for CPHA = 1.*/
-    bool enableRxFifoOverWrite;             /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
-                                                 data is ignored, the data from the transfer that generated the overflow
-                                                 is either ignored. ROOE = 1, the incoming data is shifted in to the
-                                                 shift to the shift register. */
-    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
-    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+    bool enableRxFifoOverWrite;             /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
+                                                 data is ignored and the data from the transfer that generated the overflow
+                                                 is also ignored. If ROOE = 1, the incoming data is shifted to the
+                                                 shift register. */
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
                                                Format. It's valid only when CPHA=0. */
 } dspi_slave_config_t;
 
@@ -357,7 +357,7 @@
     volatile size_t dataSize; /*!< Transfer bytes. */
 
     uint32_t
-        configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
+        configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the
                         transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
                         is used for slave.*/
 } dspi_transfer_t;
@@ -365,38 +365,39 @@
 /*! @brief DSPI master transfer handle structure used for transactional API. */
 struct _dspi_master_handle
 {
-    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
-    volatile uint32_t command;     /*!< Desired data command. */
-    volatile uint32_t lastCommand; /*!< Desired last data command. */
+    uint32_t bitsPerFrame;         /*!< The desired number of bits per frame. */
+    volatile uint32_t command;     /*!< The desired data command. */
+    volatile uint32_t lastCommand; /*!< The desired last data command. */
 
     uint8_t fifoSize; /*!< FIFO dataSize. */
 
-    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
-    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+    volatile bool
+        isPcsActiveAfterTransfer;   /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+    volatile bool isThereExtraByte;         /*!< Indicates whether there are extra bytes.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
-    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
+    volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/
 
     dspi_master_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                           /*!< Callback user data. */
 };
 
-/*! @brief DSPI slave transfer handle structure used for transactional API. */
+/*! @brief DSPI slave transfer handle structure used for the transactional API. */
 struct _dspi_slave_handle
 {
-    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
-    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+    uint32_t bitsPerFrame;          /*!< The desired number of bits per frame. */
+    volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     volatile uint8_t state; /*!< DSPI transfer state.*/
 
@@ -421,18 +422,18 @@
 /*!
  * @brief Initializes the DSPI master.
  *
- * This function initializes the DSPI master configuration. An example use case is as follows:
+ * This function initializes the DSPI master configuration. This is an example use case.
  *  @code
  *   dspi_master_config_t  masterConfig;
  *   masterConfig.whichCtar                                = kDSPI_Ctar0;
- *   masterConfig.ctarConfig.baudRate                      = 500000000;
+ *   masterConfig.ctarConfig.baudRate                      = 500000000U;
  *   masterConfig.ctarConfig.bitsPerFrame                  = 8;
  *   masterConfig.ctarConfig.cpol                          = kDSPI_ClockPolarityActiveHigh;
  *   masterConfig.ctarConfig.cpha                          = kDSPI_ClockPhaseFirstEdge;
  *   masterConfig.ctarConfig.direction                     = kDSPI_MsbFirst;
- *   masterConfig.ctarConfig.pcsToSckDelayInNanoSec        = 1000000000 / masterConfig.ctarConfig.baudRate ;
- *   masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec    = 1000000000 / masterConfig.ctarConfig.baudRate ;
- *   masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.pcsToSckDelayInNanoSec        = 1000000000U / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec    = 1000000000U / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
  *   masterConfig.whichPcs                                 = kDSPI_Pcs0;
  *   masterConfig.pcsActiveHighOrLow                       = kDSPI_PcsActiveLow;
  *   masterConfig.enableContinuousSCK                      = false;
@@ -443,8 +444,8 @@
  *  @endcode
  *
  * @param base DSPI peripheral address.
- * @param masterConfig Pointer to structure dspi_master_config_t.
- * @param srcClock_Hz Module source input clock in Hertz
+ * @param masterConfig Pointer to the structure dspi_master_config_t.
+ * @param srcClock_Hz Module source input clock in Hertz.
  */
 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
 
@@ -452,8 +453,8 @@
  * @brief Sets the dspi_master_config_t structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
- * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure
- * before calling DSPI_MasterInit().
+ * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure
+ * before calling the DSPI_MasterInit().
  * Example:
  * @code
  *  dspi_master_config_t  masterConfig;
@@ -466,7 +467,7 @@
 /*!
  * @brief DSPI slave configuration.
  *
- * This function initializes the DSPI slave configuration. An example use case is as follows:
+ * This function initializes the DSPI slave configuration. This is an example use case.
  *  @code
  *   dspi_slave_config_t  slaveConfig;
  *  slaveConfig->whichCtar                  = kDSPI_Ctar0;
@@ -481,22 +482,22 @@
  *  @endcode
  *
  * @param base DSPI peripheral address.
- * @param slaveConfig Pointer to structure dspi_master_config_t.
+ * @param slaveConfig Pointer to the structure dspi_master_config_t.
  */
 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
 
 /*!
- * @brief Sets the dspi_slave_config_t structure to default values.
+ * @brief Sets the dspi_slave_config_t structure to a default value.
  *
  * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
- * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure
- * before calling DSPI_SlaveInit().
- * Example:
+ * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure
+ * before calling the DSPI_SlaveInit().
+ * This is an example.
  * @code
  *  dspi_slave_config_t  slaveConfig;
  *  DSPI_SlaveGetDefaultConfig(&slaveConfig);
  * @endcode
- * @param slaveConfig pointer to dspi_slave_config_t structure.
+ * @param slaveConfig Pointer to the dspi_slave_config_t structure.
  */
 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
 
@@ -510,7 +511,7 @@
  * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
  *
  * @param base DSPI peripheral address.
- * @param enable pass true to enable module, false to disable module.
+ * @param enable Pass true to enable module, false to disable module.
  */
 static inline void DSPI_Enable(SPI_Type *base, bool enable)
 {
@@ -536,7 +537,7 @@
 /*!
  * @brief Gets the DSPI status flag state.
  * @param base DSPI peripheral address.
- * @return The DSPI status(in SR register).
+ * @return DSPI status (in SR register).
  */
 static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
 {
@@ -549,13 +550,13 @@
  * This function  clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
  * desired status bit to clear.  The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
  * function uses these bit positions in its algorithm to clear the desired flag state.
- * Example usage:
+ * This is an example.
  * @code
  *  DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param statusFlags The status flag , used from type dspi_flags.
+ * @param statusFlags The status flag used from the type dspi_flags.
  */
 static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
 {
@@ -574,15 +575,16 @@
 /*!
  * @brief Enables the DSPI interrupts.
  *
- * This function configures the various interrupt masks of the DSPI.  The parameters are base and an interrupt mask.
+ * This function configures the various interrupt masks of the DSPI.  The parameters are a base and an interrupt mask.
  * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
+ *       Do not use this API(write to RSER register) while DSPI is in running state.
  *
  * @code
  *  DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
  */
 void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
 
@@ -594,7 +596,7 @@
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
  */
 static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
 {
@@ -613,13 +615,13 @@
 /*!
  * @brief Enables the DSPI DMA request.
  *
- * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are a base and a DMA mask.
  * @code
  *  DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ * @param mask The interrupt mask; use the enum dspi_dma_enable.
  */
 static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
 {
@@ -629,13 +631,13 @@
 /*!
  * @brief Disables the DSPI DMA request.
  *
- * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are a base and a DMA mask.
  * @code
  *  SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ * @param mask The interrupt mask; use the enum dspi_dma_enable.
  */
 static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
 {
@@ -714,7 +716,7 @@
 /*!
  * @brief Starts the DSPI transfers and clears HALT bit in MCR.
  *
- * This function sets the module to begin data transfer in either master or slave mode.
+ * This function sets the module to start data transfer in either master or slave mode.
  *
  * @param base DSPI peripheral address.
  */
@@ -723,9 +725,9 @@
     base->MCR &= ~SPI_MCR_HALT_MASK;
 }
 /*!
- * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR.
+ * @brief Stops DSPI transfers and sets the HALT bit in MCR.
  *
- * This function stops data transfers in either master or slave mode.
+ * This function stops data transfers in either master or slave modes.
  *
  * @param base DSPI peripheral address.
  */
@@ -735,15 +737,15 @@
 }
 
 /*!
- * @brief Enables (or disables) the DSPI FIFOs.
+ * @brief Enables or disables the DSPI FIFOs.
  *
- * This function  allows the caller to disable/enable the Tx and Rx FIFOs (independently).
- * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration.  To enable,
- * the caller must pass in a logic 1 (true).
+ * This function  allows the caller to disable/enable the Tx and Rx FIFOs independently.
+ * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration.  To enable,
+ * pass in a logic 1 (true).
  *
  * @param base DSPI peripheral address.
- * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
- * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
+ * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO
+ * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO
  */
 static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
 {
@@ -755,8 +757,8 @@
  * @brief Flushes the DSPI FIFOs.
  *
  * @param base DSPI peripheral address.
- * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
- * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
+ * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO
+ * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO
  */
 static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
 {
@@ -766,13 +768,13 @@
 
 /*!
  * @brief Configures the DSPI peripheral chip select polarity simultaneously.
- * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of
+ * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of
  * PCSs is specific to the device.
  * @code
  *  DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
    @endcode
  * @param base DSPI peripheral address.
- * @param mask The PCS polarity mask ,  can use the enum _dspi_pcs_polarity.
+ * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity.
  */
 static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
 {
@@ -801,19 +803,19 @@
  * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
  *
  * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
- * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).
+ * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT).
  *
- * These delay names are available in type dspi_delay_type_t.
+ * These delay names are available in the type dspi_delay_type_t.
  *
- * The user passes the delay to configure along with the prescaler and scaler value.
- * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply
- * wish to manually increment either value.
+ * The user passes the delay to the configuration along with the prescaler and scaler value.
+ * This allows the user to directly set the prescaler/scaler values if pre-calculated or
+ * to manually increment either value.
  *
  * @param base DSPI peripheral address.
  * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
  * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
  * @param scaler The scaler delay value (can be any integer between 0 to 15).
- * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t
  */
 void DSPI_MasterSetDelayScaler(
     SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
@@ -821,19 +823,19 @@
 /*!
  * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
  *
- * This function calculates the values for:
+ * This function calculates the values for the following.
  * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
  * After SCK delay pre-scalar (PASC) and scalar (ASC), or
- * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ * Delay after transfer pre-scalar (PDT) and scalar (DT).
  *
- * These delay names are available in type dspi_delay_type_t.
+ * These delay names are available in the type dspi_delay_type_t.
  *
- * The user passes which delay they want to configure along with the desired delay value in nanoseconds.  The function
- * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact
+ * The user passes which delay to configure along with the desired delay value in nanoseconds.  The function
+ * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact
  * delay match may not be possible. In this case, the closest match is calculated without going below the desired
  * delay value input.
  * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
- * supported delay is returned. The higher level peripheral driver alerts the user of an out of range delay
+ * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
  * input.
  *
  * @param base DSPI peripheral address.
@@ -853,11 +855,11 @@
  * @brief Writes data into the data buffer for master mode.
  *
  * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
- * provides characteristics of the data such as the optional continuous chip select
+ * provides characteristics of the data, such as the optional continuous chip select
  * operation between transfers, the desired Clock and Transfer Attributes register to use for the
  * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
  * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
- * sending the first frame of a data packet). This is an example:
+ * sending the first frame of a data packet). This is an example.
  * @code
  *  dspi_command_data_config_t commandConfig;
  *  commandConfig.isPcsContinuous = true;
@@ -869,7 +871,7 @@
    @endcode
  *
  * @param base DSPI peripheral address.
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @param data The data word to be sent.
  */
 static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
@@ -883,14 +885,14 @@
  * @brief Sets the dspi_command_data_config_t structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
- * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure
- * before calling DSPI_MasterWrite_xx().
- * Example:
+ * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure
+ * before calling the DSPI_MasterWrite_xx().
+ * This is an example.
  * @code
  *  dspi_command_data_config_t  command;
  *  DSPI_GetDefaultDataCommandConfig(&command);
  * @endcode
- * @param command pointer to dspi_command_data_config_t structure.
+ * @param command Pointer to the dspi_command_data_config_t structure.
  */
 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
 
@@ -898,11 +900,11 @@
  * @brief Writes data into the data buffer master mode and waits till complete to return.
  *
  * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
- * provides characteristics of the data such as the optional continuous chip select
+ * provides characteristics of the data, such as the optional continuous chip select
  * operation between transfers, the desired Clock and Transfer Attributes register to use for the
  * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
  * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
- * sending the first frame of a data packet). This is an example:
+ * sending the first frame of a data packet). This is an example.
  * @code
  *  dspi_command_config_t commandConfig;
  *  commandConfig.isPcsContinuous = true;
@@ -915,10 +917,10 @@
  *
  * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
  * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
- * receive data is available when transmit completes.
+ * the received data is available when the transmit completes.
  *
  * @param base DSPI peripheral address.
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @param data The data word to be sent.
  */
 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
@@ -933,10 +935,10 @@
  * improve performance in cases where the command structure is constant. For example, the user calls this function
  * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
  * this formatted command word with the desired data to transmit. This process increases transmit performance when
- * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a
+ * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode,  which format the command word each time a
  * data word is to be sent.
  *
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @return The command word formatted to the PUSHR data register bit field.
  */
 static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
@@ -949,24 +951,25 @@
 
 /*!
  * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
- *        buffer, master mode and waits till complete to return.
+ *        buffer master mode and waits till complete to return.
  *
- * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word
+ * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total
+* 32-bit word
  * as the data to send.
- * The command portion provides characteristics of the data such as the optional continuous chip select operation
-* between
- * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
+ * The command portion provides characteristics of the data, such as the optional continuous chip select operation
+ * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the
+* desired PCS
  * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
  * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
  * appending this command with the data to send. This is an example:
  * @code
  *  dataWord = <16-bit command> | <16-bit data>;
- *  DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);
+ *  DSPI_MasterWriteCommandDataBlocking(base, dataWord);
  * @endcode
  *
  * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
  * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
- * Because the SPI is a synchronous protocol, the receive data is available when transmit completes.
+ * Because the SPI is a synchronous protocol, the received data is available when the transmit completes.
  *
  *  For a blocking polling transfer, see methods below.
  *  Option 1:
@@ -985,7 +988,7 @@
 *   DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
 *
  * @param base DSPI peripheral address.
- * @param data The data word (command and data combined) to be sent
+ * @param data The data word (command and data combined) to be sent.
  */
 void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
 
@@ -1025,6 +1028,14 @@
 }
 
 /*!
+ * @brief Set up the dummy data.
+ *
+ * @param base DSPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+
+/*!
  *@}
 */
 
@@ -1037,13 +1048,13 @@
 /*!
  * @brief Initializes the DSPI master handle.
  *
- * This function initializes the DSPI handle which can be used for other DSPI transactional APIs.  Usually, for a
+ * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance,  call this API once to get the initialized handle.
  *
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_master_handle_t.
- * @param callback dspi callback.
- * @param userData callback function parameter.
+ * @param callback DSPI callback.
+ * @param userData Callback function parameter.
  */
 void DSPI_MasterTransferCreateHandle(SPI_Type *base,
                                      dspi_master_handle_t *handle,
@@ -1053,12 +1064,11 @@
 /*!
  * @brief DSPI master transfer data using polling.
  *
- * This function transfers data with polling. This is a blocking function, which does not return until all transfers
- * have been
- * completed.
+ * This function transfers data using polling. This is a blocking function, which does not return until all transfers
+ * have been completed.
  *
  * @param base DSPI peripheral base address.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
@@ -1067,12 +1077,11 @@
  * @brief DSPI master transfer data using interrupts.
  *
  * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
- data
- * have been transferred, the callback function is called.
+ * data is transferred, the callback function is called.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
@@ -1083,19 +1092,19 @@
  * This function gets the master transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
 
 /*!
- * @brief DSPI master aborts transfer using an interrupt.
+ * @brief DSPI master aborts a transfer using an interrupt.
  *
  * This function aborts a transfer using an interrupt.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
 
@@ -1105,7 +1114,7 @@
  * This function processes the DSPI transmit and receive IRQ.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
 
@@ -1115,10 +1124,10 @@
  * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance, call this API once to get the initialized handle.
  *
- * @param handle DSPI handle pointer to dspi_slave_handle_t.
+ * @param handle DSPI handle pointer to the dspi_slave_handle_t.
  * @param base DSPI peripheral base address.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData Callback function parameter.
  */
 void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
                                     dspi_slave_handle_t *handle,
@@ -1129,12 +1138,11 @@
  * @brief DSPI slave transfers data using an interrupt.
  *
  * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
- * data
- * have been transferred, the callback function is called.
+ * data is transferred, the callback function is called.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
@@ -1145,8 +1153,8 @@
  * This function gets the slave transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
@@ -1154,10 +1162,10 @@
 /*!
  * @brief DSPI slave aborts a transfer using an interrupt.
  *
- * This function aborts transfer using an interrupt.
+ * This function aborts a transfer using an interrupt.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
 
@@ -1167,7 +1175,7 @@
  * This function processes the DSPI transmit and receive IRQ.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi_edma.h"
 
@@ -57,7 +57,7 @@
 ***********************************************************************************************************************/
 /*!
 * @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
                                     void *g_dspiEdmaPrivateHandle,
@@ -66,7 +66,7 @@
 
 /*!
 * @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
                                    void *g_dspiEdmaPrivateHandle,
@@ -102,6 +102,9 @@
                                          edma_handle_t *edmaIntermediaryToTxRegHandle)
 {
     assert(handle);
+    assert(edmaRxRegToRxDataHandle);
+    assert(edmaTxDataToIntermediaryHandle);
+    assert(edmaIntermediaryToTxRegHandle);
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(*handle));
@@ -121,7 +124,8 @@
 
 status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If the transfer count is zero, then return immediately.*/
     if (transfer->dataSize == 0)
@@ -141,9 +145,11 @@
         return kStatus_DSPI_Busy;
     }
 
+    handle->state = kDSPI_Busy;
+
     uint32_t instance = DSPI_GetInstance(base);
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -156,9 +162,7 @@
     edma_transfer_config_t transferConfigB;
     edma_transfer_config_t transferConfigC;
 
-    handle->txBuffIfNull = ((uint32_t)DSPI_MASTER_DUMMY_DATA << 8) | DSPI_MASTER_DUMMY_DATA;
-
-    handle->state = kDSPI_Busy;
+    handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
 
     dspi_command_data_config_t commandStruct;
     DSPI_StopTransfer(base);
@@ -174,6 +178,7 @@
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
     handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -193,39 +198,70 @@
     handle->remainingReceiveByteCount = transfer->dataSize;
     handle->totalByteCount = transfer->dataSize;
 
-    /* this limits the amount of data we can transfer due to the linked channel.
-    * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+    * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        limited_size = 32767u;
+    }
+    else
+    {
+        limited_size = 511u;
+    }
+
     if (handle->bitsPerFrame > 8)
     {
-        if (transfer->dataSize > 1022)
+        if (transfer->dataSize > (limited_size << 1u))
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
     else
     {
-        if (transfer->dataSize > 511)
+        if (transfer->dataSize > limited_size)
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
 
+    /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
+    if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
+    {
+        handle->state = kDSPI_Idle;
+        return kStatus_InvalidArgument;
+    }
+
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
                      &s_dspiMasterEdmaPrivateHandle[instance]);
 
-    handle->isThereExtraByte = false;
-    if (handle->bitsPerFrame > 8)
-    {
-        if (handle->remainingSendByteCount % 2 == 1)
-        {
-            handle->remainingSendByteCount++;
-            handle->remainingReceiveByteCount--;
-            handle->isThereExtraByte = true;
-        }
-    }
+    /*
+    (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
+    channel_A minor link to channel_B , channel_B minor link to channel_C.
+
+    Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
+    channel_A:SPI_POPR to rxData,
+    channel_B:next txData to handle->command (low 16 bits),
+    channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
+    (handle->lastCommand to SPI_PUSHR).
+
+    (2)For DSPI instances with separate RX and TX DMA requests:
+    Rx DMA request -> channel_A
+    Tx DMA request -> channel_C -> channel_B .
+    channel_C major link to channel_B.
+    So need prepare the first data in "intermediary"  before the DMA
+    transfer and then channel_B is used to prepare the next data to "intermediary"
+
+    channel_A:SPI_POPR to rxData,
+    channel_C: handle->command (32 bits) to SPI_PUSHR,
+    channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
+    (handle->lastCommand to handle->Command).
+    */
 
     /*If dspi has separate dma request , prepare the first data in "intermediary" .
     else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
@@ -243,22 +279,16 @@
             {
                 if (handle->txData)
                 {
-                    if (handle->isThereExtraByte)
-                    {
-                        wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
-                    }
-                    else
-                    {
-                        wordToSend = *(handle->txData);
-                        ++handle->txData; /* increment to next data byte */
-                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                    }
+                    wordToSend = *(handle->txData);
+                    ++handle->txData; /* increment to next data byte */
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
                 }
                 else
                 {
                     wordToSend = ((uint32_t)dummyData << 8) | dummyData;
                 }
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else /* For all words except the last word , frame > 8bits */
             {
@@ -291,6 +321,7 @@
             if (handle->remainingSendByteCount == 1)
             {
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else
             {
@@ -315,21 +346,13 @@
                 {
                     if (handle->txData)
                     {
-                        if (handle->isThereExtraByte)
-                        {
-                            wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
-                        }
-                        else
-                        {
-                            wordToSend = *(handle->txData);
-                            ++handle->txData;
-                            wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                        }
+                        wordToSend = *(handle->txData);
+                        ++handle->txData;
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
                     }
                     else
                     {
                         wordToSend = ((uint32_t)dummyData << 8) | dummyData;
-                        ;
                     }
                     handle->remainingSendByteCount = 0;
                     base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
@@ -347,7 +370,6 @@
                     else
                     {
                         wordToSend = ((uint32_t)dummyData << 8) | dummyData;
-                        ;
                     }
                     handle->remainingSendByteCount -= 2;
                     base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
@@ -404,7 +426,7 @@
         }
     }
 
-    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
     EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
 
     transferConfigA.srcAddr = (uint32_t)rxAddr;
@@ -435,6 +457,10 @@
         transferConfigA.minorLoopBytes = 2;
         transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
     }
+
+    /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
+    handle->nbytes = transferConfigA.minorLoopBytes;
+
     EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                            &transferConfigA, NULL);
     EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
@@ -443,68 +469,10 @@
     /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
     write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
     SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
+
     EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
 
-    if (handle->remainingSendByteCount > 0)
-    {
-        if (handle->txData)
-        {
-            transferConfigB.srcAddr = (uint32_t)(handle->txData);
-            transferConfigB.srcOffset = 1;
-        }
-        else
-        {
-            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
-            transferConfigB.srcOffset = 0;
-        }
-
-        transferConfigB.destAddr = (uint32_t)(&handle->command);
-        transferConfigB.destOffset = 0;
-
-        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
-
-        if (handle->bitsPerFrame <= 8)
-        {
-            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigB.minorLoopBytes = 1;
-
-            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
-            {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
-            }
-            else
-            {
-                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
-                majorlink , the majorlink would not trigger the channel_C*/
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
-            }
-        }
-        else
-        {
-            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
-            transferConfigB.minorLoopBytes = 2;
-            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
-            {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
-            }
-            else
-            {
-                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
-                * majorlink*/
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
-            }
-        }
-
-        EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
-                               handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
-    }
-
-    /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
-    handle the last data */
-    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
-
+    /*Calculate the last data : handle->lastCommand*/
     if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
         ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
           ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
@@ -536,17 +504,9 @@
             }
             else
             {
-                if (handle->isThereExtraByte)
-                {
-                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 2] |
-                                          ((uint32_t)dummyData << 8);
-                }
-                else
-                {
-                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
-                                          ((uint32_t)handle->txData[bufferIndex - 1] << 8) |
-                                          handle->txData[bufferIndex - 2];
-                }
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
+                                      ((uint32_t)handle->txData[bufferIndex - 1] << 8) |
+                                      handle->txData[bufferIndex - 2];
             }
         }
         else
@@ -563,8 +523,104 @@
         }
     }
 
-    if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
-        ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
+    /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to handle->Command*/
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+        transferConfigB.destAddr = (uint32_t) & (handle->command);
+        transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.srcOffset = 0;
+        transferConfigB.destOffset = 0;
+        transferConfigB.minorLoopBytes = 4;
+        transferConfigB.majorLoopCounts = 1;
+
+        EDMA_TcdReset(softwareTCD);
+        EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+    }
+
+    /*User_Send_Buffer(txData) to intermediary(handle->command)*/
+    if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+          ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) &&
+         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+        (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
+    {
+        if (handle->txData)
+        {
+            transferConfigB.srcAddr = (uint32_t)(handle->txData);
+            transferConfigB.srcOffset = 1;
+        }
+        else
+        {
+            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigB.srcOffset = 0;
+        }
+
+        transferConfigB.destAddr = (uint32_t)(&handle->command);
+        transferConfigB.destOffset = 0;
+
+        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigB.minorLoopBytes = 1;
+
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                majorlink , the majorlink would not trigger the channel_C*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
+            }
+        }
+        else
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigB.minorLoopBytes = 2;
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                * majorlink*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
+            }
+        }
+
+        if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD);
+            EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
+                                       handle->edmaIntermediaryToTxRegHandle->channel, false);
+        }
+        else
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+        }
+    }
+    else
+    {
+        EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                               handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+    }
+
+    /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
+    handle the last data */
+
+    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
+    /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to SPI_PUSHR*/
+    if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
     {
         transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -580,7 +636,8 @@
     }
 
     if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
-        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)))
+        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) ||
+        (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
     {
         transferConfigC.srcAddr = (uint32_t)(&(handle->command));
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -590,18 +647,28 @@
         transferConfigC.srcOffset = 0;
         transferConfigC.destOffset = 0;
         transferConfigC.minorLoopBytes = 4;
+        if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+        {
+            if (handle->bitsPerFrame <= 8)
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            }
+            else
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            }
 
-        if (handle->bitsPerFrame <= 8)
-        {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         }
         else
         {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            transferConfigC.majorLoopCounts = 1;
+
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
         }
 
-        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
-                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
                                    handle->edmaIntermediaryToTxRegHandle->channel, false);
     }
@@ -673,20 +740,15 @@
                                         &preemption_config_t);
     }
 
-    /*Set the channel link.
-    For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
-    For DSPI instances with separate RX and TX DMA requests:
-    Rx DMA request -> channel_A
-    Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary"  before the DMA
-    transfer and then channel_B is used to prepare the next data to "intermediary" ) */
+    /*Set the channel link.*/
     if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
         /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
-        to prepare the next 32bits data (User_send_buffer to handle->command) */
+        to prepare the next 32bits data (txData to handle->command) */
         if (handle->remainingSendByteCount > 1)
         {
             EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
-                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink,
+                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
                                 handle->edmaTxDataToIntermediaryHandle->channel);
         }
 
@@ -699,12 +761,6 @@
             EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                                 kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel);
 
-            if (handle->isThereExtraByte)
-            {
-                EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
-                                    kEDMA_MajorLink, handle->edmaTxDataToIntermediaryHandle->channel);
-            }
-
             EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base,
                                 handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink,
                                 handle->edmaIntermediaryToTxRegHandle->channel);
@@ -723,37 +779,28 @@
                                     bool transferDone,
                                     uint32_t tcds)
 {
+    assert(edmaHandle);
+    assert(g_dspiEdmaPrivateHandle);
+
     dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle;
 
     dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
 
-    uint32_t dataReceived;
-
     DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
-    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
-    {
-        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
-        {
-        }
-        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
-        if (dspiEdmaPrivateHandle->handle->rxData)
-        {
-            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
-        }
-    }
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 
     if (dspiEdmaPrivateHandle->handle->callback)
     {
         dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
                                                 kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
     }
-
-    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 }
 
 void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
@@ -783,7 +830,8 @@
 
     size_t bytes;
 
-    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+    bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
+                                                                       handle->edmaRxRegToRxDataHandle->channel);
 
     *count = handle->totalByteCount - bytes;
 
@@ -798,6 +846,8 @@
                                         edma_handle_t *edmaTxDataToTxRegHandle)
 {
     assert(handle);
+    assert(edmaRxRegToRxDataHandle);
+    assert(edmaTxDataToTxRegHandle);
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(*handle));
@@ -816,7 +866,8 @@
 
 status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If send/receive length is zero */
     if (transfer->dataSize == 0)
@@ -836,7 +887,7 @@
         return kStatus_DSPI_Busy;
     }
 
-    edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
+    handle->state = kDSPI_Busy;
 
     uint32_t instance = DSPI_GetInstance(base);
     uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
@@ -846,54 +897,51 @@
     /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
-    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        limited_size = 32767u;
+    }
+    else
     {
-        if (handle->bitsPerFrame > 8)
+        limited_size = 511u;
+    }
+
+    if (handle->bitsPerFrame > 8)
+    {
+        if (transfer->dataSize > (limited_size << 1u))
         {
-            if (transfer->dataSize > 1022)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
-        else
+    }
+    else
+    {
+        if (transfer->dataSize > limited_size)
         {
-            if (transfer->dataSize > 511)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
     }
 
-    if ((handle->bitsPerFrame > 8) && (transfer->dataSize < 2))
+    /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
+    if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
     {
+        handle->state = kDSPI_Idle;
         return kStatus_InvalidArgument;
     }
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
 
-    handle->state = kDSPI_Busy;
-
     /* Store transfer information */
     handle->txData = transfer->txData;
     handle->rxData = transfer->rxData;
     handle->remainingSendByteCount = transfer->dataSize;
     handle->remainingReceiveByteCount = transfer->dataSize;
     handle->totalByteCount = transfer->dataSize;
-    handle->errorCount = 0;
-
-    handle->isThereExtraByte = false;
-    if (handle->bitsPerFrame > 8)
-    {
-        if (handle->remainingSendByteCount % 2 == 1)
-        {
-            handle->remainingSendByteCount++;
-            handle->remainingReceiveByteCount--;
-            handle->isThereExtraByte = true;
-        }
-    }
 
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_SLAVE_DUMMY_DATA;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -929,16 +977,9 @@
                 {
                     wordToSend = *(handle->txData);
                     ++handle->txData; /* Increment to next data byte */
-                    if ((handle->remainingSendByteCount == 2) && (handle->isThereExtraByte))
-                    {
-                        wordToSend |= (unsigned)(dummyData) << 8U;
-                        ++handle->txData; /* Increment to next data byte */
-                    }
-                    else
-                    {
-                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                        ++handle->txData; /* Increment to next data byte */
-                    }
+
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    ++handle->txData; /* Increment to next data byte */
                 }
                 else
                 {
@@ -1025,6 +1066,10 @@
             transferConfigA.minorLoopBytes = 2;
             transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
         }
+
+        /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
+        handle->nbytes = transferConfigA.minorLoopBytes;
+
         EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                                &transferConfigA, NULL);
         EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
@@ -1036,98 +1081,47 @@
         /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
         EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
 
-        /*If there is extra byte , it would use the */
-        if (handle->isThereExtraByte)
+        transferConfigC.destAddr = (uint32_t)txAddr;
+        transferConfigC.destOffset = 0;
+
+        if (handle->txData)
         {
-            if (handle->txData)
-            {
-                handle->txLastData =
-                    handle->txData[handle->remainingSendByteCount - 2] | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8);
-            }
-            else
-            {
-                handle->txLastData = DSPI_SLAVE_DUMMY_DATA | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8);
-            }
-            transferConfigC.srcAddr = (uint32_t)(&(handle->txLastData));
-            transferConfigC.destAddr = (uint32_t)txAddr;
-            transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigC.srcOffset = 0;
-            transferConfigC.destOffset = 0;
-            transferConfigC.minorLoopBytes = 4;
-            transferConfigC.majorLoopCounts = 1;
-
-            EDMA_TcdReset(softwareTCD);
-            EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL);
-        }
-
-        /*Set another  transferConfigC*/
-        if ((handle->isThereExtraByte) && (handle->remainingSendByteCount == 2))
-        {
-            EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                   &transferConfigC, NULL);
+            transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
+            transferConfigC.srcOffset = 1;
         }
         else
         {
-            transferConfigC.destAddr = (uint32_t)txAddr;
-            transferConfigC.destOffset = 0;
-
-            if (handle->txData)
+            transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigC.srcOffset = 0;
+            if (handle->bitsPerFrame <= 8)
             {
-                transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
-                transferConfigC.srcOffset = 1;
+                handle->txBuffIfNull = DSPI_DUMMY_DATA;
             }
             else
             {
-                transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
-                transferConfigC.srcOffset = 0;
-                if (handle->bitsPerFrame <= 8)
-                {
-                    handle->txBuffIfNull = DSPI_SLAVE_DUMMY_DATA;
-                }
-                else
-                {
-                    handle->txBuffIfNull = (DSPI_SLAVE_DUMMY_DATA << 8) | DSPI_SLAVE_DUMMY_DATA;
-                }
-            }
-
-            transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
-
-            if (handle->bitsPerFrame <= 8)
-            {
-                transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigC.minorLoopBytes = 1;
-                transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
+                handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
             }
-            else
-            {
-                transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
-                transferConfigC.minorLoopBytes = 2;
-                if (handle->isThereExtraByte)
-                {
-                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
-                }
-                else
-                {
-                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
-                }
-            }
+        }
+
+        transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
 
-            if (handle->isThereExtraByte)
-            {
-                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                       &transferConfigC, softwareTCD);
-                EDMA_EnableAutoStopRequest(handle->edmaTxDataToTxRegHandle->base,
-                                           handle->edmaTxDataToTxRegHandle->channel, false);
-            }
-            else
-            {
-                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                       &transferConfigC, NULL);
-            }
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigC.minorLoopBytes = 1;
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
+        }
+        else
+        {
+            transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigC.minorLoopBytes = 2;
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
+        }
 
-            EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
-        }
+        EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                               &transferConfigC, NULL);
+
+        EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
     }
 
     EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
@@ -1195,37 +1189,28 @@
                                    bool transferDone,
                                    uint32_t tcds)
 {
+    assert(edmaHandle);
+    assert(g_dspiEdmaPrivateHandle);
+
     dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle;
 
     dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
 
-    uint32_t dataReceived;
-
     DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
-    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
-    {
-        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
-        {
-        }
-        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
-        if (dspiEdmaPrivateHandle->handle->rxData)
-        {
-            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
-        }
-    }
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 
     if (dspiEdmaPrivateHandle->handle->callback)
     {
         dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
                                                 kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
     }
-
-    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
@@ -1254,7 +1239,8 @@
 
     size_t bytes;
 
-    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+    bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
+                                                                       handle->edmaRxRegToRxDataHandle->channel);
 
     *count = handle->totalByteCount - bytes;
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,8 +37,6 @@
  * @{
  */
 
-/*! @file */
-
 /***********************************************************************************************************************
  * Definitions
  **********************************************************************************************************************/
@@ -57,9 +55,9 @@
  * @brief Completion callback function pointer type.
  *
  * @param base DSPI peripheral base address.
- * @param handle Pointer to the handle for the DSPI master.
+ * @param handle A pointer to the handle for the DSPI master.
  * @param status Success or error code describing whether the transfer completed.
- * @param userData Arbitrary pointer-dataSized value passed from the application.
+ * @param userData An arbitrary pointer-dataSized value passed from the application.
  */
 typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base,
                                                      dspi_master_edma_handle_t *handle,
@@ -69,38 +67,39 @@
  * @brief Completion callback function pointer type.
  *
  * @param base DSPI peripheral base address.
- * @param handle Pointer to the handle for the DSPI slave.
+ * @param handle A pointer to the handle for the DSPI slave.
  * @param status Success or error code describing whether the transfer completed.
- * @param userData Arbitrary pointer-dataSized value passed from the application.
+ * @param userData An arbitrary pointer-dataSized value passed from the application.
  */
 typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base,
                                                     dspi_slave_edma_handle_t *handle,
                                                     status_t status,
                                                     void *userData);
 
-/*! @brief DSPI master eDMA transfer handle structure used for transactional API. */
+/*! @brief DSPI master eDMA transfer handle structure used for the transactional API. */
 struct _dspi_master_edma_handle
 {
-    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
-    volatile uint32_t command;     /*!< Desired data command. */
-    volatile uint32_t lastCommand; /*!< Desired last data command. */
+    uint32_t bitsPerFrame;         /*!< The desired number of bits per frame. */
+    volatile uint32_t command;     /*!< The desired data command. */
+    volatile uint32_t lastCommand; /*!< The desired last data command. */
 
     uint8_t fifoSize; /*!< FIFO dataSize. */
 
-    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
-    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+    volatile bool
+        isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal keeps active after the last frame transfer.*/
+
+    uint8_t nbytes;         /*!< eDMA minor byte transfer count initially configured. */
+    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
     uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
 
-    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
-
     dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                                /*!< Callback user data. */
 
@@ -111,33 +110,30 @@
     edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
 };
 
-/*! @brief DSPI slave eDMA transfer handle structure used for transactional API.*/
+/*! @brief DSPI slave eDMA transfer handle structure used for the transactional API.*/
 struct _dspi_slave_edma_handle
 {
-    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
-    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+    uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
     uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
     uint32_t txLastData;   /*!< Used if there is an extra byte when 16bits per frame for DMA purpose.*/
 
-    volatile uint8_t state; /*!< DSPI transfer state.*/
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
 
-    uint32_t errorCount; /*!< Error count for slave transfer.*/
+    volatile uint8_t state; /*!< DSPI transfer state.*/
 
     dspi_slave_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                               /*!< Callback user data. */
 
     edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
     edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
-
-    edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
 };
 
 /***********************************************************************************************************************
@@ -153,17 +149,18 @@
  * @brief Initializes the DSPI master eDMA handle.
  *
  * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
- * specified DSPI instance, user need only call this API once to get the initialized handle.
+ * specified DSPI instance, call this API once to get the initialized handle.
  *
- * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX  and TX are the same source) DMA request source.
- * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
+ * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX  and TX are the same source) DMA request
+ * source.
+ * (1) For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
  * TX DMAMUX source for edmaIntermediaryToTxRegHandle.
- * (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
+ * (2) For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
  *
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_master_edma_handle_t.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData A callback function parameter.
  * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
  * @param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t.
  * @param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t.
@@ -179,34 +176,34 @@
 /*!
  * @brief DSPI master transfer data using eDMA.
  *
- * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
- * have been transfer, the callback function is called.
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param transfer A pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer);
 
 /*!
- * @brief DSPI master aborts a transfer which using eDMA.
+ * @brief DSPI master aborts a transfer which is using eDMA.
  *
- * This function aborts a transfer which using eDMA.
+ * This function aborts a transfer which is using eDMA.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle);
 
 /*!
  * @brief Gets the master eDMA transfer count.
  *
- * This function get the master eDMA transfer count.
+ * This function gets the master eDMA transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count);
@@ -217,7 +214,8 @@
  * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance, call this API once to get the initialized handle.
  *
- * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX  and TX are the same source) DMA request source.
+ * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX  and TX are the same source) DMA request
+ * source.
  * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
  * TX DMAMUX source for edmaTxDataToTxRegHandle.
  * (2)For the shared DMA request source,  enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
@@ -225,7 +223,7 @@
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_slave_edma_handle_t.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData A callback function parameter.
  * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
  * @param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
  */
@@ -239,25 +237,25 @@
 /*!
  * @brief DSPI slave transfer data using eDMA.
  *
- * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
- * have been transfer, the callback function is called.
- * Note that slave EDMA transfer cannot support the situation that transfer_size is 1 when the bitsPerFrame is greater
- * than 8 .
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ * Note that the slave eDMA transfer doesn't support transfer_size is 1 when the bitsPerFrame is greater
+ * than eight.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param transfer A pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer);
 
 /*!
- * @brief DSPI slave aborts a transfer which using eDMA.
+ * @brief DSPI slave aborts a transfer which is using eDMA.
  *
- * This function aborts a transfer which using eDMA.
+ * This function aborts a transfer which is using eDMA.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle);
 
@@ -267,8 +265,8 @@
  * This function gets the slave eDMA transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred so far by the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count);

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_edma.h"
 
@@ -63,11 +63,13 @@
 /*! @brief Array to map EDMA instance number to base pointer. */
 static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map EDMA instance number to clock name. */
 static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Array to map EDMA instance number to IRQ number. */
-static const IRQn_Type s_edmaIRQNumber[] = DMA_CHN_IRQS;
+static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
 
 /*! @brief Pointers to transfer handle for each EDMA channel. */
 static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
@@ -81,7 +83,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_EDMA_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
     {
         if (s_edmaBases[instance] == base)
         {
@@ -89,7 +91,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_EDMA_COUNT);
+    assert(instance < ARRAY_SIZE(s_edmaBases));
 
     return instance;
 }
@@ -122,8 +124,10 @@
 
     uint32_t tmpreg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate EDMA periphral clock */
     CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* Configure EDMA peripheral according to the configuration structure. */
     tmpreg = base->CR;
     tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
@@ -134,8 +138,10 @@
 
 void EDMA_Deinit(DMA_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate EDMA periphral clock */
     CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void EDMA_GetDefaultConfig(edma_config_t *config)
@@ -409,46 +415,32 @@
     }
 }
 
-uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
 {
     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    uint32_t nbytes = 0;
-    uint32_t remainingBytes = 0;
+    uint32_t remainingCount = 0;
 
     if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
     {
-        remainingBytes = 0;
+        remainingCount = 0;
     }
     else
     {
-        /* Calculate the nbytes */
-        if (base->TCD[channel].NBYTES_MLOFFYES & (DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK))
-        {
-            nbytes = (base->TCD[channel].NBYTES_MLOFFYES & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >>
-                     DMA_NBYTES_MLOFFYES_NBYTES_SHIFT;
-        }
-        else
-        {
-            nbytes =
-                (base->TCD[channel].NBYTES_MLOFFNO & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT;
-        }
         /* Calculate the unfinished bytes */
         if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
         {
-            remainingBytes = ((base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >>
-                              DMA_CITER_ELINKYES_CITER_SHIFT) *
-                             nbytes;
+            remainingCount =
+                (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
         }
         else
         {
-            remainingBytes =
-                ((base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT) *
-                nbytes;
+            remainingCount =
+                (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
         }
     }
 
-    return remainingBytes;
+    return remainingCount;
 }
 
 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
@@ -497,14 +489,19 @@
     uint32_t channelIndex;
     edma_tcd_t *tcdRegs;
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     handle->base = base;
     handle->channel = channel;
     /* Get the DMA instance number */
     edmaInstance = EDMA_GetInstance(base);
     channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
     s_EDMAHandle[channelIndex] = handle;
+
     /* Enable NVIC interrupt */
-    EnableIRQ(s_edmaIRQNumber[channelIndex]);
+    EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
+
     /*
        Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
        CSR will be 0. Because in order to suit EDMA busy check mechanism in
@@ -558,8 +555,8 @@
     assert(config != NULL);
     assert(srcAddr != NULL);
     assert(destAddr != NULL);
-    assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U || srcWidth == 16U || srcWidth == 32U);
-    assert(destWidth == 1U || destWidth == 2U || destWidth == 4U || destWidth == 16U || destWidth == 32U);
+    assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
+    assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
     assert(transferBytes % bytesEachRequest == 0);
 
     config->destAddr = (uint32_t)destAddr;
@@ -825,11 +822,11 @@
 
     /* Clear EDMA interrupt flag */
     handle->base->CINT = handle->channel;
-    if (handle->tcdPool == NULL)
+    if ((handle->tcdPool == NULL) && (handle->callback != NULL))
     {
         (handle->callback)(handle, handle->userData, true, 0);
     }
-    else /* Use the TCD queue. */
+    else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
     {
         uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
         uint32_t sga_index;
@@ -839,19 +836,19 @@
 
         /* Check if transfer is already finished. */
         transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
-        /* Get the offset of the current transfer TCD blcoks. */
+        /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */
         sga -= (uint32_t)handle->tcdPool;
-        /* Get the index of the current transfer TCD blcoks. */
+        /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */
         sga_index = sga / sizeof(edma_tcd_t);
         /* Adjust header positions. */
         if (transfer_done)
         {
-            /* New header shall point to the next TCD (current one is already finished) */
+            /* New header shall point to the next TCD to be loaded (current one is already finished) */
             new_header = sga_index;
         }
         else
         {
-            /* New header shall point to this descriptor (not finished yet) */
+            /* New header shall point to this descriptor currently loaded (not finished yet) */
             new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
         }
         /* Calculate the number of finished TCDs */
@@ -863,7 +860,7 @@
             }
             else
             {
-                /* Internal error occurs. */
+                /* No TCD in the memory are going to be loaded or internal error occurs. */
                 tcds_done = 0;
             }
         }
@@ -875,9 +872,9 @@
                 tcds_done += handle->tcdSize;
             }
         }
-        /* Advance header to the point beyond the last finished TCD block. */
+        /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
         handle->header = new_header;
-        /* Release TCD blocks. */
+        /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
         handle->tcdUsed -= tcds_done;
         /* Invoke callback function. */
         if (handle->callback)
@@ -937,12 +934,260 @@
         EDMA_HandleIRQ(s_EDMAHandle[7]);
     }
 }
+
+#if defined(DMA1)
+void DMA1_04_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA1_15_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA1_26_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA1_37_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+#endif
 #endif /* 8 channels (Shared) */
 
+/* 16 channels (Shared): K32H844P */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
+
+void DMA0_08_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+}
+
+void DMA0_19_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+}
+
+void DMA0_210_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+}
+
+void DMA0_311_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+}
+
+void DMA0_412_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA0_513_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA0_614_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA0_715_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+
+#if defined(DMA1)
+void DMA1_08_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[16]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[24]);
+    }
+}
+
+void DMA1_19_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[17]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[25]);
+    }
+}
+
+void DMA1_210_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[18]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[26]);
+    }
+}
+
+void DMA1_311_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[19]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[27]);
+    }
+}
+
+void DMA1_412_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[20]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[28]);
+    }
+}
+
+void DMA1_513_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[21]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[29]);
+    }
+}
+
+void DMA1_614_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[22]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[30]);
+    }
+}
+
+void DMA1_715_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[23]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[31]);
+    }
+}
+#endif
+#endif /* 16 channels (Shared) */
+
 /* 32 channels (Shared): k80 */
 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
 
-void DMA0_DMA16_IRQHandler(void)
+void DMA0_DMA16_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -954,7 +1199,7 @@
     }
 }
 
-void DMA1_DMA17_IRQHandler(void)
+void DMA1_DMA17_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -966,7 +1211,7 @@
     }
 }
 
-void DMA2_DMA18_IRQHandler(void)
+void DMA2_DMA18_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -978,7 +1223,7 @@
     }
 }
 
-void DMA3_DMA19_IRQHandler(void)
+void DMA3_DMA19_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -990,7 +1235,7 @@
     }
 }
 
-void DMA4_DMA20_IRQHandler(void)
+void DMA4_DMA20_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1002,7 +1247,7 @@
     }
 }
 
-void DMA5_DMA21_IRQHandler(void)
+void DMA5_DMA21_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1014,7 +1259,7 @@
     }
 }
 
-void DMA6_DMA22_IRQHandler(void)
+void DMA6_DMA22_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1026,7 +1271,7 @@
     }
 }
 
-void DMA7_DMA23_IRQHandler(void)
+void DMA7_DMA23_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1038,7 +1283,7 @@
     }
 }
 
-void DMA8_DMA24_IRQHandler(void)
+void DMA8_DMA24_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1050,7 +1295,7 @@
     }
 }
 
-void DMA9_DMA25_IRQHandler(void)
+void DMA9_DMA25_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1062,7 +1307,7 @@
     }
 }
 
-void DMA10_DMA26_IRQHandler(void)
+void DMA10_DMA26_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1074,7 +1319,7 @@
     }
 }
 
-void DMA11_DMA27_IRQHandler(void)
+void DMA11_DMA27_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1086,7 +1331,7 @@
     }
 }
 
-void DMA12_DMA28_IRQHandler(void)
+void DMA12_DMA28_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1098,7 +1343,7 @@
     }
 }
 
-void DMA13_DMA29_IRQHandler(void)
+void DMA13_DMA29_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1110,7 +1355,7 @@
     }
 }
 
-void DMA14_DMA30_IRQHandler(void)
+void DMA14_DMA30_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1122,7 +1367,7 @@
     }
 }
 
-void DMA15_DMA31_IRQHandler(void)
+void DMA15_DMA31_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1135,6 +1380,202 @@
 }
 #endif /* 32 channels (Shared) */
 
+/* 32 channels (Shared): MCIMX7U5_M4 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+
+void DMA0_0_4_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+}
+
+void DMA0_1_5_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+}
+
+void DMA0_2_6_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+}
+
+void DMA0_3_7_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+}
+
+void DMA0_8_12_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA0_9_13_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA0_10_14_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA0_11_15_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+
+void DMA0_16_20_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[16]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[20]);
+    }
+}
+
+void DMA0_17_21_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[17]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[21]);
+    }
+}
+
+void DMA0_18_22_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[18]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[22]);
+    }
+}
+
+void DMA0_19_23_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[19]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[23]);
+    }
+}
+
+void DMA0_24_28_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[24]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[28]);
+    }
+}
+
+void DMA0_25_29_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[25]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[29]);
+    }
+}
+
+void DMA0_26_30_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[26]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[30]);
+    }
+}
+
+void DMA0_27_31_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[27]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[31]);
+    }
+}
+#endif /* 32 channels (Shared): MCIMX7U5 */
+
 /* 4 channels (No Shared): kv10  */
 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _FSL_EDMA_H_
 #define _FSL_EDMA_H_
@@ -34,11 +34,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup edma_driver
+ * @addtogroup edma
  * @{
  */
 
-/*! @file */
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -46,7 +45,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief eDMA driver version */
-#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
 /*@}*/
 
 /*! @brief Compute the offset unit from DCHPRI3 */
@@ -78,28 +77,28 @@
     kEDMA_Modulo128bytes,       /*!< Circular buffer size is 128 bytes. */
     kEDMA_Modulo256bytes,       /*!< Circular buffer size is 256 bytes. */
     kEDMA_Modulo512bytes,       /*!< Circular buffer size is 512 bytes. */
-    kEDMA_Modulo1Kbytes,        /*!< Circular buffer size is 1K bytes. */
-    kEDMA_Modulo2Kbytes,        /*!< Circular buffer size is 2K bytes. */
-    kEDMA_Modulo4Kbytes,        /*!< Circular buffer size is 4K bytes. */
-    kEDMA_Modulo8Kbytes,        /*!< Circular buffer size is 8K bytes. */
-    kEDMA_Modulo16Kbytes,       /*!< Circular buffer size is 16K bytes. */
-    kEDMA_Modulo32Kbytes,       /*!< Circular buffer size is 32K bytes. */
-    kEDMA_Modulo64Kbytes,       /*!< Circular buffer size is 64K bytes. */
-    kEDMA_Modulo128Kbytes,      /*!< Circular buffer size is 128K bytes. */
-    kEDMA_Modulo256Kbytes,      /*!< Circular buffer size is 256K bytes. */
-    kEDMA_Modulo512Kbytes,      /*!< Circular buffer size is 512K bytes. */
-    kEDMA_Modulo1Mbytes,        /*!< Circular buffer size is 1M bytes. */
-    kEDMA_Modulo2Mbytes,        /*!< Circular buffer size is 2M bytes. */
-    kEDMA_Modulo4Mbytes,        /*!< Circular buffer size is 4M bytes. */
-    kEDMA_Modulo8Mbytes,        /*!< Circular buffer size is 8M bytes. */
-    kEDMA_Modulo16Mbytes,       /*!< Circular buffer size is 16M bytes. */
-    kEDMA_Modulo32Mbytes,       /*!< Circular buffer size is 32M bytes. */
-    kEDMA_Modulo64Mbytes,       /*!< Circular buffer size is 64M bytes. */
-    kEDMA_Modulo128Mbytes,      /*!< Circular buffer size is 128M bytes. */
-    kEDMA_Modulo256Mbytes,      /*!< Circular buffer size is 256M bytes. */
-    kEDMA_Modulo512Mbytes,      /*!< Circular buffer size is 512M bytes. */
-    kEDMA_Modulo1Gbytes,        /*!< Circular buffer size is 1G bytes. */
-    kEDMA_Modulo2Gbytes,        /*!< Circular buffer size is 2G bytes. */
+    kEDMA_Modulo1Kbytes,        /*!< Circular buffer size is 1 K bytes. */
+    kEDMA_Modulo2Kbytes,        /*!< Circular buffer size is 2 K bytes. */
+    kEDMA_Modulo4Kbytes,        /*!< Circular buffer size is 4 K bytes. */
+    kEDMA_Modulo8Kbytes,        /*!< Circular buffer size is 8 K bytes. */
+    kEDMA_Modulo16Kbytes,       /*!< Circular buffer size is 16 K bytes. */
+    kEDMA_Modulo32Kbytes,       /*!< Circular buffer size is 32 K bytes. */
+    kEDMA_Modulo64Kbytes,       /*!< Circular buffer size is 64 K bytes. */
+    kEDMA_Modulo128Kbytes,      /*!< Circular buffer size is 128 K bytes. */
+    kEDMA_Modulo256Kbytes,      /*!< Circular buffer size is 256 K bytes. */
+    kEDMA_Modulo512Kbytes,      /*!< Circular buffer size is 512 K bytes. */
+    kEDMA_Modulo1Mbytes,        /*!< Circular buffer size is 1 M bytes. */
+    kEDMA_Modulo2Mbytes,        /*!< Circular buffer size is 2 M bytes. */
+    kEDMA_Modulo4Mbytes,        /*!< Circular buffer size is 4 M bytes. */
+    kEDMA_Modulo8Mbytes,        /*!< Circular buffer size is 8 M bytes. */
+    kEDMA_Modulo16Mbytes,       /*!< Circular buffer size is 16 M bytes. */
+    kEDMA_Modulo32Mbytes,       /*!< Circular buffer size is 32 M bytes. */
+    kEDMA_Modulo64Mbytes,       /*!< Circular buffer size is 64 M bytes. */
+    kEDMA_Modulo128Mbytes,      /*!< Circular buffer size is 128 M bytes. */
+    kEDMA_Modulo256Mbytes,      /*!< Circular buffer size is 256 M bytes. */
+    kEDMA_Modulo512Mbytes,      /*!< Circular buffer size is 512 M bytes. */
+    kEDMA_Modulo1Gbytes,        /*!< Circular buffer size is 1 G bytes. */
+    kEDMA_Modulo2Gbytes,        /*!< Circular buffer size is 2 G bytes. */
 } edma_modulo_t;
 
 /*! @brief Bandwidth control */
@@ -143,7 +142,7 @@
 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
     kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
 #endif
-    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit will be 0, otherwise be 1 */
+    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
 };
 
 /*! @brief eDMA interrupt source */
@@ -178,7 +177,7 @@
                                            the link channel is itself. */
     bool enableHaltOnError;           /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
                                            Subsequently, all service requests are ignored until the HALT bit is cleared.*/
-    bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority
+    bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority
                                            arbitration is used for channel selection */
     bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
                                a new channel. Executing channels are allowed to complete. */
@@ -212,15 +211,15 @@
                                                 form the next-state value as each source read is completed. */
     int16_t destOffset;                    /*!< Sign-extended offset applied to the current destination address to
                                                 form the next-state value as each destination write is completed. */
-    uint16_t minorLoopBytes;               /*!< Bytes to transfer in a minor loop*/
+    uint32_t minorLoopBytes;               /*!< Bytes to transfer in a minor loop*/
     uint32_t majorLoopCounts;              /*!< Major loop iteration count. */
 } edma_transfer_config_t;
 
 /*! @brief eDMA channel priority configuration */
 typedef struct _edma_channel_Preemption_config
 {
-    bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */
-    bool enablePreemptAbility;    /*!< If true: channel can suspend other channel with low priority */
+    bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */
+    bool enablePreemptAbility;    /*!< If true: a channel can suspend other channel with low priority */
     uint8_t channelPriority;      /*!< Channel priority */
 } edma_channel_Preemption_config_t;
 
@@ -229,14 +228,14 @@
 {
     bool enableSrcMinorOffset;  /*!< Enable(true) or Disable(false) source minor loop offset. */
     bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
-    uint32_t minorOffset;       /*!< Offset for minor loop mapping. */
+    uint32_t minorOffset;       /*!< Offset for a minor loop mapping. */
 } edma_minor_offset_config_t;
 
 /*!
  * @brief eDMA TCD.
  *
  * This structure is same as TCD register which is described in reference manual,
- * and is used to configure scatter/gather feature as a next hardware TCD.
+ * and is used to configure the scatter/gather feature as a next hardware TCD.
  */
 typedef struct _edma_tcd
 {
@@ -256,20 +255,21 @@
 /*! @brief Callback for eDMA */
 struct _edma_handle;
 
-/*! @brief Define Callback function for eDMA. */
+/*! @brief Define callback function for eDMA. */
 typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
 
 /*! @brief eDMA transfer handle structure */
 typedef struct _edma_handle
 {
-    edma_callback callback;  /*!< Callback function for major count exhausted. */
-    void *userData;          /*!< Callback function parameter. */
-    DMA_Type *base;          /*!< eDMA peripheral base address. */
-    edma_tcd_t *tcdPool;     /*!< Pointer to memory stored TCDs. */
-    uint8_t channel;         /*!< eDMA channel number. */
-    volatile int8_t header;  /*!< The first TCD index. */
-    volatile int8_t tail;    /*!< The last TCD index. */
-    volatile int8_t tcdUsed; /*!< The number of used TCD slots. */
+    edma_callback callback; /*!< Callback function for major count exhausted. */
+    void *userData;         /*!< Callback function parameter. */
+    DMA_Type *base;         /*!< eDMA peripheral base address. */
+    edma_tcd_t *tcdPool;    /*!< Pointer to memory stored TCDs. */
+    uint8_t channel;        /*!< eDMA channel number. */
+    volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */
+    volatile int8_t tail;   /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */
+    volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in
+                                the memory. */
     volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
     uint8_t flags;           /*!< The status of the current channel. */
 } edma_handle_t;
@@ -282,24 +282,24 @@
 #endif /* __cplusplus */
 
 /*!
- * @name eDMA initialization and De-initialization
+ * @name eDMA initialization and de-initialization
  * @{
  */
 
 /*!
- * @brief Initializes eDMA peripheral.
+ * @brief Initializes the eDMA peripheral.
  *
- * This function ungates the eDMA clock and configure eDMA peripheral according
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
  * to the configuration structure.
  *
  * @param base eDMA peripheral base address.
- * @param config Pointer to configuration structure, see "edma_config_t".
- * @note This function enable the minor loop map feature.
+ * @param config A pointer to the configuration structure, see "edma_config_t".
+ * @note This function enables the minor loop map feature.
  */
 void EDMA_Init(DMA_Type *base, const edma_config_t *config);
 
 /*!
- * @brief Deinitializes eDMA peripheral.
+ * @brief Deinitializes the eDMA peripheral.
  *
  * This function gates the eDMA clock.
  *
@@ -310,8 +310,8 @@
 /*!
  * @brief Gets the eDMA default configuration structure.
  *
- * This function sets the configuration structure to a default value.
- * The default configuration is set to the following value:
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
  * @code
  *   config.enableContinuousLinkMode = false;
  *   config.enableHaltOnError = true;
@@ -319,7 +319,7 @@
  *   config.enableDebugMode = false;
  * @endcode
  *
- * @param config Pointer to eDMA configuration structure.
+ * @param config A pointer to the eDMA configuration structure.
  */
 void EDMA_GetDefaultConfig(edma_config_t *config);
 
@@ -330,22 +330,22 @@
  */
 
 /*!
- * @brief Sets all TCD registers to a default value.
+ * @brief Sets all TCD registers to default values.
  *
- * This function sets TCD registers for this channel to default value.
+ * This function sets TCD registers for this channel to default values.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @note This function must not be called while the channel transfer is on-going,
- *       or it will case unpredicated results.
- * @note This function will enable auto stop request feature.
+ * @note This function must not be called while the channel transfer is ongoing
+ *       or it causes unpredictable results.
+ * @note This function enables the auto stop request feature.
  */
 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
 
 /*!
  * @brief Configures the eDMA transfer attribute.
  *
- * This function configure the transfer attribute, including source address, destination address,
+ * This function configures the transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the TCD address.
  * Example:
@@ -361,11 +361,11 @@
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
  * @param config Pointer to eDMA transfer configuration structure.
- * @param nextTcd Point to TCD structure. It can be NULL if user
+ * @param nextTcd Point to TCD structure. It can be NULL if users
  *                do not want to enable scatter/gather feature.
- * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
- *       And DREQ bit will be cleared in the previous transfer configuration which
- *       will be set in eDMA_ResetChannel.
+ * @note If nextTcd is not NULL, it means scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the eDMA_ResetChannel.
  */
 void EDMA_SetTransferConfig(DMA_Type *base,
                             uint32_t channel,
@@ -375,12 +375,12 @@
 /*!
  * @brief Configures the eDMA minor offset feature.
  *
- * Minor offset means signed-extended value added to source address or destination
+ * The minor offset means that the signed-extended value is added to the source address or destination
  * address after each minor loop.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param config Pointer to Minor offset configuration structure.
+ * @param config A pointer to the minor offset configuration structure.
  */
 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
 
@@ -391,7 +391,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number
- * @param config Pointer to channel preemption configuration structure.
+ * @param config A pointer to the channel preemption configuration structure.
  */
 static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
                                                    uint32_t channel,
@@ -408,30 +408,31 @@
 /*!
  * @brief Sets the channel link for the eDMA transfer.
  *
- * This function configures  minor link or major link mode. The minor link means that the channel link is
- * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
+ * This function configures either the minor link or the major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param type Channel link type, it can be one of:
+ * @param type A channel link type, which can be one of the following:
  *   @arg kEDMA_LinkNone
  *   @arg kEDMA_MinorLink
  *   @arg kEDMA_MajorLink
  * @param linkedChannel The linked channel number.
- * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  */
 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
 
 /*!
  * @brief Sets the bandwidth for the eDMA transfer.
  *
- * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
  * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param bandWidth Bandwidth setting, it can be one of:
+ * @param bandWidth A bandwidth setting, which can be one of the following:
  *     @arg kEDMABandwidthStallNone
  *     @arg kEDMABandwidthStall4Cycle
  *     @arg kEDMABandwidthStall8Cycle
@@ -439,7 +440,7 @@
 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
 
 /*!
- * @brief Sets the source modulo and destination modulo for eDMA transfer.
+ * @brief Sets the source modulo and the destination modulo for the eDMA transfer.
  *
  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
  * calculation is performed or the original register value. It provides the ability to implement a circular data
@@ -447,8 +448,8 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param srcModulo Source modulo value.
- * @param destModulo Destination modulo value.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
  */
 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
 
@@ -458,7 +459,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param enable The command for enable(ture) or disable(false).
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
@@ -475,7 +476,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param enable The command for enable (true) or disable (false).
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
@@ -489,7 +490,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -499,7 +500,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of interrupt source to be set. Use
+ * @param mask The mask of the interrupt source to be set. Use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -516,15 +517,15 @@
  * This function sets all fields for this TCD structure to default value.
  *
  * @param tcd Pointer to the TCD structure.
- * @note This function will enable auto stop request feature.
+ * @note This function enables the auto stop request feature.
  */
 void EDMA_TcdReset(edma_tcd_t *tcd);
 
 /*!
  * @brief Configures the eDMA TCD transfer attribute.
  *
- * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers.
- * STCD is used in scatter-gather mode.
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The STCD is used in the scatter-gather mode.
  * This function configures the TCD transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the next TCD address.
@@ -540,33 +541,34 @@
  *
  * @param tcd Pointer to the TCD structure.
  * @param config Pointer to eDMA transfer configuration structure.
- * @param nextTcd Pointer to the next TCD structure. It can be NULL if user
+ * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
  *                do not want to enable scatter/gather feature.
- * @note TCD address should be 32 bytes aligned, or it will cause eDMA error.
- * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
- *       And DREQ bit will be cleared in the previous transfer configuration which
- *       will be set in EDMA_TcdReset.
+ * @note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * @note If the nextTcd is not NULL, the scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the EDMA_TcdReset.
  */
 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
 
 /*!
  * @brief Configures the eDMA TCD minor offset feature.
  *
- * Minor offset is a signed-extended value added to the source address or destination
+ * A minor offset is a signed-extended value added to the source address or a destination
  * address after each minor loop.
  *
- * @param tcd Point to the TCD structure.
- * @param config Pointer to Minor offset configuration structure.
+ * @param tcd A point to the TCD structure.
+ * @param config A pointer to the minor offset configuration structure.
  */
 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
 
 /*!
- * @brief Sets the channel link for eDMA TCD.
+ * @brief Sets the channel link for the eDMA TCD.
  *
  * This function configures either a minor link or a major link. The minor link means the channel link is
- * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is exhausted.
+ * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
+ * exhausted.
  *
- * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  * @param tcd Point to the TCD structure.
  * @param type Channel link type, it can be one of:
  *   @arg kEDMA_LinkNone
@@ -579,11 +581,11 @@
 /*!
  * @brief Sets the bandwidth for the eDMA TCD.
  *
- * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
- * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
- * @param tcd Point to the TCD structure.
- * @param bandWidth Bandwidth setting, it can be one of:
+ * @param tcd A pointer to the TCD structure.
+ * @param bandWidth A bandwidth setting, which can be one of the following:
  *     @arg kEDMABandwidthStallNone
  *     @arg kEDMABandwidthStall4Cycle
  *     @arg kEDMABandwidthStall8Cycle
@@ -597,15 +599,15 @@
 }
 
 /*!
- * @brief Sets the source modulo and destination modulo for eDMA TCD.
+ * @brief Sets the source modulo and the destination modulo for the eDMA TCD.
  *
  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
  * calculation is performed or the original register value. It provides the ability to implement a circular data
  * queue easily.
  *
- * @param tcd Point to the TCD structure.
- * @param srcModulo Source modulo value.
- * @param destModulo Destination modulo value.
+ * @param tcd A pointer to the TCD structure.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
  */
 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
 
@@ -614,8 +616,8 @@
  *
  * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
  *
- * @param tcd Point to the TCD structure.
- * @param enable The command for enable(ture) or disable(false).
+ * @param tcd A pointer to the TCD structure.
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
 {
@@ -629,7 +631,7 @@
  * @brief Enables the interrupt source for the eDMA TCD.
  *
  * @param tcd Point to the TCD structure.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
@@ -638,7 +640,7 @@
  * @brief Disables the interrupt source for the eDMA TCD.
  *
  * @param tcd Point to the TCD structure.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
@@ -680,7 +682,7 @@
 }
 
 /*!
- * @brief Starts the eDMA transfer by software trigger.
+ * @brief Starts the eDMA transfer by using the software trigger.
  *
  * This function starts a minor loop transfer.
  *
@@ -701,25 +703,34 @@
  */
 
 /*!
- * @brief Gets the Remaining bytes from the eDMA current channel TCD.
+ * @brief Gets the remaining major loop count from the eDMA current channel TCD.
  *
  * This function checks the TCD (Task Control Descriptor) status for a specified
- * eDMA channel and returns the the number of bytes that have not finished.
+ * eDMA channel and returns the the number of major loop count that has not finished.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @return Bytes have not been transferred yet for the current TCD.
- * @note This function can only be used to get unfinished bytes of transfer without
- *       the next TCD, or it might be inaccuracy.
+ * @return Major loop count which has not been transferred yet for the current TCD.
+ * @note 1. This function can only be used to get unfinished major loop count of transfer without
+ *          the next TCD, or it might be inaccuracy.
+ *       2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
+ *          the channel is running.
+ *          Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
+ *          register is needed while the eDMA IP does not support getting it while a channel is active.
+ *          In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
+ *          is working with while a channel is running.
+ *          Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
+ *          copied before enabling the channel) is needed. The formula to calculate it is shown below:
+ *          RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
  */
-uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel);
 
 /*!
  * @brief Gets the eDMA channel error status flags.
  *
  * @param base eDMA peripheral base address.
- * @return The mask of error status flags. User need to use the
- *         _edma_error_status_flags type to decode the return variables.
+ * @return The mask of error status flags. Users need to use the
+*         _edma_error_status_flags type to decode the return variables.
  */
 static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
 {
@@ -731,7 +742,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @return The mask of channel status flags. User need to use the
+ * @return The mask of channel status flags. Users need to use the
  *         _edma_channel_status_flags type to decode the return variables.
  */
 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
@@ -741,7 +752,7 @@
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of channel status to be cleared. User need to use
+ * @param mask The mask of channel status to be cleared. Users need to use
  *             the defined _edma_channel_status_flags type.
  */
 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -754,8 +765,8 @@
 /*!
  * @brief Creates the eDMA handle.
  *
- * This function is called if using transaction API for eDMA. This function
- * initializes the internal state of eDMA handle.
+ * This function is called if using the transactional API for eDMA. This function
+ * initializes the internal state of the eDMA handle.
  *
  * @param handle eDMA handle pointer. The eDMA handle stores callback function and
  *               parameters.
@@ -765,12 +776,12 @@
 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
 
 /*!
- * @brief Installs the TCDs memory pool into eDMA handle.
+ * @brief Installs the TCDs memory pool into the eDMA handle.
  *
  * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
  *
  * @param handle eDMA handle pointer.
- * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned.
+ * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
  * @param tcdSize The number of TCD slots.
  */
 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
@@ -778,12 +789,12 @@
 /*!
  * @brief Installs a callback function for the eDMA transfer.
  *
- * This callback is called in eDMA IRQ handler. Use the callback to do something after
+ * This callback is called in the eDMA IRQ handler. Use the callback to do something after
  * the current major loop transfer completes.
  *
  * @param handle eDMA handle pointer.
  * @param callback eDMA callback function pointer.
- * @param userData Parameter for callback function.
+ * @param userData A parameter for the callback function.
  */
 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
 
@@ -801,8 +812,8 @@
  * @param transferBytes eDMA transfer bytes to be transferred.
  * @param type eDMA transfer type.
  * @note The data address and the data width must be consistent. For example, if the SRC
- *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
- *       source address error(SAE).
+ *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
+ *       source address error (SAE).
  */
 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
                           void *srcAddr,
@@ -817,7 +828,7 @@
  * @brief Submits the eDMA transfer request.
  *
  * This function submits the eDMA transfer request according to the transfer configuration structure.
- * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * If submitting the transfer request repeatedly, this function packs an unprocessed request as
  * a TCD and enables scatter/gather feature to process it in the next time.
  *
  * @param handle eDMA handle pointer.
@@ -829,9 +840,9 @@
 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
 
 /*!
- * @brief eDMA start transfer.
+ * @brief eDMA starts transfer.
  *
- * This function enables the channel request. User can call this function after submitting the transfer request
+ * This function enables the channel request. Users can call this function after submitting the transfer request
  * or before submitting the transfer request.
  *
  * @param handle eDMA handle pointer.
@@ -839,9 +850,9 @@
 void EDMA_StartTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA stop transfer.
+ * @brief eDMA stops transfer.
  *
- * This function disables the channel request to pause the transfer. User can call EDMA_StartTransfer()
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
  * again to resume the transfer.
  *
  * @param handle eDMA handle pointer.
@@ -849,20 +860,40 @@
 void EDMA_StopTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA abort transfer.
+ * @brief eDMA aborts transfer.
  *
  * This function disables the channel request and clear transfer status bits.
- * User can submit another transfer after calling this API.
+ * Users can submit another transfer after calling this API.
  *
  * @param handle DMA handle pointer.
  */
 void EDMA_AbortTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA IRQ handler for current major loop transfer complete.
+ * @brief eDMA IRQ handler for the current major loop transfer completion.
+ *
+ * This function clears the channel major interrupt flag and calls
+ * the callback function if it is not NULL.
+ *
+ * Note:
+ * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
+ * These include the final address adjustments and reloading of the BITER field into the CITER.
+ * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
+ * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
  *
- * This function clears the channel major interrupt flag and call
- * the callback function if it is not NULL.
+ * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
+ * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
+ * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
+ * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
+ * been loaded into the eDMA engine at this point already.).
+ *
+ * For the last two continuous ISRs in a scatter/gather process, they  both load the last TCD (The last ISR does not
+ * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
+ * Therefore, ensure that the header and tcdUsed updated are identical for them.
+ * tcdUsed are both 0 in this case as no TCD to be loaded.
+ *
+ * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
+ * further details.
  *
  * @param handle eDMA handle pointer.
  */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_enet.h"
 
@@ -90,10 +90,8 @@
 #define ENET_IPV6VERSION 0x0006U
 /*! @brief Ethernet mac address length. */
 #define ENET_FRAME_MACLEN 6U
-/*! @brief Ethernet Frame header length. */
-#define ENET_FRAME_HEADERLEN 14U
 /*! @brief Ethernet VLAN header length. */
-#define ENET_FRAME_VLAN_HEADERLEN 18U
+#define ENET_FRAME_VLAN_TAGLEN 4U
 /*! @brief MDC frequency. */
 #define ENET_MDC_FREQUENCY 2500000U
 /*! @brief NanoSecond in one second. */
@@ -238,8 +236,10 @@
 /*! @brief Pointers to enet handles for each instance. */
 static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL};
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to enet clocks for each instance. */
 const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to enet transmit IRQ number for each instance. */
 static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
@@ -259,6 +259,7 @@
 static enet_isr_t s_enetTxIsr;
 static enet_isr_t s_enetRxIsr;
 static enet_isr_t s_enetErrIsr;
+static enet_isr_t s_enetTsIsr;
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -268,7 +269,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_ENET_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++)
     {
         if (s_enetBases[instance] == base)
         {
@@ -276,7 +277,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_ENET_COUNT);
+    assert(instance < ARRAY_SIZE(s_enetBases));
 
     return instance;
 }
@@ -314,10 +315,11 @@
     assert(bufferConfig->rxBufferAlign);
     assert(macAddr);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     uint32_t instance = ENET_GetInstance(base);
-
     /* Ungate ENET clock. */
     CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset ENET module. */
     ENET_Reset(base);
@@ -346,8 +348,10 @@
     /* Disable ENET. */
     base->ECR &= ~ENET_ECR_ETHEREN_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disables the clock source. */
     CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData)
@@ -407,7 +411,13 @@
     uint32_t tcr = 0;
     uint32_t ecr = 0;
     uint32_t macSpecialConfig = config->macSpecialConfig;
-    uint32_t instance = ENET_GetInstance(base);
+    uint32_t maxFrameLen = config->rxMaxFrameLen;
+
+    /* Maximum frame length check. */
+    if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN))
+    {
+        maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN);
+    }
 
     /* Configures MAC receive controller with user configure structure. */
     rcr = ENET_RCR_NLC(!!(macSpecialConfig & kENET_ControlRxPayloadCheckEnable)) |
@@ -417,16 +427,16 @@
           ENET_RCR_BC_REJ(!!(macSpecialConfig & kENET_ControlRxBroadCastRejectEnable)) |
           ENET_RCR_PROM(!!(macSpecialConfig & kENET_ControlPromiscuousEnable)) | ENET_RCR_MII_MODE(1) |
           ENET_RCR_RMII_MODE(config->miiMode) | ENET_RCR_RMII_10T(!config->miiSpeed) |
-          ENET_RCR_MAX_FL(config->rxMaxFrameLen) | ENET_RCR_CRCFWD(1);
+          ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD(1);
     /* Receive setting for half duplex. */
     if (config->miiDuplex == kENET_MiiHalfDuplex)
     {
-        rcr |= ENET_RCR_DRT(1);
+        rcr |= ENET_RCR_DRT_MASK;
     }
     /* Sets internal loop only for MII mode. */
     if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode == kENET_MiiMode))
     {
-        rcr |= ENET_RCR_LOOP(1);
+        rcr |= ENET_RCR_LOOP_MASK;
         rcr &= ~ENET_RCR_DRT_MASK;
     }
     base->RCR = rcr;
@@ -446,7 +456,7 @@
         uint32_t reemReg;
         base->OPD = config->pauseDuration;
         reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold);
-#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
+#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
         reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold);
 #endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */
         base->RSEM = reemReg;
@@ -492,7 +502,22 @@
         ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable));
     }
 
-    /* Enables Ethernet interrupt and NVIC. */
+/* Enables Ethernet interrupt and NVIC. */
+#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+    if (config->intCoalesceCfg)
+    {
+        uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK);
+
+        /* Clear all buffer interrupts. */
+        base->EIMR &= ~intMask;
+
+        /* Set the interrupt coalescence. */
+        base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) |
+                     config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK;
+        base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) |
+                     config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK;
+    }
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
     ENET_EnableInterrupts(base, config->interrupt);
 
     /* ENET control register setting. */
@@ -545,7 +570,6 @@
         /* Increase the index. */
         curBuffDescrip++;
     }
-
 }
 
 static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign,
@@ -688,6 +712,46 @@
     base->MMFR = mmfr;
 }
 
+#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+    uint32_t mmfr = 0;
+
+    /* Parse the address from the input register. */
+    uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU;
+    uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU);
+
+    /* Address write firstly. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
+    base->MMFR = mmfr;
+
+    /* Build MII write command. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(data);
+    base->MMFR = mmfr;
+}
+
+void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
+{
+    uint32_t mmfr = 0;
+
+    /* Parse the address from the input register. */
+    uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU;
+    uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU);
+
+    /* Address write firstly. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
+    base->MMFR = mmfr;
+
+    /* Build MII read command. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2);
+    base->MMFR = mmfr;
+}
+#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic)
 {
     assert(handle);
@@ -769,13 +833,15 @@
     assert(handle->rxBdCurrent);
     assert(length);
 
+    /* Reset the length to zero. */
+    *length = 0;
+
     uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
     volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent;
 
     /* Check the current buffer descriptor's empty flag.  if empty means there is no frame received. */
     if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)
     {
-        *length = 0;
         return kStatus_ENET_RxFrameEmpty;
     }
 
@@ -791,7 +857,6 @@
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
                     )
             {
-                *length = 0;
                 return kStatus_ENET_RxFrameError;
             }
             /* FCS is removed by MAC. */
@@ -821,8 +886,9 @@
 
     uint32_t len = 0;
     uint32_t offset = 0;
+    uint16_t control;
     bool isLastBuff = false;
-    volatile enet_rx_bd_struct_t *curBuffDescrip;
+    volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent;
     status_t result = kStatus_Success;
 
     /* For data-NULL input, only update the buffer descriptor. */
@@ -830,37 +896,24 @@
     {
         do
         {
-            /* Get the current buffer descriptor. */
-            curBuffDescrip = handle->rxBdCurrent;
-            /* Increase current buffer descriptor to the next one. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
+            /* Update the control flag. */
+            control = handle->rxBdCurrent->control;
+            /* Updates the receive buffer descriptors. */
+            ENET_UpdateReadBuffers(base, handle);
+
+            /* Find the last buffer descriptor for the frame. */
+            if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
             {
-                handle->rxBdCurrent = handle->rxBdBase;
-            }
-            else
-            {
-                handle->rxBdCurrent++;
+                break;
             }
 
-            /* The last buffer descriptor of a frame. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
-            {
-                /* Find the last buffer descriptor for the frame*/
-                break;
-            }
-        } while (handle->rxBdCurrent != handle->rxBdDirty);
-
-        /* Update all receive buffer descriptors for the whole frame. */
-        ENET_UpdateReadBuffers(base, handle);
+        } while (handle->rxBdCurrent != curBuffDescrip);
 
         return result;
     }
     else
     {
-        /* Frame read from the MAC to user buffer and update the buffer descriptors.
-        Process the frame, a frame on several receive buffers are considered . */
-        /* Get the current buffer descriptor. */
-        curBuffDescrip = handle->rxBdCurrent;
+/* A frame on one buffer or several receive buffers are both considered. */
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         enet_ptp_time_data_t ptpTimestamp;
         bool isPtpEventMessage = false;
@@ -871,16 +924,6 @@
 
         while (!isLastBuff)
         {
-            /* Increase current buffer descriptor to the next one. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
-            {
-                handle->rxBdCurrent = handle->rxBdBase;
-            }
-            else
-            {
-                handle->rxBdCurrent++;
-            }
-
             /* The last buffer descriptor of a frame. */
             if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
             {
@@ -900,28 +943,39 @@
                         result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp);
                     }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
+
+                    /* Updates the receive buffer descriptors. */
                     ENET_UpdateReadBuffers(base, handle);
                     return result;
                 }
+                else
+                {
+                    /* Updates the receive buffer descriptors. */
+                    ENET_UpdateReadBuffers(base, handle);
+                }
             }
             else
             {
-                /* Store the fragments of a frame on several buffer descriptors. */
+                /* Store a frame on several buffer descriptors. */
                 isLastBuff = false;
-                memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
-                offset += handle->rxBuffSizeAlign;
+                /* Length check. */
                 if (offset >= length)
                 {
                     break;
                 }
+
+                memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
+                offset += handle->rxBuffSizeAlign;
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateReadBuffers(base, handle);
             }
 
             /* Get the current buffer descriptor. */
             curBuffDescrip = handle->rxBdCurrent;
         }
-        /* All error happens will break the while loop and arrive here to update receive buffers. */
-        ENET_UpdateReadBuffers(base, handle);
     }
+
     return kStatus_ENET_RxFrameFail;
 }
 
@@ -929,26 +983,23 @@
 {
     assert(handle);
 
-    do
+    /* Clears status. */
+    handle->rxBdCurrent->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK;
+    /* Sets the receive buffer descriptor with the empty flag. */
+    handle->rxBdCurrent->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
+
+    /* Increase current buffer descriptor to the next one. */
+    if (handle->rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
     {
-        /* Clears status. */
-        handle->rxBdDirty->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK;
-        /* Sets the receive buffer descriptor with the empty flag. */
-        handle->rxBdDirty->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
-        /* Increases the buffer descriptor to the next one. */
-        if (handle->rxBdDirty->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
-        {
-            handle->rxBdDirty = handle->rxBdBase;
-        }
-        else
-        {
-            handle->rxBdDirty++;
-        }
+        handle->rxBdCurrent = handle->rxBdBase;
+    }
+    else
+    {
+        handle->rxBdCurrent++;
+    }
 
-        /* Actives the receive buffer descriptor. */
-        base->RDAR = ENET_RDAR_RDAR_MASK;
-
-    } while (handle->rxBdDirty != handle->rxBdCurrent);
+    /* Actives the receive buffer descriptor. */
+    base->RDAR = ENET_RDAR_RDAR_MASK;
 }
 
 status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
@@ -956,7 +1007,7 @@
     assert(handle);
     assert(handle->txBdCurrent);
     assert(data);
-    assert(length <= (ENET_FRAME_MAX_VALNFRAMELEN - 4));
+    assert(length <= ENET_FRAME_MAX_FRAMELEN);
 
     volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdCurrent;
     uint32_t len = 0;
@@ -985,6 +1036,11 @@
         {
             curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
         }
+        else
+        {
+            curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
+        }
+
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
         curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK);
 
@@ -1013,6 +1069,10 @@
             {
                 curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
             }
+            else
+            {
+                curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
+            }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
             /* Increase the buffer descriptor address. */
@@ -1034,6 +1094,7 @@
                 curBuffDescrip->length = handle->txBuffSizeAlign;
                 len += handle->txBuffSizeAlign;
                 /* Sets the control flag. */
+                curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
                 curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
                 /* Active the transmit buffer descriptor*/
                 base->TDAR = ENET_TDAR_TDAR_MASK;
@@ -1054,7 +1115,7 @@
 
         } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
 
-        return kStatus_ENET_TxFrameFail;
+        return kStatus_ENET_TxFrameBusy;
     }
 }
 
@@ -1216,7 +1277,7 @@
     /* Check for VLAN frame. */
     if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN))
     {
-        buffer += (ENET_FRAME_VLAN_HEADERLEN - ENET_FRAME_HEADERLEN);
+        buffer += ENET_FRAME_VLAN_TAGLEN;
     }
 
     ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET);
@@ -1299,7 +1360,8 @@
 
     /* Enables the time stamp interrupt for the master clock on a device. */
     ENET_EnableInterrupts(base, kENET_TsTimerInterrupt);
-    /* Enables the transmit interrupt to store the transmit frame time-stamp. */
+    /* Enables only frame interrupt for transmit side to store the transmit
+    frame time-stamp when the whole frame is transmitted out. */
     ENET_EnableInterrupts(base, kENET_TxFrameInterrupt);
     ENET_DisableInterrupts(base, kENET_TxBufferInterrupt);
 
@@ -1318,6 +1380,7 @@
 
     /* Set the IRQ handler when the interrupt is enabled. */
     s_enetTxIsr = ENET_TransmitIRQHandler;
+    s_enetTsIsr = ENET_Ptp1588TimerIRQHandler;
     EnableIRQ(s_enetTsIrqId[instance]);
     EnableIRQ(s_enetTxIrqId[instance]);
 }
@@ -1624,8 +1687,8 @@
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         if (base->EIR & kENET_TxFrameInterrupt)
         {
-        /* Store the transmit timestamp from the buffer descriptor should be done here. */
-        ENET_StoreTxFrameTime(base, handle);
+            /* Store the transmit timestamp from the buffer descriptor should be done here. */
+            ENET_StoreTxFrameTime(base, handle);
         }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
@@ -1665,7 +1728,7 @@
     uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt |
                        kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt;
 
-    /* Check if the PTP time stamp interrupt happen. */
+    /* Check if the error interrupt happen. */
     if (kENET_WakeupInterrupt & base->EIR)
     {
         /* Clear the wakeup interrupt. */
@@ -1680,7 +1743,7 @@
     }
     else
     {
-        /* Clear the time stamp interrupt. */
+        /* Clear the error interrupt event status. */
         errMask &= base->EIR;
         base->EIR = errMask;
         /* Callback function. */
@@ -1721,13 +1784,34 @@
         }
     }
 }
-
-void ENET_1588_Timer_IRQHandler(void)
-{
-    ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
-}
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
+void ENET_CommonFrame0IRQHandler(ENET_Type *base)
+{
+    uint32_t event = base->EIR;
+    uint32_t instance = ENET_GetInstance(base);
+
+    if (event & ENET_TX_INTERRUPT)
+    {
+        s_enetTxIsr(base, s_ENETHandle[instance]);
+    }
+
+    if (event & ENET_RX_INTERRUPT)
+    {
+        s_enetRxIsr(base, s_ENETHandle[instance]);
+    }
+
+    if (event & ENET_TS_INTERRUPT)
+    {
+        s_enetTsIsr(base, s_ENETHandle[instance]);
+    }
+    if (event & ENET_ERR_INTERRUPT)
+    {
+        s_enetErrIsr(base, s_ENETHandle[instance]);
+    }
+}
+
+#if defined(ENET)
 void ENET_Transmit_IRQHandler(void)
 {
     s_enetTxIsr(ENET, s_ENETHandle[0]);
@@ -1742,3 +1826,10 @@
 {
     s_enetErrIsr(ENET, s_ENETHandle[0]);
 }
+
+void ENET_1588_Timer_IRQHandler(void)
+{
+    s_enetTsIsr(ENET, s_ENETHandle[0]);
+}
+#endif
+

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
 /*@}*/
 
 /*! @name Control and status region bit masks of the receive buffer descriptor. */
@@ -124,18 +123,18 @@
 #endif
 #define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt)
 #define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)
+#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt)
 #define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \
     kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt)
 
+
 /*! @name Defines the maximum Ethernet frame size. */
 /*@{*/
-#define ENET_FRAME_MAX_FRAMELEN 1518U     /*!< Maximum Ethernet frame size. */
-#define ENET_FRAME_MAX_VALNFRAMELEN 1522U /*!< Maximum VLAN frame size. */
+#define ENET_FRAME_MAX_FRAMELEN 1518U     /*!< Default maximum Ethernet frame size. */
 /*@}*/
 
 #define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */
 #define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */
-#define ENET_BUFF_ALIGNMENT 16U /*!< Ethernet buffer alignment. */
 
 /*! @brief Defines the PHY address scope for the ENET. */
 #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT)
@@ -191,6 +190,15 @@
     kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */
 } enet_mii_read_t;
 
+#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */
+typedef enum _enet_mii_extend_opcode {
+    kENET_MiiAddrWrite_C45 = 0U,  /*!< Address Write operation. */
+    kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */
+    kENET_MiiReadFrame_C45 = 3U   /*!< Read frame operation for a valid MII management frame. */
+} enet_mii_extend_opcode;
+#endif  /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 /*! @brief Defines a special configuration for ENET MAC controller.
  *
  * These control flags are provided for special user requirements.
@@ -237,12 +245,9 @@
     kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK,    /*!< Collision Retry Limit interrupt source */
     kENET_UnderrunInterrupt = ENET_EIR_UN_MASK,      /*!< Transmit FIFO underrun interrupt source */
     kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK,    /*!< Payload Receive interrupt source */
-    kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK     /*!< WAKEUP interrupt source */
-#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
-    ,
+    kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK,     /*!< WAKEUP interrupt source */
     kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */
     kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK  /*!< TS WRAP interrupt source for PTP */
-#endif                                               /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_interrupt_enable_t;
 
 /*! @brief Defines the common interrupt event for callback use. */
@@ -252,10 +257,8 @@
     kENET_TxEvent,     /*!< Transmit event. */
     kENET_ErrEvent,    /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */
     kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */
-#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
     kENET_TimeStampEvent,     /*!< Time stamp event. */
     kENET_TimeStampAvailEvent /*!< Time stamp available event.*/
-#endif                        /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_event_t;
 
 /*! @brief Defines the transmit accelerator configuration. */
@@ -380,15 +383,20 @@
 #endif                                   /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_data_error_stats_t;
 
-/*! @brief Defines the receive buffer descriptor configure structure.
+/*! @brief Defines the receive buffer descriptor configuration structure.
  *
- * Note: For the internal DMA requirements, the buffers have a corresponding alignment requirement:
- * 1. The aligned receive and transmit buffer size must be evenly divisible by 16.
+ * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.
+ * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT.
+ *    when the data buffers are in cacheable region when cache is enabled, all those size should be
+ *    aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size.
  * 2. The aligned transmit and receive buffer descriptor start address must be at
- *    least 64 bit aligned. However, it's recommended to be evenly divisible by 16.
- * 3. The aligned transmit and receive buffer start address must be evenly divisible by 16.
+ *    least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT.
+ *    buffer descriptors should be put in non-cacheable region when cache is enabled.
+ * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT.
  *    Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign".
  *    Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign".
+ *    when the data buffers are in cacheable region when cache is enabled, all those size should be
+ *    aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 
  */
 typedef struct _enet_buffer_config
 {
@@ -429,7 +437,7 @@
     enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */
 } enet_ptp_time_data_ring_t;
 
-/*! @brief Defines the ENET PTP configure structure. */
+/*! @brief Defines the ENET PTP configuration structure. */
 typedef struct _enet_ptp_config
 {
     uint8_t ptpTsRxBuffNum;            /*!< Receive 1588 timestamp buffer number*/
@@ -441,19 +449,28 @@
 } enet_ptp_config_t;
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
-
+#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+/*! @brief Defines the interrupt coalescing configure structure. */
+typedef struct _enet_intcoalesce_config
+{
+    uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */
+    uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */
+    uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */
+    uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */
+} enet_intcoalesce_config_t;
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
 
 /*! @brief Defines the basic configuration structure for the ENET device.
  *
  * Note:
- *  1. macSpecialConfig is used for a special control configuration, A logical OR of
+ *  1. macSpecialConfig is used for a special control configuration, a logical OR of
  *  "enet_special_control_flag_t". For a special configuration for MAC,
  *  set this parameter to 0.
- *  2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes:
+ *  2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes.
  *  0/1  - 64 bytes written to TX FIFO before transmission of a frame begins.
  *  2    - 128 bytes written to TX FIFO ....
  *  3    - 192 bytes written to TX FIFO ....
- *  The maximum of txWatermark is 0x2F   - 4032 bytes written to TX FIFO ....
+ *  The maximum of txWatermark is 0x2F   - 4032 bytes written to TX FIFO.
  *  txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1
  *  or for larger bus access latency 3 or larger due to contention for the system bus.
  *  3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX.
@@ -485,7 +502,7 @@
     uint16_t pauseDuration;       /*!< For flow control enabled case: Pause duration. */
     uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case:  when RX FIFO level reaches this value,
                                      it makes MAC generate XOFF pause frame. */
-#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
+#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
     uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO,
                                     independent of size, that can be accept. If the limit is reached, reception
                                     continues and a pause frame is triggered. */
@@ -494,6 +511,10 @@
                                       the MAC receive ready status. */
     uint8_t txFifoWatermark;          /*!< For store and forward disable case, the data required in TX FIFO
                                       before a frame transmit start. */
+#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+    enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set
+                                         to NULL. */
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
 } enet_config_t;
 
 /* Forward declaration of the handle typedef. */
@@ -507,7 +528,6 @@
 {
     volatile enet_rx_bd_struct_t *rxBdBase;    /*!< Receive buffer descriptor base address pointer. */
     volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */
-    volatile enet_rx_bd_struct_t *rxBdDirty;   /*!< The dirty receive buffer descriptor needed to be updated from. */
     volatile enet_tx_bd_struct_t *txBdBase;    /*!< Transmit buffer descriptor base address pointer. */
     volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */
     volatile enet_tx_bd_struct_t *txBdDirty;   /*!< The dirty transmit buffer descriptor needed to be updated from. */
@@ -533,7 +553,7 @@
 #endif
 
 /*!
-  * @name Initialization and De-initialization
+  * @name Initialization and de-initialization
   * @{
   */
 
@@ -541,10 +561,10 @@
  * @brief Gets the ENET default configuration structure.
  *
  * The purpose of this API is to get the default ENET MAC controller
- * configure structure for ENET_Init(). User may use the initialized
- * structure unchanged in ENET_Init(), or modify some fields of the
+ * configuration structure for ENET_Init(). Users may use the initialized
+ * structure unchanged in ENET_Init() or modify fields of the
  * structure before calling ENET_Init().
- * Example:
+ * This is an example.
    @code
    enet_config_t config;
    ENET_GetDefaultConfig(&config);
@@ -560,18 +580,18 @@
  *
  * @param base    ENET peripheral base address.
  * @param handle  ENET handler pointer.
- * @param config  ENET mac configuration structure pointer.
+ * @param config  ENET Mac configuration structure pointer.
  *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
  *        can be used directly. It is also possible to verify the Mac configuration using other methods.
  * @param bufferConfig  ENET buffer configuration structure pointer.
  *        The buffer configuration should be prepared for ENET Initialization.
- * @param macAddr  ENET mac address of Ethernet device. This MAC address should be
+ * @param macAddr  ENET mac address of the Ethernet device. This Mac address should be
  *        provided.
  * @param srcClock_Hz The internal module clock source for MII clock.
  *
- * @note ENET has two buffer descriptors: legacy buffer descriptors and
- * enhanced 1588 buffer descriptors. The legacy descriptor is used by default. To
- * use 1588 feature, use the enhanced 1588 buffer descriptor
+ * @note ENET has two buffer descriptors legacy buffer descriptors and
+ * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To
+ * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor
  * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure()
  * to configure the 1588 feature and related buffers after calling ENET_Init().
  */
@@ -593,8 +613,8 @@
 /*!
  * @brief Resets the ENET module.
  *
- * This function restores the ENET module to reset state.
- * Note that this function sets all registers to
+ * This function restores the ENET module to the reset state.
+ * Note that this function sets all registers to the
  * reset state. As a result, the ENET module can't work after calling this function.
  *
  * @param base  ENET peripheral base address.
@@ -621,7 +641,7 @@
 void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex);
 
 /*!
- * @brief Sets the ENET SMI(serial management interface)- MII management interface.
+ * @brief Sets the ENET SMI (serial management interface) - MII management interface.
  *
  * @param base  ENET peripheral base address.
  * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution.
@@ -634,7 +654,7 @@
 /*!
  * @brief Gets the ENET SMI- MII management interface configuration.
  *
- * This API is used to get the SMI configuration to check if the MII management
+ * This API is used to get the SMI configuration to check whether the MII management
  * interface has been set.
  *
  * @param base  ENET peripheral base address.
@@ -646,7 +666,7 @@
 }
 
 /*!
- * @brief Reads data from the PHY register through SMI interface.
+ * @brief Reads data from the PHY register through an SMI interface.
  *
  * @param base  ENET peripheral base address.
  * @return The data read from PHY
@@ -667,7 +687,7 @@
 void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation);
 
 /*!
- * @brief Starts a SMI write command.
+ * @brief Starts an SMI write command.
  *
  * @param base  ENET peripheral base address.
  * @param phyAddr The PHY address.
@@ -677,6 +697,31 @@
  */
 void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data);
 
+#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+/*!
+ * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ */
+void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg);
+
+/*!
+ * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ * @param data The data written to PHY.
+ */
+void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 /* @} */
 
 /*!
@@ -721,7 +766,7 @@
 /* @} */
 
 /*!
- * @name Other basic operation
+ * @name Other basic operations
  * @{
  */
 
@@ -762,13 +807,13 @@
 }
 
 /*!
- * @brief Gets ENET transmit and receive accelerator functions from MAC controller.
+ * @brief Gets ENET transmit and receive accelerator functions from the MAC controller.
  *
  * @param base  ENET peripheral base address.
  * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is
- *         recommended to be used to as the mask to get the exact the accelerator option.
+ *         recommended  as the mask to get the exact the accelerator option.
  * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is
- *         recommended to be used to as the mask to get the exact the accelerator option.
+ *         recommended as the mask to get the exact the accelerator option.
  */
 static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)
 {
@@ -782,7 +827,7 @@
 /* @} */
 
 /*!
- * @name Interrupts.
+ * @name Interrupts
  * @{
  */
 
@@ -791,7 +836,7 @@
  *
  * This function enables the ENET interrupt according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t.
- * For example, to enable the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to enable the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -810,7 +855,7 @@
  *
  * This function disables the ENET interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t.
- * For example, to disable the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to disable the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -841,7 +886,7 @@
  *
  * This function clears enabled ENET interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t.
- * For example, to clear the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -863,8 +908,8 @@
  */
 
 /*!
- * @brief Set the callback function.
- * This API is provided for application callback required case when ENET
+ * @brief Sets the callback function.
+ * This API is provided for the application callback required case when ENET
  * interrupt is enabled. This API should be called after calling ENET_Init.
  *
  * @param handle ENET handler pointer. Should be provided by application.
@@ -879,7 +924,7 @@
  * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame().
  * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError,
  * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics.
- * For example:
+ * This is an example.
  * @code
  *       status = ENET_GetRxFrameSize(&g_handle, &length);
  *       if (status == kStatus_ENET_RxFrameError)
@@ -911,29 +956,54 @@
  */
 status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic);
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
-       /*!
-       * @brief Gets the size of the read frame.
-       * This function reads a received frame size from the ENET buffer descriptors.
-       * @note The FCS of the frame is removed by MAC controller and the size is the length without the FCS.
-       * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
-       * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
-       *
-       * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
-       * @param length The length of the valid frame received.
-       * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
-       * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
-       *         and NULL length to update the receive buffers.
-       * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
-       *         should be called with the right data buffer and the captured data length input.
-       */
+/*!
+* @brief Gets the size of the read frame.
+* This function gets a received frame size from the ENET buffer descriptors.
+* @note The FCS of the frame is automatically removed by Mac and the size is the length without the FCS.
+* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+*
+* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+* @param length The length of the valid frame received.
+* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+*         and NULL length to update the receive buffers.
+* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+*         should be called with the right data buffer and the captured data length input.
+*/
 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length);
 
 /*!
  * @brief Reads a frame from the ENET device.
  * This function reads a frame (both the data and the length) from the ENET buffer descriptors.
  * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
- * @note The FCS of the frame is removed by MAC controller and is not delivered to the application.
- *
+ * This is an example.
+ * @code
+ *       uint32_t length;
+ *       enet_handle_t g_handle;
+ *       //Get the received frame size firstly.
+ *       status = ENET_GetRxFrameSize(&g_handle, &length);
+ *       if (length != 0)
+ *       {
+ *           //Allocate memory here with the size of "length"
+ *           uint8_t *data = memory allocate interface;
+ *           if (!data)
+ *           {
+ *               ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *               //Add the console warning log.
+ *           }
+ *           else
+ *           {
+ *              status = ENET_ReadFrame(ENET, &g_handle, data, length);
+ *              //Call stack input API to deliver the data to stack
+ *           }
+ *       }
+ *       else if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *          //Update the received buffer when a error frame is received.
+ *           ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *       }
+ * @endcode
  * @param base  ENET peripheral base address.
  * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
  * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
@@ -952,8 +1022,10 @@
  * @param data The data buffer provided by user to be send.
  * @param length The length of the data to be send.
  * @retval kStatus_Success  Send frame succeed.
- * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmit.
- * @retval kStatus_ENET_TxFrameFail  Transmit frame fail.
+ * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
  */
 status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length);
 
@@ -981,6 +1053,14 @@
  */
 void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle);
 
+/*!
+ * @brief the common IRQ handler for the tx/rx/error etc irq handler.
+ *
+ * This is used for the combined tx/rx/error interrupt for single ring (ring 0).
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_CommonFrame0IRQHandler(ENET_Type *base);
 /* @} */
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -990,7 +1070,7 @@
  */
 
 /*!
- * @brief Configures the ENET PTP 1588 feature with the basic configuration.
+ * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration.
  * The function sets the clock for PTP 1588 timer and enables
  * time stamp interrupts and transmit interrupts for PTP 1588 features.
  * This API should be called when the 1588 feature is enabled
@@ -1044,7 +1124,7 @@
 void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod);
 
 /*!
- * @brief Sets ENET PTP 1588 timer channel mode.
+ * @brief Sets the ENET PTP 1588 timer channel mode.
  *
  * @param base  ENET peripheral base address.
  * @param channel The ENET PTP timer channel number.
@@ -1064,8 +1144,55 @@
     base->CHANNEL[channel].TCSR = tcrReg;
 }
 
+#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
 /*!
- * @brief Sets ENET PTP 1588 timer channel comparison value.
+ * @brief Sets ENET PTP 1588 timer channel mode pulse width.
+ *
+ * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare
+ * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock.
+ * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. 
+ * so call this function if you need to set the timer channel mode for 
+ * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare
+ * with pulse width more than one 1588 clock,
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The ENET PTP timer channel number.
+ * @param isOutputLow  True --- timer channel is configured for output compare 
+ *                              pulse output low.
+ *                     false --- timer channel is configured for output compare
+ *                              pulse output high.
+ * @param pulseWidth  The pulse width control value, range from 0 ~ 31.
+ *                     0  --- pulse width is one 1588 clock cycle.
+ *                     31 --- pulse width is thirty two 1588 clock cycles.      
+ * @param intEnable Enables or disables the interrupt.
+ */
+static inline void ENET_Ptp1588SetChannelOutputPulseWidth(ENET_Type *base,
+                                              enet_ptp_timer_channel_t channel,
+                                              bool isOutputLow,
+                                              uint8_t pulseWidth,
+                                              bool intEnable)
+{
+    uint32_t tcrReg;
+
+    tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth);
+    
+    if (isOutputLow)
+    {
+        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare);
+    }
+    else
+    {
+        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare);
+    }
+
+    /* Disable channel mode first. */
+    base->CHANNEL[channel].TCSR = 0;
+    base->CHANNEL[channel].TCSR = tcrReg;
+}
+#endif   /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */
+
+/*!
+ * @brief Sets the ENET PTP 1588 timer channel comparison value.
  *
  * @param base  ENET peripheral base address.
  * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t".

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -40,7 +40,12 @@
 
     uint32_t value = 0U;
 
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif
     value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) |
             EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt);
 #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
@@ -59,7 +64,12 @@
 void EWM_Deinit(EWM_Type *base)
 {
     EWM_DisableInterrupts(base, kEWM_InterruptEnable);
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
 }
 
 void EWM_GetDefaultConfig(ewm_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup ewm_driver
+ * @addtogroup ewm
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -49,14 +48,14 @@
 #define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-/*! @brief Describes ewm clock source. */
+/*! @brief Describes EWM clock source. */
 #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
 typedef enum _ewm_lpo_clock_source
 {
-    kEWM_LpoClockSource0 = 0U, /*!< ewm clock sourced from lpo_clk[0]*/
-    kEWM_LpoClockSource1 = 1U, /*!< ewm clock sourced from lpo_clk[1]*/
-    kEWM_LpoClockSource2 = 2U, /*!< ewm clock sourced from lpo_clk[2]*/
-    kEWM_LpoClockSource3 = 3U, /*!< ewm clock sourced from lpo_clk[3]*/
+    kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/
+    kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/
+    kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/
+    kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/
 } ewm_lpo_clock_source_t;
 #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
 
@@ -77,18 +76,18 @@
 #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
     uint8_t prescaler;        /*!< Clock prescaler value */
 #endif                        /* FSL_FEATURE_EWM_HAS_PRESCALER */
-    uint8_t compareLowValue;  /*!< Compare low register value */
-    uint8_t compareHighValue; /*!< Compare high register value */
+    uint8_t compareLowValue;  /*!< Compare low-register value */
+    uint8_t compareHighValue; /*!< Compare high-register value */
 } ewm_config_t;
 
 /*!
- * @brief EWM interrupt configuration structure, default settings all disabled.
+ * @brief EWM interrupt configuration structure with default settings all disabled.
  *
- * This structure contains the settings for all of the EWM interrupt configurations.
+ * This structure contains the settings for all of EWM interrupt configurations.
  */
 enum _ewm_interrupt_enable_t
 {
-    kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/
+    kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/
 };
 
 /*!
@@ -98,7 +97,7 @@
  */
 enum _ewm_status_flags_t
 {
-    kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when ewm is enabled*/
+    kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/
 };
 
 /*******************************************************************************
@@ -110,7 +109,7 @@
 #endif /* __cplusplus */
 
 /*!
- * @name EWM Initialization and De-initialization
+ * @name EWM initialization and de-initialization
  * @{
  */
 
@@ -119,10 +118,10 @@
  *
  * This function is used to initialize the EWM. After calling, the EWM
  * runs immediately according to the configuration.
- * Note that except for interrupt enable control bit, other control bits and registers are write once after a
+ * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
  * CPU reset. Modifying them more than once generates a bus transfer error.
  *
- * Example:
+ * This is an example.
  * @code
  *   ewm_config_t config;
  *   EWM_GetDefaultConfig(&config);
@@ -131,7 +130,7 @@
  * @endcode
  *
  * @param base EWM peripheral base address
- * @param config The configuration of EWM
+ * @param config The configuration of the EWM
 */
 void EWM_Init(EWM_Type *base, const ewm_config_t *config);
 
@@ -147,8 +146,8 @@
 /*!
  * @brief Initializes the EWM configuration structure.
  *
- * This function initializes the EWM configure structure to default values. The default
- * values are:
+ * This function initializes the EWM configuration structure to default values. The default
+ * values are as follows.
  * @code
  *   ewmConfig->enableEwm = true;
  *   ewmConfig->enableEwmInput = false;
@@ -160,7 +159,7 @@
  *   ewmConfig->compareHighValue = 0xFEU;
  * @endcode
  *
- * @param config Pointer to EWM configuration structure.
+ * @param config Pointer to the EWM configuration structure.
  * @see ewm_config_t
  */
 void EWM_GetDefaultConfig(ewm_config_t *config);
@@ -179,7 +178,7 @@
  *
  * @param base EWM peripheral base address
  * @param mask The interrupts to enable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined
  *        @arg kEWM_InterruptEnable
  */
 static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)
@@ -194,7 +193,7 @@
  *
  * @param base EWM peripheral base address
  * @param mask The interrupts to disable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined
  *        @arg kEWM_InterruptEnable
  */
 static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)
@@ -203,19 +202,19 @@
 }
 
 /*!
- * @brief Gets EWM all status flags.
+ * @brief Gets all status flags.
  *
  * This function gets all status flags.
  *
- * Example for getting Running Flag:
+ * This is an example for getting the running flag.
  * @code
  *   uint32_t status;
  *   status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;
  * @endcode
  * @param base        EWM peripheral base address
  * @return            State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t
- *                    - true: related status flag has been set.
- *                    - false: related status flag is not set.
+ *                    - True: a related status flag has been set.
+ *                    - False: a related status flag is not set.
  */
 static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
 {
@@ -223,9 +222,9 @@
 }
 
 /*!
- * @brief Service EWM.
+ * @brief Services the EWM.
  *
- * This function reset EWM counter to zero.
+ * This function resets the EWM counter to zero.
  *
  * @param base EWM peripheral base address
 */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,6 +38,7 @@
  * @name Misc utility defines
  * @{
  */
+/*! @brief Alignment utility. */
 #ifndef ALIGN_DOWN
 #define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
 #endif
@@ -45,18 +46,74 @@
 #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
 #endif
 
-#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU))
-#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU))
-#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU))
-#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU))
-#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU))
-#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \
-    ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU))
-#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w)                                                      \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \
-     ((uint32_t)(w)&0xFFU))
+/*! @brief Join bytes to word utility. */
+#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24)
+#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16)
+#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8)
+#define B1P1(b) ((uint32_t)(b)&0xFFU)
+#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16)
+#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8)
+#define B2P1(b) ((uint32_t)(b)&0xFFFFU)
+#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8)
+#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU)
+#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y))
+#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y))
+#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y))
+#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z))
+#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z))
+#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z))
+#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w))
+/*@}*/
+
+/*!
+ * @name Secondary flash configuration
+ * @{
+ */
+/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK)
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1)
+#else
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0)
+#endif
+
+/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK)
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1)
+#else
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0)
+#endif
+/*@}*/
+
+/*!
+ * @name Flash cache ands speculation control defines
+ * @{
+ */
+#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0)
+#endif
+#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0)
+#endif
+#if defined(MCM_PLACR_DFCS_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0)
+#endif
+#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0)
+#endif
+#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \
+    defined(FMC_PFB01CR_S_B_INV_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0)
+#endif
 /*@}*/
 
 /*! @brief Data flash IFR map Field*/
@@ -121,6 +178,7 @@
 #define FTFx_ERASE_BLOCK 0x08U                     /*!< ERSBLK*/
 #define FTFx_ERASE_SECTOR 0x09U                    /*!< ERSSCR*/
 #define FTFx_PROGRAM_SECTION 0x0BU                 /*!< PGMSEC*/
+#define FTFx_GENERATE_CRC 0x0CU                    /*!< CRCGEN*/
 #define FTFx_VERIFY_ALL_BLOCK 0x40U                /*!< RD1ALL*/
 #define FTFx_READ_ONCE 0x41U                       /*!< RDONCE or RDINDEX*/
 #define FTFx_PROGRAM_ONCE 0x43U                    /*!< PGMONCE or PGMINDEX*/
@@ -192,19 +250,56 @@
 /*@}*/
 
 /*!
+ * @name Common flash register access info defines
+ * @{
+ */
+#define FTFx_FCCOB3_REG (FTFx->FCCOB3)
+#define FTFx_FCCOB5_REG (FTFx->FCCOB5)
+#define FTFx_FCCOB6_REG (FTFx->FCCOB6)
+#define FTFx_FCCOB7_REG (FTFx->FCCOB7)
+
+#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK)
+#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3)
+#define FTFx_FPROTH3_REG (FTFx->FPROTH3)
+#define FTFx_FPROTH2_REG (FTFx->FPROTH2)
+#define FTFx_FPROTH1_REG (FTFx->FPROTH1)
+#define FTFx_FPROTH0_REG (FTFx->FPROTH0)
+#endif
+
+#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3)
+#define FTFx_FPROTL3_REG (FTFx->FPROTL3)
+#define FTFx_FPROTL2_REG (FTFx->FPROTL2)
+#define FTFx_FPROTL1_REG (FTFx->FPROTL1)
+#define FTFx_FPROTL0_REG (FTFx->FPROTL0)
+#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROT3)
+#define FTFx_FPROTL3_REG (FTFx->FPROT3)
+#define FTFx_FPROTL2_REG (FTFx->FPROT2)
+#define FTFx_FPROTL1_REG (FTFx->FPROT1)
+#define FTFx_FPROTL0_REG (FTFx->FPROT0)
+#endif
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+#define FTFx_FPROTSH_REG (FTFx->FPROTSH)
+#define FTFx_FPROTSL_REG (FTFx->FPROTSL)
+#endif
+
+#define FTFx_XACCH3_REG (FTFx->XACCH3)
+#define FTFx_XACCL3_REG (FTFx->XACCL3)
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+#define FTFx_XACCSH_REG (FTFx->XACCSH)
+#define FTFx_XACCSL_REG (FTFx->XACCSL)
+#endif
+/*@}*/
+
+/*!
  * @brief Enumeration for access segment property.
  */
 enum _flash_access_segment_property
 {
-    kFLASH_accessSegmentBase = 256UL,
-};
-
-/*!
- * @brief Enumeration for acceleration ram property.
- */
-enum _flash_acceleration_ram_property
-{
-    kFLASH_accelerationRamSize = 0x400U
+    kFLASH_AccessSegmentBase = 256UL,
 };
 
 /*!
@@ -212,25 +307,78 @@
  */
 enum _flash_config_area_range
 {
-    kFLASH_configAreaStart = 0x400U,
-    kFLASH_configAreaEnd = 0x40FU
+    kFLASH_ConfigAreaStart = 0x400U,
+    kFLASH_ConfigAreaEnd = 0x40FU
 };
 
-/*! @brief program Flash block base address*/
-#define PFLASH_BLOCK_BASE 0x00U
-
-/*! @brief Total flash region count*/
-#define FSL_FEATURE_FTFx_REGION_COUNT (32U)
-
 /*!
  * @name Flash register access type defines
  * @{
  */
-#if FLASH_DRIVER_IS_FLASH_RESIDENT
-#define FTFx_REG_ACCESS_TYPE volatile uint8_t *
+#define FTFx_REG8_ACCESS_TYPE volatile uint8_t *
 #define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
-#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
-       /*@}*/
+/*@}*/
+
+/*!
+ * @brief MCM cache register access info defines.
+ */
+#if defined(MCM_PLACR_CFCC_MASK)
+#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK
+#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT
+#if defined(MCM)
+#define MCM0_CACHE_REG MCM->PLACR
+#elif defined(MCM0)
+#define MCM0_CACHE_REG MCM0->PLACR
+#endif
+#if defined(MCM1)
+#define MCM1_CACHE_REG MCM1->PLACR
+#endif
+#elif defined(MCM_CPCR2_CCBC_MASK)
+#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK
+#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT
+#if defined(MCM)
+#define MCM0_CACHE_REG MCM->CPCR2
+#elif defined(MCM0)
+#define MCM0_CACHE_REG MCM0->CPCR2
+#endif
+#if defined(MCM1)
+#define MCM1_CACHE_REG MCM1->CPCR2
+#endif
+#endif
+
+/*!
+ * @brief MSCM cache register access info defines.
+ */
+#if defined(MSCM_OCMDR_OCM1_MASK)
+#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK
+#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT
+#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x)
+#elif defined(MSCM_OCMDR_OCMC1_MASK)
+#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK
+#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT
+#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x)
+#endif
+
+/*!
+ * @brief MSCM prefetch speculation defines.
+ */
+#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U)
+#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U)
+
+#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U)
+#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U)
+
+/*!
+ * @brief Flash size encoding rule.
+ */
+#define FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2 (0x00U)
+#define FLASH_MEMORY_SIZE_ENCODING_RULE_K3 (0x01U)
+
+#if defined(K32W042S1M2_M0P_SERIES) || defined(K32W042S1M2_M4_SERIES)
+#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K3)
+#else
+#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2)
+#endif
 
 /*******************************************************************************
  * Prototypes
@@ -238,9 +386,9 @@
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief Copy flash_run_command() to RAM*/
-static void copy_flash_run_command(uint8_t *flashRunCommand);
+static void copy_flash_run_command(uint32_t *flashRunCommand);
 /*! @brief Copy flash_cache_clear_command() to RAM*/
-static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand);
+static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation);
 /*! @brief Check whether flash execute-in-ram functions are ready*/
 static status_t flash_check_execute_in_ram_function_info(flash_config_t *config);
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
@@ -251,6 +399,9 @@
 /*! @brief Perform the cache clear to the flash*/
 void flash_cache_clear(flash_config_t *config);
 
+/*! @brief Process the cache to the flash*/
+static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process);
+
 /*! @brief Validates the range and alignment of the given address range.*/
 static status_t flash_check_range(flash_config_t *config,
                                   uint32_t startAddress,
@@ -291,44 +442,131 @@
 static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option);
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
 
+/*! @brief Gets the flash protection information (region size, region count).*/
+static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/
+static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info);
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(flash_config_t *config);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(void);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(bool enable);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(void);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
 /*! @brief Access to FTFx->FCCOB */
-#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3;
-#else
-#error "Unknown flash controller"
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG;
+/*! @brief Access to FTFx->FPROT */
+volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG;
+#if defined(FTFx_FPROT_HIGH_REG)
+volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG;
 #endif
 
-/*! @brief Access to FTFx->FPROT */
-#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3;
-#else
-#error "Unknown flash controller"
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG;
+volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG;
 #endif
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief A function pointer used to point to relocated flash_run_command() */
-static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat);
-/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */
-static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg);
+static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat);
+/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */
+static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base,
+                                           uint32_t bitMask,
+                                           uint32_t bitShift,
+                                           uint32_t bitValue);
+
+/*!
+ * @brief Position independent code of flash_run_command()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat)
+ *   {
+ *       // clear CCIF bit
+ *       *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+ *
+ *       // Check CCIF bit of the flash status register, wait till it is set.
+ *       // IP team indicates that this loop will always complete.
+ *       while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+ *       {
+ *       }
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+const static uint16_t s_flashRunCommandFunctionCode[] = {
+    0x2180, /* MOVS  R1, #128 ; 0x80 */
+    0x7001, /* STRB  R1, [R0] */
+    /* @4: */
+    0x7802, /* LDRB  R2, [R0] */
+    0x420a, /* TST   R2, R1 */
+    0xd0fc, /* BEQ.N @4 */
+    0x4770  /* BX    LR */
+};
+
+/*!
+ * @brief Position independent code of flash_common_bit_operation()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t
+ * bitValue)
+ *   {
+ *       if (bitMask)
+ *       {
+ *           uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask);
+ *           *base = (*base & (~bitMask)) | value;
+ *       }
+ *
+ *       __ISB();
+ *       __DSB();
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+const static uint16_t s_flashCommonBitOperationFunctionCode[] = {
+    0xb510, /* PUSH  {R4, LR} */
+    0x2900, /* CMP   R1, #0 */
+    0xd005, /* BEQ.N @12 */
+    0x6804, /* LDR   R4, [R0] */
+    0x438c, /* BICS  R4, R4, R1 */
+    0x4093, /* LSLS  R3, R3, R2 */
+    0x4019, /* ANDS  R1, R1, R3 */
+    0x4321, /* ORRS  R1, R1, R4 */
+    0x6001, /* STR   R1, [R0] */
+    /*  @12: */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0xbd10          /* POP   {R4, PC} */
+};
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 
 #if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
 /*! @brief A static buffer used to hold flash_run_command() */
-static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize];
-/*! @brief A static buffer used to hold flash_cache_clear_command() */
-static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize];
+static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
+/*! @brief A static buffer used to hold flash_common_bit_operation() */
+static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
 /*! @brief Flash execute-in-ram function information */
 static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo;
 #endif
@@ -351,6 +589,7 @@
  *      flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
  *  @endcode
  */
+#if (FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2)
 const uint16_t kPFlashDensities[] = {
     8,    /* 0x0 - 8192, 8KB */
     16,   /* 0x1 - 16384, 16KB */
@@ -369,6 +608,26 @@
     1536, /* 0xe - 1572864, 1.5MB */
     /* 2048,  0xf - 2097152, 2MB */
 };
+#elif(FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K3)
+const uint16_t kPFlashDensities[] = {
+    0,    /* 0x0 - undefined */
+    0,    /* 0x1 - undefined */
+    0,    /* 0x2 - undefined */
+    0,    /* 0x3 - undefined */
+    0,    /* 0x4 - undefined */
+    0,    /* 0x5 - undefined */
+    0,    /* 0x6 - undefined */
+    0,    /* 0x7 - undefined */
+    0,    /* 0x8 - undefined */
+    0,    /* 0x9 - undefined */
+    256,  /* 0xa - 262144, 256KB */
+    0,    /* 0xb - undefined */
+    1024, /* 0xc - 1048576, 1MB */
+    0,    /* 0xd - undefined */
+    0,    /* 0xe - undefined */
+    0,    /* 0xf - undefined */
+};
+#endif
 
 /*******************************************************************************
  * Code
@@ -376,39 +635,86 @@
 
 status_t FLASH_Init(flash_config_t *config)
 {
-    uint32_t flashDensity;
-
     if (config == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    /* calculate the flash density from SIM_FCFG1.PFSIZE */
-    uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
-    /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
-     * We just use the pre-defined flash size in feature file here to support pre-production parts */
-    if (pfsize == 0xf)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
     {
-        flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+/* calculate the flash density from SIM_FCFG1.PFSIZE */
+#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK)
+        uint32_t flashDensity;
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT;
+        if (pfsize == 0xf)
+        {
+            flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+        }
+        else
+        {
+            flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+        }
+        config->PFlashTotalSize = flashDensity;
+#else
+        /* Unused code to solve MISRA-C issue*/
+        config->PFlashBlockBase = kPFlashDensities[0];
+        config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+#endif
+        config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS;
+        config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT;
+        config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE;
     }
     else
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
     {
-        flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+        uint32_t flashDensity;
+
+/* calculate the flash density from SIM_FCFG1.PFSIZE */
+#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK)
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT;
+#elif defined(SIM_FCFG1_PFSIZE_MASK)
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+#else
+#error "Unknown flash size"
+#endif
+        /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
+         * We just use the pre-defined flash size in feature file here to support pre-production parts */
+        if (pfsize == 0xf)
+        {
+            flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+        }
+        else
+        {
+            flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+        }
+
+        /* fill out a few of the structure members */
+        config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+        config->PFlashTotalSize = flashDensity;
+        config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+        config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
     }
 
-    /* fill out a few of the structure members */
-    config->PFlashBlockBase = PFLASH_BLOCK_BASE;
-    config->PFlashTotalSize = flashDensity;
-    config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
-    config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
-
+    {
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
-    config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS;
-    config->PFlashAccessSegmentCount = FTFx->FACSN;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+        {
+            config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS;
+            config->PFlashAccessSegmentCount = FTFx->FACSNS;
+        }
+        else
+#endif
+        {
+            config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS;
+            config->PFlashAccessSegmentCount = FTFx->FACSN;
+        }
 #else
-    config->PFlashAccessSegmentSize = 0;
-    config->PFlashAccessSegmentCount = 0;
+        config->PFlashAccessSegmentSize = 0;
+        config->PFlashAccessSegmentCount = 0;
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+    }
 
     config->PFlashCallback = NULL;
 
@@ -418,7 +724,7 @@
     {
         s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0;
         s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand;
-        s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand;
+        s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation;
         config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount;
         FLASH_PrepareExecuteInRamFunctions(config);
     }
@@ -467,8 +773,8 @@
     flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
 
     copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand);
-    copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand);
-    flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum;
+    copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation);
+    flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum;
 
     return kStatus_FLASH_Success;
 }
@@ -493,6 +799,8 @@
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -513,22 +821,29 @@
 status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
 {
     uint32_t sectorSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
     uint32_t endAddress;      /* storing end address */
     uint32_t numberOfSectors; /* number of sectors calculated by endAddress */
     status_t returnCode;
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
-    sectorSize = flashInfo.activeSectorSize;
+    /* Validate the user key */
+    returnCode = flash_check_user_key(key);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    start = flashOperationInfo.convertedAddress;
+    sectorSize = flashOperationInfo.activeSectorSize;
 
     /* calculating Flash end address */
     endAddress = start + lengthInBytes - 1;
@@ -541,6 +856,8 @@
         endAddress = numberOfSectors * sectorSize - 1;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* the start address will increment to the next sector address
      * until it reaches the endAdddress */
     while (start <= endAddress)
@@ -548,13 +865,6 @@
         /* preparing passing parameter to erase a flash block */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start);
 
-        /* Validate the user key */
-        returnCode = flash_check_user_key(key);
-        if (returnCode)
-        {
-            return returnCode;
-        }
-
         /* calling flash command sequence function to execute the command */
         returnCode = flash_command_sequence(config);
 
@@ -601,6 +911,8 @@
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -639,6 +951,8 @@
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -650,33 +964,35 @@
 status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if (src == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
+    start = flashOperationInfo.convertedAddress;
+
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
 
     while (lengthInBytes > 0)
     {
         /* preparing passing parameter to program the flash block */
         kFCCOBx[1] = *src++;
-        if (4 == flashInfo.blockWriteUnitSize)
+        if (4 == flashOperationInfo.blockWriteUnitSize)
         {
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start);
         }
-        else if (8 == flashInfo.blockWriteUnitSize)
+        else if (8 == flashOperationInfo.blockWriteUnitSize)
         {
             kFCCOBx[2] = *src++;
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start);
@@ -702,10 +1018,10 @@
         else
         {
             /* update start address for next iteration */
-            start += flashInfo.blockWriteUnitSize;
+            start += flashOperationInfo.blockWriteUnitSize;
 
             /* update lengthInBytes for next iteration */
-            lengthInBytes -= flashInfo.blockWriteUnitSize;
+            lengthInBytes -= flashOperationInfo.blockWriteUnitSize;
         }
     }
 
@@ -742,6 +1058,8 @@
     }
 #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -755,7 +1073,7 @@
 {
     status_t returnCode;
     uint32_t sectorSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
     bool needSwitchFlexRamMode = false;
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
@@ -765,17 +1083,17 @@
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
-    sectorSize = flashInfo.activeSectorSize;
+    start = flashOperationInfo.convertedAddress;
+    sectorSize = flashOperationInfo.activeSectorSize;
 
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
     /* Switch function of FlexRAM if needed */
@@ -783,7 +1101,7 @@
     {
         needSwitchFlexRamMode = true;
 
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_SetFlexramAsRamError;
@@ -791,6 +1109,8 @@
     }
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     while (lengthInBytes > 0)
     {
         /* Make sure the write operation doesn't span two sectors */
@@ -819,9 +1139,9 @@
             uint32_t programSizeOfCurrentPass;
             uint32_t numberOfPhases;
 
-            if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize)
+            if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize)
             {
-                programSizeOfCurrentPass = kFLASH_accelerationRamSize;
+                programSizeOfCurrentPass = kFLASH_AccelerationRamSize;
             }
             else
             {
@@ -833,7 +1153,7 @@
             /* Set start address of the data to be programmed */
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset);
             /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */
-            numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment;
+            numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment;
 
             kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU);
 
@@ -867,7 +1187,7 @@
     /* Restore function of FlexRAM if needed. */
     if (needSwitchFlexRamMode)
     {
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_RecoverFlexramAsEepromError;
@@ -904,7 +1224,7 @@
     {
         needSwitchFlexRamMode = true;
 
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_SetFlexramAsEepromError;
@@ -950,7 +1270,7 @@
     /* Switch function of FlexRAM if needed */
     if (needSwitchFlexRamMode)
     {
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_RecoverFlexramAsRamError;
@@ -966,17 +1286,18 @@
     flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if ((config == NULL) || (dst == NULL))
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option);
+    returnCode =
+        flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option);
     if (returnCode != kStatus_FLASH_Success)
     {
         return returnCode;
@@ -986,11 +1307,11 @@
     {
         /* preparing passing parameter */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start);
-        if (flashInfo.resourceCmdAddressAligment == 4)
+        if (flashOperationInfo.resourceCmdAddressAligment == 4)
         {
             kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
         }
-        else if (flashInfo.resourceCmdAddressAligment == 8)
+        else if (flashOperationInfo.resourceCmdAddressAligment == 8)
         {
             kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
         }
@@ -1008,14 +1329,14 @@
 
         /* fetch data */
         *dst++ = kFCCOBx[1];
-        if (flashInfo.resourceCmdAddressAligment == 8)
+        if (flashOperationInfo.resourceCmdAddressAligment == 8)
         {
             *dst++ = kFCCOBx[2];
         }
         /* update start address for next iteration */
-        start += flashInfo.resourceCmdAddressAligment;
+        start += flashOperationInfo.resourceCmdAddressAligment;
         /* update lengthInBytes for next iteration */
-        lengthInBytes -= flashInfo.resourceCmdAddressAligment;
+        lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment;
     }
 
     return (returnCode);
@@ -1075,7 +1396,7 @@
     if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK))
     {
         /* Flash in unsecured state */
-        *state = kFLASH_securityStateNotSecure;
+        *state = kFLASH_SecurityStateNotSecure;
     }
     else
     {
@@ -1084,12 +1405,12 @@
         if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK))
         {
             /* Backdoor key security enabled */
-            *state = kFLASH_securityStateBackdoorEnabled;
+            *state = kFLASH_SecurityStateBackdoorEnabled;
         }
         else
         {
             /* Backdoor key security disabled */
-            *state = kFLASH_securityStateBackdoorDisabled;
+            *state = kFLASH_SecurityStateBackdoorDisabled;
         }
     }
 
@@ -1146,22 +1467,22 @@
 {
     /* Check arguments. */
     uint32_t blockSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
     uint32_t nextBlockStartAddress;
     uint32_t remainingBytes;
     status_t returnCode;
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
-
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
+
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
-    start = flashInfo.convertedAddress;
-    blockSize = flashInfo.activeBlockSize;
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
+    start = flashOperationInfo.convertedAddress;
+    blockSize = flashOperationInfo.activeBlockSize;
 
     nextBlockStartAddress = ALIGN_UP(start, blockSize);
     if (nextBlockStartAddress == start)
@@ -1180,7 +1501,7 @@
             verifyLength = remainingBytes;
         }
 
-        numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment;
+        numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment;
 
         /* Fill in verify section command parameters. */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start);
@@ -1210,22 +1531,22 @@
                              uint32_t *failedData)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if (expectedData == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
-
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
+
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
+    start = flashOperationInfo.convertedAddress;
 
     while (lengthInBytes)
     {
@@ -1251,9 +1572,9 @@
             break;
         }
 
-        lengthInBytes -= flashInfo.checkCmdAddressAligment;
-        expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData);
-        start += flashInfo.checkCmdAddressAligment;
+        lengthInBytes -= flashOperationInfo.checkCmdAddressAligment;
+        expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData);
+        start += flashOperationInfo.checkCmdAddressAligment;
     }
 
     return (returnCode);
@@ -1279,19 +1600,21 @@
                            flash_protection_state_t *protection_state)
 {
     uint32_t endAddress;           /* end address for protection check */
-    uint32_t protectionRegionSize; /* size of flash protection region */
     uint32_t regionCheckedCounter; /* increments each time the flash address was checked for
                                     * protection status */
     uint32_t regionCounter;        /* incrementing variable used to increment through the flash
                                     * protection regions */
     uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */
 
-    uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each
+    uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection
+                                                                      * status for each
                                                                       * protection region */
-    uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1];  /* array of the start addresses for each flash
-                                                                      * protection region. Note this is REGION_COUNT+1
-                                                                      * due to requiring the next start address after
-                                                                      * the end of flash for loop-check purposes below */
+    uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT +
+                                1];                /* array of the start addresses for each flash
+                                 * protection region. Note this is REGION_COUNT+1
+                                 * due to requiring the next start address after
+                                 * the end of flash for loop-check purposes below */
+    flash_protection_config_t flashProtectionInfo; /* flash protection information */
     status_t returnCode;
 
     if (protection_state == NULL)
@@ -1306,28 +1629,24 @@
         return returnCode;
     }
 
+    /* Get necessary flash protection information. */
+    returnCode = flash_get_protection_info(config, &flashProtectionInfo);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
     /* calculating Flash end address */
     endAddress = start + lengthInBytes;
 
-    /* Calculate the size of the flash protection region
-     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
-     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
-    if (config->PFlashTotalSize > 32 * 1024)
-    {
-        protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT;
-    }
-    else
-    {
-        protectionRegionSize = 1024;
-    }
-
     /* populate the flashRegionAddress array with the start address of each flash region */
     regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
 
     /* populate up to 33rd element of array, this is the next address after end of flash array */
-    while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT)
+    while (regionCounter <= flashProtectionInfo.regionCount)
     {
-        flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter;
+        flashRegionAddress[regionCounter] =
+            flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter;
         regionCounter++;
     }
 
@@ -1341,24 +1660,80 @@
      * regionCounter is used to determine which FPROT[3:0] register to check for protection status
      * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
     regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
-    while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT)
+    while (regionCounter < flashProtectionInfo.regionCount)
     {
-        if (regionCounter < 8)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
         {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u);
-        }
-        else if ((regionCounter >= 8) && (regionCounter < 16))
-        {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u);
-        }
-        else if ((regionCounter >= 16) && (regionCounter < 24))
-        {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u);
+            if (regionCounter < 8)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u);
+            }
+            else if ((regionCounter >= 8) && (regionCounter < 16))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u);
+            }
+            else
+            {
+                break;
+            }
         }
         else
+#endif
         {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u);
+            /* Note: So far protection region count may be 16/20/24/32/64 */
+            if (regionCounter < 8)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u);
+            }
+            else if ((regionCounter >= 8) && (regionCounter < 16))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u);
+            }
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16)
+#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20)
+            else if ((regionCounter >= 16) && (regionCounter < 20))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u);
+            }
+#else
+            else if ((regionCounter >= 16) && (regionCounter < 24))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u);
+            }
+#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */
+#endif
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24)
+            else if ((regionCounter >= 24) && (regionCounter < 32))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u);
+            }
+#endif
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \
+    (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64)
+            else if (regionCounter < 40)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u);
+            }
+            else if (regionCounter < 48)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u);
+            }
+            else if (regionCounter < 56)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u);
+            }
+            else if (regionCounter < 64)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u);
+            }
+#endif
+            else
+            {
+                break;
+            }
         }
+
         regionCounter++;
     }
 
@@ -1386,7 +1761,7 @@
                 /* increment protectStatusCounter to indicate this region is protected */
                 protectStatusCounter++;
             }
-            start += protectionRegionSize; /* increment to an address within the next region */
+            start += flashProtectionInfo.regionSize; /* increment to an address within the next region */
         }
         regionCounter++; /* increment regionCounter to check for the next flash protection region */
     }
@@ -1394,18 +1769,18 @@
     /* if protectStatusCounter == 0, then no region of the desired flash region is protected */
     if (protectStatusCounter == 0)
     {
-        *protection_state = kFLASH_protectionStateUnprotected;
+        *protection_state = kFLASH_ProtectionStateUnprotected;
     }
     /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */
     else if (protectStatusCounter == regionCheckedCounter)
     {
-        *protection_state = kFLASH_protectionStateProtected;
+        *protection_state = kFLASH_ProtectionStateProtected;
     }
     /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed
      * In other words, some regions are protected while others are unprotected */
     else
     {
-        *protection_state = kFLASH_protectionStateMixed;
+        *protection_state = kFLASH_ProtectionStateMixed;
     }
 
     return (returnCode);
@@ -1416,6 +1791,9 @@
                              uint32_t lengthInBytes,
                              flash_execute_only_access_state_t *access_state)
 {
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    flash_access_config_t flashAccessInfo; /* flash Execute-Only information */
+#endif                                     /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
     status_t returnCode;
 
     if (access_state == NULL)
@@ -1431,6 +1809,13 @@
     }
 
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    /* Get necessary flash Execute-Only information. */
+    returnCode = flash_get_access_info(config, &flashAccessInfo);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
     {
         uint32_t executeOnlySegmentCounter = 0;
 
@@ -1438,31 +1823,56 @@
         uint32_t endAddress = start + lengthInBytes;
 
         /* Aligning start address and end address */
-        uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize);
-        uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize);
+        uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize);
+        uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize);
 
         uint32_t segmentIndex = 0;
         uint32_t maxSupportedExecuteOnlySegmentCount =
-            (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize;
+            (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize;
 
         while (start < endAddress)
         {
             uint32_t xacc;
 
-            segmentIndex = start / config->PFlashAccessSegmentSize;
-
-            if (segmentIndex < 32)
+            segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize;
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+            if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
             {
-                xacc = *(const volatile uint32_t *)&FTFx->XACCL3;
-            }
-            else if (segmentIndex < config->PFlashAccessSegmentCount)
-            {
-                xacc = *(const volatile uint32_t *)&FTFx->XACCH3;
-                segmentIndex -= 32;
+                /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size.
+                 */
+                if (segmentIndex < 8)
+                {
+                    xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG;
+                }
+                else if (segmentIndex < flashAccessInfo.SegmentCount)
+                {
+                    xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG;
+                    segmentIndex -= 8;
+                }
+                else
+                {
+                    break;
+                }
             }
             else
+#endif
             {
-                break;
+                /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size.
+                 */
+                if (segmentIndex < 32)
+                {
+                    xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG;
+                }
+                else if (segmentIndex < flashAccessInfo.SegmentCount)
+                {
+                    xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG;
+                    segmentIndex -= 32;
+                }
+                else
+                {
+                    break;
+                }
             }
 
             /* Determine if this address range is in a execute-only protection flash segment. */
@@ -1471,24 +1881,24 @@
                 executeOnlySegmentCounter++;
             }
 
-            start += config->PFlashAccessSegmentSize;
+            start += flashAccessInfo.SegmentSize;
         }
 
         if (executeOnlySegmentCounter < 1u)
         {
-            *access_state = kFLASH_accessStateUnLimited;
+            *access_state = kFLASH_AccessStateUnLimited;
         }
         else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount)
         {
-            *access_state = kFLASH_accessStateMixed;
+            *access_state = kFLASH_AccessStateMixed;
         }
         else
         {
-            *access_state = kFLASH_accessStateExecuteOnly;
+            *access_state = kFLASH_AccessStateExecuteOnly;
         }
     }
 #else
-    *access_state = kFLASH_accessStateUnLimited;
+    *access_state = kFLASH_AccessStateUnLimited;
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
 
     return (returnCode);
@@ -1503,27 +1913,27 @@
 
     switch (whichProperty)
     {
-        case kFLASH_propertyPflashSectorSize:
+        case kFLASH_PropertyPflashSectorSize:
             *value = config->PFlashSectorSize;
             break;
 
-        case kFLASH_propertyPflashTotalSize:
+        case kFLASH_PropertyPflashTotalSize:
             *value = config->PFlashTotalSize;
             break;
 
-        case kFLASH_propertyPflashBlockSize:
+        case kFLASH_PropertyPflashBlockSize:
             *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
             break;
 
-        case kFLASH_propertyPflashBlockCount:
-            *value = config->PFlashBlockCount;
+        case kFLASH_PropertyPflashBlockCount:
+            *value = (uint32_t)config->PFlashBlockCount;
             break;
 
-        case kFLASH_propertyPflashBlockBaseAddr:
+        case kFLASH_PropertyPflashBlockBaseAddr:
             *value = config->PFlashBlockBase;
             break;
 
-        case kFLASH_propertyPflashFacSupport:
+        case kFLASH_PropertyPflashFacSupport:
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL)
             *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL;
 #else
@@ -1531,31 +1941,39 @@
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
             break;
 
-        case kFLASH_propertyPflashAccessSegmentSize:
+        case kFLASH_PropertyPflashAccessSegmentSize:
             *value = config->PFlashAccessSegmentSize;
             break;
 
-        case kFLASH_propertyPflashAccessSegmentCount:
+        case kFLASH_PropertyPflashAccessSegmentCount:
             *value = config->PFlashAccessSegmentCount;
             break;
 
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+            *value = config->FlexRAMBlockBase;
+            break;
+
+        case kFLASH_PropertyFlexRamTotalSize:
+            *value = config->FlexRAMTotalSize;
+            break;
+
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
-        case kFLASH_propertyDflashSectorSize:
+        case kFLASH_PropertyDflashSectorSize:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
             break;
-        case kFLASH_propertyDflashTotalSize:
+        case kFLASH_PropertyDflashTotalSize:
             *value = config->DFlashTotalSize;
             break;
-        case kFLASH_propertyDflashBlockSize:
+        case kFLASH_PropertyDflashBlockSize:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE;
             break;
-        case kFLASH_propertyDflashBlockCount:
+        case kFLASH_PropertyDflashBlockCount:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
             break;
-        case kFLASH_propertyDflashBlockBaseAddr:
+        case kFLASH_PropertyDflashBlockBaseAddr:
             *value = config->DFlashBlockBase;
             break;
-        case kFLASH_propertyEepromTotalSize:
+        case kFLASH_PropertyEepromTotalSize:
             *value = config->EEpromTotalSize;
             break;
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
@@ -1567,6 +1985,65 @@
     return kStatus_FLASH_Success;
 }
 
+status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value)
+{
+    status_t status = kStatus_FLASH_Success;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    switch (whichProperty)
+    {
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+        case kFLASH_PropertyFlashMemoryIndex:
+            if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) &&
+                (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash))
+            {
+                return kStatus_FLASH_InvalidPropertyValue;
+            }
+            config->FlashMemoryIndex = (uint8_t)value;
+            break;
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
+
+        case kFLASH_PropertyFlashCacheControllerIndex:
+            if ((value != (uint32_t)kFLASH_CacheControllerIndexForCore0) &&
+                (value != (uint32_t)kFLASH_CacheControllerIndexForCore1))
+            {
+                return kStatus_FLASH_InvalidPropertyValue;
+            }
+            config->FlashCacheControllerIndex = (uint8_t)value;
+            break;
+
+        case kFLASH_PropertyPflashSectorSize:
+        case kFLASH_PropertyPflashTotalSize:
+        case kFLASH_PropertyPflashBlockSize:
+        case kFLASH_PropertyPflashBlockCount:
+        case kFLASH_PropertyPflashBlockBaseAddr:
+        case kFLASH_PropertyPflashFacSupport:
+        case kFLASH_PropertyPflashAccessSegmentSize:
+        case kFLASH_PropertyPflashAccessSegmentCount:
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+        case kFLASH_PropertyFlexRamTotalSize:
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+        case kFLASH_PropertyDflashSectorSize:
+        case kFLASH_PropertyDflashTotalSize:
+        case kFLASH_PropertyDflashBlockSize:
+        case kFLASH_PropertyDflashBlockCount:
+        case kFLASH_PropertyDflashBlockBaseAddr:
+        case kFLASH_PropertyEepromTotalSize:
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+            status = kStatus_FLASH_ReadOnlyProperty;
+            break;
+        default: /* catch inputs that are not recognized */
+            status = kStatus_FLASH_UnknownProperty;
+            break;
+    }
+
+    return status;
+}
+
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
 status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option)
 {
@@ -1611,7 +2088,7 @@
 
     /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */
     if ((address >= (config->PFlashTotalSize / 2)) ||
-        ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd)))
+        ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd)))
     {
         return kStatus_FLASH_SwapIndicatorAddressError;
     }
@@ -1628,9 +2105,9 @@
 
     returnCode = flash_command_sequence(config);
 
-    returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5;
-    returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6;
-    returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7;
+    returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG;
+    returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG;
+    returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG;
 
     return returnCode;
 }
@@ -1646,23 +2123,23 @@
 
     do
     {
-        returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo);
+        returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo);
         if (returnCode != kStatus_FLASH_Success)
         {
             return returnCode;
         }
 
-        if (kFLASH_swapFunctionOptionDisable == option)
+        if (kFLASH_SwapFunctionOptionDisable == option)
         {
-            if (returnInfo.flashSwapState == kFLASH_swapStateDisabled)
+            if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled)
             {
                 return kStatus_FLASH_Success;
             }
-            else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized)
+            else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized)
             {
                 /* The swap system changed to the DISABLED state with Program flash block 0
                  * located at relative flash address 0x0_0000 */
-                returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo);
+                returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo);
             }
             else
             {
@@ -1679,12 +2156,12 @@
              *    Complete. */
             switch (returnInfo.flashSwapState)
             {
-                case kFLASH_swapStateUninitialized:
+                case kFLASH_SwapStateUninitialized:
                     /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */
                     returnCode =
-                        FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo);
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo);
                     break;
-                case kFLASH_swapStateReady:
+                case kFLASH_SwapStateReady:
                     /* Validate whether the address provided to the swap system is matched to
                      * swap indicator address in the IFR */
                     returnCode = flash_validate_swap_indicator_address(config, address);
@@ -1692,23 +2169,23 @@
                     {
                         /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */
                         returnCode =
-                            FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo);
+                            FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo);
                     }
                     break;
-                case kFLASH_swapStateUpdate:
+                case kFLASH_SwapStateUpdate:
                     /* If current swap mode is Update, Erase indicator sector in non active block
                      * to proceed swap system to update-erased state */
                     returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1),
-                                             FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey);
+                                             FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey);
                     break;
-                case kFLASH_swapStateUpdateErased:
+                case kFLASH_SwapStateUpdateErased:
                     /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */
                     returnCode =
-                        FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo);
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo);
                     break;
-                case kFLASH_swapStateComplete:
+                case kFLASH_SwapStateComplete:
                     break;
-                case kFLASH_swapStateDisabled:
+                case kFLASH_SwapStateDisabled:
                     /* When swap system is in disabled state, We need to clear swap system back to uninitialized
                      * by issuing EraseAllBlocks command */
                     returnCode = kStatus_FLASH_SwapSystemNotInUninitialized;
@@ -1722,7 +2199,7 @@
         {
             break;
         }
-    } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option)));
+    } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option)));
 
     return returnCode;
 }
@@ -1750,6 +2227,8 @@
     kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option);
     kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU);
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -1766,31 +2245,70 @@
 }
 #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
 
-status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus)
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus)
 {
     if (config == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    *kFPROT = protectStatus;
-
-    if (protectStatus != *kFPROT)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
     {
-        return kStatus_FLASH_CommandFailure;
+        *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl;
+        if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+
+        *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh;
+        if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+    }
+    else
+#endif
+    {
+        *kFPROTL = protectStatus->valueLow32b.protl32b;
+        if (protectStatus->valueLow32b.protl32b != *kFPROTL)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+
+#if defined(FTFx_FPROT_HIGH_REG)
+        *kFPROTH = protectStatus->valueHigh32b.proth32b;
+        if (protectStatus->valueHigh32b.proth32b != *kFPROTH)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+#endif
     }
 
     return kStatus_FLASH_Success;
 }
 
-status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus)
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus)
 {
     if ((config == NULL) || (protectStatus == NULL))
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    *protectStatus = *kFPROT;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+    {
+        protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL;
+        protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH;
+    }
+    else
+#endif
+    {
+        protectStatus->valueLow32b.protl32b = *kFPROTL;
+#if defined(FTFx_FPROT_HIGH_REG)
+        protectStatus->valueHigh32b.proth32b = *kFPROTH;
+#endif
+    }
 
     return kStatus_FLASH_Success;
 }
@@ -1881,70 +2399,215 @@
 }
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
 
+status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus)
+{
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        FTFx_REG32_ACCESS_TYPE regBase;
+#if defined(MCM)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR;
+#elif defined(MCM0)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR;
+#endif
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable)
+        {
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                return kStatus_FLASH_InvalidSpeculationOption;
+            }
+            else
+            {
+                *regBase |= MCM_PLACR_DFCS_MASK;
+            }
+        }
+        else
+        {
+            *regBase &= ~MCM_PLACR_DFCS_MASK;
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                *regBase |= MCM_PLACR_EFDS_MASK;
+            }
+            else
+            {
+                *regBase &= ~MCM_PLACR_EFDS_MASK;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        FTFx_REG32_ACCESS_TYPE regBase;
+        uint32_t b0dpeMask, b0ipeMask;
+#if defined(FMC_PFB01CR_B0DPE_MASK)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+        b0dpeMask = FMC_PFB01CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB01CR_B0IPE_MASK;
+#elif defined(FMC_PFB0CR_B0DPE_MASK)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+        b0dpeMask = FMC_PFB0CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB0CR_B0IPE_MASK;
+#endif
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable)
+        {
+            *regBase |= b0ipeMask;
+        }
+        else
+        {
+            *regBase &= ~b0ipeMask;
+        }
+        if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+        {
+            *regBase |= b0dpeMask;
+        }
+        else
+        {
+            *regBase &= ~b0dpeMask;
+        }
+
+/* Invalidate Prefetch Speculation Buffer */
+#if defined(FMC_PFB01CR_S_INV_MASK)
+        FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK;
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+        FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK;
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+        FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK;
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+        FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK;
+#endif
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+    {
+        FTFx_REG32_ACCESS_TYPE regBase;
+        uint32_t flashSpeculationMask, dataPrefetchMask;
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0];
+        flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK;
+        dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK;
+
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable)
+        {
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                return kStatus_FLASH_InvalidSpeculationOption;
+            }
+            else
+            {
+                *regBase |= flashSpeculationMask;
+            }
+        }
+        else
+        {
+            *regBase &= ~flashSpeculationMask;
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                *regBase &= ~dataPrefetchMask;
+            }
+            else
+            {
+                *regBase |= dataPrefetchMask;
+            }
+        }
+    }
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
+
+    return kStatus_FLASH_Success;
+}
+
+status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus)
+{
+    memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t));
+
+    /* Assuming that all speculation options are enabled. */
+    speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable;
+    speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable;
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        uint32_t value;
+#if defined(MCM)
+        value = MCM->PLACR;
+#elif defined(MCM0)
+        value = MCM0->PLACR;
+#endif
+        if (value & MCM_PLACR_DFCS_MASK)
+        {
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (!(value & MCM_PLACR_EFDS_MASK))
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        uint32_t value;
+        uint32_t b0dpeMask, b0ipeMask;
+#if defined(FMC_PFB01CR_B0DPE_MASK)
+        value = FMC->PFB01CR;
+        b0dpeMask = FMC_PFB01CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB01CR_B0IPE_MASK;
+#elif defined(FMC_PFB0CR_B0DPE_MASK)
+        value = FMC->PFB0CR;
+        b0dpeMask = FMC_PFB0CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB0CR_B0IPE_MASK;
+#endif
+        if (!(value & b0dpeMask))
+        {
+            /* Do not prefetch in response to data references. */
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        if (!(value & b0ipeMask))
+        {
+            /* Do not prefetch in response to instruction fetches. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+    {
+        uint32_t value;
+        uint32_t flashSpeculationMask, dataPrefetchMask;
+        value = MSCM->OCMDR[0];
+        flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK;
+        dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK;
+
+        if (value & flashSpeculationMask)
+        {
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (value & dataPrefetchMask)
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+            }
+        }
+    }
+#endif
+
+    return kStatus_FLASH_Success;
+}
+
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*!
- * @brief Run flash command
- *
- * This function should be copied to RAM for execution to make sure that code works
- * properly even flash cache is disabled.
- * It is for flash-resident bootloader only, not technically required for ROM or
- *  flashloader (RAM-resident bootloader).
+ * @brief Copy PIC of flash_run_command() to RAM
  */
-void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat)
-{
-    /* clear CCIF bit */
-    *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
-
-    /* Check CCIF bit of the flash status register, wait till it is set.
-     * IP team indicates that this loop will always complete. */
-    while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
-    {
-    }
-}
-
-/*!
- * @brief Be used for determining the size of flash_run_command()
- *
- * This function must be defined that lexically follows flash_run_command(),
- * so we can determine the size of flash_run_command() at runtime and not worry
- * about toolchain or code generation differences.
- */
-void flash_run_command_end(void)
+static void copy_flash_run_command(uint32_t *flashRunCommand)
 {
-}
-
-/*!
- * @brief Copy flash_run_command() to RAM
- *
- * This function copys the memory between flash_run_command() and flash_run_command_end()
- * into the buffer which is also means that copying flash_run_command() to RAM.
- */
-static void copy_flash_run_command(uint8_t *flashRunCommand)
-{
-    /* Calculate the valid length of flash_run_command() memory.
-     * Set max size(64 bytes) as default function size, in case some compiler allocates
-     * flash_run_command_end ahead of flash_run_command. */
-    uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
-    uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U);
-    uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U);
-    if (flash_run_command_end_addr > flash_run_command_start_addr)
-    {
-        funcLength = flash_run_command_end_addr - flash_run_command_start_addr;
-
-        assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
-
-        /* In case some compiler allocates other function in the middle of flash_run_command
-         * and flash_run_command_end. */
-        if (funcLength > kFLASH_executeInRamFunctionMaxSize)
-        {
-            funcLength = kFLASH_executeInRamFunctionMaxSize;
-        }
-    }
+    assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
 
     /* Since the value of ARM function pointer is always odd, but the real start address
-     * of function memory should be even, that's why -1 and +1 operation exist. */
-    memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength);
-    callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode));
+    callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
 }
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 
@@ -1973,7 +2636,7 @@
     /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
      * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
      * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
-    callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT));
+    callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT));
 #else
     /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
     FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
@@ -2015,100 +2678,173 @@
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*!
- * @brief Run flash cache clear command
+ * @brief Copy PIC of flash_common_bit_operation() to RAM
  *
- * This function should be copied to RAM for execution to make sure that code works
- * properly even flash cache is disabled.
- * It is for flash-resident bootloader only, not technically required for ROM or
- * flashloader (RAM-resident bootloader).
  */
-void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg)
+static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation)
+{
+    assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode,
+           sizeof(s_flashCommonBitOperationFunctionCode));
+    callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift,
+                                            uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1);
+    /* Workround for some devices which doesn't need this function */
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(flash_config_t *config)
 {
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-    *ftfx_reg |= MCM_PLACR_CFCC_MASK;
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG;
+
+#if defined(MCM0) && defined(MCM1)
+    if (config->FlashCacheControllerIndex == (uint8_t)kFLASH_CacheControllerIndexForCore1)
+    {
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG;
+    }
+#endif
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U);
+#else  /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+    *regBase |= MCM_CACHE_CLEAR_MASK;
+
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(void)
+{
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0;
 #if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU);
 #else
-    *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU);
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    *ftfx_reg |= MSCM_OCMDR_OCMC1(2);
-    *ftfx_reg |= MSCM_OCMDR_OCMC1(1);
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+    FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
 #else
-/*    #error "Unknown flash cache controller"  */
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-       /* Memory barriers for good measure.
-        * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+#endif
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
     __ISB();
     __DSB();
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 }
-
-/*!
- * @brief Be used for determining the size of flash_cache_clear_command()
- *
- * This function must be defined that lexically follows flash_cache_clear_command(),
- * so we can determine the size of flash_cache_clear_command() at runtime and not worry
- * about toolchain or code generation differences.
- */
-void flash_cache_clear_command_end(void)
-{
-}
-
-/*!
- * @brief Copy flash_cache_clear_command() to RAM
- *
- * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end()
- * into the buffer which is also means that copying flash_cache_clear_command() to RAM.
- */
-static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand)
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(bool enable)
 {
-    /* Calculate the valid length of flash_cache_clear_command() memory.
-     * Set max size(64 bytes) as default function size, in case some compiler allocates
-     * flash_cache_clear_command_end ahead of flash_cache_clear_command. */
-    uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
-    uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U);
-    uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U);
-    if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr)
+    uint8_t setValue;
+    if (enable)
+    {
+        setValue = 0x0U;
+    }
+    else
     {
-        funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr;
-
-        assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
-
-        /* In case some compiler allocates other function in the middle of flash_cache_clear_command
-         * and flash_cache_clear_command_end. */
-        if (funcLength > kFLASH_executeInRamFunctionMaxSize)
-        {
-            funcLength = kFLASH_executeInRamFunctionMaxSize;
-        }
+        setValue = 0x3U;
     }
 
-    /* Since the value of ARM function pointer is always odd, but the real start address
-     * of function memory should be even, that's why -1 and +1 operation exist. */
-    memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength);
-    callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1);
+/* The OCMDR[0] is always used to prefetch main Pflash*/
+/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash.
+ * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0], MSCM_SPECULATION_DISABLE_MASK,
+                                MSCM_SPECULATION_DISABLE_SHIFT, setValue);
+#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1], MSCM_SPECULATION_DISABLE_MASK,
+                                MSCM_SPECULATION_DISABLE_SHIFT, setValue);
+#endif
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+    MSCM->OCMDR[0] |= MSCM_SPECULATION_DISABLE(setValue);
+
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH
+    MSCM->OCMDR[1] |= MSCM_SPECULATION_DISABLE(setValue);
+
+    /* Each cahce clear instaruction should be followed by below code*/
+    __ISB();
+    __DSB();
+#endif
+
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 }
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(void)
+{
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0;
+#if defined(FMC_PFB01CR_S_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U);
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_B_INV_MASK, FMC_PFB01CR_S_B_INV_SHIFT, 1U);
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U);
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U);
+#endif
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+#if defined(FMC_PFB01CR_S_INV_MASK)
+    FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK;
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+    FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK;
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+    FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK;
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+    FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK;
+#endif
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
 
 /*!
  * @brief Flash Cache Clear
  *
- * This function is used to perform the cache clear to the flash.
+ * This function is used to perform the cache and prefetch speculation clear to the flash.
  */
-#if (defined(__GNUC__))
-/* #pragma GCC push_options */
-/* #pragma GCC optimize("O0") */
-void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config)
-#else
-#if (defined(__ICCARM__))
-#pragma optimize = none
-#endif
-#if (defined(__CC_ARM))
-#pragma push
-#pragma O0
-#endif
 void flash_cache_clear(flash_config_t *config)
-#endif
+{
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPost);
+}
+
+/*!
+ * @brief Flash Cache Clear Process
+ *
+ * This function is used to perform the cache and prefetch speculation clear process to the flash.
+ */
+static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process)
 {
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
     status_t returnCode = flash_check_execute_in_ram_function_info(config);
@@ -2116,66 +2852,33 @@
     {
         return;
     }
-
-/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using
- * pre-processed MACROs or a global variable in flash_cache_clear_comamnd()
- * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-#if defined(MCM)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR);
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+    /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using
+     * pre-processed MACROs or a global variable in flash_common_bit_operation()
+     * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */
+    if (process == kFLASH_CacheClearProcessPost)
+    {
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+        mcm_flash_cache_clear(config);
 #endif
-#if defined(MCM0)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR);
-#endif
-#if defined(MCM1)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR);
-#endif
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
-#if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR);
-#else
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR);
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+        fmc_flash_cache_clear();
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]);
-#else
-    /* #error "Unknown flash cache controller" */
-    /* meaningless code, just a workaround to solve warning*/
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0);
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-
-#else
-
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-#if defined(MCM)
-    MCM->PLACR |= MCM_PLACR_CFCC_MASK;
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(true);
 #endif
-#if defined(MCM0)
-    MCM0->PLACR |= MCM_PLACR_CFCC_MASK;
-#endif
-#if defined(MCM1)
-    MCM1->PLACR |= MCM_PLACR_CFCC_MASK;
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+        fmc_flash_prefetch_speculation_clear();
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
-#if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
-#else
-    FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+    }
+    if (process == kFLASH_CacheClearProcessPre)
+    {
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(false);
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2);
-    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1);
-#else
-/*    #error "Unknown flash cache controller" */
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+    }
 }
-#if (defined(__CC_ARM))
-#pragma pop
-#endif
-#if (defined(__GNUC__))
-/* #pragma GCC pop_options */
-#endif
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief Check whether flash execute-in-ram functions are ready  */
@@ -2191,7 +2894,7 @@
     flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
 
     if ((config->flashExecuteInRamFunctionInfo) &&
-        (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
+        (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
     {
         return kStatus_FLASH_Success;
     }
@@ -2217,21 +2920,19 @@
         return kStatus_FLASH_AlignmentError;
     }
 
-/* check for valid range of the target addresses */
-#if !FLASH_SSD_IS_FLEXNVM_ENABLED
-    if ((startAddress < config->PFlashBlockBase) ||
-        ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize)))
-#else
-    if (!(((startAddress >= config->PFlashBlockBase) &&
-           ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) ||
-          ((startAddress >= config->DFlashBlockBase) &&
-           ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize)))))
+    /* check for valid range of the target addresses */
+    if (
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+        ((startAddress >= config->DFlashBlockBase) &&
+         ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) ||
 #endif
+        ((startAddress >= config->PFlashBlockBase) &&
+         ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))))
     {
-        return kStatus_FLASH_AddressError;
+        return kStatus_FLASH_Success;
     }
 
-    return kStatus_FLASH_Success;
+    return kStatus_FLASH_AddressError;
 }
 
 /*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
@@ -2250,6 +2951,8 @@
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
     if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize)))
     {
+        /* When required by the command, address bit 23 selects between program flash memory
+         * (=0) and data flash memory (=1).*/
         info->convertedAddress = address - config->DFlashBlockBase + 0x800000U;
         info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
         info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
@@ -2263,11 +2966,25 @@
     else
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
     {
-        info->convertedAddress = address;
+        info->convertedAddress = address - config->PFlashBlockBase;
         info->activeSectorSize = config->PFlashSectorSize;
         info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount;
-
-        info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+        {
+#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+            /* When required by the command, address bit 23 selects between main flash memory
+             * (=0) and secondary flash memory (=1).*/
+            info->convertedAddress += 0x800000U;
+#endif
+            info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE;
+        }
+        else
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
+        {
+            info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+        }
+
         info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
         info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
         info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT;
@@ -2281,7 +2998,7 @@
 static status_t flash_check_user_key(uint32_t key)
 {
     /* Validate the user key */
-    if (key != kFLASH_apiEraseKey)
+    if (key != kFLASH_ApiEraseKey)
     {
         return kStatus_FLASH_EraseKeyError;
     }
@@ -2307,13 +3024,17 @@
         return kStatus_FLASH_InvalidArgument;
     }
 
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
     /* Get FlexNVM memory partition info from data flash IFR */
     returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut,
-                                    sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr);
+                                    sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr);
     if (returnCode != kStatus_FLASH_Success)
     {
         return kStatus_FLASH_PartitionStatusUpdateFailure;
     }
+#else
+#error "Cannot get FlexNVM memory partition info"
+#endif
 
     /* Fill out partitioned EEPROM size */
     dataIFRReadOut.EEPROMDataSetSize &= 0x0FU;
@@ -2515,27 +3236,27 @@
     status = kStatus_FLASH_Success;
 
     maxReadbleAddress = start + lengthInBytes - 1;
-    if (option == kFLASH_resourceOptionVersionId)
+    if (option == kFLASH_ResourceOptionVersionId)
     {
-        if ((start != kFLASH_resourceRangeVersionIdStart) ||
-            ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd))
+        if ((start != kFLASH_ResourceRangeVersionIdStart) ||
+            ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd))
         {
             status = kStatus_FLASH_InvalidArgument;
         }
     }
-    else if (option == kFLASH_resourceOptionFlashIfr)
+    else if (option == kFLASH_ResourceOptionFlashIfr)
     {
-        if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes)
+        if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes)
         {
         }
 #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
-        else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) &&
-                 (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd))
+        else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd))
         {
         }
 #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
-        else if ((start >= kFLASH_resourceRangeDflashIfrStart) &&
-                 (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd))
+        else if ((start >= kFLASH_ResourceRangeDflashIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd))
         {
         }
         else
@@ -2556,9 +3277,9 @@
 /*! @brief Validates the gived swap control option.*/
 static status_t flash_check_swap_control_option(flash_swap_control_option_t option)
 {
-    if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) ||
-        (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) ||
-        (option == kFLASH_swapControlOptionDisableSystem))
+    if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) ||
+        (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) ||
+        (option == kFLASH_SwapControlOptionDisableSystem))
     {
         return kStatus_FLASH_Success;
     }
@@ -2571,21 +3292,48 @@
 /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
 static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address)
 {
-    flash_swap_ifr_field_config_t flashSwapIfrField;
+    flash_swap_ifr_field_data_t flashSwapIfrFieldData;
     uint32_t swapIndicatorAddress;
 
     status_t returnCode;
-    returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField,
-                                    sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr);
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+    returnCode =
+        FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData,
+                           sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr);
+
     if (returnCode != kStatus_FLASH_Success)
     {
         return returnCode;
     }
-
-    /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
-     * the low 4 bit value of Swap Indicator Address is always 4'b0000 */
-    swapIndicatorAddress =
-        (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
+#else
+    {
+        /* From RM, the actual info are stored in FCCOB6,7 */
+        uint32_t returnValue[2];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0];
+    }
+#endif
+
+    /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
+     * the low severval bit value of Swap Indicator Address is always 1'b0 */
+    swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress *
+                           FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
     if (address != swapIndicatorAddress)
     {
         return kStatus_FLASH_SwapIndicatorAddressError;
@@ -2599,8 +3347,8 @@
 /*! @brief Validates the gived flexram function option.*/
 static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option)
 {
-    if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) &&
-        (option != kFLASH_flexramFunctionOptionAvailableForEeprom))
+    if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) &&
+        (option != kFLASH_FlexramFunctionOptionAvailableForEeprom))
     {
         return kStatus_FLASH_InvalidArgument;
     }
@@ -2608,3 +3356,77 @@
     return kStatus_FLASH_Success;
 }
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*! @brief Gets the flash protection information (region size, region count).*/
+static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info)
+{
+    uint32_t pflashTotalSize;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Clean up info Structure*/
+    memset(info, 0, sizeof(flash_protection_config_t));
+
+/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER)
+    pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE +
+                      FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+    info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+#else
+    pflashTotalSize = config->PFlashTotalSize;
+    info->regionBase = config->PFlashBlockBase;
+#endif
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+    {
+        info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT;
+    }
+    else
+#endif
+    {
+        info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT;
+    }
+
+    /* Calculate the size of the flash protection region
+     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
+     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
+    if (pflashTotalSize > info->regionCount * 1024)
+    {
+        info->regionSize = (pflashTotalSize) / info->regionCount;
+    }
+    else
+    {
+        info->regionSize = 1024;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/
+static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Clean up info Structure*/
+    memset(info, 0, sizeof(flash_access_config_t));
+
+/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER)
+    info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+#else
+    info->SegmentBase = config->PFlashBlockBase;
+#endif
+    info->SegmentSize = config->PFlashAccessSegmentSize;
+    info->SegmentCount = config->PFlashAccessSegmentCount;
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -53,21 +53,21 @@
  * @name Flash version
  * @{
  */
-/*! @brief Construct the version number for drivers. */
+/*! @brief Constructs the version number for drivers. */
 #if !defined(MAKE_VERSION)
 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
 #endif
 
-/*! @brief FLASH driver version for SDK*/
-#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+/*! @brief Flash driver version for SDK*/
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */
 
-/*! @brief FLASH driver version for ROM*/
+/*! @brief Flash driver version for ROM*/
 enum _flash_driver_version_constants
 {
-    kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/
-    kFLASH_driverVersionMajor = 2,  /*!< Major flash driver version.*/
-    kFLASH_driverVersionMinor = 1,  /*!< Minor flash driver version.*/
-    kFLASH_driverVersionBugfix = 0  /*!< Bugfix for flash driver version.*/
+    kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/
+    kFLASH_DriverVersionMajor = 2,  /*!< Major flash driver version.*/
+    kFLASH_DriverVersionMinor = 3,  /*!< Minor flash driver version.*/
+    kFLASH_DriverVersionBugfix = 1  /*!< Bugfix for flash driver version.*/
 };
 /*@}*/
 
@@ -75,29 +75,41 @@
  * @name Flash configuration
  * @{
  */
-/*! @brief Whether to support FlexNVM in flash driver */
+/*! @brief Indicates whether to support FlexNVM in the Flash driver */
 #if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT)
-#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */
+#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */
 #endif
 
-/*! @brief Whether the FlexNVM is enabled in flash driver */
+/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */
 #define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM)
 
+/*! @brief Indicates whether to support Secondary flash in the Flash driver */
+#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT)
+#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */
+#endif
+
+/*! @brief Indicates whether the secondary flash is supported in the Flash driver */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT)
+#else
+#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0)
+#endif
+
 /*! @brief Flash driver location. */
 #if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT)
 #if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM))
-#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */
 #else
-#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */
 #endif
 #endif
 
 /*! @brief Flash Driver Export option */
 #if !defined(FLASH_DRIVER_IS_EXPORTED)
 #if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH))
-#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */
+#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */
 #else
-#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */
+#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */
 #endif
 #endif
 /*@}*/
@@ -118,7 +130,7 @@
 #define kStatusGroupFlashDriver 1
 #endif
 
-/*! @brief Construct a status code value from a group and code number. */
+/*! @brief Constructs a status code value from a group and a code number. */
 #if !defined(MAKE_STATUS)
 #define MAKE_STATUS(group, code) ((((group)*100) + (code)))
 #endif
@@ -128,37 +140,43 @@
  */
 enum _flash_status
 {
-    kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0),         /*!< Api is executed successfully*/
+    kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0),         /*!< API is executed successfully*/
     kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
     kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0),   /*!< Error size*/
     kStatus_FLASH_AlignmentError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
     kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
     kStatus_FLASH_AccessError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */
+        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
     kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
         kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
     kStatus_FLASH_CommandFailure =
         MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
-    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6),   /*!< Unknown property.*/
-    kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7),     /*!< Api erase key is invalid.*/
-    kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/
+    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
+    kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7),   /*!< API erase key is invalid.*/
+    kStatus_FLASH_RegionExecuteOnly =
+        MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/
     kStatus_FLASH_ExecuteInRamFunctionNotReady =
-        MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/
     kStatus_FLASH_PartitionStatusUpdateFailure =
         MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/
     kStatus_FLASH_SetFlexramAsEepromError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/
     kStatus_FLASH_RecoverFlexramAsRamError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/
-    kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/
+    kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/
     kStatus_FLASH_RecoverFlexramAsEepromError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/
-    kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/
+    kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/
     kStatus_FLASH_SwapSystemNotInUninitialized =
-        MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/
     kStatus_FLASH_SwapIndicatorAddressError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/
+    kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/
+    kStatus_FLASH_InvalidPropertyValue =
+        MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/
+    kStatus_FLASH_InvalidSpeculationOption =
+        MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/
 };
 /*@}*/
 
@@ -166,13 +184,13 @@
  * @name Flash API key
  * @{
  */
-/*! @brief Construct the four char code for flash driver API key. */
+/*! @brief Constructs the four character code for the Flash driver API key. */
 #if !defined(FOUR_CHAR_CODE)
 #define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
 #endif
 
 /*!
- * @brief Enumeration for flash driver API keys.
+ * @brief Enumeration for Flash driver API keys.
  *
  * @note The resulting value is built with a byte order such that the string
  * being readable in expected order when viewed in a hex editor, if the value
@@ -180,7 +198,7 @@
  */
 enum _flash_driver_api_keys
 {
-    kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
+    kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
 };
 /*@}*/
 
@@ -189,10 +207,10 @@
  */
 typedef enum _flash_margin_value
 {
-    kFLASH_marginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
-    kFLASH_marginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
-    kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
-    kFLASH_marginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
+    kFLASH_MarginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
+    kFLASH_MarginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
+    kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
+    kFLASH_MarginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
 } flash_margin_value_t;
 
 /*!
@@ -200,9 +218,9 @@
  */
 typedef enum _flash_security_state
 {
-    kFLASH_securityStateNotSecure,       /*!< Flash is not secure.*/
-    kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
-    kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
+    kFLASH_SecurityStateNotSecure,       /*!< Flash is not secure.*/
+    kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
+    kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
 } flash_security_state_t;
 
 /*!
@@ -210,9 +228,9 @@
  */
 typedef enum _flash_protection_state
 {
-    kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/
-    kFLASH_protectionStateProtected,   /*!< Flash region is protected.*/
-    kFLASH_protectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
+    kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/
+    kFLASH_ProtectionStateProtected,   /*!< Flash region is protected.*/
+    kFLASH_ProtectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
 } flash_protection_state_t;
 
 /*!
@@ -220,9 +238,9 @@
  */
 typedef enum _flash_execute_only_access_state
 {
-    kFLASH_accessStateUnLimited,   /*!< Flash region is unLimited.*/
-    kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/
-    kFLASH_accessStateMixed        /*!< Flash is mixed with unLimited and execute only region.*/
+    kFLASH_AccessStateUnLimited,   /*!< Flash region is unlimited.*/
+    kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/
+    kFLASH_AccessStateMixed        /*!< Flash is mixed with unlimited and execute only region.*/
 } flash_execute_only_access_state_t;
 
 /*!
@@ -230,41 +248,43 @@
  */
 typedef enum _flash_property_tag
 {
-    kFLASH_propertyPflashSectorSize = 0x00U,         /*!< Pflash sector size property.*/
-    kFLASH_propertyPflashTotalSize = 0x01U,          /*!< Pflash total size property.*/
-    kFLASH_propertyPflashBlockSize = 0x02U,          /*!< Pflash block size property.*/
-    kFLASH_propertyPflashBlockCount = 0x03U,         /*!< Pflash block count property.*/
-    kFLASH_propertyPflashBlockBaseAddr = 0x04U,      /*!< Pflash block base address property.*/
-    kFLASH_propertyPflashFacSupport = 0x05U,         /*!< Pflash fac support property.*/
-    kFLASH_propertyPflashAccessSegmentSize = 0x06U,  /*!< Pflash access segment size property.*/
-    kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
-    kFLASH_propertyFlexRamBlockBaseAddr = 0x08U,     /*!< FlexRam block base address property.*/
-    kFLASH_propertyFlexRamTotalSize = 0x09U,         /*!< FlexRam total size property.*/
-    kFLASH_propertyDflashSectorSize = 0x10U,         /*!< Dflash sector size property.*/
-    kFLASH_propertyDflashTotalSize = 0x11U,          /*!< Dflash total size property.*/
-    kFLASH_propertyDflashBlockSize = 0x12U,          /*!< Dflash block count property.*/
-    kFLASH_propertyDflashBlockCount = 0x13U,         /*!< Dflash block base address property.*/
-    kFLASH_propertyDflashBlockBaseAddr = 0x14U,      /*!< Eeprom total size property.*/
-    kFLASH_propertyEepromTotalSize = 0x15U
+    kFLASH_PropertyPflashSectorSize = 0x00U,         /*!< Pflash sector size property.*/
+    kFLASH_PropertyPflashTotalSize = 0x01U,          /*!< Pflash total size property.*/
+    kFLASH_PropertyPflashBlockSize = 0x02U,          /*!< Pflash block size property.*/
+    kFLASH_PropertyPflashBlockCount = 0x03U,         /*!< Pflash block count property.*/
+    kFLASH_PropertyPflashBlockBaseAddr = 0x04U,      /*!< Pflash block base address property.*/
+    kFLASH_PropertyPflashFacSupport = 0x05U,         /*!< Pflash fac support property.*/
+    kFLASH_PropertyPflashAccessSegmentSize = 0x06U,  /*!< Pflash access segment size property.*/
+    kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
+    kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U,     /*!< FlexRam block base address property.*/
+    kFLASH_PropertyFlexRamTotalSize = 0x09U,         /*!< FlexRam total size property.*/
+    kFLASH_PropertyDflashSectorSize = 0x10U,         /*!< Dflash sector size property.*/
+    kFLASH_PropertyDflashTotalSize = 0x11U,          /*!< Dflash total size property.*/
+    kFLASH_PropertyDflashBlockSize = 0x12U,          /*!< Dflash block size property.*/
+    kFLASH_PropertyDflashBlockCount = 0x13U,         /*!< Dflash block count property.*/
+    kFLASH_PropertyDflashBlockBaseAddr = 0x14U,      /*!< Dflash block base address property.*/
+    kFLASH_PropertyEepromTotalSize = 0x15U,          /*!< EEPROM total size property.*/
+    kFLASH_PropertyFlashMemoryIndex = 0x20U,         /*!< Flash memory index property.*/
+    kFLASH_PropertyFlashCacheControllerIndex = 0x21U /*!< Flash cache controller index property.*/
 } flash_property_tag_t;
 
 /*!
- * @brief Constants for execute-in-ram flash function.
+ * @brief Constants for execute-in-RAM flash function.
  */
 enum _flash_execute_in_ram_function_constants
 {
-    kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/
-    kFLASH_executeInRamFunctionTotalNum = 2U  /*!< Total number of execute-in-ram functions.*/
+    kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/
+    kFLASH_ExecuteInRamFunctionTotalNum = 2U         /*!< Total number of execute-in-RAM functions.*/
 };
 
 /*!
- * @brief Flash execute-in-ram function information.
+ * @brief Flash execute-in-RAM function information.
  */
 typedef struct _flash_execute_in_ram_function_config
 {
-    uint32_t activeFunctionCount;    /*!< Number of available execute-in-ram functions.*/
-    uint8_t *flashRunCommand;        /*!< execute-in-ram function: flash_run_command.*/
-    uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/
+    uint32_t activeFunctionCount;      /*!< Number of available execute-in-RAM functions.*/
+    uint32_t *flashRunCommand;         /*!< Execute-in-RAM function: flash_run_command.*/
+    uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/
 } flash_execute_in_ram_function_config_t;
 
 /*!
@@ -272,9 +292,9 @@
  */
 typedef enum _flash_read_resource_option
 {
-    kFLASH_resourceOptionFlashIfr =
+    kFLASH_ResourceOptionFlashIfr =
         0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */
-    kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/
+    kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/
 } flash_read_resource_option_t;
 
 /*!
@@ -283,124 +303,262 @@
 enum _flash_read_resource_range
 {
 #if (FSL_FEATURE_FLASH_IS_FTFE == 1)
-    kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdSizeInBytes = 8U,    /*!< Version ID IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdStart = 0x08U,       /*!< Version ID IFR start address.*/
-    kFLASH_resourceRangeVersionIdEnd = 0x0FU,         /*!< Version ID IFR end address.*/
-#else                                                 /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
-    kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdSizeInBytes = 8U,   /*!< Version ID IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdStart = 0x00U,      /*!< Version ID IFR start address.*/
-    kFLASH_resourceRangeVersionIdEnd = 0x07U,        /*!< Version ID IFR end address.*/
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,     /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x08U,        /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x0FU,          /*!< Version ID IFR end address.*/
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/
+#else                                                      /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 256U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,    /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x00U,       /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x07U,         /*!< Version ID IFR end address.*/
+#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/
+#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/
+#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/
+#else
+    kFLASH_ResourceRangePflashSwapIfrStart = 0,
 #endif
-    kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
-    kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU,   /*!< Pflash swap IFR end address.*/
-    kFLASH_resourceRangeDflashIfrStart = 0x800000U,    /*!< Dflash IFR start address.*/
-    kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU,      /*!< Dflash IFR end address.*/
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/
+#endif
+    kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/
+    kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU,   /*!< Dflash IFR end address.*/
 };
 
 /*!
- * @brief Enumeration for the two possilbe options of set flexram function command.
+ * @brief Enumeration for the index of read/program once record
+ */
+enum _k3_flash_read_once_index
+{
+    kFLASH_RecordIndexSwapAddr = 0xA1U,    /*!< Index of Swap indicator address.*/
+    kFLASH_RecordIndexSwapEnable = 0xA2U,  /*!< Index of Swap system enable.*/
+    kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/
+};
+
+/*!
+ * @brief Enumeration for the two possilbe options of set FlexRAM function command.
  */
 typedef enum _flash_flexram_function_option
 {
-    kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU,    /*!< Option used to make FlexRAM available as RAM */
-    kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */
+    kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU,    /*!< An option used to make FlexRAM available as RAM */
+    kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */
 } flash_flexram_function_option_t;
 
 /*!
+ * @brief Enumeration for acceleration RAM property.
+ */
+enum _flash_acceleration_ram_property
+{
+    kFLASH_AccelerationRamSize = 0x400U
+};
+
+/*!
  * @brief Enumeration for the possible options of Swap function
  */
 typedef enum _flash_swap_function_option
 {
-    kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */
-    kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */
+    kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */
+    kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */
 } flash_swap_function_option_t;
 
 /*!
- * @brief Enumeration for the possible options of Swap Control commands
+ * @brief Enumeration for the possible options of Swap control commands
  */
 typedef enum _flash_swap_control_option
 {
-    kFLASH_swapControlOptionIntializeSystem = 0x01U,    /*!< Option used to Intialize Swap System */
-    kFLASH_swapControlOptionSetInUpdateState = 0x02U,   /*!< Option used to Set Swap in Update State */
-    kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */
-    kFLASH_swapControlOptionReportStatus = 0x08U,       /*!< Option used to Report Swap Status */
-    kFLASH_swapControlOptionDisableSystem = 0x10U       /*!< Option used to Disable Swap Status */
+    kFLASH_SwapControlOptionIntializeSystem = 0x01U,    /*!< An option used to initialize the Swap system */
+    kFLASH_SwapControlOptionSetInUpdateState = 0x02U,   /*!< An option used to set the Swap in an update state */
+    kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */
+    kFLASH_SwapControlOptionReportStatus = 0x08U,       /*!< An option used to report the Swap status */
+    kFLASH_SwapControlOptionDisableSystem = 0x10U       /*!< An option used to disable the Swap status */
 } flash_swap_control_option_t;
 
 /*!
- * @brief Enumeration for the possible flash swap status.
+ * @brief Enumeration for the possible flash Swap status.
  */
 typedef enum _flash_swap_state
 {
-    kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/
-    kFLASH_swapStateReady = 0x01U,         /*!< Flash swap system is in ready state.*/
-    kFLASH_swapStateUpdate = 0x02U,        /*!< Flash swap system is in update state.*/
-    kFLASH_swapStateUpdateErased = 0x03U,  /*!< Flash swap system is in updateErased state.*/
-    kFLASH_swapStateComplete = 0x04U,      /*!< Flash swap system is in complete state.*/
-    kFLASH_swapStateDisabled = 0x05U       /*!< Flash swap system is in disabled state.*/
+    kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/
+    kFLASH_SwapStateReady = 0x01U,         /*!< Flash Swap system is in a ready state.*/
+    kFLASH_SwapStateUpdate = 0x02U,        /*!< Flash Swap system is in an update state.*/
+    kFLASH_SwapStateUpdateErased = 0x03U,  /*!< Flash Swap system is in an updateErased state.*/
+    kFLASH_SwapStateComplete = 0x04U,      /*!< Flash Swap system is in a complete state.*/
+    kFLASH_SwapStateDisabled = 0x05U       /*!< Flash Swap system is in a disabled state.*/
 } flash_swap_state_t;
 
 /*!
- * @breif Enumeration for the possible flash swap block status
+ * @breif Enumeration for the possible flash Swap block status
  */
 typedef enum _flash_swap_block_status
 {
-    kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero =
+    kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero =
         0x00U, /*!< Swap block status is that lower half program block at zero.*/
-    kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero =
+    kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero =
         0x01U, /*!< Swap block status is that upper half program block at zero.*/
 } flash_swap_block_status_t;
 
 /*!
- * @brief Flash Swap information.
+ * @brief Flash Swap information
  */
 typedef struct _flash_swap_state_config
 {
-    flash_swap_state_t flashSwapState;                /*!< Current swap system status.*/
-    flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/
-    flash_swap_block_status_t nextSwapBlockStatus;    /*!< Next swap block status.*/
+    flash_swap_state_t flashSwapState;                /*!<The current Swap system status.*/
+    flash_swap_block_status_t currentSwapBlockStatus; /*!< The current Swap block status.*/
+    flash_swap_block_status_t nextSwapBlockStatus;    /*!< The next Swap block status.*/
 } flash_swap_state_config_t;
 
 /*!
- * @brief Flash Swap IFR fileds.
+ * @brief Flash Swap IFR fields
  */
 typedef struct _flash_swap_ifr_field_config
 {
-    uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/
-    uint16_t swapEnableWord;       /*!< Swap enable word field.*/
-    uint8_t reserved0[6];          /*!< Reserved field.*/
-    uint16_t swapDisableWord;      /*!< Swap disable word field.*/
-    uint8_t reserved1[4];          /*!< Reserved field.*/
+    uint16_t swapIndicatorAddress; /*!< A Swap indicator address field.*/
+    uint16_t swapEnableWord;       /*!< A Swap enable word field.*/
+    uint8_t reserved0[4];          /*!< A reserved field.*/
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    uint8_t reserved1[2];     /*!< A reserved field.*/
+    uint16_t swapDisableWord; /*!< A Swap disable word field.*/
+    uint8_t reserved2[4];     /*!< A reserved field.*/
+#endif
 } flash_swap_ifr_field_config_t;
 
 /*!
- * @brief Enumeration for FlexRAM load during reset option.
+ * @brief Flash Swap IFR field data
+ */
+typedef union _flash_swap_ifr_field_data
+{
+    uint32_t flashSwapIfrData[2];                    /*!< A flash Swap IFR field data .*/
+    flash_swap_ifr_field_config_t flashSwapIfrField; /*!< A flash Swap IFR field structure.*/
+} flash_swap_ifr_field_data_t;
+
+/*!
+ * @brief PFlash protection status - low 32bit
+ */
+typedef union _pflash_protection_status_low
+{
+    uint32_t protl32b; /*!< PROT[31:0] .*/
+    struct
+    {
+        uint8_t protsl; /*!< PROTS[7:0] .*/
+        uint8_t protsh; /*!< PROTS[15:8] .*/
+        uint8_t reserved[2];
+    } prots16b;
+} pflash_protection_status_low_t;
+
+/*!
+ * @brief PFlash protection status - full
+ */
+typedef struct _pflash_protection_status
+{
+    pflash_protection_status_low_t valueLow32b; /*!< PROT[31:0] or PROTS[15:0].*/
+#if ((FSL_FEATURE_FLASH_IS_FTFA == 1) && (defined(FTFA_FPROTH0_PROT_MASK))) || \
+    ((FSL_FEATURE_FLASH_IS_FTFE == 1) && (defined(FTFE_FPROTH0_PROT_MASK))) || \
+    ((FSL_FEATURE_FLASH_IS_FTFL == 1) && (defined(FTFL_FPROTH0_PROT_MASK)))
+    // uint32_t protHigh; /*!< PROT[63:32].*/
+    struct
+    {
+        uint32_t proth32b;
+    } valueHigh32b;
+#endif
+} pflash_protection_status_t;
+
+/*!
+ * @brief Enumeration for the FlexRAM load during reset option.
  */
 typedef enum _flash_partition_flexram_load_option
 {
-    kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData =
+    kFLASH_PartitionFlexramLoadOptionLoadedWithValidEepromData =
         0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/
-    kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
+    kFLASH_PartitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
 } flash_partition_flexram_load_option_t;
 
-/*! @brief callback type used for pflash block*/
+/*!
+ * @brief Enumeration for the flash memory index.
+ */
+typedef enum _flash_memory_index
+{
+    kFLASH_MemoryIndexPrimaryFlash = 0x00U,   /*!< Current flash memory is primary flash.*/
+    kFLASH_MemoryIndexSecondaryFlash = 0x01U, /*!< Current flash memory is secondary flash.*/
+} flash_memory_index_t;
+
+/*!
+ * @brief Enumeration for the flash cache controller index.
+ */
+typedef enum _flash_cache_controller_index
+{
+    kFLASH_CacheControllerIndexForCore0 = 0x00U, /*!< Current flash cache controller is for core 0.*/
+    kFLASH_CacheControllerIndexForCore1 = 0x01U, /*!< Current flash cache controller is for core 1.*/
+} flash_cache_controller_index_t;
+
+/*! @brief A callback type used for the Pflash block*/
 typedef void (*flash_callback_t)(void);
 
 /*!
- * @brief Active flash information for current operation.
+ * @brief Enumeration for the two possible options of flash prefetch speculation.
+ */
+typedef enum _flash_prefetch_speculation_option
+{
+    kFLASH_prefetchSpeculationOptionEnable = 0x00U,
+    kFLASH_prefetchSpeculationOptionDisable = 0x01U
+} flash_prefetch_speculation_option_t;
+
+/*!
+ * @brief Flash prefetch speculation status.
+ */
+typedef struct _flash_prefetch_speculation_status
+{
+    flash_prefetch_speculation_option_t instructionOption; /*!< Instruction speculation.*/
+    flash_prefetch_speculation_option_t dataOption;        /*!< Data speculation.*/
+} flash_prefetch_speculation_status_t;
+
+/*!
+ * @brief Flash cache clear process code.
+ */
+typedef enum _flash_cache_clear_process
+{
+    kFLASH_CacheClearProcessPre = 0x00U,  /*!< Pre flash cache clear process.*/
+    kFLASH_CacheClearProcessPost = 0x01U, /*!< Post flash cache clear process.*/
+} flash_cache_clear_process_t;
+
+/*!
+ * @brief Active flash protection information for the current operation.
+ */
+typedef struct _flash_protection_config
+{
+    uint32_t regionBase;  /*!< Base address of flash protection region.*/
+    uint32_t regionSize;  /*!< size of flash protection region.*/
+    uint32_t regionCount; /*!< flash protection region count.*/
+} flash_protection_config_t;
+
+/*!
+ * @brief Active flash Execute-Only access information for the current operation.
+ */
+typedef struct _flash_access_config
+{
+    uint32_t SegmentBase;  /*!< Base address of flash Execute-Only segment.*/
+    uint32_t SegmentSize;  /*!< size of flash Execute-Only segment.*/
+    uint32_t SegmentCount; /*!< flash Execute-Only segment count.*/
+} flash_access_config_t;
+
+/*!
+ * @brief Active flash information for the current operation.
  */
 typedef struct _flash_operation_config
 {
-    uint32_t convertedAddress;           /*!< Converted address for current flash type.*/
-    uint32_t activeSectorSize;           /*!< Sector size of current flash type.*/
-    uint32_t activeBlockSize;            /*!< Block size of current flash type.*/
-    uint32_t blockWriteUnitSize;         /*!< write unit size.*/
-    uint32_t sectorCmdAddressAligment;   /*!< Erase sector command address alignment.*/
-    uint32_t sectionCmdAddressAligment;  /*!< Program/Verify section command address alignment.*/
-    uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/
-    uint32_t checkCmdAddressAligment;    /*!< Program check command address alignment.*/
+    uint32_t convertedAddress;           /*!< A converted address for the current flash type.*/
+    uint32_t activeSectorSize;           /*!< A sector size of the current flash type.*/
+    uint32_t activeBlockSize;            /*!< A block size of the current flash type.*/
+    uint32_t blockWriteUnitSize;         /*!< The write unit size.*/
+    uint32_t sectorCmdAddressAligment;   /*!< An erase sector command address alignment.*/
+    uint32_t sectionCmdAddressAligment;  /*!< A program/verify section command address alignment.*/
+    uint32_t resourceCmdAddressAligment; /*!< A read resource command address alignment.*/
+    uint32_t checkCmdAddressAligment;    /*!< A program check command address alignment.*/
 } flash_operation_config_t;
 
 /*! @brief Flash driver state information.
@@ -410,25 +568,29 @@
  */
 typedef struct _flash_config
 {
-    uint32_t PFlashBlockBase;                /*!< Base address of the first PFlash block */
-    uint32_t PFlashTotalSize;                /*!< Size of all combined PFlash block. */
-    uint32_t PFlashBlockCount;               /*!< Number of PFlash blocks. */
-    uint32_t PFlashSectorSize;               /*!< Size in bytes of a sector of PFlash. */
-    flash_callback_t PFlashCallback;         /*!< Callback function for flash API. */
-    uint32_t PFlashAccessSegmentSize;        /*!< Size in bytes of a access segment of PFlash. */
-    uint32_t PFlashAccessSegmentCount;       /*!< Number of PFlash access segments. */
-    uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */
-    uint32_t FlexRAMBlockBase;               /*!< For FlexNVM device, this is the base address of FlexRAM
-                                                  For non-FlexNVM device, this is the base address of acceleration RAM memory */
-    uint32_t FlexRAMTotalSize;               /*!< For FlexNVM device, this is the size of FlexRAM
-                                                  For non-FlexNVM device, this is the size of acceleration RAM memory */
-    uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory);
-                                   For non-FlexNVM device, this field is unused */
-    uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory;
-                                   For non-FlexNVM device, this field is unused */
-    uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned
-                                 from FlexRAM;
-                                   For non-FlexNVM device, this field is unused */
+    uint32_t PFlashBlockBase;                /*!< A base address of the first PFlash block */
+    uint32_t PFlashTotalSize;                /*!< The size of the combined PFlash block. */
+    uint8_t PFlashBlockCount;                /*!< A number of PFlash blocks. */
+    uint8_t FlashMemoryIndex;                /*!< 0 - primary flash; 1 - secondary flash*/
+    uint8_t FlashCacheControllerIndex;       /*!< 0 - Controller for core 0; 1 - Controller for core 1 */
+    uint8_t Reserved0;                       /*!< Reserved field 0 */
+    uint32_t PFlashSectorSize;               /*!< The size in bytes of a sector of PFlash. */
+    flash_callback_t PFlashCallback;         /*!< The callback function for the flash API. */
+    uint32_t PFlashAccessSegmentSize;        /*!< A size in bytes of an access segment of PFlash. */
+    uint32_t PFlashAccessSegmentCount;       /*!< A number of PFlash access segments. */
+    uint32_t *flashExecuteInRamFunctionInfo; /*!< An information structure of the flash execute-in-RAM function. */
+    uint32_t FlexRAMBlockBase;               /*!< For the FlexNVM device, this is the base address of the FlexRAM */
+    /*!< For the non-FlexNVM device, this is the base address of the acceleration RAM memory */
+    uint32_t FlexRAMTotalSize; /*!< For the FlexNVM device, this is the size of the FlexRAM */
+                               /*!< For the non-FlexNVM device, this is the size of the acceleration RAM memory */
+    uint32_t
+        DFlashBlockBase; /*!< For the FlexNVM device, this is the base address of the D-Flash memory (FlexNVM memory) */
+                         /*!< For the non-FlexNVM device, this field is unused */
+    uint32_t DFlashTotalSize; /*!< For the FlexNVM device, this is the total size of the FlexNVM memory; */
+                              /*!< For the non-FlexNVM device, this field is unused */
+    uint32_t EEpromTotalSize; /*!< For the FlexNVM device, this is the size in bytes of the EEPROM area which was
+                                 partitioned from FlexRAM */
+    /*!< For the non-FlexNVM device, this field is unused */
 } flash_config_t;
 
 /*******************************************************************************
@@ -445,37 +607,37 @@
  */
 
 /*!
- * @brief Initializes global flash properties structure members
+ * @brief Initializes the global flash properties structure members.
  *
- * This function checks and initializes Flash module for the other Flash APIs.
+ * This function checks and initializes the Flash module for the other Flash APIs.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config Pointer to the storage for the driver runtime state.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 status_t FLASH_Init(flash_config_t *config);
 
 /*!
- * @brief Set the desired flash callback function
+ * @brief Sets the desired flash callback function.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param callback callback function to be stored in driver
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param callback A callback function to be stored in the driver.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback);
 
 /*!
- * @brief Prepare flash execute-in-ram functions
+ * @brief Prepares flash execute-in-RAM functions.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config Pointer to the storage for the driver runtime state.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config);
@@ -491,59 +653,59 @@
 /*!
  * @brief Erases entire flash
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 status_t FLASH_EraseAll(flash_config_t *config, uint32_t key);
 
 /*!
- * @brief Erases flash sectors encompassed by parameters passed into function
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
  *
  * This function erases the appropriate number of flash sectors based on the
  * desired start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config The pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be erased.
- *              The start address does not need to be sector aligned but must be word-aligned.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words)
- *                      to be erased. Must be word aligned.
- * @param key value used to validate all flash erase APIs.
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
+ * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
 
 /*!
- * @brief Erases entire flash, including protected sectors.
+ * @brief Erases the entire flash, including protected sectors.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
 status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
@@ -552,16 +714,16 @@
 /*!
  * @brief Erases all program flash execute-only segments defined by the FXACC registers.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key);
 
@@ -573,101 +735,101 @@
  */
 
 /*!
- * @brief Programs flash with data at locations passed in through parameters
+ * @brief Programs flash with data at locations passed in through parameters.
  *
- * This function programs the flash memory with desired data for a given
- * flash area as determined by the start address and length.
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
 
 /*!
- * @brief Programs Program Once Field through parameters
+ * @brief Programs Program Once Field through parameters.
  *
- * This function programs the Program Once Field with desired data for a given
+ * This function programs the Program Once Field with the desired data for a given
  * flash area as determined by the index and length.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param index The index indicating which area of Program Once Field to be programmed.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating which area of the Program Once Field to be programmed.
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the Program Once Field.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
 
 /*!
- * @brief Programs flash with data at locations passed in through parameters via Program Section command
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
  *
- * This function programs the flash memory with desired data for a given
+ * This function programs the flash memory with the desired data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as RAM.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom
+ * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
 status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
 #endif
 
 /*!
- * @brief Programs EEPROM with data at locations passed in through parameters
+ * @brief Programs the EEPROM with data at locations passed in through parameters.
  *
- * This function programs the Emulated EEPROM with desired data for a given
+ * This function programs the emulated EEPROM with the desired data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
  * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram
+ * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover the FlexRAM as RAM.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
@@ -681,27 +843,27 @@
  */
 
 /*!
- * @brief Read resource with data at locations passed in through parameters
+ * @brief Reads the resource with data at locations passed in through parameters.
  *
- * This function reads the flash memory with desired location for a given
+ * This function reads the flash memory with the desired location for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param dst Pointer to the destination buffer of data that is used to store
+ * @param dst A pointer to the destination buffer of data that is used to store
  *        data to be read.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be read. Must be word-aligned.
  * @param option The resource option which indicates which area should be read back.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
 status_t FLASH_ReadResource(
@@ -709,23 +871,23 @@
 #endif
 
 /*!
- * @brief Read Program Once Field through parameters
+ * @brief Reads the Program Once Field through parameters.
  *
- * This function reads the read once feild with given index and length
+ * This function reads the read once feild with given index and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param index The index indicating the area of program once field to be read.
- * @param dst Pointer to the destination buffer of data that is used to store
+ * @param dst A pointer to the destination buffer of data that is used to store
  *        data to be read.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
 
@@ -737,35 +899,35 @@
  */
 
 /*!
- * @brief Returns the security state via the pointer passed into the function
+ * @brief Returns the security state via the pointer passed into the function.
  *
- * This function retrieves the current Flash security status, including the
+ * This function retrieves the current flash security status, including the
  * security enabling state and the backdoor key enabling state.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param state Pointer to the value returned for the current security status code:
+ * @param config A pointer to storage for the driver runtime state.
+ * @param state A pointer to the value returned for the current security status code:
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state);
 
 /*!
- * @brief Allows user to bypass security with a backdoor key
+ * @brief Allows users to bypass security with a backdoor key.
  *
- * If the MCU is in secured state, this function will unsecure the MCU by
- * comparing the provided backdoor key with ones in the Flash Configuration
- * Field.
+ * If the MCU is in secured state, this function unsecures the MCU by
+ * comparing the provided backdoor key with ones in the flash configuration
+ * field.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param backdoorKey Pointer to the user buffer containing the backdoor key.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param backdoorKey A pointer to the user buffer containing the backdoor key.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey);
 
@@ -777,75 +939,75 @@
  */
 
 /*!
- * @brief Verifies erasure of entire flash at specified margin level
+ * @brief Verifies erasure of the entire flash at a specified margin level.
  *
- * This function will check to see if the flash have been erased to the
+ * This function checks whether the flash is erased to the
  * specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param margin Read margin choice
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin);
 
 /*!
- * @brief Verifies erasure of desired flash area at specified margin level
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
  *
- * This function will check the appropriate number of flash sectors based on
- * the desired start address and length to see if the flash have been erased
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
  * to the specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be verified.
- *        The start address does not need to be sector aligned but must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be verified. Must be word-aligned.
- * @param margin Read margin choice
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin);
 
 /*!
- * @brief Verifies programming of desired flash area at specified margin level
+ * @brief Verifies programming of the desired flash area at a specified margin level.
  *
  * This function verifies the data programed in the flash memory using the
- * Flash Program Check Command and compares it with expected data for a given
+ * Flash Program Check Command and compares it to the expected data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be verified. Must be word-aligned.
- * @param expectedData Pointer to the expected data that is to be
+ * @param expectedData A pointer to the expected data that is to be
  *        verified against.
- * @param margin Read margin choice
- * @param failedAddress Pointer to returned failing address.
- * @param failedData Pointer to returned failing data.  Some derivitives do
- *        not included failed data as part of the FCCOBx registers.  In this
+ * @param margin Read margin choice.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
  *        case, zeros are returned upon failure.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t start,
@@ -856,18 +1018,18 @@
                              uint32_t *failedData);
 
 /*!
- * @brief Verifies if the program flash executeonly segments have been erased to
- *  the specified read margin level
+ * @brief Verifies whether the program flash execute-only segments have been erased to
+ *  the specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param margin Read margin choice
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin);
 
@@ -879,22 +1041,22 @@
  */
 
 /*!
- * @brief Returns the protection state of desired flash area via the pointer passed into the function
+ * @brief Returns the protection state of the desired flash area via the pointer passed into the function.
  *
- * This function retrieves the current Flash protect status for a given
+ * This function retrieves the current flash protect status for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words)
  *        to be checked.  Must be word-aligned.
- * @param protection_state Pointer to the value returned for the current
+ * @param protection_state A pointer to the value returned for the current
  *        protection status code for the desired flash area.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
  */
 status_t FLASH_IsProtected(flash_config_t *config,
                            uint32_t start,
@@ -902,22 +1064,22 @@
                            flash_protection_state_t *protection_state);
 
 /*!
- * @brief Returns the access state of desired flash area via the pointer passed into the function
+ * @brief Returns the access state of the desired flash area via the pointer passed into the function.
  *
- * This function retrieves the current Flash access status for a given
+ * This function retrieves the current flash access status for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be checked.  Must be word-aligned.
- * @param access_state Pointer to the value returned for the current
+ * @param access_state A pointer to the value returned for the current
  *        access status code for the desired flash area.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned to the specified baseline.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
  */
 status_t FLASH_IsExecuteOnly(flash_config_t *config,
                              uint32_t start,
@@ -934,17 +1096,33 @@
 /*!
  * @brief Returns the desired flash property.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param whichProperty The desired property from the list of properties in
  *        enum flash_property_tag_t
- * @param value Pointer to the value returned for the desired flash property
+ * @param value A pointer to the value returned for the desired flash property.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_UnknownProperty unknown property tag
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
  */
 status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
 
+/*!
+ * @brief Sets the desired flash property.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value A to set for the desired flash property.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
+ * @retval #kStatus_FLASH_InvalidPropertyValue An invalid property value.
+ * @retval #kStatus_FLASH_ReadOnlyProperty An read-only property tag.
+ */
+status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value);
+
 /*@}*/
 
 /*!
@@ -953,17 +1131,17 @@
  */
 
 /*!
- * @brief Set FlexRAM Function command
+ * @brief Sets the FlexRAM function command.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param option The option used to set work mode of FlexRAM
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option The option used to set the work mode of FlexRAM.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
 status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option);
@@ -977,21 +1155,21 @@
  */
 
 /*!
- * @brief Configure Swap function or Check the swap state of Flash Module
+ * @brief Configures the Swap function or checks the the swap state of the Flash module.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param address Address used to configure the flash swap function
- * @param option The possible option used to configure Flash Swap function or check the flash swap status
- * @param returnInfo Pointer to the data which is used to return the information of flash swap.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param address Address used to configure the flash Swap function.
+ * @param option The possible option used to configure Flash Swap function or check the flash Swap status
+ * @param returnInfo A pointer to the data which is used to return the information of flash Swap.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
 status_t FLASH_SwapControl(flash_config_t *config,
@@ -1001,21 +1179,21 @@
 #endif
 
 /*!
- * @brief Swap the lower half flash with the higher half flaock
+ * @brief Swaps the lower half flash with the higher half flash.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param address Address used to configure the flash swap function
- * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ * @param option The possible option used to configure the Flash Swap function or check the flash Swap status.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state
+ * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in an uninitialzed state.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
 status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option);
@@ -1036,9 +1214,9 @@
  * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
  *        memory supporting EEPROM functions.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
  * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
@@ -1058,51 +1236,54 @@
 */
 
 /*!
- * @brief Set PFLASH Protection to the intended protection status.
+ * @brief Sets the PFlash Protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is
- * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest
- * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * @param config A pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * corresponding to protection of 1/32(64) of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of PFlash. The most significant bit is corresponding to the highest address area of PFlash. There are
  * two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
-status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus);
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus);
 
 /*!
- * @brief Get PFLASH Protection Status.
+ * @brief Gets the PFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the
- * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant
- * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below:
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  Protect status returned by the PFlash IP. Each bit is corresponding to the protection of
+ * 1/32(64)
+ * of the
+ * total PFlash. The least significant bit corresponds to the lowest address area of the PFlash. The most significant
+ * bit corresponds to the highest address area of PFlash. There are two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
-status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus);
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus);
 
 /*!
- * @brief Set DFLASH Protection to the intended protection status.
+ * @brief Sets the DFlash protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is
- * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest
- * address area of DFlash. The most significant bit is corresponding to the highest address area of  DFlash. There are
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the DFlash protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total DFlash. The least significant bit corresponds to the lowest
+ * address area of the DFlash. The most significant bit corresponds to the highest address area of  the DFlash. There
+ * are
  * two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
@@ -1110,38 +1291,39 @@
 #endif
 
 /*!
- * @brief Get DFLASH Protection Status.
+ * @brief Gets the DFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
- * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most
- * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total DFlash. The least significant bit corresponds to the lowest address area of the DFlash. The most
+ * significant bit corresponds to the highest address area of the DFlash, and so on. There are two possible cases as
  * below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus);
 #endif
 
 /*!
- * @brief Set EEPROM Protection to the intended protection status.
+ * @brief Sets the EEPROM protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is
- * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest
- * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the EEPROM protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total EEPROM. The least significant bit corresponds to the lowest
+ * address area of the EEPROM. The most significant bit corresponds to the highest address area of EEPROM, and so on.
  * There are two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
@@ -1149,18 +1331,19 @@
 #endif
 
 /*!
- * @brief Get DFLASH Protection Status.
+ * @brief Gets the DFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
- * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most
- * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below:
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total EEPROM. The least significant bit corresponds to the lowest address area of the EEPROM. The most
+ * significant bit corresponds to the highest address area of the EEPROM. There are two possible cases as below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus);
@@ -1168,6 +1351,32 @@
 
 /*@}*/
 
+/*@}*/
+
+/*!
+* @name Flash Speculation Utilities
+* @{
+*/
+
+/*!
+ * @brief Sets the PFlash prefetch speculation to the intended speculation status.
+ *
+ * @param speculationStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidSpeculationOption An invalid speculation option argument is provided.
+ */
+status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus);
+
+/*!
+ * @brief Gets the PFlash prefetch speculation status.
+ *
+ * @param speculationStatus  Speculation status returned by the PFlash IP.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ */
+status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus);
+
+/*@}*/
+
 #if defined(__cplusplus)
 }
 #endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -50,8 +50,10 @@
 /*! @brief Pointers to FLEXBUS bases for each instance. */
 static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to FLEXBUS clocks for each instance. */
 static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -62,7 +64,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FB_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_flexbusBases); instance++)
     {
         if (s_flexbusBases[instance] == base)
         {
@@ -70,7 +72,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FB_COUNT);
+    assert(instance < ARRAY_SIZE(s_flexbusBases));
 
     return instance;
 }
@@ -84,8 +86,10 @@
     uint32_t chip = 0;
     uint32_t reg_value = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock for FLEXBUS */
     CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset all the register to default state */
     for (chip = 0; chip < FB_CSAR_COUNT; chip++)
@@ -168,8 +172,10 @@
 
 void FLEXBUS_Deinit(FB_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate clock for FLEXBUS */
-    CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+    CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 /*@}*/
 
 /*!
@@ -197,11 +196,11 @@
  *
  * This function enables the clock gate for FlexBus module.
  * Only chip 0 is validated and set to known values. Other chips are disabled.
- * NOTE: In this function, certain parameters, depending on external memories,  must
- * be set before using FLEXBUS_Init() function.
+ * Note that in this function, certain parameters, depending on external memories,  must
+ * be set before using the FLEXBUS_Init() function.
  * This example shows how to set up the uart_state_t and the
  * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
- * in these parameters:
+ * in these parameters.
    @code
     flexbus_config_t flexbusConfig;
     FLEXBUS_GetDefaultConfig(&flexbusConfig);
@@ -212,7 +211,7 @@
    @endcode
  *
  * @param base FlexBus peripheral address.
- * @param config Pointer to the configure structure
+ * @param config Pointer to the configuration structure
 */
 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config);
 
@@ -229,7 +228,7 @@
  * @brief Initializes the FlexBus configuration structure.
  *
  * This function initializes the FlexBus configuration structure to default value. The default
- * values are:
+ * values are.
    @code
    fbConfig->chip                   = 0;
    fbConfig->writeProtect           = 0;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -165,8 +165,6 @@
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-/* Array of FlexCAN handle. */
-static flexcan_handle_t *s_flexcanHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT];
 
 /* Array of FlexCAN peripheral base address. */
 static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
@@ -179,8 +177,17 @@
 static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS;
 static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
 
+/* Array of FlexCAN handle. */
+static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)];
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of FlexCAN clock name. */
 static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+/* Array of FlexCAN serial clock name. */
+static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS;
+#endif /* FLEXCAN_PERIPH_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* FlexCAN ISR for transactional APIs. */
 static flexcan_isr_t s_flexcanIsr;
@@ -194,7 +201,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FLEXCAN_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++)
     {
         if (s_flexcanBases[instance] == base)
         {
@@ -202,7 +209,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FLEXCAN_COUNT);
+    assert(instance < ARRAY_SIZE(s_flexcanBases));
 
     return instance;
 }
@@ -314,9 +321,13 @@
     else
     {
         if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32))))
+        {
             return true;
+        }
         else
+        {
             return false;
+        }
     }
 #endif
 }
@@ -420,14 +431,25 @@
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz)
 {
     uint32_t mcrTemp;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance;
+#endif
 
     /* Assertion. */
     assert(config);
     assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)));
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    instance = FLEXCAN_GetInstance(base);
     /* Enable FlexCAN clock. */
-    CLOCK_EnableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]);
+    CLOCK_EnableClock(s_flexcanClock[instance]);
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+    /* Enable FlexCAN serial clock. */
+    CLOCK_EnableClock(s_flexcanPeriphClock[instance]);
+#endif /* FLEXCAN_PERIPH_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     /* Disable FlexCAN Module. */
     FLEXCAN_Enable(base, false);
 
@@ -436,6 +458,7 @@
      */
     base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK :
                                                            base->CTRL1 | CAN_CTRL1_CLKSRC_MASK;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
 
     /* Enable FlexCAN Module for configuartion. */
     FLEXCAN_Enable(base, true);
@@ -472,14 +495,24 @@
 
 void FLEXCAN_Deinit(CAN_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance;
+#endif
     /* Reset all Register Contents. */
     FLEXCAN_Reset(base);
 
     /* Disable FlexCAN module. */
     FLEXCAN_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    instance = FLEXCAN_GetInstance(base);
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+    /* Disable FlexCAN serial clock. */
+    CLOCK_DisableClock(s_flexcanPeriphClock[instance]);
+#endif /* FLEXCAN_PERIPH_CLOCKS */
     /* Disable FlexCAN clock. */
-    CLOCK_DisableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]);
+    CLOCK_DisableClock(s_flexcanClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
@@ -488,7 +521,9 @@
     assert(config);
 
     /* Initialize FlexCAN Module config struct with default value. */
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     config->clkSrc = kFLEXCAN_ClkSrcOsc;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
     config->baudRate = 125000U;
     config->maxMbNum = 16;
     config->enableLoopBack = false;
@@ -1293,13 +1328,13 @@
            (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
                             kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
 #else
-        while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
-               (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
-                                kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
+    while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
+            (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
+                            kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
 #endif
 }
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 0)
+#if defined(CAN0)
 void CAN0_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[0]);
@@ -1308,7 +1343,7 @@
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 1)
+#if defined(CAN1)
 void CAN1_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[1]);
@@ -1317,7 +1352,7 @@
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 2)
+#if defined(CAN2)
 void CAN2_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[2]);
@@ -1326,7 +1361,7 @@
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 3)
+#if defined(CAN3)
 void CAN3_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[3]);
@@ -1335,7 +1370,7 @@
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 4)
+#if defined(CAN4)
 void CAN4_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[4]);
@@ -1343,3 +1378,30 @@
     s_flexcanIsr(CAN4, s_flexcanHandle[4]);
 }
 #endif
+
+#if defined(DMA_CAN0)
+void DMA_FLEXCAN0_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
+
+    s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
+}
+#endif
+
+#if defined(DMA_CAN1)
+void DMA_FLEXCAN1_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
+
+    s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
+}
+#endif
+
+#if defined(DMA_CAN2)
+void DMA_FLEXCAN2_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
+
+    s_flexcanIsr(DMA_CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
+}
+#endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,15 +37,14 @@
  * @{
  */
 
-
 /******************************************************************************
  * Definitions
  *****************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexCAN driver version 2.1.0. */
-#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief FlexCAN driver version 2.2.0. */
+#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 /*! @brief FlexCAN Frame ID helper macro. */
@@ -69,19 +68,18 @@
      (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)                     \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-     (FLEXCAN_ID_STD(id) << 16)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
+     (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
-     FLEXCAN_ID_STD(id)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
+     (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
-#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)                                                                 \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. \
-                                                */
+    (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
+#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
+    (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
+    (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
+    (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)                          \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
      (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
@@ -157,7 +155,7 @@
     kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6),     /*!< Rx Message FIFO is Busy. */
     kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7),     /*!< Rx Message FIFO is Idle. */
     kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
-    kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 0),  /*!< Rx Message FIFO is almost overflowed. */
+    kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9),  /*!< Rx Message FIFO is almost overflowed. */
     kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10),   /*!< FlexCAN Module Error and Status. */
     kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11),     /*!< UnHadled Interrupt asserted. */
 };
@@ -176,12 +174,14 @@
     kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
 } flexcan_frame_type_t;
 
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
 /*! @brief FlexCAN clock source. */
 typedef enum _flexcan_clock_source
 {
     kFLEXCAN_ClkSrcOsc = 0x0U,  /*!< FlexCAN Protocol Engine clock from Oscillator. */
     kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
 } flexcan_clock_source_t;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
 
 /*! @brief FlexCAN Rx Fifo Filter type. */
 typedef enum _flexcan_rx_fifo_filter_type
@@ -195,7 +195,7 @@
 } flexcan_rx_fifo_filter_type_t;
 
 /*!
- * @brief FlexCAN Rx FIFO priority
+ * @brief FlexCAN Rx FIFO priority.
  *
  * The matching process starts from the Rx MB(or Rx FIFO) with higher priority.
  * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with
@@ -326,7 +326,9 @@
 typedef struct _flexcan_config
 {
     uint32_t baudRate;             /*!< FlexCAN baud rate in bps. */
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
     uint8_t maxMbNum;              /*!< The maximum number of Message Buffers used by user. */
     bool enableLoopBack;           /*!< Enable or Disable Loop Back Self Test Mode. */
     bool enableSelfWakeup;         /*!< Enable or Disable Self Wakeup Mode. */
@@ -366,7 +368,7 @@
 /*! @brief FlexCAN Rx FIFO configuration structure. */
 typedef struct _flexcan_rx_fifo_config
 {
-    uint32_t *idFilterTable;                    /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
+    uint32_t *idFilterTable;                    /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */
     uint8_t idFilterNum;                        /*!< The quantity of filter elements. */
     flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */
     flexcan_rx_fifo_priority_t priority;        /*!< The FlexCAN Rx FIFO receive priority. */
@@ -431,7 +433,7 @@
  *
  * This function initializes the FlexCAN module with user-defined settings.
  * This example shows how to set up the flexcan_config_t parameters and how
- * to call the FLEXCAN_Init function by passing in these parameters:
+ * to call the FLEXCAN_Init function by passing in these parameters.
  *  @code
  *   flexcan_config_t flexcanConfig;
  *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
@@ -445,7 +447,7 @@
  *   @endcode
  *
  * @param base FlexCAN peripheral base address.
- * @param config Pointer to user-defined configuration structure.
+ * @param config Pointer to the user-defined configuration structure.
  * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
  */
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz);
@@ -453,18 +455,18 @@
 /*!
  * @brief De-initializes a FlexCAN instance.
  *
- * This function disable the FlexCAN module clock and set all register value
- * to reset value.
+ * This function disables the FlexCAN module clock and sets all register values
+ * to the reset value.
  *
  * @param base FlexCAN peripheral base address.
  */
 void FLEXCAN_Deinit(CAN_Type *base);
 
 /*!
- * @brief Get the default configuration structure.
+ * @brief Gets the default configuration structure.
  *
- * This function initializes the FlexCAN configuration structure to default value. The default
- * value are:
+ * This function initializes the FlexCAN configuration structure to default values. The default
+ * values are as follows.
  *   flexcanConfig->clkSrc            = KFLEXCAN_ClkSrcOsc;
  *   flexcanConfig->baudRate          = 125000U;
  *   flexcanConfig->maxMbNum          = 16;
@@ -473,7 +475,7 @@
  *   flexcanConfig->enableIndividMask = false;
  *   flexcanConfig->enableDoze        = false;
  *
- * @param config Pointer to FlexCAN configuration structure.
+ * @param config Pointer to the FlexCAN configuration structure.
  */
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config);
 
@@ -503,7 +505,7 @@
 /*!
  * @brief Sets the FlexCAN receive message buffer global mask.
  *
- * This function sets the global mask for FlexCAN message buffer in a matching process.
+ * This function sets the global mask for the FlexCAN message buffer in a matching process.
  * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
  *
  * @param base FlexCAN peripheral base address.
@@ -524,12 +526,12 @@
 /*!
  * @brief Sets the FlexCAN receive individual mask.
  *
- * This function sets the individual mask for FlexCAN matching process.
- * The configuration is only effective when the Rx individual mask is enabled in FLEXCAN_Init().
- * If Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
- * If Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
- * the Rx Filter with same index. What calls for special attention is that only the first 32
- * individual masks can be used as Rx FIFO filter mask.
+ * This function sets the individual mask for the FlexCAN matching process.
+ * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init().
+ * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
+ * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
+ * the Rx Filter with the same index. Note that only the first 32
+ * individual masks can be used as the Rx FIFO filter mask.
  *
  * @param base FlexCAN peripheral base address.
  * @param maskIdx The Index of individual Mask.
@@ -545,7 +547,7 @@
  *
  * @param base FlexCAN peripheral base address.
  * @param mbIdx The Message Buffer index.
- * @param enable Enable/Disable Tx Message Buffer.
+ * @param enable Enable/disable Tx Message Buffer.
  *               - true: Enable Tx Message Buffer.
  *               - false: Disable Tx Message Buffer.
  */
@@ -559,8 +561,8 @@
  *
  * @param base FlexCAN peripheral base address.
  * @param mbIdx The Message Buffer index.
- * @param config Pointer to FlexCAN Message Buffer configuration structure.
- * @param enable Enable/Disable Rx Message Buffer.
+ * @param config Pointer to the FlexCAN Message Buffer configuration structure.
+ * @param enable Enable/disable Rx Message Buffer.
  *               - true: Enable Rx Message Buffer.
  *               - false: Disable Rx Message Buffer.
  */
@@ -572,8 +574,8 @@
  * This function configures the Rx FIFO with given Rx FIFO configuration.
  *
  * @param base FlexCAN peripheral base address.
- * @param config Pointer to FlexCAN Rx FIFO configuration structure.
- * @param enable Enable/Disable Rx FIFO.
+ * @param config Pointer to the FlexCAN Rx FIFO configuration structure.
+ * @param enable Enable/disable Rx FIFO.
  *               - true: Enable Rx FIFO.
  *               - false: Disable Rx FIFO.
  */
@@ -676,7 +678,7 @@
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFF);
+    base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
     base->IFLAG2 = (uint32_t)(mask >> 32);
 #else
     base->IFLAG1 = mask;
@@ -691,9 +693,9 @@
  */
 
 /*!
- * @brief Enables FlexCAN interrupts according to provided mask.
+ * @brief Enables FlexCAN interrupts according to the provided mask.
  *
- * This function enables the FlexCAN interrupts according to provided mask. The mask
+ * This function enables the FlexCAN interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
  *
  * @param base FlexCAN peripheral base address.
@@ -712,9 +714,9 @@
 }
 
 /*!
- * @brief Disables FlexCAN interrupts according to provided mask.
+ * @brief Disables FlexCAN interrupts according to the provided mask.
  *
- * This function disables the FlexCAN interrupts according to provided mask. The mask
+ * This function disables the FlexCAN interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
  *
  * @param base FlexCAN peripheral base address.
@@ -735,7 +737,7 @@
 /*!
  * @brief Enables FlexCAN Message Buffer interrupts.
  *
- * This function enables the interrupts of given Message Buffers
+ * This function enables the interrupts of given Message Buffers.
  *
  * @param base FlexCAN peripheral base address.
  * @param mask The ORed FlexCAN Message Buffer mask.
@@ -747,7 +749,7 @@
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFF);
+    base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
     base->IMASK2 |= (uint32_t)(mask >> 32);
 #else
     base->IMASK1 |= mask;
@@ -757,7 +759,7 @@
 /*!
  * @brief Disables FlexCAN Message Buffer interrupts.
  *
- * This function disables the interrupts of given Message Buffers
+ * This function disables the interrupts of given Message Buffers.
  *
  * @param base FlexCAN peripheral base address.
  * @param mask The ORed FlexCAN Message Buffer mask.
@@ -769,7 +771,7 @@
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFF));
+    base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
     base->IMASK2 &= ~((uint32_t)(mask >> 32));
 #else
     base->IMASK1 &= ~mask;
@@ -846,7 +848,7 @@
 }
 
 /*!
- * @brief Writes a FlexCAN Message to Transmit Message Buffer.
+ * @brief Writes a FlexCAN Message to the Transmit Message Buffer.
  *
  * This function writes a CAN Message to the specified Transmit Message Buffer
  * and changes the Message Buffer state to start CAN Message transmit. After
@@ -938,7 +940,7 @@
 /*!
  * @brief Initializes the FlexCAN handle.
  *
- * This function initializes the FlexCAN handle which can be used for other FlexCAN
+ * This function initializes the FlexCAN handle, which can be used for other FlexCAN
  * transactional APIs. Usually, for a specified FlexCAN instance,
  * call this API once to get the initialized handle.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -72,8 +72,10 @@
 /*! @brief Pointers to FTM bases for each instance. */
 static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to FTM clocks for each instance. */
 static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -228,8 +230,10 @@
         return kStatus_Fail;
     }
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the FTM clock*/
     CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure the fault mode, enable FTM mode and disable write protection */
     base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK;
@@ -266,7 +270,13 @@
 #endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */
 
     /* FTM deadtime insertion control */
-    base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue));
+    base->DEADTIME = (0u | 
+#if defined(FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) && (FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE)
+                        /* Has extended deadtime value register) */
+                        FTM_DEADTIME_DTVALEX(config->deadTimeValue >> 6) | 
+#endif /* FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE */
+                        FTM_DEADTIME_DTPS(config->deadTimePrescale) | 
+                        FTM_DEADTIME_DTVAL(config->deadTimeValue));
 
     /* FTM fault filter value */
     reg = base->FLTCTRL;
@@ -282,8 +292,10 @@
     /* Set clock source to none to disable counter */
     base->SC &= ~(FTM_SC_CLKS_MASK);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the FTM clock */
     CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FTM_GetDefaultConfig(ftm_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
+#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+                                                       /*@}*/
 
 /*!
  * @brief List of FTM channels
@@ -162,7 +161,7 @@
 typedef struct _ftm_fault_param
 {
     bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
-    bool faultLevel;       /*!< True: Fault polarity is active low i.e., '0' indicates a fault;
+    bool faultLevel;       /*!< True: Fault polarity is active low; in other words, '0' indicates a fault;
                                 False: Fault polarity is active high */
     bool useFaultFilter;   /*!< True: Use the filtered fault signal;
                                 False: Use the direct path from fault input */
@@ -311,6 +310,17 @@
 } ftm_status_flags_t;
 
 /*!
+ * @brief List of FTM Quad Decoder flags.
+ */
+enum _ftm_quad_decoder_flags
+{
+    kFTM_QuadDecoderCountingIncreaseFlag = FTM_QDCTRL_QUADIR_MASK, /*!< Counting direction is increasing (FTM counter
+                                                                        increment), or the direction is decreasing. */
+    kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top
+                                                                             or the bottom of counting. */
+};
+
+/*!
  * @brief FTM configuration structure
  *
  * This structure holds the configuration settings for the FTM peripheral. To initialize this
@@ -333,7 +343,9 @@
     ftm_fault_mode_t faultMode;               /*!< FTM fault control mode */
     uint8_t faultFilterValue;                 /*!< Fault input filter value */
     ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */
-    uint8_t deadTimeValue;                    /*!< The dead time value */
+    uint32_t deadTimeValue;                   /*!< The dead time value
+                                                   deadTimeValue's available range is 0-1023 when register has DTVALEX,
+                                                   otherwise its available range is 0-63. */
     uint32_t extTriggers;                     /*!< External triggers to enable. Multiple trigger sources can be
                                                    enabled by providing an OR'ed list of options available in
                                                    enumeration ::ftm_external_trigger_t. */
@@ -359,7 +371,7 @@
 /*!
  * @brief Ungates the FTM clock and configures the peripheral for basic operation.
  *
- * @note This API should be called at the beginning of the application using the FTM driver.
+ * @note This API should be called at the beginning of the application which is using the FTM driver.
  *
  * @param base   FTM peripheral base address
  * @param config Pointer to the user configuration structure.
@@ -509,19 +521,6 @@
 /*! @}*/
 
 /*!
- * @brief Configures the parameters and activates the quadrature decoder mode.
- *
- * @param base         FTM peripheral base address
- * @param phaseAParams Phase A configuration parameters
- * @param phaseBParams Phase B configuration parameters
- * @param quadMode     Selects encoding mode used in quadrature decoder mode
- */
-void FTM_SetupQuadDecode(FTM_Type *base,
-                         const ftm_phase_params_t *phaseAParams,
-                         const ftm_phase_params_t *phaseBParams,
-                         ftm_quad_decode_mode_t quadMode);
-
-/*!
  * @brief Sets up the working of the FTM fault protection.
  *
  * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter.
@@ -594,6 +593,48 @@
 /*! @}*/
 
 /*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the MOD register.
+ *
+ * @note
+ * 1. This API allows the user to use the FTM module as a timer. Do not mix usage
+ *    of this API with FTM's PWM setup API's.
+ * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base FTM peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks)
+{
+    base->MOD = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base FTM peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base)
+{
+    return (uint32_t)((base->CNT & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
+}
+
+/*! @}*/
+/*!
  * @name Timer Start and Stop
  * @{
  */
@@ -711,7 +752,7 @@
 
 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
 /*!
- * @brief Allows user to enable an output on an FTM channel.
+ * @brief Allows users to enable an output on an FTM channel.
  *
  * To enable the PWM channel output call this function with val=true. For input mode,
  * call this function with val=false.
@@ -817,6 +858,76 @@
 /*! @}*/
 
 /*!
+ * @name Quad Decoder
+ * @{
+ */
+
+/*!
+ * @brief Configures the parameters and activates the quadrature decoder mode.
+ *
+ * @param base         FTM peripheral base address
+ * @param phaseAParams Phase A configuration parameters
+ * @param phaseBParams Phase B configuration parameters
+ * @param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void FTM_SetupQuadDecode(FTM_Type *base,
+                         const ftm_phase_params_t *phaseAParams,
+                         const ftm_phase_params_t *phaseBParams,
+                         ftm_quad_decode_mode_t quadMode);
+
+/*!
+ * @brief Gets the FTM Quad Decoder flags.
+ *
+ * @param base FTM peripheral base address.
+ * @return Flag mask of FTM Quad Decoder, see #_ftm_quad_decoder_flags.
+ */
+static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base)
+{
+    return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK);
+}
+
+/*!
+ * @brief Sets the modulo values for Quad Decoder.
+ *
+ * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes
+ * over, the counter value goes to the other side and decrease/increase again.
+ *
+ * @param base FTM peripheral base address.
+ * @param startValue The low limit value for Quad Decoder counter.
+ * @param overValue The high limit value for Quad Decoder counter.
+ */
+static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)
+{
+    base->CNTIN = startValue;
+    base->MOD = overValue;
+}
+
+/*!
+ * @brief Gets the current Quad Decoder counter value.
+ *
+ * @param base FTM peripheral base address.
+ * @return Current quad Decoder counter value.
+ */
+static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)
+{
+    return base->CNT;
+}
+
+/*!
+ * @brief Clears the current Quad Decoder counter value.
+ *
+ * The counter is set as the initial value.
+ *
+ * @param base FTM peripheral base address.
+ */
+static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)
+{
+    base->CNT = base->CNTIN;
+}
+
+/*! @}*/
+
+/*!
  * @brief Enables or disables the FTM software trigger for PWM synchronization.
  *
  * @param base   FTM peripheral base address

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -57,7 +57,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
     {
         if (s_gpioBases[instance] == base)
         {
@@ -65,7 +65,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_GPIO_COUNT);
+    assert(instance < ARRAY_SIZE(s_gpioBases));
 
     return instance;
 }
@@ -103,6 +103,14 @@
     portBase->ISFR = mask;
 }
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
 
 /*******************************************************************************
@@ -130,7 +138,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
     {
         if (s_fgpioBases[instance] == base)
         {
@@ -138,7 +146,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT);
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
 
     return instance;
 }
@@ -176,4 +184,12 @@
     portBase->ISFR = mask;
 }
 
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -38,38 +38,60 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief GPIO driver version 2.1.0. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief GPIO driver version 2.1.1. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/
 
-/*! @brief GPIO direction definition*/
+/*! @brief GPIO direction definition */
 typedef enum _gpio_pin_direction
 {
     kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
     kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
 } gpio_pin_direction_t;
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*! @brief GPIO checker attribute */
+typedef enum _gpio_checker_attribute
+{
+    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
+        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
+        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
+        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
+        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
+        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
+        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
+        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
+        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
+    kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */
+} gpio_checker_attribute_t;
+#endif
+
 /*!
  * @brief The GPIO pin configuration structure.
  *
- * Every pin can only be configured as either output pin or input pin at a time.
- * If configured as a input pin, then leave the outputConfig unused
- * Note : In some cases, the corresponding port property should be configured in advance
- *        with the PORT_SetPinConfig()
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ * Note that in some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig().
  */
 typedef struct _gpio_pin_config
 {
-    gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */
-    /* Output configurations, please ignore if configured as a input one */
-    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations; ignore if configured as an input pin */
+    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
 } gpio_pin_config_t;
 
 /*! @} */
@@ -93,10 +115,10 @@
 /*!
  * @brief Initializes a GPIO pin used by the board.
  *
- * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
  * Then, call the GPIO_PinInit() function.
  *
- * This is an example to define an input pin or output pin configuration:
+ * This is an example to define an input pin or an output pin configuration.
  * @code
  * // Define a digital input pin configuration,
  * gpio_pin_config_t config =
@@ -112,7 +134,7 @@
  * }
  * @endcode
  *
- * @param base   GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
  * @param pin    GPIO port pin number
  * @param config GPIO pin configuration pointer
  */
@@ -126,29 +148,29 @@
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
  *
- * @param base    GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin's number
+ * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
  * @param output  GPIO pin output logic level.
- *        - 0: corresponding pin output low logic level.
- *        - 1: corresponding pin output high logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
  */
 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
 {
     if (output == 0U)
     {
-        base->PCOR = 1 << pin;
+        base->PCOR = 1U << pin;
     }
     else
     {
-        base->PSOR = 1 << pin;
+        base->PSOR = 1U << pin;
     }
 }
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -158,8 +180,8 @@
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 0.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -167,10 +189,10 @@
 }
 
 /*!
- * @brief Reverses current output logic of the multiple GPIO pins.
+ * @brief Reverses the current output logic of the multiple GPIO pins.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -182,13 +204,13 @@
 /*@{*/
 
 /*!
- * @brief Reads the current input value of the whole GPIO port.
+ * @brief Reads the current input value of the GPIO port.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin's number
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
  * @retval GPIO port input value
- *        - 0: corresponding pin input low logic level.
- *        - 1: corresponding pin input high logic level.
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
  */
 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
 {
@@ -200,7 +222,7 @@
 /*@{*/
 
 /*!
- * @brief Reads whole GPIO port interrupt status flag.
+ * @brief Reads the GPIO port interrupt status flag.
  *
  * If a pin is configured to generate the DMA request, the corresponding flag
  * is cleared automatically at the completion of the requested DMA transfer.
@@ -208,20 +230,34 @@
  * If configured for a level sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
  *         pin 0 and 17 have the interrupt.
  */
 uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
 
 /*!
- * @brief Clears multiple GPIO pins' interrupt status flag.
+ * @brief Clears multiple GPIO pin interrupt status flags.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
 /*@}*/
 /*! @} */
 
@@ -231,10 +267,10 @@
  */
 
 /*
- * Introduce the FGPIO feature.
+ * Introduces the FGPIO feature.
  *
- * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT
- * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore
+ * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
  * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
  */
 
@@ -246,10 +282,10 @@
 /*!
  * @brief Initializes a FGPIO pin used by the board.
  *
- * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file.
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
  * Then, call the FGPIO_PinInit() function.
  *
- * This is an example to define an input pin or output pin configuration:
+ * This is an example to define an input pin or an output pin configuration:
  * @code
  * // Define a digital input pin configuration,
  * gpio_pin_config_t config =
@@ -265,7 +301,7 @@
  * }
  * @endcode
  *
- * @param base   FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
  * @param pin    FGPIO port pin number
  * @param config FGPIO pin configuration pointer
  */
@@ -279,11 +315,11 @@
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
  *
- * @param base    FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     FGPIO pin's number
+ * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin     FGPIO pin number
  * @param output  FGPIOpin output logic level.
- *        - 0: corresponding pin output low logic level.
- *        - 1: corresponding pin output high logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
  */
 static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
 {
@@ -300,8 +336,8 @@
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -311,8 +347,8 @@
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -320,10 +356,10 @@
 }
 
 /*!
- * @brief Reverses current output logic of the multiple FGPIO pins.
+ * @brief Reverses the current output logic of the multiple FGPIO pins.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -335,13 +371,13 @@
 /*@{*/
 
 /*!
- * @brief Reads the current input value of the whole FGPIO port.
+ * @brief Reads the current input value of the FGPIO port.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin  FGPIO pin's number
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin  FGPIO pin number
  * @retval FGPIO port input value
- *        - 0: corresponding pin input low logic level.
- *        - 1: corresponding pin input high logic level.
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
  */
 static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
 {
@@ -353,28 +389,42 @@
 /*@{*/
 
 /*!
- * @brief Reads the whole FGPIO port interrupt status flag.
+ * @brief Reads the FGPIO port interrupt status flag.
  *
- * If a pin is configured to generate the DMA request,  the corresponding flag
+ * If a pin is configured to generate the DMA request, the corresponding flag
  * is cleared automatically at the completion of the requested DMA transfer.
  * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
  *         pin 0 and 17 have the interrupt.
  */
 uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
 
 /*!
- * @brief Clears the multiple FGPIO pins' interrupt status flag.
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
 /*@}*/
 
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -76,6 +76,19 @@
 uint32_t I2C_GetInstance(I2C_Type *base);
 
 /*!
+* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the
+* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop
+* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided,
+* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT
+* value, then the related SDA hold time, SCL start and SCL stop hold time is used.
+*
+* @param base I2C peripheral base address.
+* @param sourceClock_Hz I2C functional clock frequency in Hertz.
+* @param sclStopHoldTime_ns SCL stop hold time in ns.
+*/
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz);
+
+/*!
  * @brief Set up master transfer, send slave address and decide the initial
  * transfer state.
  *
@@ -125,20 +138,22 @@
 static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL};
 
 /*! @brief SCL clock divider used to calculate baudrate. */
-const uint16_t s_i2cDividerTable[] = {20,   22,   24,   26,   28,   30,   34,   40,   28,   32,   36,   40,  44,
-                                      48,   56,   68,   48,   56,   64,   72,   80,   88,   104,  128,  80,  96,
-                                      112,  128,  144,  160,  192,  240,  160,  192,  224,  256,  288,  320, 384,
-                                      480,  320,  384,  448,  512,  576,  640,  768,  960,  640,  768,  896, 1024,
-                                      1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
+static const uint16_t s_i2cDividerTable[] = {
+    20,  22,  24,  26,   28,   30,   34,   40,   28,   32,   36,   40,   44,   48,   56,   68,
+    48,  56,  64,  72,   80,   88,   104,  128,  80,   96,   112,  128,  144,  160,  192,  240,
+    160, 192, 224, 256,  288,  320,  384,  480,  320,  384,  448,  512,  576,  640,  768,  960,
+    640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
 
 /*! @brief Pointers to i2c bases for each instance. */
 static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
 
 /*! @brief Pointers to i2c IRQ number for each instance. */
-const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
+static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to i2c clocks for each instance. */
-const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointer to master IRQ handler for each instance. */
 static i2c_isr_t s_i2cMasterIsr;
@@ -155,7 +170,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++)
     {
         if (s_i2cBases[instance] == base)
         {
@@ -163,16 +178,63 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_I2C_COUNT);
+    assert(instance < ARRAY_SIZE(s_i2cBases));
 
     return instance;
 }
 
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz)
+{
+    uint32_t multiplier;
+    uint32_t computedSclHoldTime;
+    uint32_t absError;
+    uint32_t bestError = UINT32_MAX;
+    uint32_t bestMult = 0u;
+    uint32_t bestIcr = 0u;
+    uint8_t mult;
+    uint8_t i;
+
+    /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
+     * and ranges from 0-2. It selects the multiplier factor for the divider. */
+    /* SDA hold time = bus period (s) * mul * SDA hold value. */
+    /* SCL start hold time = bus period (s) * mul * SCL start hold value. */
+    /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */
+
+    for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
+    {
+        multiplier = 1u << mult;
+
+        /* Scan table to find best match. */
+        for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i)
+        {
+            /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */
+            computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz;
+            absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) :
+                                                                  (computedSclHoldTime - sclStopHoldTime_ns);
+
+            if (absError < bestError)
+            {
+                bestMult = mult;
+                bestIcr = i;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching because we won't find a better match. */
+                if (absError == 0)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set frequency register based on best settings. */
+    base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
+}
+
 static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
 {
     status_t result = kStatus_Success;
     i2c_direction_t direction = xfer->direction;
-    uint16_t timeout = UINT16_MAX;
 
     /* Initialize the handle transfer information. */
     handle->transfer = *xfer;
@@ -183,27 +245,13 @@
     /* Initial transfer state. */
     if (handle->transfer.subaddressSize > 0)
     {
-        handle->state = kSendCommandState;
         if (xfer->direction == kI2C_Read)
         {
             direction = kI2C_Write;
         }
     }
-    else
-    {
-        handle->state = kCheckAddressState;
-    }
 
-    /* Wait until the data register is ready for transmit. */
-    while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
-    {
-    }
-
-    /* Failed to start the transfer. */
-    if (timeout == 0)
-    {
-        return kStatus_I2C_Timeout;
-    }
+    handle->state = kCheckAddressState;
 
     /* Clear all status before transfer. */
     I2C_MasterClearStatusFlags(base, kClearFlags);
@@ -265,34 +313,41 @@
         result = kStatus_Success;
     }
 
-    if (result)
-    {
-        return result;
-    }
-
     /* Handle Check address state to check the slave address is Acked in slave
        probe application. */
     if (handle->state == kCheckAddressState)
     {
         if (statusFlags & kI2C_ReceiveNakFlag)
         {
-            return kStatus_I2C_Nak;
+            result = kStatus_I2C_Addr_Nak;
         }
         else
         {
-            if (handle->transfer.direction == kI2C_Write)
+            if (handle->transfer.subaddressSize > 0)
             {
-                /* Next state, send data. */
-                handle->state = kSendDataState;
+                handle->state = kSendCommandState;
             }
             else
             {
-                /* Next state, receive data begin. */
-                handle->state = kReceiveDataBeginState;
+                if (handle->transfer.direction == kI2C_Write)
+                {
+                    /* Next state, send data. */
+                    handle->state = kSendDataState;
+                }
+                else
+                {
+                    /* Next state, receive data begin. */
+                    handle->state = kReceiveDataBeginState;
+                }
             }
         }
     }
 
+    if (result)
+    {
+        return result;
+    }
+
     /* Run state machine. */
     switch (handle->state)
     {
@@ -375,6 +430,10 @@
                     {
                         result = I2C_MasterStop(base);
                     }
+                    else
+                    {
+                        base->C1 |= I2C_C1_TX_MASK;
+                    }
                 }
 
                 /* Send NAK at the last receive byte. */
@@ -407,6 +466,7 @@
     {
         s_i2cSlaveIsr(base, handle);
     }
+    __DSB();
 }
 
 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
@@ -415,12 +475,26 @@
 
     /* Temporary register for filter read. */
     uint8_t fltReg;
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    uint8_t c2Reg;
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    uint8_t s2Reg;
 #endif
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable I2C clock. */
     CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F = 0;
+    base->C1 = 0;
+    base->S = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
 
     /* Disable I2C prior to configuring it. */
     base->C1 &= ~(I2C_C1_IICEN_MASK);
@@ -431,14 +505,6 @@
     /* Configure baud rate. */
     I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
 
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    /* Configure high drive feature. */
-    c2Reg = base->C2;
-    c2Reg &= ~(I2C_C2_HDRS_MASK);
-    c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive);
-    base->C2 = c2Reg;
-#endif
-
     /* Read out the FLT register. */
     fltReg = base->FLT;
 
@@ -455,6 +521,12 @@
     /* Write the register value back to the filter register. */
     base->FLT = fltReg;
 
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    s2Reg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
+#endif
+
     /* Enable the I2C peripheral based on the configuration. */
     base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
 }
@@ -464,8 +536,10 @@
     /* Disable I2C module. */
     I2C_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable I2C clock. */
     CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
@@ -475,11 +549,6 @@
     /* Default baud rate at 100kbps. */
     masterConfig->baudRate_Bps = 100000U;
 
-/* Default pin high drive is disabled. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    masterConfig->enableHighDrive = false;
-#endif
-
 /* Default stop hold enable is disabled. */
 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
     masterConfig->enableStopHold = false;
@@ -488,12 +557,21 @@
     /* Default glitch filter value is no filter. */
     masterConfig->glitchFilterWidth = 0U;
 
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    masterConfig->enableDoubleBuffering = true;
+#endif
+
     /* Enable the I2C peripheral. */
     masterConfig->enableMaster = true;
 }
 
 void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
 {
+#ifdef I2C_HAS_STOP_DETECT
+    uint8_t fltReg;
+#endif
+
     if (mask & kI2C_GlobalInterruptEnable)
     {
         base->C1 |= I2C_C1_IICIE_MASK;
@@ -502,14 +580,28 @@
 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
     if (mask & kI2C_StopDetectInterruptEnable)
     {
-        base->FLT |= I2C_FLT_STOPIE_MASK;
+        fltReg = base->FLT;
+
+        /* Keep STOPF flag. */
+        fltReg &= ~I2C_FLT_STOPF_MASK;
+
+        /* Stop detect enable. */
+        fltReg |= I2C_FLT_STOPIE_MASK;
+        base->FLT = fltReg;
     }
 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
 
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
     if (mask & kI2C_StartStopDetectInterruptEnable)
     {
-        base->FLT |= I2C_FLT_SSIE_MASK;
+        fltReg = base->FLT;
+
+        /* Keep STARTF and STOPF flags. */
+        fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+
+        /* Start and stop detect enable. */
+        fltReg |= I2C_FLT_SSIE_MASK;
+        base->FLT = fltReg;
     }
 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 }
@@ -524,14 +616,14 @@
 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
     if (mask & kI2C_StopDetectInterruptEnable)
     {
-        base->FLT &= ~I2C_FLT_STOPIE_MASK;
+        base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
     }
 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
 
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
     if (mask & kI2C_StartStopDetectInterruptEnable)
     {
-        base->FLT &= ~I2C_FLT_SSIE_MASK;
+        base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
     }
 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 }
@@ -623,7 +715,7 @@
         base->F = savedMult & (~I2C_F_MULT_MASK);
 
         /* We are already in a transfer, so send a repeated start. */
-        base->C1 |= I2C_C1_RSTA_MASK;
+        base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK;
 
         /* Restore the multiplier factor. */
         base->F = savedMult;
@@ -690,7 +782,7 @@
     return statusFlags;
 }
 
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
 {
     status_t result = kStatus_Success;
     uint8_t statusFlags = 0;
@@ -728,7 +820,7 @@
             result = kStatus_I2C_ArbitrationLost;
         }
 
-        if (statusFlags & kI2C_ReceiveNakFlag)
+        if ((statusFlags & kI2C_ReceiveNakFlag) && txSize)
         {
             base->S = kI2C_ReceiveNakFlag;
             result = kStatus_I2C_Nak;
@@ -741,10 +833,19 @@
         }
     }
 
+    if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
+    {
+        /* Clear the IICIF flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Send stop. */
+        result = I2C_MasterStop(base);
+    }
+
     return result;
 }
 
-status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
 {
     status_t result = kStatus_Success;
     volatile uint8_t dummy = 0;
@@ -786,8 +887,16 @@
         /* Single byte use case. */
         if (rxSize == 0)
         {
-            /* Read the final byte. */
-            result = I2C_MasterStop(base);
+            if (!(flags & kI2C_TransferNoStopFlag))
+            {
+                /* Issue STOP command before reading last byte. */
+                result = I2C_MasterStop(base);
+            }
+            else
+            {
+                /* Change direction to Tx to avoid extra clocks. */
+                base->C1 |= I2C_C1_TX_MASK;
+            }
         }
 
         if (rxSize == 1)
@@ -840,19 +949,42 @@
         return result;
     }
 
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
+    }
+
+    /* Check if there's transfer error. */
+    result = I2C_CheckAndClearError(base, base->S);
+
+    /* Return if error. */
+    if (result)
+    {
+        if (result == kStatus_I2C_Nak)
+        {
+            result = kStatus_I2C_Addr_Nak;
+
+            I2C_MasterStop(base);
+        }
+
+        return result;
+    }
+
     /* Send subaddress. */
     if (xfer->subaddressSize)
     {
         do
         {
+            /* Clear interrupt pending flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            xfer->subaddressSize--;
+            base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
+
             /* Wait until data transfer complete. */
             while (!(base->S & kI2C_IntPendingFlag))
             {
             }
 
-            /* Clear interrupt pending flag. */
-            base->S = kI2C_IntPendingFlag;
-
             /* Check if there's transfer error. */
             result = I2C_CheckAndClearError(base, base->S);
 
@@ -866,34 +998,13 @@
                 return result;
             }
 
-            xfer->subaddressSize--;
-            base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
-
         } while ((xfer->subaddressSize > 0) && (result == kStatus_Success));
 
         if (xfer->direction == kI2C_Read)
         {
-            /* Wait until data transfer complete. */
-            while (!(base->S & kI2C_IntPendingFlag))
-            {
-            }
-
             /* Clear pending flag. */
             base->S = kI2C_IntPendingFlag;
 
-            /* Check if there's transfer error. */
-            result = I2C_CheckAndClearError(base, base->S);
-
-            if (result)
-            {
-                if (result == kStatus_I2C_Nak)
-                {
-                    I2C_MasterStop(base);
-                }
-
-                return result;
-            }
-
             /* Send repeated start and slave address. */
             result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
 
@@ -902,48 +1013,40 @@
             {
                 return result;
             }
-        }
-    }
 
-    /* Wait until address + command transfer complete. */
-    while (!(base->S & kI2C_IntPendingFlag))
-    {
-    }
+            /* Wait until data transfer complete. */
+            while (!(base->S & kI2C_IntPendingFlag))
+            {
+            }
+
+            /* Check if there's transfer error. */
+            result = I2C_CheckAndClearError(base, base->S);
 
-    /* Check if there's transfer error. */
-    result = I2C_CheckAndClearError(base, base->S);
+            if (result)
+            {
+                if (result == kStatus_I2C_Nak)
+                {
+                    result = kStatus_I2C_Addr_Nak;
 
-    /* Return if error. */
-    if (result)
-    {
-        if (result == kStatus_I2C_Nak)
-        {
-            I2C_MasterStop(base);
+                    I2C_MasterStop(base);
+                }
+
+                return result;
+            }
         }
-
-        return result;
     }
 
     /* Transmit data. */
     if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
     {
         /* Send Data. */
-        result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize);
-
-        if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
-        {
-            /* Clear the IICIF flag. */
-            base->S = kI2C_IntPendingFlag;
-
-            /* Send stop. */
-            result = I2C_MasterStop(base);
-        }
+        result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
     }
 
     /* Receive Data. */
     if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
     {
-        result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize);
+        result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
     }
 
     return result;
@@ -1006,11 +1109,37 @@
 {
     assert(handle);
 
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
     /* Disable interrupt. */
     I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
 
     /* Reset the state to idle. */
     handle->state = kIdleState;
+
+    /* Send STOP signal. */
+    if (handle->transfer.direction == kI2C_Read)
+    {
+        base->C1 |= I2C_C1_TXAK_MASK;
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+        base->S = kI2C_IntPendingFlag;
+
+        base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+        dummy = base->D;
+    }
+    else
+    {
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+        base->S = kI2C_IntPendingFlag;
+        base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+    }
 }
 
 status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
@@ -1044,7 +1173,8 @@
     if (isDone || result)
     {
         /* Send stop command if transfer done or received Nak. */
-        if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak))
+        if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) ||
+            (result == kStatus_I2C_Addr_Nak))
         {
             /* Ensure stop command is a need. */
             if ((base->C1 & I2C_C1_MST_MASK))
@@ -1070,13 +1200,28 @@
     }
 }
 
-void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
 {
     assert(slaveConfig);
 
     uint8_t tmpReg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F = 0;
+    base->C1 = 0;
+    base->S = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
 
     /* Configure addressing mode. */
     switch (slaveConfig->addressingMode)
@@ -1101,15 +1246,20 @@
     tmpReg &= ~I2C_C1_WUEN_MASK;
     base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
 
-    /* Configure general call & baud rate control & high drive feature. */
+    /* Configure general call & baud rate control. */
     tmpReg = base->C2;
     tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
     tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    tmpReg &= ~I2C_C2_HDRS_MASK;
-    tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive);
+    base->C2 = tmpReg;
+
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    tmpReg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
 #endif
-    base->C2 = tmpReg;
+
+    /* Set hold time. */
+    I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz);
 }
 
 void I2C_SlaveDeinit(I2C_Type *base)
@@ -1117,8 +1267,10 @@
     /* Disable I2C module. */
     I2C_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable I2C clock. */
     CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
@@ -1134,13 +1286,16 @@
     /* Slave address match waking up MCU from low power mode is disabled. */
     slaveConfig->enableWakeUp = false;
 
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    /* Default pin high drive is disabled. */
-    slaveConfig->enableHighDrive = false;
+    /* Independent slave mode baud rate at maximum frequency is disabled. */
+    slaveConfig->enableBaudRateCtl = false;
+
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    slaveConfig->enableDoubleBuffering = true;
 #endif
 
-    /* Independent slave mode baud rate at maximum frequency is disabled. */
-    slaveConfig->enableBaudRateCtl = false;
+    /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */
+    slaveConfig->sclStopHoldTime_ns = 4000;
 
     /* Enable the I2C peripheral. */
     slaveConfig->enableSlave = true;
@@ -1148,34 +1303,89 @@
 
 status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
 {
-    return I2C_MasterWriteBlocking(base, txBuff, txSize);
+    status_t result = kStatus_Success;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Wait for address match flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
+    {
+    }
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag);
+
+    /* Switch to receive mode. */
+    base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    return result;
 }
 
 void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
 {
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+/* Wait until address match. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
     /* Clear the IICIF flag. */
     base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 
-    /* Wait until the data register is ready for receive. */
-    while (!(base->S & kI2C_TransferCompleteFlag))
+    /* Wait for address match and int pending flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
     {
     }
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
+    }
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
 
     /* Setup the I2C peripheral to receive data. */
     base->C1 &= ~(I2C_C1_TX_MASK);
 
     while (rxSize--)
     {
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
         /* Clear the IICIF flag. */
         base->S = kI2C_IntPendingFlag;
 
         /* Read from the data register. */
         *rxBuff++ = base->D;
-
-        /* Wait until data transfer complete. */
-        while (!(base->S & kI2C_IntPendingFlag))
-        {
-        }
     }
 }
 
@@ -1226,7 +1436,7 @@
         handle->isBusy = true;
 
         /* Set up event mask. tx and rx are always enabled. */
-        handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+        handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent;
 
         /* Clear all flags. */
         I2C_SlaveClearStatusFlags(base, kClearFlags);
@@ -1315,7 +1525,10 @@
             }
         }
 
-        return;
+        if (!(status & kI2C_AddressMatchFlag))
+        {
+            return;
+        }
     }
 #endif /* I2C_HAS_STOP_DETECT */
 
@@ -1328,7 +1541,7 @@
         /* Clear the interrupt flag. */
         base->S = kI2C_IntPendingFlag;
 
-        xfer->event = kI2C_SlaveRepeatedStartEvent;
+        xfer->event = kI2C_SlaveStartEvent;
 
         if ((handle->eventMask & xfer->event) && (handle->callback))
         {
@@ -1385,31 +1598,12 @@
         handle->isBusy = true;
         xfer->event = kI2C_SlaveAddressMatchEvent;
 
-        if ((handle->eventMask & xfer->event) && (handle->callback))
-        {
-            handle->callback(base, xfer, handle->userData);
-        }
-
         /* Slave transmit, master reading from slave. */
         if (status & kI2C_TransferDirectionFlag)
         {
             /* Change direction to send data. */
             base->C1 |= I2C_C1_TX_MASK;
 
-            /* If we're out of data, invoke callback to get more. */
-            if ((!xfer->data) || (!xfer->dataSize))
-            {
-                xfer->event = kI2C_SlaveTransmitEvent;
-
-                if (handle->callback)
-                {
-                    handle->callback(base, xfer, handle->userData);
-                }
-
-                /* Clear the transferred count now that we have a new buffer. */
-                xfer->transferredCount = 0;
-            }
-
             doTransmit = true;
         }
         else
@@ -1417,6 +1611,30 @@
             /* Slave receive, master writing to slave. */
             base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
 
+            /* Read dummy to release the bus. */
+            dummy = base->D;
+
+            if (dummy == 0)
+            {
+                xfer->event = kI2C_SlaveGenaralcallEvent;
+            }
+        }
+
+        if ((handle->eventMask & xfer->event) && (handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+    }
+    /* Check transfer complete flag. */
+    else if (status & kI2C_TransferCompleteFlag)
+    {
+        /* Slave transmit, master reading from slave. */
+        if (status & kI2C_TransferDirectionFlag)
+        {
+            doTransmit = true;
+        }
+        else
+        {
             /* If we're out of data, invoke callback to get more. */
             if ((!xfer->data) || (!xfer->dataSize))
             {
@@ -1431,20 +1649,6 @@
                 xfer->transferredCount = 0;
             }
 
-            /* Read dummy to release the bus. */
-            dummy = base->D;
-        }
-    }
-    /* Check transfer complete flag. */
-    else if (status & kI2C_TransferCompleteFlag)
-    {
-        /* Slave transmit, master reading from slave. */
-        if (status & kI2C_TransferDirectionFlag)
-        {
-            doTransmit = true;
-        }
-        else
-        {
             /* Slave receive, master writing to slave. */
             uint8_t data = base->D;
 
@@ -1480,6 +1684,20 @@
     /* Send data if there is the need. */
     if (doTransmit)
     {
+        /* If we're out of data, invoke callback to get more. */
+        if ((!xfer->data) || (!xfer->dataSize))
+        {
+            xfer->event = kI2C_SlaveTransmitEvent;
+
+            if (handle->callback)
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+
+            /* Clear the transferred count now that we have a new buffer. */
+            xfer->transferredCount = 0;
+        }
+
         if (handle->transfer.dataSize)
         {
             /* Send data. */
@@ -1510,27 +1728,30 @@
     }
 }
 
+#if defined(I2C0)
 void I2C0_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
 }
+#endif
 
-#if (FSL_FEATURE_SOC_I2C_COUNT > 1)
+#if defined(I2C1)
 void I2C1_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
 }
-#endif /* I2C COUNT > 1 */
+#endif
 
-#if (FSL_FEATURE_SOC_I2C_COUNT > 2)
+#if defined(I2C2)
 void I2C2_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
 }
-#endif /* I2C COUNT > 2 */
-#if (FSL_FEATURE_SOC_I2C_COUNT > 3)
+#endif
+
+#if defined(I2C3)
 void I2C3_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
 }
-#endif /* I2C COUNT > 3 */
+#endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,16 +37,14 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief I2C driver version 2.0.0. */
-#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief I2C driver version 2.0.3. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 #if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \
@@ -62,6 +60,7 @@
     kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2),             /*!< NAK received during transfer. */
     kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */
     kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4),         /*!< Wait event timeout. */
+    kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5),        /*!< NAK received during the address probe. */
 };
 
 /*!
@@ -109,11 +108,11 @@
 #endif                                                       /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 };
 
-/*! @brief Direction of master and slave transfers. */
+/*! @brief The direction of master and slave transfers. */
 typedef enum _i2c_direction
 {
-    kI2C_Write = 0x0U, /*!< Master transmit to slave. */
-    kI2C_Read = 0x1U,  /*!< Master receive from slave. */
+    kI2C_Write = 0x0U, /*!< Master transmits to the slave. */
+    kI2C_Read = 0x1U,  /*!< Master receives from the slave. */
 } i2c_direction_t;
 
 /*! @brief Addressing mode. */
@@ -126,17 +125,17 @@
 /*! @brief I2C transfer control flag. */
 enum _i2c_master_transfer_flags
 {
-    kI2C_TransferDefaultFlag = 0x0U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
-    kI2C_TransferNoStartFlag = 0x1U,       /*!< Transfer starts without a start signal. */
-    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */
-    kI2C_TransferNoStopFlag = 0x4U,        /*!< Transfer ends without a stop signal. */
+    kI2C_TransferDefaultFlag = 0x0U,       /*!< A transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x1U,       /*!< A transfer starts without a start signal. */
+    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */
+    kI2C_TransferNoStopFlag = 0x4U,        /*!< A transfer ends without a stop signal. */
 };
 
 /*!
  * @brief Set of events sent to the callback for nonblocking slave transfers.
  *
  * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
- * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable.
  * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
  * parameter.
  *
@@ -145,34 +144,36 @@
 typedef enum _i2c_slave_transfer_event
 {
     kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
-    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< A callback is requested to provide data to transmit
                                                 (slave-transmitter role). */
-    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< A callback is requested to provide a buffer in which to place received
                                                  data (slave-receiver role). */
-    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< Callback needs to either transmit an ACK or NACK. */
+    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< A callback needs to either transmit an ACK or NACK. */
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
-    kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */
+    kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
 #endif
-    kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */
+    kI2C_SlaveCompletionEvent = 0x20U,  /*!< A stop was detected or finished transfer, completing the transfer. */
+    kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */
 
-    /*! Bit mask of all available events. */
+    /*! A bit mask of all available events. */
     kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
-                          kI2C_SlaveRepeatedStartEvent |
+                          kI2C_SlaveStartEvent |
 #endif
-                          kI2C_SlaveCompletionEvent,
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent,
 } i2c_slave_transfer_event_t;
 
 /*! @brief I2C master user configuration. */
 typedef struct _i2c_master_config
 {
     bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
-#endif
 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
     bool enableStopHold; /*!< Controls the stop hold enable. */
 #endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
+#endif
     uint32_t baudRate_Bps;     /*!< Baud rate configuration of I2C peripheral. */
     uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */
 } i2c_master_config_t;
@@ -181,15 +182,20 @@
 typedef struct _i2c_slave_config
 {
     bool enableSlave;       /*!< Enables the I2C peripheral at initialization time. */
-    bool enableGeneralCall; /*!< Enable general call addressing mode. */
-    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low power mode. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
+    bool enableGeneralCall; /*!< Enables the general call addressing mode. */
+    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low-power mode. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
 #endif
     bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */
-    uint16_t slaveAddress;  /*!< Slave address configuration. */
-    uint16_t upperAddress;  /*!< Maximum boundary slave address used in range matching mode. */
-    i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */
+    uint16_t slaveAddress;  /*!< A slave address configuration. */
+    uint16_t upperAddress;  /*!< A maximum boundary slave address used in a range matching mode. */
+    i2c_slave_address_mode_t
+        addressingMode;          /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */
+    uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+                                    data) while SCL is high (stop condition), SDA hold time and SCL start hold time
+                                    are also configured according to the SCL stop hold time. */
 } i2c_slave_config_t;
 
 /*! @brief I2C master handle typedef. */
@@ -207,13 +213,13 @@
 /*! @brief I2C master transfer structure. */
 typedef struct _i2c_master_transfer
 {
-    uint32_t flags;            /*!< Transfer flag which controls the transfer. */
+    uint32_t flags;            /*!< A transfer flag which controls the transfer. */
     uint8_t slaveAddress;      /*!< 7-bit slave address. */
-    i2c_direction_t direction; /*!< Transfer direction, read or write. */
-    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
-    uint8_t subaddressSize;    /*!< Size of command buffer. */
-    uint8_t *volatile data;    /*!< Transfer buffer. */
-    volatile size_t dataSize;  /*!< Transfer size. */
+    i2c_direction_t direction; /*!< A transfer direction, read or write. */
+    uint32_t subaddress;       /*!< A sub address. Transferred MSB first. */
+    uint8_t subaddressSize;    /*!< A size of the command buffer. */
+    uint8_t *volatile data;    /*!< A transfer buffer. */
+    volatile size_t dataSize;  /*!< A transfer size. */
 } i2c_master_transfer_t;
 
 /*! @brief I2C master handle structure. */
@@ -221,20 +227,21 @@
 {
     i2c_master_transfer_t transfer;                    /*!< I2C master transfer copy. */
     size_t transferSize;                               /*!< Total bytes to be transferred. */
-    uint8_t state;                                     /*!< Transfer state maintained during transfer. */
-    i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */
-    void *userData;                                    /*!< Callback parameter passed to callback function. */
+    uint8_t state;                                     /*!< A transfer state maintained during transfer. */
+    i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */
+    void *userData;                                    /*!< A callback parameter passed to the callback function. */
 };
 
 /*! @brief I2C slave transfer structure. */
 typedef struct _i2c_slave_transfer
 {
-    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
-    uint8_t *volatile data;           /*!< Transfer buffer. */
-    volatile size_t dataSize;         /*!< Transfer size. */
+    i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */
+    uint8_t *volatile data;           /*!< A transfer buffer. */
+    volatile size_t dataSize;         /*!< A transfer size. */
     status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
                                          #kI2C_SlaveCompletionEvent. */
-    size_t transferredCount;          /*!< Number of bytes actually transferred since start or last repeated start. */
+    size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated
+                                start. */
 } i2c_slave_transfer_t;
 
 /*! @brief I2C slave transfer callback typedef. */
@@ -243,11 +250,11 @@
 /*! @brief I2C slave handle structure. */
 struct _i2c_slave_handle
 {
-    bool isBusy;                            /*!< Whether transfer is busy. */
+    volatile bool isBusy;                   /*!< Indicates whether a transfer is busy. */
     i2c_slave_transfer_t transfer;          /*!< I2C slave transfer copy. */
-    uint32_t eventMask;                     /*!< Mask of enabled events. */
-    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
-    void *userData;                         /*!< Callback parameter passed to callback. */
+    uint32_t eventMask;                     /*!< A mask of enabled events. */
+    i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */
+    void *userData;                         /*!< A callback parameter passed to the callback. */
 };
 
 /*******************************************************************************
@@ -267,12 +274,12 @@
  * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
  * and configure the I2C with master configuration.
  *
- * @note This API should be called at the beginning of the application to use
- * the I2C driver, or any operation to the I2C module could cause hard fault
- * because clock is not enabled. The configuration structure can be filled by user
- * from scratch, or be set with default values by I2C_MasterGetDefaultConfig().
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can be custom filled
+ * or it can be set with default values by using the I2C_MasterGetDefaultConfig().
  * After calling this API, the master is ready to transfer.
- * Example:
+ * This is an example.
  * @code
  * i2c_master_config_t config = {
  * .enableMaster = true,
@@ -285,20 +292,20 @@
  * @endcode
  *
  * @param base I2C base pointer
- * @param masterConfig pointer to master configuration structure
+ * @param masterConfig A pointer to the master configuration structure
  * @param srcClock_Hz I2C peripheral clock frequency in Hz
  */
 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
 
 /*!
  * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
- * and initializes the I2C with slave configuration.
+ * and initialize the I2C with the slave configuration.
  *
- * @note This API should be called at the beginning of the application to use
- * the I2C driver, or any operation to the I2C module can cause a hard fault
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
  * because the clock is not enabled. The configuration structure can partly be set
- * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user.
- * Example
+ * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user.
+ * This is an example.
  * @code
  * i2c_slave_config_t config = {
  * .enableSlave = true,
@@ -307,15 +314,17 @@
  * .slaveAddress = 0x1DU,
  * .enableWakeUp = false,
  * .enablehighDrive = false,
- * .enableBaudRateCtl = false
+ * .enableBaudRateCtl = false,
+ * .sclStopHoldTime_ns = 4000
  * };
- * I2C_SlaveInit(I2C0, &config);
+ * I2C_SlaveInit(I2C0, &config, 12000000U);
  * @endcode
  *
  * @param base I2C base pointer
- * @param slaveConfig pointer to slave configuration structure
+ * @param slaveConfig A pointer to the slave configuration structure
+ * @param srcClock_Hz I2C peripheral clock frequency in Hz
  */
-void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig);
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
 
 /*!
  * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
@@ -335,28 +344,28 @@
  * @brief  Sets the I2C master configuration structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
- * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of
- * the structure before calling I2C_MasterConfigure().
- * Example:
+ * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify
+ * the structure before calling the I2C_MasterConfigure().
+ * This is an example.
  * @code
  * i2c_master_config_t config;
  * I2C_MasterGetDefaultConfig(&config);
  * @endcode
- * @param masterConfig Pointer to the master configuration structure.
+ * @param masterConfig A pointer to the master configuration structure.
 */
 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
 
 /*!
  * @brief  Sets the I2C slave configuration structure to default values.
  *
- * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure().
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure().
  * Modify fields of the structure before calling the I2C_SlaveConfigure().
- * Example:
+ * This is an example.
  * @code
  * i2c_slave_config_t config;
  * I2C_SlaveGetDefaultConfig(&config);
  * @endcode
- * @param slaveConfig Pointer to the slave configuration structure.
+ * @param slaveConfig A pointer to the slave configuration structure.
  */
 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
 
@@ -364,7 +373,7 @@
  * @brief Enables or disabless the I2C peripheral operation.
  *
  * @param base I2C base pointer
- * @param enable pass true to enable module, false to disable module
+ * @param enable Pass true to enable and false to disable the module.
  */
 static inline void I2C_Enable(I2C_Type *base, bool enable)
 {
@@ -389,7 +398,7 @@
  * @brief Gets the I2C status flags.
  *
  * @param base I2C base pointer
- * @return status flag, use status flag to AND #_i2c_flags could get the related status.
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
  */
 uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
 
@@ -397,7 +406,7 @@
  * @brief Gets the I2C status flags.
  *
  * @param base I2C base pointer
- * @return status flag, use status flag to AND #_i2c_flags could get the related status.
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
  */
 static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
 {
@@ -407,11 +416,11 @@
 /*!
  * @brief Clears the I2C status flag state.
  *
- * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag.
  *
  * @param base I2C base pointer
  * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
- *      The parameter could be any combination of the following values:
+ *      The parameter can be any combination of the following values:
  *          @arg kI2C_StartDetectFlag (if available)
  *          @arg kI2C_StopDetectFlag (if available)
  *          @arg kI2C_ArbitrationLostFlag
@@ -442,11 +451,11 @@
 /*!
  * @brief Clears the I2C status flag state.
  *
- * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
  *
   * @param base I2C base pointer
   * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
- *      The parameter could be any combination of the following values:
+ *      The parameter can be any combination of the following values:
  *          @arg kI2C_StartDetectFlag (if available)
  *          @arg kI2C_StopDetectFlag (if available)
  *          @arg kI2C_ArbitrationLostFlag
@@ -574,19 +583,21 @@
 status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
 
 /*!
- * @brief Performs a polling send transaction on the I2C bus without a STOP signal.
+ * @brief Performs a polling send transaction on the I2C bus.
  *
  * @param base  The I2C peripheral base pointer.
  * @param txBuff The pointer to the data to be transferred.
  * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+*  to issue a stop and kI2C_TransferNoStop to not send a stop.
  * @retval kStatus_Success Successfully complete the data transmission.
  * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
  * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
  */
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags);
 
 /*!
- * @brief Performs a polling receive transaction on the I2C bus with a STOP signal.
+ * @brief Performs a polling receive transaction on the I2C bus.
  *
  * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
  * Without stopping the bus prior for the final read, the bus issues another read, resulting
@@ -595,10 +606,12 @@
  * @param base I2C peripheral base pointer.
  * @param rxBuff The pointer to the data to store the received data.
  * @param rxSize The length in bytes of the data to be received.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+*  to issue a stop and kI2C_TransferNoStop to not send a stop.
  * @retval kStatus_Success Successfully complete the data transmission.
  * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
  */
-status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags);
 
 /*!
  * @brief Performs a polling send transaction on the I2C bus.
@@ -650,7 +663,7 @@
  * @param base I2C base pointer.
  * @param handle pointer to i2c_master_handle_t structure to store the transfer state.
  * @param callback pointer to user callback function.
- * @param userData user paramater passed to the callback function.
+ * @param userData user parameter passed to the callback function.
  */
 void I2C_MasterTransferCreateHandle(I2C_Type *base,
                                     i2c_master_handle_t *handle,
@@ -660,15 +673,15 @@
 /*!
  * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
  *
- * @note Calling the API will return immediately after transfer initiates, user needs
+ * @note Calling the API returns immediately after transfer initiates. The user needs
  * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
- * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer
+ * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
  * is finished.
  *
  * @param base I2C base pointer.
  * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
  * @param xfer pointer to i2c_master_transfer_t structure.
- * @retval kStatus_Success Sucessully start the data transmission.
+ * @retval kStatus_Success Successfully start the data transmission.
  * @retval kStatus_I2C_Busy Previous transmission still not finished.
  * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
  */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -162,6 +162,26 @@
             result = I2C_MasterStop(i2cPrivateHandle->base);
         }
     }
+    else
+    {
+        if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read)
+        {
+            /* Change to send NAK at the last byte. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK;
+
+            /* Wait the last data to be received. */
+            while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Change direction to send. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK;
+
+            /* Read the last data byte. */
+            *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) =
+                i2cPrivateHandle->base->D;
+        }
+    }
 
     i2cPrivateHandle->handle->state = kIdleState;
 
@@ -203,7 +223,6 @@
     assert(xfer);
 
     status_t result = kStatus_Success;
-    uint16_t timeout = UINT16_MAX;
 
     if (handle->state != kIdleState)
     {
@@ -221,16 +240,6 @@
 
         handle->state = kTransferDataState;
 
-        /* Wait until ready to complete. */
-        while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
-        {
-        }
-
-        /* Failed to start the transfer. */
-        if (timeout == 0)
-        {
-            return kStatus_I2C_Timeout;
-        }
         /* Clear all status before transfer. */
         I2C_MasterClearStatusFlags(base, kClearFlags);
 
@@ -250,22 +259,55 @@
             result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
         }
 
+        if (result)
+        {
+            return result;
+        }
+
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        /* Check if there's transfer error. */
+        result = I2C_CheckAndClearError(base, base->S);
+
+        /* Return if error. */
+        if (result)
+        {
+            if (result == kStatus_I2C_Nak)
+            {
+                result = kStatus_I2C_Addr_Nak;
+
+                if (I2C_MasterStop(base) != kStatus_Success)
+                {
+                    result = kStatus_I2C_Timeout;
+                }
+
+                if (handle->completionCallback)
+                {
+                    (handle->completionCallback)(base, handle, result, handle->userData);
+                }
+            }
+
+            return result;
+        }
+
         /* Send subaddress. */
         if (handle->transfer.subaddressSize)
         {
             do
             {
-                /* Wait until data transfer complete. */
-                while (!(base->S & kI2C_IntPendingFlag))
-                {
-                }
-
                 /* Clear interrupt pending flag. */
                 base->S = kI2C_IntPendingFlag;
 
                 handle->transfer.subaddressSize--;
                 base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize));
 
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
+
                 /* Check if there's transfer error. */
                 result = I2C_CheckAndClearError(base, base->S);
 
@@ -278,34 +320,34 @@
 
             if (handle->transfer.direction == kI2C_Read)
             {
-                /* Wait until data transfer complete. */
-                while (!(base->S & kI2C_IntPendingFlag))
-                {
-                }
-
                 /* Clear pending flag. */
                 base->S = kI2C_IntPendingFlag;
 
                 /* Send repeated start and slave address. */
                 result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
-            }
-        }
+
+                if (result)
+                {
+                    return result;
+                }
 
-        if (result)
-        {
-            return result;
-        }
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
 
-        /* Wait until data transfer complete. */
-        while (!(base->S & kI2C_IntPendingFlag))
-        {
+                /* Check if there's transfer error. */
+                result = I2C_CheckAndClearError(base, base->S);
+
+                if (result)
+                {
+                    return result;
+                }
+            }
         }
 
         /* Clear pending flag. */
         base->S = kI2C_IntPendingFlag;
-
-        /* Check if there's transfer error. */
-        result = I2C_CheckAndClearError(base, base->S);
     }
 
     return result;
@@ -319,17 +361,7 @@
     {
         transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base);
         transfer_config.destAddr = (uint32_t)(handle->transfer.data);
-
-        /* Send stop if kI2C_TransferNoStop flag is not asserted. */
-        if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
-        {
-            transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
-        }
-        else
-        {
-            transfer_config.majorLoopCounts = handle->transfer.dataSize;
-        }
-
+        transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
         transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
         transfer_config.srcOffset = 0;
         transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
@@ -348,6 +380,9 @@
         transfer_config.minorLoopBytes = 1;
     }
 
+    /* Store the initially configured eDMA minor byte transfer count into the I2C handle */
+    handle->nbytes = transfer_config.minorLoopBytes;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config);
     EDMA_StartTransfer(handle->dmaHandle);
 }
@@ -427,7 +462,7 @@
         if (handle->transfer.direction == kI2C_Read)
         {
             /* Change direction for receive. */
-            base->C1 &= ~I2C_C1_TX_MASK;
+            base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
 
             /* Read dummy to release the bus. */
             dummy = base->D;
@@ -479,6 +514,11 @@
         {
             result = I2C_MasterStop(base);
         }
+        else
+        {
+            /* Change direction to send. */
+            base->C1 |= I2C_C1_TX_MASK;
+        }
 
         /* Read the last byte of data. */
         if (handle->transfer.direction == kI2C_Read)
@@ -504,7 +544,9 @@
 
     if (kIdleState != handle->state)
     {
-        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+        *count = (handle->transferSize -
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
     else
     {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,31 +39,30 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
-/*! @brief I2C master edma handle typedef. */
+/*! @brief I2C master eDMA handle typedef. */
 typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t;
 
-/*! @brief I2C master edma transfer callback typedef. */
+/*! @brief I2C master eDMA transfer callback typedef. */
 typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base,
                                                     i2c_master_edma_handle_t *handle,
                                                     status_t status,
                                                     void *userData);
 
-/*! @brief I2C master edma transfer structure. */
+/*! @brief I2C master eDMA transfer structure. */
 struct _i2c_master_edma_handle
 {
-    i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */
+    i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */
     size_t transferSize;            /*!< Total bytes to be transferred. */
+    uint8_t nbytes;                 /*!< eDMA minor byte transfer count initially configured. */
     uint8_t state;                  /*!< I2C master transfer status. */
     edma_handle_t *dmaHandle;       /*!< The eDMA handler used. */
     i2c_master_edma_transfer_callback_t
-        completionCallback; /*!< Callback function called after edma transfer finished. */
-    void *userData;         /*!< Callback parameter passed to callback function. */
+        completionCallback; /*!< A callback function called after the eDMA transfer is finished. */
+    void *userData;         /*!< A callback parameter passed to the callback function. */
 };
 
 /*******************************************************************************
@@ -75,18 +74,18 @@
 #endif /*_cplusplus. */
 
 /*!
- * @name I2C Block EDMA Transfer Operation
+ * @name I2C Block eDMA Transfer Operation
  * @{
  */
 
 /*!
- * @brief Init the I2C handle which is used in transcational functions.
+ * @brief Initializes the I2C handle which is used in transcational functions.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param callback pointer to user callback function.
- * @param userData user param passed to the callback function.
- * @param edmaHandle EDMA handle pointer.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param callback A pointer to the user callback function.
+ * @param userData A user parameter passed to the callback function.
+ * @param edmaHandle eDMA handle pointer.
  */
 void I2C_MasterCreateEDMAHandle(I2C_Type *base,
                                 i2c_master_edma_handle_t *handle,
@@ -95,33 +94,33 @@
                                 edma_handle_t *edmaHandle);
 
 /*!
- * @brief Performs a master edma non-blocking transfer on the I2C bus.
+ * @brief Performs a master eDMA non-blocking transfer on the I2C bus.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param xfer pointer to transfer structure of i2c_master_transfer_t.
- * @retval kStatus_Success Sucessully complete the data transmission.
- * @retval kStatus_I2C_Busy Previous transmission still not finished.
- * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param xfer A pointer to the transfer structure of i2c_master_transfer_t.
+ * @retval kStatus_Success Sucessfully completed the data transmission.
+ * @retval kStatus_I2C_Busy A previous transmission is still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout.
  * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
- * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
  */
 status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer);
 
 /*!
- * @brief Get master transfer status during a edma non-blocking transfer.
+ * @brief Gets a master transfer status during the eDMA non-blocking transfer.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param count A number of bytes transferred by the non-blocking transaction.
  */
 status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count);
 
 /*!
- * @brief Abort a master edma non-blocking transfer in a early time.
+ * @brief Aborts a master eDMA non-blocking transfer early.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
  */
 void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup llwu */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -52,9 +51,9 @@
  */
 typedef enum _llwu_external_pin_mode
 {
-    kLLWU_ExternalPinDisable = 0U,     /*!< Pin disabled as wakeup input.           */
-    kLLWU_ExternalPinRisingEdge = 1U,  /*!< Pin enabled with rising edge detection. */
-    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/
+    kLLWU_ExternalPinDisable = 0U,     /*!< Pin disabled as a wakeup input.           */
+    kLLWU_ExternalPinRisingEdge = 1U,  /*!< Pin enabled with the rising edge detection. */
+    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/
     kLLWU_ExternalPinAnyEdge = 3U      /*!< Pin enabled with any change detection.  */
 } llwu_external_pin_mode_t;
 
@@ -75,9 +74,9 @@
  */
 typedef struct _llwu_version_id
 {
-    uint16_t feature; /*!< Feature Specification Number. */
-    uint8_t minor;    /*!< Minor version number.         */
-    uint8_t major;    /*!< Major version number.         */
+    uint16_t feature; /*!< A feature specification number. */
+    uint8_t minor;    /*!< The minor version number.         */
+    uint8_t major;    /*!< The major version number.         */
 } llwu_version_id_t;
 #endif /* FSL_FEATURE_LLWU_HAS_VERID */
 
@@ -87,20 +86,20 @@
  */
 typedef struct _llwu_param
 {
-    uint8_t filters; /*!< Number of pin filter.      */
-    uint8_t dmas;    /*!< Number of wakeup DMA.      */
-    uint8_t modules; /*!< Number of wakeup module.   */
-    uint8_t pins;    /*!< Number of wake up pin.     */
+    uint8_t filters; /*!< A number of the pin filter.      */
+    uint8_t dmas;    /*!< A number of the wakeup DMA.      */
+    uint8_t modules; /*!< A number of the wakeup module.   */
+    uint8_t pins;    /*!< A number of the wake up pin.     */
 } llwu_param_t;
 #endif /* FSL_FEATURE_LLWU_HAS_PARAM */
 
 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
 /*!
- * @brief External input pin filter control structure
+ * @brief An external input pin filter control structure
  */
 typedef struct _llwu_external_pin_filter_mode
 {
-    uint32_t pinIndex;                 /*!< Pin number  */
+    uint32_t pinIndex;                 /*!< A pin number  */
     llwu_pin_filter_mode_t filterMode; /*!< Filter mode */
 } llwu_external_pin_filter_mode_t;
 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
@@ -122,11 +121,11 @@
 /*!
  * @brief Gets the LLWU version ID.
  *
- * This function gets the LLWU version ID, including major version number,
- * minor version number, and feature specification number.
+ * This function gets the LLWU version ID, including the major version number,
+ * the minor version number, and the feature specification number.
  *
  * @param base LLWU peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     A pointer to the version ID structure.
  */
 static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId)
 {
@@ -138,11 +137,11 @@
 /*!
  * @brief Gets the LLWU parameter.
  *
- * This function gets the LLWU parameter, including wakeup pin number, module
- * number, DMA number, and pin filter number.
+ * This function gets the LLWU parameter, including a wakeup pin number, a module
+ * number, a DMA number, and a pin filter number.
  *
  * @param base LLWU peripheral base address.
- * @param param         Pointer to LLWU param structure.
+ * @param param         A pointer to the LLWU parameter structure.
  */
 static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param)
 {
@@ -158,8 +157,8 @@
  * as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex pin index which to be enabled as external wakeup source, start from 1.
- * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t
+ * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1.
+ * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t.
  */
 void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode);
 
@@ -167,11 +166,11 @@
  * @brief Gets the external wakeup source flag.
  *
  * This function checks the external pin flag to detect whether the MCU is
- * woke up by the specific pin.
+ * woken up by the specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex     pin index, start from 1.
- * @return true if the specific pin is wake up source.
+ * @param pinIndex     A pin index, which starts from 1.
+ * @return True if the specific pin is a wakeup source.
  */
 bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
 
@@ -181,7 +180,7 @@
  * This function clears the external wakeup source flag for a specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex pin index, start from 1.
+ * @param pinIndex A pin index, which starts from 1.
  */
 void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
@@ -194,8 +193,8 @@
  * as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex   module index which to be enabled as internal wakeup source, start from 1.
- * @param enable        enable or disable setting
+ * @param moduleIndex   A module index to be enabled as an internal wakeup source starting from 1.
+ * @param enable        An enable or a disable setting
  */
 static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
 {
@@ -213,31 +212,31 @@
  * @brief Gets the external wakeup source flag.
  *
  * This function checks the external pin flag to detect whether the system is
- * woke up by the specific pin.
+ * woken up by the specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex  module index, start from 1.
- * @return true if the specific pin is wake up source.
+ * @param moduleIndex  A module index, which starts from 1.
+ * @return True if the specific pin is a wake up source.
  */
 static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex)
 {
+#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF)
 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
     return (bool)(base->MF & (1U << moduleIndex));
 #else
+    return (bool)(base->MF5 & (1U << moduleIndex));
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+#else
 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
-#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
-    return (bool)(base->MF5 & (1U << moduleIndex));
-#else
     return (bool)(base->F5 & (1U << moduleIndex));
-#endif /* FSL_FEATURE_LLWU_HAS_PF */
 #else
 #if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
     return (bool)(base->PF3 & (1U << moduleIndex));
 #else
     return (bool)(base->F3 & (1U << moduleIndex));
-#endif
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
-#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+#endif /* FSL_FEATURE_LLWU_HAS_MF */
 }
 #endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */
 
@@ -248,8 +247,8 @@
  * This function enables/disables the internal DMA that is used as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex   Internal module index which used as DMA request source, start from 1.
- * @param enable        Enable or disable DMA request source
+ * @param moduleIndex   An internal module index which is used as a DMA request source, starting from 1.
+ * @param enable        Enable or disable the DMA request source
  */
 static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
 {
@@ -271,8 +270,8 @@
  * This function sets the pin filter configuration.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1.
- * @param filterMode filter mode configuration
+ * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1.
+ * @param filterMode A filter mode configuration
  */
 void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode);
 
@@ -282,18 +281,18 @@
  * This function gets the pin filter flag.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index, start from 1.
- * @return true if the flag is a source of existing a low-leakage power mode.
+ * @param filterIndex A pin filter index, which starts from 1.
+ * @return True if the flag is a source of the existing low-leakage power mode.
  */
 bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
 
 /*!
- * @brief Clear the pin filter configuration.
+ * @brief Clears the pin filter configuration.
  *
- * This function clear the pin filter flag.
+ * This function clears the pin filter flag.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index which to be clear the flag, start from 1.
+ * @param filterIndex A pin filter index to clear the flag, starting from 1.
  */
 void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
 
@@ -303,10 +302,10 @@
 /*!
  * @brief Sets the reset pin mode.
  *
- * This function sets how the reset pin is used as a low leakage mode exit source.
+ * This function determines how the reset pin is used as a low leakage mode exit source.
  *
- * @param pinEnable       Enable reset pin filter
- * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode.
+ * @param pinEnable       Enable reset the pin filter
+ * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode.
  */
 void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode);
 #endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,7 +48,7 @@
         LMEM_CodeCacheInvalidateAll(base);
 
         /* Now enable the cache. */
-        base->PCCCR |= LMEM_PCCCR_ENCACHE_MASK | LMEM_PCCCR_ENWRBUF_MASK;
+        base->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
     }
     else
     {
@@ -56,7 +56,7 @@
         LMEM_CodeCachePushAll(base);
 
         /* Now disable the cache. */
-        base->PCCCR &= ~(LMEM_PCCCR_ENCACHE_MASK | LMEM_PCCCR_ENWRBUF_MASK);
+        base->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
     }
 }
 
@@ -236,7 +236,7 @@
         }
     }
 }
-
+#if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode)
 {
     uint32_t mode = base->PCCRMR;
@@ -255,6 +255,7 @@
         return kStatus_Success;
     }
 }
+#endif /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
 
 #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable)
@@ -265,7 +266,7 @@
         LMEM_SystemCacheInvalidateAll(base);
 
         /* Now enable the cache. */
-        base->PSCCR |= LMEM_PSCCR_ENCACHE_MASK | LMEM_PSCCR_ENWRBUF_MASK;
+        base->PSCCR |= LMEM_PSCCR_ENCACHE_MASK ;
     }
     else
     {
@@ -273,7 +274,7 @@
         LMEM_SystemCachePushAll(base);
 
         /* Now disable the cache. */
-        base->PSCCR &= ~(LMEM_PSCCR_ENCACHE_MASK | LMEM_PSCCR_ENWRBUF_MASK);
+        base->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
     }
 }
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LMEM controller driver version 2.0.0. */
-#define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief LMEM controller driver version 2.1.0. */
+#define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 #define LMEM_CACHE_LINE_SIZE (0x10U)   /*!< Cache line is 16-bytes. */
@@ -55,9 +54,9 @@
 /*! @brief LMEM cache mode options. */
 typedef enum _lmem_cache_mode
 {
-    kLMEM_NonCacheable = 0x0U,      /*!< CACHE mode: non-cacheable. */
-    kLMEM_CacheWriteThrough = 0x2U, /*!< CACHE mode: write-through. */
-    kLMEM_CacheWriteBack = 0x3U     /*!< CACHE mode: write-back. */
+    kLMEM_NonCacheable = 0x0U,      /*!< Cache mode: non-cacheable. */
+    kLMEM_CacheWriteThrough = 0x2U, /*!< Cache mode: write-through. */
+    kLMEM_CacheWriteBack = 0x3U     /*!< Cache mode: write-back. */
 } lmem_cache_mode_t;
 
 /*! @brief LMEM cache regions. */
@@ -106,7 +105,7 @@
 /*!
  * @brief Enables/disables the processor code bus cache.
  * This function enables/disables the cache.  The function first invalidates the entire cache
- * and then enables/disable both the cache and write buffers.
+ * and then enables/disables both the cache and write buffers.
  *
  * @param base LMEM peripheral base address.
  * @param enable The enable or disable flag.
@@ -116,6 +115,26 @@
 void LMEM_EnableCodeCache(LMEM_Type *base, bool enable);
 
 /*!
+ * @brief Enables/disables the processor code bus write buffer.
+ *
+ * @param base LMEM peripheral base address.
+ * @param enable The enable or disable flag.
+ *       true  - enable the code bus write buffer.
+ *       false - disable the code bus write buffer.
+ */
+static inline void LMEM_EnableCodeWriteBuffer(LMEM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
+    }
+    else
+    {
+        base->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
+    }
+}
+
+/*!
  * @brief Invalidates the processor code bus cache.
  * This function invalidates the cache both ways, which means that
  * it unconditionally clears valid bits and modifies bits of a cache entry.
@@ -163,10 +182,10 @@
  * This function invalidates multiple lines in the cache
  * based on the physical address and length in bytes passed in by the
  * user.  If the function detects that the length meets or exceeds half the
- * cache. Then the function performs an entire cache invalidate function, which is
+ * cache, the function performs an entire cache invalidate function, which is
  * more efficient than invalidating the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Invalidate - Unconditionally clear valid and modified bits of a cache entry.
  *
  * @param base LMEM peripheral base address.
@@ -197,8 +216,8 @@
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an cache push function, which is
  * more efficient than pushing the modified lines in the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If
  * the entry is not valid or not modified, leave as is. This action does not clear the valid
  * bit. A cache push is synonymous with a cache flush.
@@ -230,8 +249,8 @@
  * user.  If the function detects that the length meets or exceeds half the total amount of
  * cache, the function performs a cache clear function which is
  * more efficient than clearing the lines in the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Clear - Push a cache entry if it is valid and modified, then clear the valid and
  * modify bits. If entry not valid or not modified, clear the valid bit.
  *
@@ -242,6 +261,7 @@
  */
 void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
 
+#if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
 /*!
  * @brief Demotes the cache mode of a region in processor code bus cache.
  * This function allows the user to demote the cache mode of a region within the device's
@@ -264,6 +284,7 @@
  * kStatus_Fail The cache demote operation is failure.
  */
 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
+#endif  /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
 
 /*@}*/
 
@@ -286,6 +307,26 @@
 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable);
 
 /*!
+ * @brief Enables/disables the processor system bus write buffer.
+ *
+ * @param base LMEM peripheral base address.
+ * @param enable The enable or disable flag.
+ *       true  - enable the system bus write buffer.
+ *       false - disable the system bus write buffer.
+ */
+static inline void LMEM_EnableSystemWriteBuffer(LMEM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;       
+    }
+    else
+    {
+        base->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;               
+    }
+}
+
+/*!
  * @brief Invalidates the processor system bus cache.
  * This function invalidates the entire cache both ways.
  * Invalidate - Unconditionally clear valid and modify bits of a cache entry
@@ -320,7 +361,7 @@
  * @brief Invalidates a specific line in the processor system bus cache.
  * This function invalidates a specific line in the cache
  * based on the physical address passed in by the user.
- * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ * Invalidate - Unconditionally clears valid and modify bits of a cache entry.
  *
  * @param base LMEM peripheral base address. Should be 16-byte aligned address.
  * If not, it is changed to the 16-byte aligned memory address.
@@ -335,8 +376,8 @@
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache invalidate function (which is
  * more efficient than invalidating the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address  searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Invalidate - Unconditionally clear valid and modify bits of a cache entry
  *
  * @param base LMEM peripheral base address.
@@ -367,8 +408,8 @@
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache push function (which is
  * more efficient than pushing the modified lines in the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
  * the entry is not valid or not modified, leave as is. This action does not clear the valid
  * bit. A cache push is synonymous with a cache flush.
@@ -400,8 +441,8 @@
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache clear function (which is
  * more efficient than clearing the lines in the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Clear - Push a cache entry if it is valid and modified, then clear the valid and
  * modify bits. If the entry is not valid or not modified, clear the valid bit.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,9 +48,17 @@
 /*! @brief Pointers to LPTMR bases for each instance. */
 static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to LPTMR clocks for each instance. */
 static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS;
 
+#if defined(LPTMR_PERIPH_CLOCKS)
+/* Array of LPTMR functional clock name. */
+static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -59,7 +67,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++)
     {
         if (s_lptmrBases[instance] == base)
         {
@@ -67,7 +75,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT);
+    assert(instance < ARRAY_SIZE(s_lptmrBases));
 
     return instance;
 }
@@ -76,8 +84,17 @@
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    
+    uint32_t instance = LPTMR_GetInstance(base);
+
     /* Ungate the LPTMR clock*/
-    CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+    CLOCK_EnableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure the timers operation mode and input pin setup */
     base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) |
@@ -92,8 +109,17 @@
 {
     /* Disable the LPTMR and reset the internal logic */
     base->CSR &= ~LPTMR_CSR_TEN_MASK;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    uint32_t instance = LPTMR_GetInstance(base);
+
     /* Gate the LPTMR clock*/
-    CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+    CLOCK_DisableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void LPTMR_GetDefaultConfig(lptmr_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,22 +33,20 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup lptmr_driver
+ * @addtogroup lptmr
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
 /*@}*/
 
-/*! @brief LPTMR pin selection, used in pulse counter mode.*/
+/*! @brief LPTMR pin selection used in pulse counter mode.*/
 typedef enum _lptmr_pin_select
 {
     kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
@@ -57,7 +55,7 @@
     kLPTMR_PinSelectInput_3 = 0x3U  /*!< Pulse counter input 3 is selected */
 } lptmr_pin_select_t;
 
-/*! @brief LPTMR pin polarity, used in pulse counter mode.*/
+/*! @brief LPTMR pin polarity used in pulse counter mode.*/
 typedef enum _lptmr_pin_polarity
 {
     kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
@@ -104,13 +102,13 @@
     kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
 } lptmr_prescaler_clock_select_t;
 
-/*! @brief List of LPTMR interrupts */
+/*! @brief List of the LPTMR interrupts */
 typedef enum _lptmr_interrupt_enable
 {
     kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
 } lptmr_interrupt_enable_t;
 
-/*! @brief List of LPTMR status flags */
+/*! @brief List of the LPTMR status flags */
 typedef enum _lptmr_status_flags
 {
     kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
@@ -121,18 +119,18 @@
  *
  * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
  * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
- * pointer to your config structure instance.
+ * pointer to your configuration structure instance.
  *
- * The config struct can be made const so it resides in flash
+ * The configuration struct can be made constant so it resides in flash.
  */
 typedef struct _lptmr_config
 {
     lptmr_timer_mode_t timerMode;     /*!< Time counter mode or pulse counter mode */
     lptmr_pin_select_t pinSelect;     /*!< LPTMR pulse input pin select; used only in pulse counter mode */
     lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
-    bool enableFreeRunning;           /*!< true: enable free running, counter is reset on overflow
-                                           false: counter is reset when the compare flag is set */
-    bool bypassPrescaler;             /*!< true: bypass prescaler; false: use clock from prescaler */
+    bool enableFreeRunning;           /*!< True: enable free running, counter is reset on overflow
+                                           False: counter is reset when the compare flag is set */
+    bool bypassPrescaler;             /*!< True: bypass prescaler; false: use clock from prescaler */
     lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
     lptmr_prescaler_glitch_value_t value;                /*!< Prescaler or glitch filter value */
 } lptmr_config_t;
@@ -151,26 +149,26 @@
  */
 
 /*!
- * @brief Ungate the LPTMR clock and configures the peripheral for basic operation.
+ * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
  *
  * @note This API should be called at the beginning of the application using the LPTMR driver.
  *
  * @param base   LPTMR peripheral base address
- * @param config Pointer to user's LPTMR config structure.
+ * @param config A pointer to the LPTMR configuration structure.
  */
 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
 
 /*!
- * @brief Gate the LPTMR clock
+ * @brief Gates the LPTMR clock.
  *
  * @param base LPTMR peripheral base address
  */
 void LPTMR_Deinit(LPTMR_Type *base);
 
 /*!
- * @brief Fill in the LPTMR config struct with the default settings
+ * @brief Fills in the LPTMR configuration structure with default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *    config->timerMode = kLPTMR_TimerModeTimeCounter;
  *    config->pinSelect = kLPTMR_PinSelectInput_0;
@@ -180,7 +178,7 @@
  *    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
  *    config->value = kLPTMR_Prescale_Glitch_0;
  * @endcode
- * @param config Pointer to user's LPTMR config structure.
+ * @param config A pointer to the LPTMR configuration structure.
  */
 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
 
@@ -200,7 +198,12 @@
  */
 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
 {
-    base->CSR |= mask;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= mask;
+    base->CSR = reg;
 }
 
 /*!
@@ -208,11 +211,16 @@
  *
  * @param base LPTMR peripheral base address
  * @param mask The interrupts to disable. This is a logical OR of members of the
- *             enumeration ::lptmr_interrupt_enable_t
+ *             enumeration ::lptmr_interrupt_enable_t.
  */
 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
 {
-    base->CSR &= ~mask;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~mask;
+    base->CSR = reg;
 }
 
 /*!
@@ -236,7 +244,7 @@
  */
 
 /*!
- * @brief Gets the LPTMR status flags
+ * @brief Gets the LPTMR status flags.
  *
  * @param base LPTMR peripheral base address
  *
@@ -249,11 +257,11 @@
 }
 
 /*!
- * @brief  Clears the LPTMR status flags
+ * @brief  Clears the LPTMR status flags.
  *
  * @param base LPTMR peripheral base address
  * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::lptmr_status_flags_t
+ *             enumeration ::lptmr_status_flags_t.
  */
 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
 {
@@ -263,47 +271,48 @@
 /*! @}*/
 
 /*!
- * @name Read and Write the timer period
+ * @name Read and write the timer period
  * @{
  */
 
 /*!
  * @brief Sets the timer period in units of count.
  *
- * Timers counts from 0 till it equals the count value set here. The count value is written to
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
  * the CMR register.
  *
  * @note
  * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
- * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
+ * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
  *
  * @param base  LPTMR peripheral base address
- * @param ticks Timer period in units of ticks
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
  */
-static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks)
+static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
 {
-    base->CMR = ticks;
+    assert(ticks > 0);
+    base->CMR = ticks - 1;
 }
 
 /*!
  * @brief Reads the current timer counting value.
  *
- * This function returns the real-time timer counting value, in a range from 0 to a
+ * This function returns the real-time timer counting value in a range from 0 to a
  * timer period.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
  *
  * @param base LPTMR peripheral base address
  *
- * @return Current counter value in ticks
+ * @return The current counter value in ticks
  */
-static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
+static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
 {
-    /* Must first write any value to the CNR. This will synchronize and register the current value
+    /* Must first write any value to the CNR. This synchronizes and registers the current value
      * of the CNR into a temporary register which can then be read
      */
     base->CNR = 0U;
-    return (uint16_t)base->CNR;
+    return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
 }
 
 /*! @}*/
@@ -314,30 +323,40 @@
  */
 
 /*!
- * @brief Starts the timer counting.
+ * @brief Starts the timer.
  *
  * After calling this function, the timer counts up to the CMR register value.
- * Each time the timer reaches CMR value and then increments, it generates a
- * trigger pulse and sets the timeout interrupt flag. An interrupt will also be
+ * Each time the timer reaches the CMR value and then increments, it generates a
+ * trigger pulse and sets the timeout interrupt flag. An interrupt is also
  * triggered if the timer interrupt is enabled.
  *
  * @param base LPTMR peripheral base address
  */
 static inline void LPTMR_StartTimer(LPTMR_Type *base)
 {
-    base->CSR |= LPTMR_CSR_TEN_MASK;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
 }
 
 /*!
- * @brief Stops the timer counting.
+ * @brief Stops the timer.
  *
- * This function stops the timer counting and resets the timer's counter register
+ * This function stops the timer and resets the timer's counter register.
  *
  * @param base LPTMR peripheral base address
  */
 static inline void LPTMR_StopTimer(LPTMR_Type *base)
 {
-    base->CSR &= ~LPTMR_CSR_TEN_MASK;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
 }
 
 /*! @}*/

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -109,9 +109,23 @@
 /* Array of LPUART peripheral base address. */
 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
 /* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
+static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
+#else
 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of LPUART clock name. */
 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
+
+#if defined(LPUART_PERIPH_CLOCKS)
+/* Array of LPUART functional clock name. */
+static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
 /* LPUART ISR for transactional APIs. */
 static lpuart_isr_t s_lpuartIsr;
 
@@ -123,7 +137,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++)
     {
         if (s_lpuartBases[instance] == base)
         {
@@ -131,13 +145,15 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
+    assert(instance < ARRAY_SIZE(s_lpuartBases));
 
     return instance;
 }
 
 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     size_t size;
 
     if (handle->rxRingBufferTail > handle->rxRingBufferHead)
@@ -154,6 +170,8 @@
 
 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     bool full;
 
     if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
@@ -169,6 +187,8 @@
 
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking write data API assume user have ensured there is enough space in
@@ -181,33 +201,48 @@
 
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     /* The Non Blocking read data API assume user have ensured there is enough space in
     peripheral to write. */
     for (i = 0; i < length; i++)
     {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            data[i] = (base->DATA & 0x7F);
+        }
+        else
+        {
+            data[i] = base->DATA;
+        }
+#else
         data[i] = base->DATA;
+#endif
     }
 }
 
-void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
 {
     assert(config);
+    assert(config->baudRate_Bps);
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
     assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
 #endif
+
     uint32_t temp;
     uint16_t sbr, sbrTemp;
     uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
 
-    /* Enable lpuart clock */
-    CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
-
-    /* Disable LPUART TX RX before setting. */
-    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
-
     /* This LPUART instantiation uses a slightly different baud rate calculation
      * The idea is to use the best OSR (over-sampling rate) possible
      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
@@ -248,34 +283,75 @@
 
     /* Check to see if actual baud rate is within 3% of desired baud rate
      * based on the best calculate OSR value */
-    if (baudDiff < ((config->baudRate_Bps / 100) * 3))
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
     {
-        temp = base->BAUD;
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    
+    uint32_t instance = LPUART_GetInstance(base);
+
+    /* Enable lpuart clock */
+    CLOCK_EnableClock(s_lpuartClock[instance]);
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
-         * If so, then "BOTHEDGE" sampling must be turned on */
-        if ((osr > 3) && (osr < 8))
-        {
-            temp |= LPUART_BAUD_BOTHEDGE_MASK;
-        }
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+    /*Reset all internal logic and registers, except the Global Register */
+    LPUART_SoftwareReset(base);
+#else
+    /* Disable LPUART TX RX before setting. */
+    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+#endif
+
+    temp = base->BAUD;
 
-        /* program the osr value (bit value is one less than actual value) */
-        temp &= ~LPUART_BAUD_OSR_MASK;
-        temp |= LPUART_BAUD_OSR(osr - 1);
+    /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+     * If so, then "BOTHEDGE" sampling must be turned on */
+    if ((osr > 3) && (osr < 8))
+    {
+        temp |= LPUART_BAUD_BOTHEDGE_MASK;
+    }
 
-        /* write the sbr value to the BAUD registers */
-        temp &= ~LPUART_BAUD_SBR_MASK;
-        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
-    }
+    /* program the osr value (bit value is one less than actual value) */
+    temp &= ~LPUART_BAUD_OSR_MASK;
+    temp |= LPUART_BAUD_OSR(osr - 1);
+
+    /* write the sbr value to the BAUD registers */
+    temp &= ~LPUART_BAUD_SBR_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBR(sbr);
 
     /* Set bit count and parity mode. */
     base->BAUD &= ~LPUART_BAUD_M10_MASK;
 
     temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
 
-    if (kLPUART_ParityDisabled != config->parityMode)
+    temp |= (uint8_t)config->parityMode;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    if (kLPUART_SevenDataBits == config->dataBitsCount)
     {
-        temp |= (LPUART_CTRL_M_MASK | (uint8_t)config->parityMode);
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
+        }
+        else
+        {
+            temp |= LPUART_CTRL_M7_MASK;
+        }
+    }
+    else
+#endif
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
+        }
     }
 
     base->CTRL = temp;
@@ -298,17 +374,27 @@
 #endif
 
     /* Clear all status flags */
-    temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
             LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp |= LPUART_STAT_IDLE_MASK;
+    temp |= LPUART_STAT_LBKDIF_MASK;
 #endif
 
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
     temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
 #endif
 
+    /* Set data bits order. */
+    if (config->isMsb)
+    {
+        temp |= LPUART_STAT_MSBF_MASK;
+    }
+    else
+    {
+        temp &= ~LPUART_STAT_MSBF_MASK;
+    }
+
     base->STAT |= temp;
 
     /* Enable TX/RX base on configure structure. */
@@ -324,6 +410,8 @@
     }
 
     base->CTRL = temp;
+
+    return kStatus_Success;
 }
 void LPUART_Deinit(LPUART_Type *base)
 {
@@ -341,11 +429,11 @@
     }
 
     /* Clear all status flags */
-    temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
             LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp |= LPUART_STAT_IDLE_MASK;
+    temp |= LPUART_STAT_LBKDIF_MASK;
 #endif
 
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
@@ -357,15 +445,27 @@
     /* Disable the module. */
     base->CTRL = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = LPUART_GetInstance(base);
+
     /* Disable lpuart clock */
-    CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
+    CLOCK_DisableClock(s_lpuartClock[instance]);
+
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void LPUART_GetDefaultConfig(lpuart_config_t *config)
 {
     assert(config);
+
     config->baudRate_Bps = 115200U;
     config->parityMode = kLPUART_ParityDisabled;
+    config->dataBitsCount = kLPUART_EightDataBits;
+    config->isMsb = false;
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     config->stopBitCount = kLPUART_OneStopBit;
 #endif
@@ -377,18 +477,14 @@
     config->enableRx = false;
 }
 
-void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
+    assert(baudRate_Bps);
+
     uint32_t temp, oldCtrl;
     uint16_t sbr, sbrTemp;
     uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
 
-    /* Store CTRL before disable Tx and Rx */
-    oldCtrl = base->CTRL;
-
-    /* Disable LPUART TX RX before setting. */
-    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
-
     /* This LPUART instantiation uses a slightly different baud rate calculation
      * The idea is to use the best OSR (over-sampling rate) possible
      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
@@ -431,6 +527,12 @@
      * based on the best calculate OSR value */
     if (baudDiff < ((baudRate_Bps / 100) * 3))
     {
+        /* Store CTRL before disable Tx and Rx */
+        oldCtrl = base->CTRL;
+
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
         temp = base->BAUD;
 
         /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
@@ -447,17 +549,25 @@
         /* write the sbr value to the BAUD registers */
         temp &= ~LPUART_BAUD_SBR_MASK;
         base->BAUD = temp | LPUART_BAUD_SBR(sbr);
-    }
+
+        /* Restore CTRL. */
+        base->CTRL = oldCtrl;
 
-    /* Restore CTRL. */
-    base->CTRL = oldCtrl;
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
 }
 
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
     base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    base->FIFO |= ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+                 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL |= mask;
@@ -467,7 +577,8 @@
 {
     base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    base->FIFO &= ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+                 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL &= ~mask;
@@ -503,24 +614,24 @@
     status_t status;
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     temp = (uint32_t)base->FIFO;
-    temp &= (uint32_t)(~(kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag));
-    temp |= mask & (kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag);
+    temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+    temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
     base->FIFO = temp;
 #endif
     temp = (uint32_t)base->STAT;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp &= (uint32_t)(~(kLPUART_LinBreakFlag));
-    temp |= mask & kLPUART_LinBreakFlag;
+    temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
+    temp |= mask & LPUART_STAT_LBKDIF_MASK;
 #endif
-    temp &= (uint32_t)(~(kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag |
-                         kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag));
-    temp |= mask & (kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag |
-                    kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag);
+    temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                         LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
+    temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                    LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
-    temp &= (uint32_t)(~(kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag));
-    temp |= mask & (kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag);
+    temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
+    temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
 #endif
-    base->STAT |= temp;
+    base->STAT = temp;
     /* If some flags still pending. */
     if (mask & LPUART_GetStatusFlags(base))
     {
@@ -540,6 +651,8 @@
 
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     /* This API can only ensure that the data is written into the data buffer but can't
     ensure all data in the data buffer are sent into the transmit shift buffer. */
     while (length--)
@@ -553,7 +666,15 @@
 
 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     uint32_t statusFlag;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     while (length--)
     {
@@ -589,7 +710,18 @@
                 return kStatus_LPUART_ParityError;
             }
         }
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            *(data++) = (base->DATA & 0x7F);
+        }
+        else
+        {
+            *(data++) = base->DATA;
+        }
+#else
         *(data++) = base->DATA;
+#endif
     }
 
     return kStatus_Success;
@@ -603,6 +735,12 @@
     assert(handle);
 
     uint32_t instance;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(lpuart_handle_t));
@@ -615,6 +753,11 @@
     handle->callback = callback;
     handle->userData = userData;
 
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Initial seven data bits flag */
+    handle->isSevenDataBits = isSevenDataBits;
+#endif
+
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Note:
        Take care of the RX FIFO, RX interrupt request only assert when received bytes
@@ -624,7 +767,7 @@
        5 bytes are received. the last byte will be saved in FIFO but not trigger
        RX interrupt because the water mark is 2.
      */
-    base->WATER &= (~LPUART_WATER_RXWATER_SHIFT);
+    base->WATER &= (~LPUART_WATER_RXWATER_MASK);
 #endif
 
     /* Get instance from peripheral base address. */
@@ -635,8 +778,13 @@
 
     s_lpuartIsr = LPUART_TransferHandleIRQ;
 
-    /* Enable interrupt in NVIC. */
+/* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    EnableIRQ(s_lpuartRxIRQ[instance]);
+    EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
     EnableIRQ(s_lpuartIRQ[instance]);
+#endif
 }
 
 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
@@ -645,18 +793,16 @@
                                     size_t ringBufferSize)
 {
     assert(handle);
+    assert(ringBuffer);
 
     /* Setup the ring buffer address */
-    if (ringBuffer)
-    {
-        handle->rxRingBuffer = ringBuffer;
-        handle->rxRingBufferSize = ringBufferSize;
-        handle->rxRingBufferHead = 0U;
-        handle->rxRingBufferTail = 0U;
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
 
-        /* Enable the interrupt to accept the data when user need the ring buffer. */
-        LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
-    }
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
 }
 
 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
@@ -676,13 +822,12 @@
 
 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
 {
-    status_t status;
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
+    status_t status;
 
     /* Return error if current TX busy. */
     if (kLPUART_TxBusy == handle->txState)
@@ -707,6 +852,8 @@
 
 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
 
     handle->txDataSize = 0;
@@ -715,16 +862,14 @@
 
 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->txDataSizeAll - handle->txDataSize;
 
     return kStatus_Success;
@@ -735,6 +880,11 @@
                                            lpuart_transfer_t *xfer,
                                            size_t *receivedBytes)
 {
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
     uint32_t i;
     status_t status;
     /* How many bytes to copy from ring buffer to user memory. */
@@ -743,13 +893,6 @@
     size_t bytesToReceive;
     /* How many bytes currently have received. */
     size_t bytesCurrentReceived;
-    uint32_t regPrimask = 0U;
-
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
 
     /* How to get data:
        1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
@@ -773,8 +916,8 @@
         /* If RX ring buffer is used. */
         if (handle->rxRingBuffer)
         {
-            /* Disable IRQ, protect ring buffer. */
-            regPrimask = DisableGlobalIRQ();
+            /* Disable LPUART RX IRQ, protect ring buffer. */
+            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
 
             /* How many bytes in RX ring buffer currently. */
             bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
@@ -811,8 +954,8 @@
                 handle->rxDataSizeAll = bytesToReceive;
                 handle->rxState = kLPUART_RxBusy;
             }
-            /* Enable IRQ if previously enabled. */
-            EnableGlobalIRQ(regPrimask);
+            /* Enable LPUART RX IRQ if previously enabled. */
+            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
 
             /* Call user callback since all data are received. */
             if (0 == bytesToReceive)
@@ -849,6 +992,8 @@
 
 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
     if (!handle->rxRingBuffer)
     {
@@ -862,16 +1007,14 @@
 
 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->rxDataSizeAll - handle->rxDataSize;
 
     return kStatus_Success;
@@ -879,19 +1022,17 @@
 
 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     uint8_t count;
     uint8_t tempCount;
-    volatile uint8_t dummy;
-
-    assert(handle);
 
     /* If RX overrun. */
     if (LPUART_STAT_OR_MASK & base->STAT)
     {
-        /* Read base->DATA, otherwise the RX does not work. */
-        dummy = base->DATA;
-        /* Avoid optimization */
-        dummy++;
+        /* Clear overrun flag, otherwise the RX does not work. */
+        base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
+
         /* Trigger callback. */
         if (handle->callback)
         {
@@ -964,8 +1105,19 @@
                     }
                 }
 
-                /* Read data. */
+/* Read data. */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+                if (handle->isSevenDataBits)
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
+                }
+                else
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+                }
+#else
                 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+#endif
 
                 /* Increase handle->rxRingBufferHead. */
                 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
@@ -1033,71 +1185,113 @@
 
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    /* TODO: To be implemented. */
+    /* To be implemented by User. */
 }
 
 #if defined(LPUART0)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+void LPUART0_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+#else
 void LPUART0_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
 }
-void LPUART0_RX_TX_DriverIRQHandler(void)
-{
-    LPUART0_DriverIRQHandler();
-}
+#endif
 #endif
 
 #if defined(LPUART1)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART1_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+void LPUART1_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+#else
 void LPUART1_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
 }
-void LPUART1_RX_TX_DriverIRQHandler(void)
-{
-    LPUART1_DriverIRQHandler();
-}
+#endif
 #endif
 
 #if defined(LPUART2)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART2_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+void LPUART2_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+#else
 void LPUART2_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
 }
-void LPUART2_RX_TX_DriverIRQHandler(void)
-{
-    LPUART2_DriverIRQHandler();
-}
+#endif
 #endif
 
 #if defined(LPUART3)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART3_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+void LPUART3_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+#else
 void LPUART3_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
 }
-void LPUART3_RX_TX_DriverIRQHandler(void)
-{
-    LPUART3_DriverIRQHandler();
-}
+#endif
 #endif
 
 #if defined(LPUART4)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART4_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+void LPUART4_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+#else
 void LPUART4_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
 }
-void LPUART4_RX_TX_DriverIRQHandler(void)
-{
-    LPUART4_DriverIRQHandler();
-}
+#endif
 #endif
 
 #if defined(LPUART5)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART5_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+void LPUART5_RX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+#else
 void LPUART5_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
 }
-void LPUART5_RX_TX_DriverIRQHandler(void)
-{
-    LPUART5_DriverIRQHandler();
-}
 #endif
+#endif

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,36 +37,35 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPUART driver version 2.1.0. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief LPUART driver version 2.2.3. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
 /*@}*/
 
 /*! @brief Error codes for the LPUART driver. */
 enum _lpuart_status
 {
-    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),              /*!< TX busy */
-    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),              /*!< RX busy */
-    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),              /*!< LPUART transmitter is idle. */
-    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),              /*!< LPUART receiver is idle. */
-    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large  */
-    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large  */
-    kStatus_LPUART_FlagCannotClearManually =
-        MAKE_STATUS(kStatusGroup_LPUART, 6),                    /*!< Some flag can't manually clear */
-    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
+    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),                  /*!< TX busy */
+    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),                  /*!< RX busy */
+    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),                  /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),                  /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4),     /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5),     /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7),                   /*!< Error happens on LPUART. */
     kStatus_LPUART_RxRingBufferOverrun =
         MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
     kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
     kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
     kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
     kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
 };
 
 /*! @brief LPUART parity mode. */
@@ -77,6 +76,15 @@
     kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
 } lpuart_parity_mode_t;
 
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
 /*! @brief LPUART stop bit count. */
 typedef enum _lpuart_stop_bit_count
 {
@@ -158,11 +166,13 @@
 #endif
 };
 
-/*! @brief LPUART configure structure. */
+/*! @brief LPUART configuration structure. */
 typedef struct _lpuart_config
 {
-    uint32_t baudRate_Bps;           /*!< LPUART baud rate  */
-    lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
+    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
 #endif
@@ -206,7 +216,11 @@
     void *userData;                      /*!< LPUART callback function parameter.*/
 
     volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state */
+    volatile uint8_t rxState; /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
 };
 
 /*******************************************************************************
@@ -217,32 +231,59 @@
 extern "C" {
 #endif /* _cplusplus */
 
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+
+/*!
+ * @name Software Reset
+ * @{
+ */
+
+/*!
+ * @brief Resets the LPUART using software.
+ *
+ * This function resets all internal logic and registers except the Global Register.
+ * Remains set until cleared by software.
+ *
+ * @param base LPUART peripheral base address.
+ */
+static inline void LPUART_SoftwareReset(LPUART_Type *base)
+{
+    base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+}
+/* @} */
+#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
+
 /*!
  * @name Initialization and deinitialization
  * @{
  */
 
 /*!
-* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
-*
-* This function configures the LPUART module with  user-defined settings. Call the LPUART_GetDefaultConfig() function
-* to configure the configuration structure and get the default configuration.
-* The example below shows how to use this API to configure the LPUART.
-* @code
-*  lpuart_config_t lpuartConfig;
-*  lpuartConfig.baudRate_Bps = 115200U;
-*  lpuartConfig.parityMode = kLPUART_ParityDisabled;
-*  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
-*  lpuartConfig.txFifoWatermark = 0;
-*  lpuartConfig.rxFifoWatermark = 1;
-*  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
-* @endcode
-*
-* @param base LPUART peripheral base address.
-* @param config Pointer to a user-defined configuration structure.
-* @param srcClock_Hz LPUART clock source frequency in HZ.
-*/
-void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+ * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * @code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
 
 /*!
  * @brief Deinitializes a LPUART instance.
@@ -260,6 +301,8 @@
  * values are:
  *   lpuartConfig->baudRate_Bps = 115200U;
  *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
  *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
  *   lpuartConfig->txFifoWatermark = 0;
  *   lpuartConfig->rxFifoWatermark = 1;
@@ -282,8 +325,10 @@
  * @param base LPUART peripheral base address.
  * @param baudRate_Bps LPUART baudrate to be set.
  * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
  */
-void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
 
 /* @} */
 
@@ -512,24 +557,40 @@
 }
 
 /*!
- * @brief Reads the RX register.
+ * @brief Reads the receiver register.
  *
- * This function reads data from the TX register directly. The upper layer must
- * ensure that the RX register is full or that the TX FIFO has data before calling this function.
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the receiver register is full or that the RX FIFO has data before calling this function.
  *
  * @param base LPUART peripheral base address.
  * @return Data read from data register.
  */
 static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
 {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+
+    if (isSevenDataBits)
+    {
+        return (base->DATA & 0x7F);
+    }
+    else
+    {
+        return base->DATA;
+    }
+#else
     return base->DATA;
+#endif
 }
 
 /*!
- * @brief Writes to transmitter register using a blocking method.
+ * @brief Writes to the transmitter register using a blocking method.
  *
  * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
- * room and then writes data to the transmitter buffer.
+ * room, and writes data to the transmitter buffer.
  *
  * @note This function does not check whether all data has been sent out to the bus.
  * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
@@ -542,10 +603,10 @@
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
 /*!
-* @brief Reads the RX data register using a blocking method.
+* @brief Reads the receiver data register using a blocking method.
  *
- * This function polls the RX register, waits for the RX register full or RX FIFO
- * has data then reads data from the TX register.
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
  *
  * @param base LPUART peripheral base address.
  * @param data Start address of the buffer to store the received data.
@@ -601,7 +662,7 @@
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
- * @param xfer LPUART transfer structure, refer to #lpuart_transfer_t.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
  * @retval kStatus_Success Successfully start the data transmission.
  * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
  * @retval kStatus_InvalidArgument Invalid argument.
@@ -631,7 +692,7 @@
                                     size_t ringBufferSize);
 
 /*!
- * @brief Abort the background transfer and uninstall the ring buffer.
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
  *
  * This function aborts the background transfer and uninstalls the ring buffer.
  *
@@ -644,7 +705,7 @@
  * @brief Aborts the interrupt-driven data transmit.
  *
  * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
- * how many bytes are still not sent out.
+ * how many bytes are not sent out.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
@@ -652,10 +713,10 @@
 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to LPUART TX register.
+ * @brief Gets the number of bytes that have been written to the LPUART transmitter register.
  *
  * This function gets the number of bytes that have been written to LPUART TX
- * register by interrupt method.
+ * register by an interrupt method.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
@@ -686,7 +747,7 @@
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
- * @param xfer LPUART transfer structure, refer to #uart_transfer_t.
+ * @param xfer LPUART transfer structure, see #uart_transfer_t.
  * @param receivedBytes Bytes received from the ring buffer directly.
  * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
  * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
@@ -709,7 +770,7 @@
 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of bytes that have been received.
  *
  * This function gets the number of bytes that have been received.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -98,6 +98,8 @@
 
 static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid the warning for unused variables. */
@@ -118,6 +120,8 @@
 
 static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid warning for unused parameters. */
@@ -138,11 +142,11 @@
 }
 
 void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
-                             lpuart_edma_handle_t *handle,
-                             lpuart_edma_transfer_callback_t callback,
-                             void *userData,
-                             edma_handle_t *txEdmaHandle,
-                             edma_handle_t *rxEdmaHandle)
+                                     lpuart_edma_handle_t *handle,
+                                     lpuart_edma_transfer_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *txEdmaHandle,
+                                     edma_handle_t *rxEdmaHandle)
 {
     assert(handle);
 
@@ -189,19 +193,18 @@
         EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
     }
 }
+
 status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous TX not finished. */
     if (kLPUART_TxBusy == handle->txState)
     {
@@ -216,6 +219,9 @@
         EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+        /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->txEdmaHandle);
@@ -231,17 +237,15 @@
 
 status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous RX not finished. */
     if (kLPUART_RxBusy == handle->rxState)
     {
@@ -256,6 +260,9 @@
         EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
 
+        /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->rxEdmaHandle);
@@ -271,6 +278,7 @@
 
 void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
 
     /* Disable LPUART TX EDMA. */
@@ -284,6 +292,7 @@
 
 void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
 
     /* Disable LPUART RX EDMA. */
@@ -297,38 +306,36 @@
 
 status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(count);
 
     if (kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+    *count = handle->rxDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
 
     return kStatus_Success;
 }
 
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(count);
 
     if (kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+    *count = handle->txDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
 
     return kStatus_Success;
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,8 +39,6 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -67,6 +65,8 @@
     edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
     edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
 
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
     volatile uint8_t txState; /*!< TX transfer state. */
     volatile uint8_t rxState; /*!< RX transfer state */
 };
@@ -94,11 +94,11 @@
  * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
  */
 void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
-                             lpuart_edma_handle_t *handle,
-                             lpuart_edma_transfer_callback_t callback,
-                             void *userData,
-                             edma_handle_t *txEdmaHandle,
-                             edma_handle_t *rxEdmaHandle);
+                                     lpuart_edma_handle_t *handle,
+                                     lpuart_edma_transfer_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *txEdmaHandle,
+                                     edma_handle_t *rxEdmaHandle);
 
 /*!
  * @brief Sends data using eDMA.
@@ -123,7 +123,7 @@
  *
  * @param base LPUART peripheral base address.
  * @param handle Pointer to lpuart_edma_handle_t structure.
- * @param xfer LPUART eDMA transfer structure, refer to #lpuart_transfer_t.
+ * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t.
  * @retval kStatus_Success if succeed, others fail.
  * @retval kStatus_LPUART_RxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
@@ -151,9 +151,9 @@
 void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to LPUART TX register.
+ * @brief Gets the number of bytes written to the LPUART TX register.
  *
- * This function gets the number of bytes that have been written to LPUART TX
+ * This function gets the number of bytes written to the LPUART TX
  * register by DMA.
  *
  * @param base LPUART peripheral base address.
@@ -166,9 +166,9 @@
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of received bytes.
  *
- * This function gets the number of bytes that have been received.
+ * This function gets the number of received bytes.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,232 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_mpu.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Defines the register numbers of the region descriptor configure. */
-#define MPU_REGIONDESCRIPTOR_WROD_REGNUM (4U)
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS;
-
-/*******************************************************************************
- * Codes
- ******************************************************************************/
-
-void MPU_Init(MPU_Type *base, const mpu_config_t *config)
-{
-    assert(config);
-    uint8_t count;
-
-    /* Un-gate MPU clock */
-    CLOCK_EnableClock(g_mpuClock[0]);
-
-    /* Initializes the regions. */
-    for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++)
-    {
-        base->WORD[count][3] = 0; /* VLD/VID+PID. */
-        base->WORD[count][0] = 0; /* Start address. */
-        base->WORD[count][1] = 0; /* End address. */
-        base->WORD[count][2] = 0; /* Access rights. */
-        base->RGDAAC[count] = 0;  /* Alternate access rights. */
-    }
-
-    /* MPU configure. */
-    while (config)
-    {
-        MPU_SetRegionConfig(base, &(config->regionConfig));
-        config = config->next;
-    }
-    /* Enable MPU. */
-    MPU_Enable(base, true);
-}
-
-void MPU_Deinit(MPU_Type *base)
-{
-    /* Disable MPU. */
-    MPU_Enable(base, false);
-
-    /* Gate the clock. */
-    CLOCK_DisableClock(g_mpuClock[0]);
-}
-
-void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform)
-{
-    assert(hardwareInform);
-
-    uint32_t cesReg = base->CESR;
-
-    hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
-    hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
-    hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
-}
-
-void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig)
-{
-    assert(regionConfig);
-
-    uint32_t wordReg = 0;
-    uint8_t count;
-    uint8_t number = regionConfig->regionNum;
-
-    /* The start and end address of the region descriptor. */
-    base->WORD[number][0] = regionConfig->startAddress;
-    base->WORD[number][1] = regionConfig->endAddress;
-
-    /* The region descriptor access rights control. */
-    for (count = 0; count < MPU_REGIONDESCRIPTOR_WROD_REGNUM; count++)
-    {
-        wordReg |= MPU_WORD_LOW_MASTER(count, (((uint32_t)regionConfig->accessRights1[count].superAccessRights << 3U) |
-                                               (uint8_t)regionConfig->accessRights1[count].userAccessRights)) |
-                   MPU_WORD_HIGH_MASTER(count, ((uint32_t)regionConfig->accessRights2[count].readEnable << 1U |
-                                                (uint8_t)regionConfig->accessRights2[count].writeEnable));
-
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-        wordReg |= MPU_WORD_MASTER_PE(count, regionConfig->accessRights1[count].processIdentifierEnable);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-    }
-
-    /* Set region descriptor access rights. */
-    base->WORD[number][2] = wordReg;
-
-    wordReg = MPU_WORD_VLD(1);
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-
-    base->WORD[number][3] = wordReg;
-}
-
-void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr)
-{
-    base->WORD[regionNum][0] = startAddr;
-    base->WORD[regionNum][1] = endAddr;
-}
-
-void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
-                                        mpu_region_num_t regionNum,
-                                        mpu_master_t masterNum,
-                                        const mpu_low_masters_access_rights_t *accessRights)
-{
-    assert(accessRights);
-#if FSL_FEATURE_MPU_HAS_MASTER4
-    assert(masterNum < kMPU_Master4);
-#endif
-    uint32_t mask = MPU_WORD_LOW_MASTER_MASK(masterNum);
-    uint32_t right = base->RGDAAC[regionNum];
-
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    mask |= MPU_LOW_MASTER_PE_MASK(masterNum);
-#endif
-
-    /* Build rights control value. */
-    right &= ~mask;
-    right |= MPU_WORD_LOW_MASTER(masterNum,
-                                 ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    right |= MPU_WORD_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-
-    /* Set low master region access rights. */
-    base->RGDAAC[regionNum] = right;
-}
-
-void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
-                                         mpu_region_num_t regionNum,
-                                         mpu_master_t masterNum,
-                                         const mpu_high_masters_access_rights_t *accessRights)
-{
-    assert(accessRights);
-#if FSL_FEATURE_MPU_HAS_MASTER3
-    assert(masterNum > kMPU_Master3);
-#endif
-    uint32_t mask = MPU_WORD_HIGH_MASTER_MASK(masterNum);
-    uint32_t right = base->RGDAAC[regionNum];
-
-    /* Build rights control value. */
-    right &= ~mask;
-    right |= MPU_WORD_HIGH_MASTER((masterNum - (uint8_t)kMPU_RegionNum04),
-                                  (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
-    /* Set low master region access rights. */
-    base->RGDAAC[regionNum] = right;
-}
-
-bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum)
-{
-    uint8_t sperr;
-
-    sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << slaveNum);
-
-    return (sperr != 0) ? true : false;
-}
-
-void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform)
-{
-    assert(errInform);
-
-    uint16_t value;
-
-    /* Error address. */
-    errInform->address = base->SP[slaveNum].EAR;
-
-    /* Error detail information. */
-    value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT;
-    if (!value)
-    {
-        errInform->accessControl = kMPU_NoRegionHit;
-    }
-    else if (!(value & (uint16_t)(value - 1)))
-    {
-        errInform->accessControl = kMPU_NoneOverlappRegion;
-    }
-    else
-    {
-        errInform->accessControl = kMPU_OverlappRegion;
-    }
-
-    value = base->SP[slaveNum].EDR;
-    errInform->master = (mpu_master_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
-    errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
-    errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
-#endif
-
-    /*!< Clears error slave port bit. */
-    value = (base->CESR & ~MPU_CESR_SPERR_MASK) | (0x1U << slaveNum);
-    base->CESR = value;
-}

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,495 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_MPU_H_
-#define _FSL_MPU_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup mpu
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief MPU driver version 2.0.0. */
-#define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief MPU low master bit shift. */
-#define MPU_WORD_LOW_MASTER_SHIFT(n) (n * 6)
-
-/*! @brief MPU low master bit mask. */
-#define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu << MPU_WORD_LOW_MASTER_SHIFT(n))
-
-/*! @brief MPU low master bit width. */
-#define MPU_WORD_LOW_MASTER_WIDTH 5
-
-/*! @brief MPU low master priority setting. */
-#define MPU_WORD_LOW_MASTER(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_WORD_LOW_MASTER_SHIFT(n))) & MPU_WORD_LOW_MASTER_MASK(n))
-
-/*! @brief MPU low master process enable bit shift. */
-#define MPU_LOW_MASTER_PE_SHIFT(n) (n * 6 + 5)
-
-/*! @brief MPU low master process enable bit mask. */
-#define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n))
-
-/*! @brief MPU low master process enable width. */
-#define MPU_WORD_MASTER_PE_WIDTH 1
-
-/*! @brief MPU low master process enable setting. */
-#define MPU_WORD_MASTER_PE(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_LOW_MASTER_PE_SHIFT(n))) & MPU_LOW_MASTER_PE_MASK(n))
-
-/*! @brief MPU high master bit shift. */
-#define MPU_WORD_HIGH_MASTER_SHIFT(n) (n * 2 + 24)
-
-/*! @brief MPU high master bit mask. */
-#define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n))
-
-/*! @brief MPU high master bit width. */
-#define MPU_WORD_HIGH_MASTER_WIDTH 2
-
-/*! @brief MPU high master priority setting. */
-#define MPU_WORD_HIGH_MASTER(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_WORD_HIGH_MASTER_SHIFT(n))) & MPU_WORD_HIGH_MASTER_MASK(n))
-
-/*! @brief MPU region number. */
-typedef enum _mpu_region_num
-{
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U
-    kMPU_RegionNum00 = 0U, /*!< MPU region number 0. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U
-    kMPU_RegionNum01 = 1U, /*!< MPU region number 1. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U
-    kMPU_RegionNum02 = 2U, /*!< MPU region number 2. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U
-    kMPU_RegionNum03 = 3U, /*!< MPU region number 3. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U
-    kMPU_RegionNum04 = 4U, /*!< MPU region number 4. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U
-    kMPU_RegionNum05 = 5U, /*!< MPU region number 5. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U
-    kMPU_RegionNum06 = 6U, /*!< MPU region number 6. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U
-    kMPU_RegionNum07 = 7U, /*!< MPU region number 7. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U
-    kMPU_RegionNum08 = 8U, /*!< MPU region number 8. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U
-    kMPU_RegionNum09 = 9U, /*!< MPU region number 9. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U
-    kMPU_RegionNum10 = 10U, /*!< MPU region number 10. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U
-    kMPU_RegionNum11 = 11U, /*!< MPU region number 11. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U
-    kMPU_RegionNum12 = 12U, /*!< MPU region number 12. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U
-    kMPU_RegionNum13 = 13U, /*!< MPU region number 13. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U
-    kMPU_RegionNum14 = 14U, /*!< MPU region number 14. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U
-    kMPU_RegionNum15 = 15U, /*!< MPU region number 15. */
-#endif
-} mpu_region_num_t;
-
-/*! @brief MPU master number. */
-typedef enum _mpu_master
-{
-#if FSL_FEATURE_MPU_HAS_MASTER0
-    kMPU_Master0 = 0U, /*!< MPU master core. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER1
-    kMPU_Master1 = 1U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER2
-    kMPU_Master2 = 2U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER3
-    kMPU_Master3 = 3U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER4
-    kMPU_Master4 = 4U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER5
-    kMPU_Master5 = 5U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER6
-    kMPU_Master6 = 6U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER7
-    kMPU_Master7 = 7U /*!< MPU master defined in SoC. */
-#endif
-} mpu_master_t;
-
-/*! @brief Describes the number of MPU regions. */
-typedef enum _mpu_region_total_num
-{
-    kMPU_8Regions = 0x0U,  /*!< MPU supports 8 regions.  */
-    kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
-    kMPU_16Regions = 0x2U  /*!< MPU supports 16 regions. */
-} mpu_region_total_num_t;
-
-/*! @brief MPU slave port number. */
-typedef enum _mpu_slave
-{
-    kMPU_Slave0 = 4U, /*!< MPU slave port 0. */
-    kMPU_Slave1 = 3U, /*!< MPU slave port 1. */
-    kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
-    kMPU_Slave3 = 1U, /*!< MPU slave port 3. */
-    kMPU_Slave4 = 0U  /*!< MPU slave port 4. */
-} mpu_slave_t;
-
-/*! @brief MPU error access control detail. */
-typedef enum _mpu_err_access_control
-{
-    kMPU_NoRegionHit = 0U,        /*!< No region hit error. */
-    kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
-    kMPU_OverlappRegion = 2U      /*!< Access overlapping region error. */
-} mpu_err_access_control_t;
-
-/*! @brief MPU error access type. */
-typedef enum _mpu_err_access_type
-{
-    kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read.  */
-    kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
-} mpu_err_access_type_t;
-
-/*! @brief MPU access error attributes.*/
-typedef enum _mpu_err_attributes
-{
-    kMPU_InstructionAccessInUserMode = 0U,       /*!< Access instruction error in user mode. */
-    kMPU_DataAccessInUserMode = 1U,              /*!< Access data error in user mode. */
-    kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
-    kMPU_DataAccessInSupervisorMode = 3U         /*!< Access data error in supervisor mode. */
-} mpu_err_attributes_t;
-
-/*! @brief MPU access rights in supervisor mode for master port 0 ~ port 3. */
-typedef enum _mpu_supervisor_access_rights
-{
-    kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
-    kMPU_SupervisorReadExecute = 1U,      /*!< Read and execute operations are allowed in supervisor mode. */
-    kMPU_SupervisorReadWrite = 2U,        /*!< Read write operations are allowed in supervisor mode. */
-    kMPU_SupervisorEqualToUsermode = 3U   /*!< Access permission equal to user mode. */
-} mpu_supervisor_access_rights_t;
-
-/*! @brief MPU access rights in user mode for master port 0 ~ port 3. */
-typedef enum _mpu_user_access_rights
-{
-    kMPU_UserNoAccessRights = 0U,  /*!< No access allowed in user mode.  */
-    kMPU_UserExecute = 1U,         /*!< Execute operation is allowed in user mode. */
-    kMPU_UserWrite = 2U,           /*!< Write operation is allowed in user mode. */
-    kMPU_UserWriteExecute = 3U,    /*!< Write and execute operations are allowed in user mode. */
-    kMPU_UserRead = 4U,            /*!< Read is allowed in user mode. */
-    kMPU_UserReadExecute = 5U,     /*!< Read and execute operations are allowed in user mode. */
-    kMPU_UserReadWrite = 6U,       /*!< Read and write operations are allowed in user mode. */
-    kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
-} mpu_user_access_rights_t;
-
-/*! @brief MPU hardware basic information. */
-typedef struct _mpu_hardware_info
-{
-    uint8_t hardwareRevisionLevel;         /*!< Specifies the MPU's hardware and definition reversion level. */
-    uint8_t slavePortsNumbers;             /*!< Specifies the number of slave ports connected to MPU. */
-    mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
-} mpu_hardware_info_t;
-
-/*! @brief MPU detail error access information. */
-typedef struct _mpu_access_err_info
-{
-    mpu_master_t master;                    /*!< Access error master. */
-    mpu_err_attributes_t attributes;        /*!< Access error attributes. */
-    mpu_err_access_type_t accessType;       /*!< Access error type. */
-    mpu_err_access_control_t accessControl; /*!< Access error control. */
-    uint32_t address;                       /*!< Access error address. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    uint8_t processorIdentification; /*!< Access error processor identification. */
-#endif                               /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_access_err_info_t;
-
-/*! @brief MPU access rights for low master master port 0 ~ port 3. */
-typedef struct _mpu_low_masters_access_rights
-{
-    mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
-    mpu_user_access_rights_t userAccessRights;        /*!< Master access rights in user mode. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    bool processIdentifierEnable; /*!< Enables or disables process identifier. */
-#endif                            /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_low_masters_access_rights_t;
-
-/*! @brief MPU access rights mode for high master port 4 ~ port 7. */
-typedef struct _mpu_high_masters_access_rights
-{
-    bool writeEnable; /*!< Enables or disables write permission. */
-    bool readEnable;  /*!< Enables or disables read permission.  */
-} mpu_high_masters_access_rights_t;
-
-/*!
- * @brief MPU region configuration structure.
- *
- * This structure is used to configure the regionNum region.
- * The accessRights1[0] ~ accessRights1[3] are used to configure the four low master
- * numbers: master 0 ~ master 3.   The accessRights2[0] ~ accessRights2[3] are
- * used to configure the four high master numbers: master 4 ~ master 7.
- * The master port assignment is the chip configuration. Normally, the core is the
- * master 0, debugger is the master 1.
- * Note: MPU assigns a priority scheme where the debugger is treated as the highest
- * priority master followed by the core and then all the remaining masters.
- * MPU protection does not allow writes from the core to affect the "regionNum 0" start
- * and end address nor the permissions associated with the debugger. It can only write
- * the permission fields associated with the other masters. This protection guarantee
- * the debugger always has access to the entire address space and those rights can't
- * be changed by the core or any other bus master. Prepare
- * the region configuration when regionNum is kMPU_RegionNum00.
- */
-typedef struct _mpu_region_config
-{
-    mpu_region_num_t regionNum; /*!< MPU region number. */
-    uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
-                              start address is 0-modulo-32 byte address.  */
-    uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
-                            address is 31-modulo-32 byte address. */
-    mpu_low_masters_access_rights_t accessRights1[4];  /*!< Low masters access permission.  */
-    mpu_high_masters_access_rights_t accessRights2[4]; /*!< High masters access permission. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
-    uint8_t
-        processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
-#endif                 /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_region_config_t;
-
-/*!
- * @brief The configuration structure for the MPU initialization.
- *
- * This structure is used when calling the MPU_Init function.
- */
-typedef struct _mpu_config
-{
-    mpu_region_config_t regionConfig; /*!< region access permission. */
-    struct _mpu_config *next;         /*!< pointer to the next structure. */
-} mpu_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes the MPU with the user configuration structure.
- *
- * This function configures the MPU module with the user-defined configuration.
- *
- * @param base     MPU peripheral base address.
- * @param config   The pointer to the configuration structure.
- */
-void MPU_Init(MPU_Type *base, const mpu_config_t *config);
-
-/*!
- * @brief Deinitializes the MPU regions.
- *
- * @param base     MPU peripheral base address.
- */
-void MPU_Deinit(MPU_Type *base);
-
-/* @}*/
-
-/*!
- * @name Basic Control Operations
- * @{
- */
-
-/*!
- * @brief Enables/disables the MPU globally.
- *
- * Call this API to enable or disable the MPU module.
- *
- * @param base     MPU peripheral base address.
- * @param enable   True enable MPU, false disable MPU.
- */
-static inline void MPU_Enable(MPU_Type *base, bool enable)
-{
-    if (enable)
-    {
-        /* Enable the MPU globally. */
-        base->CESR |= MPU_CESR_VLD_MASK;
-    }
-    else
-    { /* Disable the MPU globally. */
-        base->CESR &= ~MPU_CESR_VLD_MASK;
-    }
-}
-
-/*!
- * @brief Enables/disables the MPU for a special region.
- *
- * When MPU is enabled, call this API to disable an unused region
- * of an enabled MPU. Call this API to minimize the power dissipation.
- *
- * @param base     MPU peripheral base address.
- * @param number   MPU region number.
- * @param enable   True enable the special region MPU, false disable the special region MPU.
- */
-static inline void MPU_RegionEnable(MPU_Type *base, mpu_region_num_t number, bool enable)
-{
-    if (enable)
-    {
-        /* Enable the #number region MPU. */
-        base->WORD[number][3] |= MPU_WORD_VLD_MASK;
-    }
-    else
-    { /* Disable the #number region MPU. */
-        base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
-    }
-}
-
-/*!
- * @brief Gets the MPU basic hardware information.
- *
- * @param base           MPU peripheral base address.
- * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
- */
-void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
-
-/*!
- * @brief Sets the MPU region.
- *
- * Note: Due to the MPU protection, the kMPU_RegionNum00 does not allow writes from the
- * core to affect the start and end address nor the permissions associated with
- * the debugger. It can only write the permission fields associated
- * with the other masters.
- *
- * @param base          MPU peripheral base address.
- * @param regionConfig  The pointer to the MPU user configuration structure. See "mpu_region_config_t".
- */
-void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
-
-/*!
- * @brief Sets the region start and end address.
- *
- * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
- * The actual start address by MPU is 0-modulo-32 byte address.
- * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
- * The actual end address used by MPU is 31-modulo-32 byte address.
- * Note: Due to the MPU protection, the startAddr and endAddr can't be
- * changed by the core when regionNum is "kMPU_RegionNum00".
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param startAddr     Region start address.
- * @param endAddr       Region end address.
- */
-void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
-
-/*!
- * @brief Sets the MPU region access rights for low master port 0 ~ port 3.
- * This can be used to change the region access rights for any master port for any region.
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param masterNum     MPU master number. Should range from kMPU_Master0 ~ kMPU_Master3.
- * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_low_masters_access_rights_t".
- */
-void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
-                                        mpu_region_num_t regionNum,
-                                        mpu_master_t masterNum,
-                                        const mpu_low_masters_access_rights_t *accessRights);
-
-/*!
- * @brief Sets the MPU region access rights for high master port 4 ~ port 7.
- * This can be used to change the region access rights for any master port for any region.
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param masterNum     MPU master number. Should range from kMPU_Master4 ~ kMPU_Master7.
- * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_high_masters_access_rights_t".
- */
-void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
-                                         mpu_region_num_t regionNum,
-                                         mpu_master_t masterNum,
-                                         const mpu_high_masters_access_rights_t *accessRights);
-
-/*!
- * @brief Gets the numbers of slave ports where errors occur.
- *
- * @param base       MPU peripheral base address.
- * @param slaveNum   MPU slave port number.
- * @return The slave ports error status.
- *         true  - error happens in this slave port.
- *         false - error didn't happen in this slave port.
- */
-bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
-
-/*!
- * @brief Gets the MPU detailed error access information.
- *
- * @param base       MPU peripheral base address.
- * @param slaveNum   MPU slave port number.
- * @param errInform  The pointer to the MPU access error information. See "mpu_access_err_info_t".
- */
-void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_MPU_H_ */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@
  ******************************************************************************/
 /*! @brief Pointers to PDB bases for each instance. */
 static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to PDB clocks for each instance. */
-const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS;
+static const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_PDB_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_pdbBases); instance++)
     {
         if (s_pdbBases[instance] == base)
         {
@@ -64,7 +66,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_PDB_COUNT);
+    assert(instance < ARRAY_SIZE(s_pdbBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     /* PDBx_SC. */
@@ -98,8 +102,10 @@
 {
     PDB_Enable(base, false); /* Disable the PDB module. */
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void PDB_GetDefaultConfig(pdb_config_t *config)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -67,32 +66,32 @@
 enum _pdb_adc_pretrigger_flags
 {
     /* PDB PreTrigger channel match flags. */
-    kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */
-    kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */
-#if (PDB_DLY_COUNT > 2)
-    kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */
-    kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */
-#endif                                                  /* PDB_DLY_COUNT > 2 */
-#if (PDB_DLY_COUNT > 4)
-    kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */
-    kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */
-    kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */
-    kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */
-#endif                                                  /* PDB_DLY_COUNT > 4 */
+    kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-trigger 0 flag. */
+    kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-trigger 1 flag. */
+#if (PDB_DLY_COUNT2 > 2)
+    kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-trigger 2 flag. */
+    kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-trigger 3 flag. */
+#endif                                                  /* PDB_DLY_COUNT2 > 2 */
+#if (PDB_DLY_COUNT2 > 4)
+    kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-trigger 4 flag. */
+    kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-trigger 5 flag. */
+    kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-trigger 6 flag. */
+    kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-trigger 7 flag. */
+#endif                                                  /* PDB_DLY_COUNT2 > 4 */
 
     /* PDB PreTrigger channel error flags. */
-    kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */
-    kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */
-#if (PDB_DLY_COUNT > 2)
-    kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */
-    kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */
-#endif                                                        /* PDB_DLY_COUNT > 2 */
-#if (PDB_DLY_COUNT > 4)
-    kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */
-    kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */
-    kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */
-    kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */
-#endif                                                        /* PDB_DLY_COUNT > 4 */
+    kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-trigger 0 Error. */
+    kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-trigger 1 Error. */
+#if (PDB_DLY_COUNT2 > 2)
+    kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-trigger 2 Error. */
+    kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-trigger 3 Error. */
+#endif                                                        /* PDB_DLY_COUNT2 > 2 */
+#if (PDB_DLY_COUNT2 > 4)
+    kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-trigger 4 Error. */
+    kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-trigger 5 Error. */
+    kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-trigger 6 Error. */
+    kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-trigger 7 Error. */
+#endif                                                        /* PDB_DLY_COUNT2 > 4 */
 };
 
 /*!
@@ -108,7 +107,7 @@
  * @brief PDB load value mode.
  *
  * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]).
- * These values are for:
+ * These values are for the following operations.
  *  - PDB counter (PDBx_MOD, PDBx_IDLY)
  *  - ADC trigger (PDBx_CHnDLYm)
  *  - DAC trigger (PDBx_DACINTx)
@@ -158,7 +157,7 @@
  * @brief Trigger input source
  *
  * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or
- * the software trigger. Refer to chip configuration details for the actual PDB input trigger connections.
+ * the software trigger. See chip configuration details for the actual PDB input trigger connections.
  */
 typedef enum _pdb_trigger_input_source
 {
@@ -177,7 +176,7 @@
     kPDB_TriggerInput12 = 12U,  /*!< Trigger-In 12. */
     kPDB_TriggerInput13 = 13U,  /*!< Trigger-In 13. */
     kPDB_TriggerInput14 = 14U,  /*!< Trigger-In 14. */
-    kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15. */
+    kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */
 } pdb_trigger_input_source_t;
 
 /*!
@@ -193,15 +192,15 @@
 } pdb_config_t;
 
 /*!
- * @brief PDB ADC Pre-Trigger configuration.
+ * @brief PDB ADC Pre-trigger configuration.
  */
 typedef struct _pdb_adc_pretrigger_config
 {
-    uint32_t enablePreTriggerMask;          /*!< PDB Channel Pre-Trigger Enable. */
-    uint32_t enableOutputMask;              /*!< PDB Channel Pre-Trigger Output Select.
+    uint32_t enablePreTriggerMask;          /*!< PDB Channel Pre-trigger Enable. */
+    uint32_t enableOutputMask;              /*!< PDB Channel Pre-trigger Output Select.
                                                  PDB channel's corresponding pre-trigger asserts when the counter
                                                  reaches the channel delay register. */
-    uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable.
+    uint32_t enableBackToBackOperationMask; /*!< PDB Channel pre-trigger Back-to-Back Operation Enable.
                                                  Back-to-back operation enables the ADC conversions complete to trigger
                                                  the next PDB channel pre-trigger and trigger output, so that the ADC
                                                  conversions can be triggered on next set of configuration and results
@@ -230,29 +229,29 @@
  */
 
 /*!
- * @brief Initializes  the PDB module.
+ * @brief Initializes the PDB module.
  *
- * This function is to make the initialization for PDB module. The operations includes are:
+ * This function initializes the PDB module. The operations included are as follows.
  *  - Enable the clock for PDB instance.
  *  - Configure the PDB module.
  *  - Enable the PDB module.
  *
  * @param base PDB peripheral base address.
- * @param config Pointer to configuration structure. See "pdb_config_t".
+ * @param config Pointer to the configuration structure. See "pdb_config_t".
  */
 void PDB_Init(PDB_Type *base, const pdb_config_t *config);
 
 /*!
- * @brief De-initializes  the PDB module.
+ * @brief De-initializes the PDB module.
  *
  * @param base PDB peripheral base address.
  */
 void PDB_Deinit(PDB_Type *base);
 
 /*!
- * @brief Initializes the PDB user configure structure.
+ * @brief Initializes the PDB user configuration structure.
  *
- * This function initializes the user configure structure to default value. the default value are:
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
  * @code
  *   config->loadValueMode = kPDB_LoadValueImmediately;
  *   config->prescalerDivider = kPDB_PrescalerDivider1;
@@ -302,7 +301,7 @@
 /*!
  * @brief Loads the counter values.
  *
- * This function is to load the counter values from their internal buffer.
+ * This function loads the counter values from the internal buffer.
  * See "pdb_load_value_mode_t" about PDB's load mode.
  *
  * @param base PDB peripheral base address.
@@ -382,7 +381,7 @@
 }
 
 /*!
- * @brief  Specifies the period of the counter.
+ * @brief  Specifies the counter period.
  *
  * @param  base  PDB peripheral base address.
  * @param  value Setting value for the modulus. 16-bit is available.
@@ -405,7 +404,7 @@
 }
 
 /*!
- * @brief Sets the value for PDB counter delay event.
+ * @brief Sets the value for the PDB counter delay event.
  *
  * @param base  PDB peripheral base address.
  * @param value Setting value for PDB counter delay event. 16-bit is available.
@@ -417,16 +416,16 @@
 /* @} */
 
 /*!
- * @name ADC Pre-Trigger
+ * @name ADC Pre-trigger
  * @{
  */
 
 /*!
- * @brief Configures the ADC PreTrigger in PDB module.
+ * @brief Configures the ADC pre-trigger in the PDB module.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for ADC instance.
- * @param config  Pointer to configuration structure. See "pdb_adc_pretrigger_config_t".
+ * @param config  Pointer to the configuration structure. See "pdb_adc_pretrigger_config_t".
  */
 static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config)
 {
@@ -434,30 +433,31 @@
     assert(NULL != config);
 
     base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) |
-                           PDB_C1_EN(config->enableOutputMask);
+                           PDB_C1_EN(config->enablePreTriggerMask);
 }
 
 /*!
- * @brief Sets the value for ADC Pre-Trigger delay event.
+ * @brief Sets the value for the ADC pre-trigger delay event.
  *
- * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's
- * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here.
+ * This function sets the value for ADC pre-trigger delay event. It specifies the delay value for the channel's
+ * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the set value.
  *
  * @param base       PDB peripheral base address.
  * @param channel    Channel index for ADC instance.
  * @param preChannel Channel group index for ADC instance.
- * @param value      Setting value for ADC Pre-Trigger delay event. 16-bit is available.
+ * @param value      Setting value for ADC pre-trigger delay event. 16-bit is available.
  */
 static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value)
 {
     assert(channel < PDB_C1_COUNT);
-    assert(preChannel < PDB_DLY_COUNT);
+    assert(preChannel < PDB_DLY_COUNT2);
+    /* xx_COUNT2 is actually the count for pre-triggers in header file. xx_COUNT is used for the count of channels. */
 
     base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value);
 }
 
 /*!
- * @brief  Gets the ADC Pre-Trigger's status flags.
+ * @brief  Gets the ADC pre-trigger's status flags.
  *
  * @param  base    PDB peripheral base address.
  * @param  channel Channel index for ADC instance.
@@ -472,7 +472,7 @@
 }
 
 /*!
- * @brief Clears the ADC Pre-Trigger's status flags.
+ * @brief Clears the ADC pre-trigger status flags.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for ADC instance.
@@ -494,19 +494,19 @@
  */
 
 /*!
- * @brief Configures the DAC trigger in PDB module.
+ * @brief Configures the DAC trigger in the PDB module.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for DAC instance.
- * @param config  Pointer to configuration structure. See "pdb_dac_trigger_config_t".
+ * @param config  Pointer to the configuration structure. See "pdb_dac_trigger_config_t".
  */
 void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config);
 
 /*!
  * @brief Sets the value for the DAC interval event.
  *
- * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update
- * buffer when the DAC interval counter is equal to the setting value here.
+ * This fucntion sets the value for DAC interval event. DAC interval trigger triggers the DAC module to update
+ * the buffer when the DAC interval counter is equal to the set value.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for DAC instance.
@@ -532,7 +532,7 @@
  *
  * @param base        PDB peripheral base address.
  * @param channelMask Channel mask value for multiple pulse out trigger channel.
- * @param enable Enable the feature or not.
+ * @param enable Whether the feature is enabled or not.
  */
 static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable)
 {
@@ -547,11 +547,11 @@
 }
 
 /*!
- * @brief Sets event values for pulse out trigger.
+ * @brief Sets event values for the pulse out trigger.
  *
- * This function is used to set event values for pulse output trigger.
- * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB
- * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the
+ * This function is used to set event values for the pulse output trigger.
+ * These pulse output trigger delay values specify the delay for the PDB Pulse-out. Pulse-out goes high when the PDB
+ * counter is equal to the pulse output high value (value1). Pulse-out goes low when the PDB counter is equal to the
  * pulse output low value (value2).
  *
  * @param base    PDB peripheral base address.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,8 +48,10 @@
 /*! @brief Pointers to PIT bases for each instance. */
 static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to PIT clocks for each instance. */
 static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -59,7 +61,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
     {
         if (s_pitBases[instance] == base)
         {
@@ -67,7 +69,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_PIT_COUNT);
+    assert(instance < ARRAY_SIZE(s_pitBases));
 
     return instance;
 }
@@ -76,8 +78,10 @@
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the PIT clock*/
     CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Enable PIT timers */
     base->MCR &= ~PIT_MCR_MDIS_MASK;
@@ -98,8 +102,10 @@
     /* Disable PIT timers */
     base->MCR |= PIT_MCR_MDIS_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the PIT clock*/
     CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup pit_driver
+ * @addtogroup pit
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -73,13 +72,13 @@
 } pit_status_flags_t;
 
 /*!
- * @brief PIT config structure
+ * @brief PIT configuration structure
  *
  * This structure holds the configuration settings for the PIT peripheral. To initialize this
  * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a
  * pointer to your config structure instance.
  *
- * The config struct can be made const so it resides in flash
+ * The configuration structure can be made constant so it resides in flash.
  */
 typedef struct _pit_config
 {
@@ -100,30 +99,30 @@
  */
 
 /*!
- * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation.
+ * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
  *
  * @note This API should be called at the beginning of the application using the PIT driver.
  *
  * @param base   PIT peripheral base address
- * @param config Pointer to user's PIT config structure
+ * @param config Pointer to the user's PIT config structure
  */
 void PIT_Init(PIT_Type *base, const pit_config_t *config);
 
 /*!
- * @brief Gate the PIT clock and disable the PIT module
+ * @brief Gates the PIT clock and disables the PIT module.
  *
  * @param base PIT peripheral base address
  */
 void PIT_Deinit(PIT_Type *base);
 
 /*!
- * @brief Fill in the PIT config struct with the default settings
+ * @brief Fills in the PIT configuration structure with the default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *     config->enableRunInDebug = false;
  * @endcode
- * @param config Pointer to user's PIT config structure.
+ * @param config Pointer to the onfiguration structure.
  */
 static inline void PIT_GetDefaultConfig(pit_config_t *config)
 {
@@ -140,9 +139,9 @@
  *
  * When a timer has a chain mode enabled, it only counts after the previous
  * timer has expired. If the timer n-1 has counted down to 0, counter n
- * decrements the value by one. Each timer is 32-bits, this allows the developers
+ * decrements the value by one. Each timer is 32-bits, which allows the developers
  * to chain timers together and form a longer timer (64-bits and larger). The first timer
- * (timer 0) cannot be chained to any other timer.
+ * (timer 0) can't be chained to any other timer.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number which is chained with the previous timer
@@ -219,7 +218,7 @@
  */
 
 /*!
- * @brief Gets the PIT status flags
+ * @brief Gets the PIT status flags.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number
@@ -256,11 +255,11 @@
  * @brief Sets the timer period in units of count.
  *
  * Timers begin counting from the value set by this function until it reaches 0,
- * then it will generate an interrupt and load this regiter value again.
- * Writing a new value to this register will not restart the timer; instead the value
- * will be loaded after the timer expires.
+ * then it generates an interrupt and load this register value again.
+ * Writing a new value to this register does not restart the timer. Instead, the value
+ * is loaded after the timer expires.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number
@@ -277,7 +276,7 @@
  * This function returns the real-time timer counting value, in a range from 0 to a
  * timer period.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup pmc */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -49,36 +48,36 @@
 
 #if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
 /*!
- * @brief Low-Voltage Detect Voltage Select
+ * @brief Low-voltage Detect Voltage Select
  */
 typedef enum _pmc_low_volt_detect_volt_select
 {
-    kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/
-    kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/
+    kPMC_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/
+    kPMC_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/
 } pmc_low_volt_detect_volt_select_t;
 #endif
 
 #if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
 /*!
- * @brief Low-Voltage Warning Voltage Select
+ * @brief Low-voltage Warning Voltage Select
  */
 typedef enum _pmc_low_volt_warning_volt_select
 {
-    kPMC_LowVoltWarningLowTrip = 0U,  /*!< Low trip point selected (VLVW = VLVW1)*/
+    kPMC_LowVoltWarningLowTrip = 0U,  /*!< Low-trip point selected (VLVW = VLVW1)*/
     kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
     kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
-    kPMC_LowVoltWarningHighTrip = 3U  /*!< High trip point selected (VLVW = VLVW4)*/
+    kPMC_LowVoltWarningHighTrip = 3U  /*!< High-trip point selected (VLVW = VLVW4)*/
 } pmc_low_volt_warning_volt_select_t;
 #endif
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief High-Voltage Detect Voltage Select
+ * @brief High-voltage Detect Voltage Select
  */
 typedef enum _pmc_high_volt_detect_volt_select
 {
-    kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/
-    kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/
+    kPMC_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/
+    kPMC_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/
 } pmc_high_volt_detect_volt_select_t;
 #endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
 
@@ -88,8 +87,8 @@
  */
 typedef enum _pmc_bandgap_buffer_drive_select
 {
-    kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive.  */
-    kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */
+    kPMC_BandgapBufferDriveLow = 0U, /*!< Low-drive.  */
+    kPMC_BandgapBufferDriveHigh = 1U /*!< High-drive. */
 } pmc_bandgap_buffer_drive_select_t;
 #endif /* FSL_FEATURE_PMC_HAS_BGBDS */
 
@@ -126,37 +125,37 @@
 #endif /* FSL_FEATURE_PMC_HAS_PARAM */
 
 /*!
- * @brief Low-Voltage Detect Configuration Structure
+ * @brief Low-voltage Detect Configuration Structure
  */
 typedef struct _pmc_low_volt_detect_config
 {
-    bool enableInt;   /*!< Enable interrupt when low voltage detect*/
-    bool enableReset; /*!< Enable system reset when low voltage detect*/
+    bool enableInt;   /*!< Enable interrupt when Low-voltage detect*/
+    bool enableReset; /*!< Enable system reset when Low-voltage detect*/
 #if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
-    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low voltage detect trip point voltage selection*/
+    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/
 #endif
 } pmc_low_volt_detect_config_t;
 
 /*!
- * @brief Low-Voltage Warning Configuration Structure
+ * @brief Low-voltage Warning Configuration Structure
  */
 typedef struct _pmc_low_volt_warning_config
 {
-    bool enableInt; /*!< Enable interrupt when low voltage warning*/
+    bool enableInt; /*!< Enable interrupt when low-voltage warning*/
 #if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
-    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low voltage warning trip point voltage selection*/
+    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/
 #endif
 } pmc_low_volt_warning_config_t;
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief High-Voltage Detect Configuration Structure
+ * @brief High-voltage Detect Configuration Structure
  */
 typedef struct _pmc_high_volt_detect_config
 {
-    bool enableInt;                                /*!< Enable interrupt when high voltage detect*/
-    bool enableReset;                              /*!< Enable system reset when high voltage detect*/
-    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High voltage detect trip point voltage selection*/
+    bool enableInt;                                /*!< Enable interrupt when high-voltage detect*/
+    bool enableReset;                              /*!< Enable system reset when high-voltage detect*/
+    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/
 } pmc_high_volt_detect_config_t;
 #endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
 
@@ -172,7 +171,7 @@
     bool enable; /*!< Enable bandgap buffer.                   */
 #endif
 #if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
-    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low power mode. */
+    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */
 #endif                         /* FSL_FEATURE_PMC_HAS_BGEN */
 #if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
     pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select.             */
@@ -196,7 +195,7 @@
  * @brief Gets the PMC version ID.
  *
  * This function gets the PMC version ID, including major version number,
- * minor version number and feature specification number.
+ * minor version number, and a feature specification number.
  *
  * @param base PMC peripheral base address.
  * @param versionId     Pointer to version ID structure.
@@ -211,7 +210,7 @@
 /*!
  * @brief Gets the PMC parameter.
  *
- * This function gets the PMC parameter, including VLPO enable and HVD enable.
+ * This function gets the PMC parameter including the VLPO enable and the HVD enable.
  *
  * @param base PMC peripheral base address.
  * @param param         Pointer to PMC param structure.
@@ -220,26 +219,25 @@
 #endif
 
 /*!
- * @brief Configure the low voltage detect setting.
+ * @brief Configures the low-voltage detect setting.
  *
- * This function configures the low voltage detect setting, including the trip
- * point voltage setting, enable interrupt or not, enable system reset or not.
+ * This function configures the low-voltage detect setting, including the trip
+ * point voltage setting, enables or disables the interrupt, enables or disables the system reset.
  *
  * @param base PMC peripheral base address.
- * @param config  Low-Voltage detect configuration structure.
+ * @param config  Low-voltage detect configuration structure.
  */
 void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config);
 
 /*!
- * @brief Get Low-Voltage Detect Flag status
+ * @brief Gets the Low-voltage Detect Flag status.
  *
- * This function  reads the current LVDF status. If it returns 1, a low
- * voltage event is detected.
+ * This function  reads the current LVDF status. If it returns 1, a low-voltage event is detected.
  *
  * @param base PMC peripheral base address.
- * @return Current low voltage detect flag
- *                - true: Low-Voltage detected
- *                - false: Low-Voltage not detected
+ * @return Current low-voltage detect flag
+ *                - true: Low-voltage detected
+ *                - false: Low-voltage not detected
  */
 static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base)
 {
@@ -247,9 +245,9 @@
 }
 
 /*!
- * @brief Acknowledge to clear the Low-Voltage Detect flag
+ * @brief Acknowledges clearing the Low-voltage Detect flag.
  *
- * This function acknowledges the low voltage detection errors (write 1 to
+ * This function acknowledges the low-voltage detection errors (write 1 to
  * clear LVDF).
  *
  * @param base PMC peripheral base address.
@@ -260,18 +258,18 @@
 }
 
 /*!
- * @brief Configure the low voltage warning setting.
+ * @brief Configures the low-voltage warning setting.
  *
- * This function configures the low voltage warning setting, including the trip
- * point voltage setting and enable interrupt or not.
+ * This function configures the low-voltage warning setting, including the trip
+ * point voltage setting and enabling or disabling the interrupt.
  *
  * @param base PMC peripheral base address.
- * @param config  Low-Voltage warning configuration structure.
+ * @param config  Low-voltage warning configuration structure.
  */
 void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config);
 
 /*!
- * @brief Get Low-Voltage Warning Flag status
+ * @brief Gets the Low-voltage Warning Flag status.
  *
  * This function polls the current LVWF status. When 1 is returned, it
  * indicates a low-voltage warning event. LVWF is set when V Supply transitions
@@ -279,8 +277,8 @@
  *
  * @param base PMC peripheral base address.
  * @return Current LVWF status
- *                  - true: Low-Voltage Warning Flag is set.
- *                  - false: the  Low-Voltage Warning does not happen.
+ *                  - true: Low-voltage Warning Flag is set.
+ *                  - false: the  Low-voltage Warning does not happen.
  */
 static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base)
 {
@@ -288,7 +286,7 @@
 }
 
 /*!
- * @brief Acknowledge to Low-Voltage Warning flag
+ * @brief Acknowledges the Low-voltage Warning flag.
  *
  * This function acknowledges the low voltage warning errors (write 1 to
  * clear LVWF).
@@ -302,26 +300,26 @@
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief Configure the high voltage detect setting.
+ * @brief Configures the high-voltage detect setting.
  *
- * This function configures the high voltage detect setting, including the trip
- * point voltage setting, enable interrupt or not, enable system reset or not.
+ * This function configures the high-voltage detect setting, including the trip
+ * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset.
  *
  * @param base PMC peripheral base address.
- * @param config  High-Voltage detect configuration structure.
+ * @param config  High-voltage detect configuration structure.
  */
 void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config);
 
 /*!
- * @brief Get High-Voltage Detect Flag status
+ * @brief Gets the High-voltage Detect Flag status.
  *
  * This function  reads the current HVDF status. If it returns 1, a low
  * voltage event is detected.
  *
  * @param base PMC peripheral base address.
- * @return Current high voltage detect flag
- *                - true: High-Voltage detected
- *                - false: High-Voltage not detected
+ * @return Current high-voltage detect flag
+ *                - true: High-voltage detected
+ *                - false: High-voltage not detected
  */
 static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base)
 {
@@ -329,9 +327,9 @@
 }
 
 /*!
- * @brief Acknowledge to clear the High-Voltage Detect flag
+ * @brief Acknowledges clearing the High-voltage Detect flag.
  *
- * This function acknowledges the high voltage detection errors (write 1 to
+ * This function acknowledges the high-voltage detection errors (write 1 to
  * clear HVDF).
  *
  * @param base PMC peripheral base address.
@@ -346,10 +344,10 @@
      (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
      (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
 /*!
- * @brief Configure the PMC bandgap
+ * @brief Configures the PMC bandgap.
  *
  * This function configures the PMC bandgap, including the drive select and
- * behavior in low power mode.
+ * behavior in low-power mode.
  *
  * @param base PMC peripheral base address.
  * @param config Pointer to the configuration structure
@@ -378,7 +376,7 @@
 }
 
 /*!
- * @brief Acknowledge to Peripherals and I/O pads isolation flag.
+ * @brief Acknowledges the isolation flag to Peripherals and I/O pads.
  *
  * This function  clears the ACK Isolation flag. Writing one to this setting
  * when it is set releases the I/O pads and certain peripherals to their normal
@@ -394,9 +392,9 @@
 
 #if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS)
 /*!
- * @brief Gets the Regulator regulation status.
+ * @brief Gets the regulator regulation status.
  *
- * This function  returns the regulator to a run regulation status. It provides
+ * This function  returns the regulator to run a regulation status. It provides
  * the current status of the internal voltage regulator.
  *
  * @param base PMC peripheral base address.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -33,59 +33,65 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup port_driver
+ * @addtogroup port
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! Version 2.0.1. */
-#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! Version 2.0.2. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
 /*! @brief Internal resistor pull feature selection */
 enum _port_pull
 {
-    kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
-    kPORT_PullDown = 2U,    /*!< internal pull-down resistor is enabled. */
-    kPORT_PullUp = 3U,      /*!< internal pull-up resistor is enabled. */
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< Internal pull-up resistor is enabled. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
 
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
 /*! @brief Slew rate selection */
 enum _port_slew_rate
 {
-    kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
-    kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
 
 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-/*! @brief Internal resistor pull feature enable/disable */
+/*! @brief Open Drain feature enable/disable */
 enum _port_open_drain_enable
 {
-    kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
-    kPORT_OpenDrainEnable = 1U,  /*!< internal pull-up resistor is enabled. */
+    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< Open drain output is enabled. */
 };
 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
 
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
 /*! @brief Passive filter feature enable/disable */
 enum _port_passive_filter_enable
 {
-    kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
-    kPORT_PassiveFilterEnable = 1U,  /*!< slow slew rate is configured. */
+    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< Passive input filter is enabled. */
 };
+#endif
 
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
 /*! @brief Configures the drive strength. */
 enum _port_drive_strength
 {
-    kPORT_LowDriveStrength = 0U,  /*!< low drive strength is configured. */
-    kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
+    kPORT_LowDriveStrength = 0U,  /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
 
 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
 /*! @brief Unlock/lock the pin control register field[15:0] */
@@ -96,18 +102,28 @@
 };
 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
 
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @brief Pin mux selection */
 typedef enum _port_mux
 {
-    kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */
-    kPORT_MuxAsGpio = 1U,           /*!< corresponding pin is configured as GPIO. */
-    kPORT_MuxAlt2 = 2U,             /*!< chip-specific */
-    kPORT_MuxAlt3 = 3U,             /*!< chip-specific */
-    kPORT_MuxAlt4 = 4U,             /*!< chip-specific */
-    kPORT_MuxAlt5 = 5U,             /*!< chip-specific */
-    kPORT_MuxAlt6 = 6U,             /*!< chip-specific */
-    kPORT_MuxAlt7 = 7U,             /*!< chip-specific */
+    kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio = 1U,           /*!< Corresponding pin is configured as GPIO. */
+    kPORT_MuxAlt2 = 2U,             /*!< Chip-specific */
+    kPORT_MuxAlt3 = 3U,             /*!< Chip-specific */
+    kPORT_MuxAlt4 = 4U,             /*!< Chip-specific */
+    kPORT_MuxAlt5 = 5U,             /*!< Chip-specific */
+    kPORT_MuxAlt6 = 6U,             /*!< Chip-specific */
+    kPORT_MuxAlt7 = 7U,             /*!< Chip-specific */
+    kPORT_MuxAlt8 = 8U,             /*!< Chip-specific */
+    kPORT_MuxAlt9 = 9U,             /*!< Chip-specific */
+    kPORT_MuxAlt10 = 10U,           /*!< Chip-specific */
+    kPORT_MuxAlt11 = 11U,           /*!< Chip-specific */
+    kPORT_MuxAlt12 = 12U,           /*!< Chip-specific */
+    kPORT_MuxAlt13 = 13U,           /*!< Chip-specific */
+    kPORT_MuxAlt14 = 14U,           /*!< Chip-specific */
+    kPORT_MuxAlt15 = 15U,           /*!< Chip-specific */
 } port_mux_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 /*! @brief Configures the interrupt generation condition. */
 typedef enum _port_interrupt
@@ -129,8 +145,8 @@
     kPORT_InterruptEitherEdge = 0xBU,  /*!< Interrupt on either edge. */
     kPORT_InterruptLogicOne = 0xCU,    /*!< Interrupt when logic one. */
 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
-    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
-    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low trigger output. */
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low-trigger output. */
 #endif
 } port_interrupt_t;
 
@@ -150,44 +166,76 @@
 } port_digital_filter_config_t;
 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
 
-/*! @brief PORT pin config structure */
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief PORT pin configuration structure */
 typedef struct _port_pin_config
 {
-    uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
-    uint16_t slewRate : 1;   /*!< fast/slow slew rate Configure */
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+#else
+    uint16_t : 2;
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
+#else
     uint16_t : 1;
-    uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
-#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-    uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
 #else
     uint16_t : 1;
-#endif                          /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
-    uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
+#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
+#else
     uint16_t : 1;
-    uint16_t mux : 3; /*!< pin mux Configure */
+#endif
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+    uint16_t mux : 3; /*!< Pin mux Configure */
+#else
+    uint16_t : 3;
+#endif
+
     uint16_t : 4;
+
 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
-    uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
 #else
     uint16_t : 1;
 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
 } port_pin_config_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 /*******************************************************************************
- * API
- ******************************************************************************/
+* API
+******************************************************************************/
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @name Configuration */
 /*@{*/
 
 /*!
  * @brief Sets the port PCR register.
  *
- * This is an example to define an input pin or output pin PCR configuration:
+ * This is an example to define an input pin or output pin PCR configuration.
  * @code
  * // Define a digital input pin PCR configuration
  * port_pin_config_t config = {
@@ -203,7 +251,7 @@
  *
  * @param base   PORT peripheral base pointer.
  * @param pin    PORT pin number.
- * @param config PORT PCR register configure structure.
+ * @param config PORT PCR register configuration structure.
  */
 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
 {
@@ -215,7 +263,7 @@
 /*!
  * @brief Sets the port PCR register for multiple pins.
  *
- * This is an example to define input pins or output pins PCR configuration:
+ * This is an example to define input pins or output pins PCR configuration.
  * @code
  * // Define a digital input pin PCR configuration
  * port_pin_config_t config = {
@@ -231,8 +279,8 @@
  * @endcode
  *
  * @param base   PORT peripheral base pointer.
- * @param mask   PORT pins' numbers macro.
- * @param config PORT PCR register configure structure.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
  */
 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
 {
@@ -265,15 +313,16 @@
  *        - #kPORT_MuxAlt6            : chip-specific.
  *        - #kPORT_MuxAlt7            : chip-specific.
  * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
- *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will
- *         be reset to zero : kPORT_PinDisabledOrAnalog).
- *         This function is recommended to use in the case you just need to reset the pin mux
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
  *
  */
 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
 {
     base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
 }
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
 
@@ -281,7 +330,7 @@
  * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
  *
  * @param base  PORT peripheral base pointer.
- * @param mask  PORT pins' numbers macro.
+ * @param mask  PORT pin number macro.
  */
 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
 {
@@ -334,8 +383,8 @@
  *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
  *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
  *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
- *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit).
- *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low trigger output(if the trigger states exit).
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
  */
 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
 {
@@ -351,9 +400,9 @@
  * If configured for a level sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param  base PORT peripheral base pointer.
+ * @param base PORT peripheral base pointer.
  * @return Current port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
+ *         pin 0 and 16 have the interrupt.
  */
 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
 {
@@ -361,10 +410,10 @@
 }
 
 /*!
- * @brief Clears the multiple pins' interrupt status flag.
+ * @brief Clears the multiple pin interrupt status flag.
  *
  * @param base PORT peripheral base pointer.
- * @param mask PORT pins' numbers macro.
+ * @param mask PORT pin number macro.
  */
 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
 {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -32,6 +32,8 @@
 
 void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config)
 {
+    assert(config);
+
 #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
     uint32_t reg;
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup rcm */
 /*! @{*/
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -43,8 +42,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief RCM driver version 2.0.0. */
-#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief RCM driver version 2.0.1. */
+#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -57,7 +56,7 @@
 #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
     kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
 #endif
-    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */
+    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */
 #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
     kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
 #endif                                 /* FSL_FEATURE_RCM_HAS_LOC */
@@ -85,7 +84,7 @@
 #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
     kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
 #endif
-    kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */
+    kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */
 #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
     kRCM_SourceLoc = RCM_SRS0_LOC_MASK,   /*!< Loss of clock reset */
 #endif /* FSL_FEATURE_RCM_HAS_LOC */
@@ -99,7 +98,7 @@
     kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U,     /*!< JTAG generated reset */
 #endif /* FSL_FEATURE_RCM_HAS_JTAG */
     kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */
-    kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */
+    kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */
 #if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
     kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U,    /*!< MDM-AP system reset */
 #endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
@@ -112,7 +111,7 @@
 } rcm_reset_source_t;
 
 /*!
- * @brief Reset pin filter select in Run and Wait modes
+ * @brief Reset pin filter select in Run and Wait modes.
  */
 typedef enum _rcm_run_wait_filter_mode
 {
@@ -136,7 +135,7 @@
 
 #if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
 /*!
- * @brief Max delay time from interrupt asserts to system reset.
+ * @brief Maximum delay time from interrupt asserts to system reset.
  */
 typedef enum _rcm_reset_delay
 {
@@ -187,7 +186,7 @@
 #endif
 
 /*!
- * @brief Reset pin filter configuration
+ * @brief Reset pin filter configuration.
  */
 typedef struct _rcm_reset_pin_filter_config
 {
@@ -214,7 +213,7 @@
  * the minor version number, and the feature specification number.
  *
  * @param base RCM peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     Pointer to the version ID structure.
  */
 static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
 {
@@ -229,7 +228,7 @@
  * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
  * Use source masks defined in the rcm_reset_source_t to get the desired source status.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t status;
 
@@ -252,7 +251,7 @@
  * This function gets the current reset source status. Use source masks
  * defined in the rcm_reset_source_t to get the desired source status.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t resetStatus;
 
@@ -283,9 +282,9 @@
  * @brief Gets the sticky reset source status.
  *
  * This function gets the current reset source status that has not been cleared
- * by software for some specific source.
+ * by software for a specific source.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t resetStatus;
 
@@ -316,7 +315,7 @@
  *
  * This function clears the sticky system reset flags indicated by source masks.
  *
- * Example:
+ * This is an example.
    @code
    // Clears multiple reset sources.
    RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
@@ -403,7 +402,7 @@
 /*!
  * @brief Sets the system reset interrupt configuration.
  *
- * For graceful shutdown, the RCM supports delaying the assertion of the system
+ * For a graceful shut down, the RCM supports delaying the assertion of the system
  * reset for a period of time when the reset interrupt is generated. This function
  * can be used to enable the interrupt and the delay period. The interrupts
  * are passed in as bit mask. See rcm_int_t for details. For example, to

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -181,10 +181,14 @@
 
 void RNGA_Init(RNG_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock gate. */
     CLOCK_EnableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset the registers for RNGA module to reset state. */
     RNG_WR_CR(base, 0);
@@ -194,8 +198,10 @@
 
 void RNGA_Deinit(RNG_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock for RNGA module.*/
     CLOCK_DisableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,11 +34,10 @@
 
 #if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
 /*!
- * @addtogroup rnga_driver
+ * @addtogroup rnga
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -74,6 +74,8 @@
  ******************************************************************************/
 static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
     /* Table of days in a month for a non leap year. First entry in the table is not used,
      * valid months start from 1
      */
@@ -88,13 +90,13 @@
     }
 
     /* Adjust the days in February for a leap year */
-    if (!(datetime->year & 3U))
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
     {
         daysPerMonth[2] = 29U;
     }
 
     /* Check the validity of the day */
-    if (datetime->day > daysPerMonth[datetime->month])
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
     {
         return false;
     }
@@ -104,6 +106,9 @@
 
 static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
     /* Number of days from begin of the non Leap-year*/
     uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
     uint32_t seconds;
@@ -131,6 +136,8 @@
 
 static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
     uint32_t x;
     uint32_t secondsRemaining, days;
     uint16_t daysInYear;
@@ -204,7 +211,9 @@
 
     uint32_t reg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Issue a software reset if timer is invalid */
     if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag)
@@ -216,7 +225,7 @@
     /* Setup the update mode and supervisor access mode */
     reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK);
     reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess);
-#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION
     /* Setup the wakeup pin select */
     reg &= ~(RTC_CR_WPS_MASK);
     reg |= RTC_CR_WPS(config->wakeupSelect);
@@ -340,6 +349,8 @@
 
 void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter)
 {
+    assert(counter);
+
     *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR));
 }
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup rtc_driver
+ * @addtogroup rtc
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -65,15 +64,19 @@
     kRTC_AlarmFlag = RTC_SR_TAF_MASK         /*!< Alarm flag*/
 } rtc_status_flags_t;
 
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
 /*! @brief List of RTC Oscillator capacitor load settings */
 typedef enum _rtc_osc_cap_load
 {
-    kRTC_Capacitor_2p = RTC_CR_SC2P_MASK,  /*!< 2pF capacitor load */
-    kRTC_Capacitor_4p = RTC_CR_SC4P_MASK,  /*!< 4pF capacitor load */
-    kRTC_Capacitor_8p = RTC_CR_SC8P_MASK,  /*!< 8pF capacitor load */
-    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */
+    kRTC_Capacitor_2p = RTC_CR_SC2P_MASK,  /*!< 2 pF capacitor load */
+    kRTC_Capacitor_4p = RTC_CR_SC4P_MASK,  /*!< 4 pF capacitor load */
+    kRTC_Capacitor_8p = RTC_CR_SC8P_MASK,  /*!< 8 pF capacitor load */
+    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */
 } rtc_osc_cap_load_t;
 
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
 /*! @brief Structure is used to hold the date and time */
 typedef struct _rtc_datetime
 {
@@ -96,7 +99,7 @@
  */
 typedef struct _rtc_config
 {
-    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32KHz clock;
+    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32 KHz clock;
                                         false:Wakeup pin used to wakeup the chip  */
     bool updateMode;               /*!< true: Registers can be written even when locked under certain
                                         conditions, false: No writes allowed when registers are locked */
@@ -122,17 +125,17 @@
 /*!
  * @brief Ungates the RTC clock and configures the peripheral for basic operation.
  *
- * This function will issue a software reset if the timer invalid flag is set.
+ * This function issues a software reset if the timer invalid flag is set.
  *
  * @note This API should be called at the beginning of the application using the RTC driver.
  *
  * @param base   RTC peripheral base address
- * @param config Pointer to user's RTC config structure.
+ * @param config Pointer to the user's RTC configuration structure.
  */
 void RTC_Init(RTC_Type *base, const rtc_config_t *config);
 
 /*!
- * @brief Stop the timer and gate the RTC clock
+ * @brief Stops the timer and gate the RTC clock.
  *
  * @param base RTC peripheral base address
  */
@@ -141,14 +144,16 @@
     /* Stop the RTC timer */
     base->SR &= ~RTC_SR_TCE_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the module clock */
     CLOCK_DisableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!
- * @brief Fill in the RTC config struct with the default settings
+ * @brief Fills in the RTC config struct with the default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *    config->wakeupSelect = false;
  *    config->updateMode = false;
@@ -156,7 +161,7 @@
  *    config->compensationInterval = 0;
  *    config->compensationTime = 0;
  * @endcode
- * @param config Pointer to user's RTC config structure.
+ * @param config Pointer to the user's RTC configuration structure.
  */
 void RTC_GetDefaultConfig(rtc_config_t *config);
 
@@ -170,11 +175,11 @@
 /*!
  * @brief Sets the RTC date and time according to the given time structure.
  *
- * The RTC counter must be stopped prior to calling this function as writes to the RTC
- * seconds register will fail if the RTC counter is running.
+ * The RTC counter must be stopped prior to calling this function because writes to the RTC
+ * seconds register fail if the RTC counter is running.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details to set are stored
+ * @param datetime Pointer to the structure where the date and time details are stored.
  *
  * @return kStatus_Success: Success in setting the time and starting the RTC
  *         kStatus_InvalidArgument: Error because the datetime format is incorrect
@@ -185,18 +190,18 @@
  * @brief Gets the RTC time and stores it in the given time structure.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details are stored.
+ * @param datetime Pointer to the structure where the date and time details are stored.
  */
 void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
 
 /*!
- * @brief Sets the RTC alarm time
+ * @brief Sets the RTC alarm time.
  *
  * The function checks whether the specified alarm time is greater than the present
  * time. If not, the function does not set the alarm and returns an error.
  *
  * @param base      RTC peripheral base address
- * @param alarmTime Pointer to structure where the alarm time is stored.
+ * @param alarmTime Pointer to the structure where the alarm time is stored.
  *
  * @return kStatus_Success: success in setting the RTC alarm
  *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
@@ -208,7 +213,7 @@
  * @brief Returns the RTC alarm time.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the alarm date and time details are stored.
+ * @param datetime Pointer to the structure where the alarm date and time details are stored.
  */
 void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
 
@@ -264,7 +269,7 @@
  */
 
 /*!
- * @brief Gets the RTC status flags
+ * @brief Gets the RTC status flags.
  *
  * @param base RTC peripheral base address
  *
@@ -319,6 +324,8 @@
 
 /*! @}*/
 
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
 /*!
  * @brief This function sets the specified capacitor configuration for the RTC oscillator.
  *
@@ -336,6 +343,8 @@
     base->CR = reg;
 }
 
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
 /*!
  * @brief Performs a software reset on the RTC module.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -95,15 +95,17 @@
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-/*!@brief SAI handle pointer */
-sai_handle_t *s_saiHandle[FSL_FEATURE_SOC_I2S_COUNT][2];
 /* Base pointer array */
 static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
+/*!@brief SAI handle pointer */
+sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
 /* IRQ number array */
 static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS;
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 /*! @brief Pointer to tx IRQ handler for each instance. */
 static sai_tx_isr_t s_saiTxIsr;
 /*! @brief Pointer to tx IRQ handler for each instance. */
@@ -181,7 +183,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_I2S_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
     {
         if (s_saiBases[instance] == base)
         {
@@ -189,7 +191,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_I2S_COUNT);
+    assert(instance < ARRAY_SIZE(s_saiBases));
 
     return instance;
 }
@@ -237,8 +239,10 @@
 {
     uint32_t val = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the SAI clock */
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     /* Master clock source setting */
@@ -339,8 +343,10 @@
 {
     uint32_t val = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable SAI clock first. */
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     /* Master clock source setting */
@@ -441,7 +447,9 @@
 {
     SAI_TxEnable(base, false);
     SAI_RxEnable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void SAI_TxGetDefaultConfig(sai_config_t *config)
@@ -632,7 +640,7 @@
     uint32_t i = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
-    for (i = 0; i < size; i++)
+    while (i < size)
     {
         /* Wait until it can write data */
         while (!(base->TCSR & I2S_TCSR_FWF_MASK))
@@ -641,6 +649,7 @@
 
         SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
+        i += bytesPerWord;
     }
 
     /* Wait until the last data is sent */
@@ -654,7 +663,7 @@
     uint32_t i = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
-    for (i = 0; i < size; i++)
+    while (i < size)
     {
         /* Wait until data is received */
         while (!(base->RCSR & I2S_RCSR_FWF_MASK))
@@ -663,6 +672,7 @@
 
         SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
+        i += bytesPerWord;
     }
 }
 
@@ -670,6 +680,9 @@
 {
     assert(handle);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     s_saiHandle[SAI_GetInstance(base)][0] = handle;
 
     handle->callback = callback;
@@ -686,6 +699,9 @@
 {
     assert(handle);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     s_saiHandle[SAI_GetInstance(base)][1] = handle;
 
     handle->callback = callback;
@@ -1024,19 +1040,30 @@
 }
 
 #if defined(I2S0)
-#if defined(FSL_FEATURE_SAI_INT_SOURCE_NUM) && (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1)
 void I2S0_DriverIRQHandler(void)
 {
-    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
     {
         s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
-    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
     {
         s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
-#else
+
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
@@ -1048,10 +1075,33 @@
     assert(s_saiHandle[0][1]);
     s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
-#endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
 
 #if defined(I2S1)
+void I2S1_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S1, s_saiHandle[1][0]);
+    }
+}
+
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
@@ -1063,4 +1113,80 @@
     assert(s_saiHandle[1][1]);
     s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
+#endif /* I2S1*/
+
+#if defined(I2S2)
+void I2S2_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
 #endif
+    {
+        s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+    }
+}
+
+void I2S2_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][0]);
+    s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+}
+
+void I2S2_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][1]);
+    s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+}
+#endif /* I2S2*/
+
+#if defined(I2S3)
+void I2S3_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+    }
+}
+
+void I2S3_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][0]);
+    s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+}
+
+void I2S3_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][1]);
+    s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+}
+#endif /* I2S3*/

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,14 +38,13 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -186,16 +185,16 @@
 /*! @brief Audio sample rate */
 typedef enum _sai_sample_rate
 {
-    kSAI_SampleRate8KHz = 8000U,     /*!< Sample rate 8000Hz */
-    kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
-    kSAI_SampleRate12KHz = 12000U,   /*!< Sample rate 12000Hz */
-    kSAI_SampleRate16KHz = 16000U,   /*!< Sample rate 16000Hz */
-    kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
-    kSAI_SampleRate24KHz = 24000U,   /*!< Sample rate 24000Hz */
-    kSAI_SampleRate32KHz = 32000U,   /*!< Sample rate 32000Hz */
-    kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
-    kSAI_SampleRate48KHz = 48000U,   /*!< Sample rate 48000Hz */
-    kSAI_SampleRate96KHz = 96000U    /*!< Sample rate 96000Hz */
+    kSAI_SampleRate8KHz = 8000U,     /*!< Sample rate 8000 Hz */
+    kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */
+    kSAI_SampleRate12KHz = 12000U,   /*!< Sample rate 12000 Hz */
+    kSAI_SampleRate16KHz = 16000U,   /*!< Sample rate 16000 Hz */
+    kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */
+    kSAI_SampleRate24KHz = 24000U,   /*!< Sample rate 24000 Hz */
+    kSAI_SampleRate32KHz = 32000U,   /*!< Sample rate 32000 Hz */
+    kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */
+    kSAI_SampleRate48KHz = 48000U,   /*!< Sample rate 48000 Hz */
+    kSAI_SampleRate96KHz = 96000U    /*!< Sample rate 96000 Hz */
 } sai_sample_rate_t;
 
 /*! @brief Audio word width */
@@ -211,7 +210,7 @@
 typedef struct _sai_transfer_format
 {
     uint32_t sampleRate_Hz;   /*!< Sample rate of audio data */
-    uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32bits */
+    uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32 bits */
     sai_mono_stereo_t stereo; /*!< Mono or stereo */
     uint32_t masterClockHz;   /*!< Master clock frequency in Hz */
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
@@ -239,7 +238,7 @@
     uint32_t state;                               /*!< Transfer status */
     sai_transfer_callback_t callback;             /*!< Callback function called at transfer event*/
     void *userData;                               /*!< Callback parameter passed to callback function*/
-    uint8_t bitWidth;                             /*!< Bit width for transfer, 8/16/24/32bits */
+    uint8_t bitWidth;                             /*!< Bit width for transfer, 8/16/24/32 bits */
     uint8_t channel;                              /*!< Transfer channel */
     sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
     size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
@@ -301,7 +300,7 @@
  * This API initializes the configuration structure for use in SAI_TxConfig().
  * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified
  *  before calling SAI_TxConfig().
- * Example:
+ * This is an example.
    @code
    sai_config_t config;
    SAI_TxGetDefaultConfig(&config);
@@ -317,7 +316,7 @@
  * This API initializes the configuration structure for use in SAI_RxConfig().
  * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified
  *  before calling SAI_RxConfig().
- * Example:
+ * This is an example.
    @code
    sai_config_t config;
    SAI_RxGetDefaultConfig(&config);
@@ -356,7 +355,7 @@
 void SAI_RxReset(I2S_Type *base);
 
 /*!
- * @brief Enables/disables SAI Tx.
+ * @brief Enables/disables the SAI Tx.
  *
  * @param base SAI base pointer
  * @param enable True means enable SAI Tx, false means disable.
@@ -364,7 +363,7 @@
 void SAI_TxEnable(I2S_Type *base, bool enable);
 
 /*!
- * @brief Enables/disables SAI Rx.
+ * @brief Enables/disables the SAI Rx.
  *
  * @param base SAI base pointer
  * @param enable True means enable SAI Rx, false means disable.
@@ -418,7 +417,7 @@
  * @brief Clears the SAI Rx status flag state.
  *
  * @param base SAI base pointer
- * @param mask State mask. It can be a combination of the following source if defined:
+ * @param mask State mask. It can be a combination of the following sources if defined.
  *        @arg kSAI_WordStartFlag
  *        @arg kSAI_SyncErrorFlag
  *        @arg kSAI_FIFOErrorFlag
@@ -436,11 +435,11 @@
  */
 
 /*!
- * @brief Enables SAI Tx interrupt requests.
+ * @brief Enables the SAI Tx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -453,11 +452,11 @@
 }
 
 /*!
- * @brief Enables SAI Rx interrupt requests.
+ * @brief Enables the SAI Rx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -470,11 +469,11 @@
 }
 
 /*!
- * @brief Disables SAI Tx interrupt requests.
+ * @brief Disables the SAI Tx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -487,11 +486,11 @@
 }
 
 /*!
- * @brief Disables SAI Rx interrupt requests.
+ * @brief Disables the SAI Rx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -511,10 +510,10 @@
  */
 
 /*!
- * @brief Enables/disables SAI Tx DMA requests.
+ * @brief Enables/disables the SAI Tx DMA requests.
  * @param base SAI base pointer
  * @param mask DMA source
- *     The parameter can be combination of the following source if defined:
+ *     The parameter can be combination of the following sources if defined.
  *     @arg kSAI_FIFOWarningDMAEnable
  *     @arg kSAI_FIFORequestDMAEnable
  * @param enable True means enable DMA, false means disable DMA.
@@ -532,10 +531,10 @@
 }
 
 /*!
- * @brief Enables/disables SAI Rx DMA requests.
+ * @brief Enables/disables the SAI Rx DMA requests.
  * @param base SAI base pointer
  * @param mask DMA source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_FIFOWarningDMAEnable
  *     @arg kSAI_FIFORequestDMAEnable
  * @param enable True means enable DMA, false means disable DMA.
@@ -555,7 +554,7 @@
 /*!
  * @brief  Gets the SAI Tx data register address.
  *
- * This API is used to provide a transfer address for SAI DMA transfer configuration.
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
  *
  * @param base SAI base pointer.
  * @param channel Which data channel used.
@@ -569,7 +568,7 @@
 /*!
  * @brief  Gets the SAI Rx data register address.
  *
- * This API is used to provide a transfer address for SAI DMA transfer configuration.
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
  *
  * @param base SAI base pointer.
  * @param channel Which data channel used.
@@ -594,10 +593,10 @@
  * format to be transferred.
  *
  * @param base SAI base pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
 */
 void SAI_TxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
@@ -611,10 +610,10 @@
  * format to be transferred.
  *
  * @param base SAI base pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
 */
 void SAI_RxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
@@ -628,7 +627,7 @@
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
- * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be written.
  * @param size Bytes to be written.
  */
@@ -653,14 +652,14 @@
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
- * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be read.
  * @param size Bytes to be read.
  */
 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
 
 /*!
- * @brief Reads data from SAI FIFO.
+ * @brief Reads data from the SAI FIFO.
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
@@ -681,26 +680,26 @@
 /*!
  * @brief Initializes the SAI Tx handle.
  *
- * This function initializes the Tx handle for SAI Tx transactional APIs. Call
- * this function one time to get the handle initialized.
+ * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
+ * this function once to get the handle initialized.
  *
  * @param base SAI base pointer
  * @param handle SAI handle pointer.
- * @param callback pointer to user callback function
- * @param userData user parameter passed to the callback function
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function
  */
 void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
 
 /*!
  * @brief Initializes the SAI Rx handle.
  *
- * This function initializes the Rx handle for SAI Rx transactional APIs. Call
- * this function one time to get the handle initialized.
+ * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
+ * this function once to get the handle initialized.
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param callback pointer to user callback function
- * @param userData user parameter passed to the callback function
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function.
  */
 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
 
@@ -712,11 +711,11 @@
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
- * clock, this value should equal to masterClockHz in format.
- * @return Status of this function. Return value is one of status_t.
+ * clock, this value should equal the masterClockHz in format.
+ * @return Status of this function. Return value is the status_t.
 */
 status_t SAI_TransferTxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
@@ -732,10 +731,10 @@
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
+ * clock, this value should equal the masterClockHz in format.
  * @return Status of this function. Return value is one of status_t.
 */
 status_t SAI_TransferRxSetFormat(I2S_Type *base,
@@ -752,9 +751,9 @@
  * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
  * is finished.
  *
- * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state
- * @param xfer pointer to sai_transfer_t structure
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
  * @retval kStatus_Success Successfully started the data receive.
  * @retval kStatus_SAI_TxBusy Previous receive still not finished.
  * @retval kStatus_InvalidArgument The input parameter is invalid.
@@ -770,8 +769,8 @@
  * is finished.
  *
  * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state
- * @param xfer pointer to sai_transfer_t structure
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
  * @retval kStatus_Success Successfully started the data receive.
  * @retval kStatus_SAI_RxBusy Previous receive still not finished.
  * @retval kStatus_InvalidArgument The input parameter is invalid.
@@ -782,7 +781,7 @@
  * @brief Gets a set byte count.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  * @param count Bytes count sent.
  * @retval kStatus_Success Succeed get the transfer count.
  * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
@@ -793,7 +792,7 @@
  * @brief Gets a received byte count.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  * @param count Bytes count received.
  * @retval kStatus_Success Succeed get the transfer count.
  * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
@@ -807,18 +806,18 @@
  * to abort the transfer early.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  */
 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle);
 
 /*!
  * @brief Aborts the the current IRQ receive.
  *
- * @note This API can be called any time when an interrupt non-blocking transfer initiates
+ * @note This API can be called when an interrupt non-blocking transfer initiates
  * to abort the transfer early.
  *
  * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  */
 void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle);
 
@@ -826,7 +825,7 @@
  * @brief Tx interrupt handler.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure.
+ * @param handle Pointer to the sai_handle_t structure.
  */
 void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
 
@@ -834,7 +833,7 @@
  * @brief Tx interrupt handler.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure.
+ * @param handle Pointer to the sai_handle_t structure.
  */
 void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -132,6 +132,9 @@
 
     uint32_t instance = SAI_GetInstance(base);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
     handle->callback = callback;
@@ -157,6 +160,9 @@
 
     uint32_t instance = SAI_GetInstance(base);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
     handle->callback = callback;
@@ -187,7 +193,14 @@
     SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
     /* Get the tranfer size from format, this should be used in EDMA configuration */
-    handle->bytesPerFrame = format->bitWidth / 8U;
+    if (format->bitWidth == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = format->bitWidth / 8U;
+    }
 
     /* Update the data channel SAI used */
     handle->channel = format->channel;
@@ -210,7 +223,14 @@
     SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
     /* Get the tranfer size from format, this should be used in EDMA configuration */
-    handle->bytesPerFrame = format->bitWidth / 8U;
+    if (format->bitWidth == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = format->bitWidth / 8U;
+    }
 
     /* Update the data channel SAI used */
     handle->channel = format->channel;
@@ -253,6 +273,9 @@
     EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
                          handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+    /* Store the initially configured eDMA minor byte transfer count into the SAI handle */
+    handle->nbytes = handle->count * handle->bytesPerFrame;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &config);
 
     /* Start DMA transfer */
@@ -298,6 +321,9 @@
     EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
                          handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory);
 
+    /* Store the initially configured eDMA minor byte transfer count into the SAI handle */
+    handle->nbytes = handle->count * handle->bytesPerFrame;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &config);
 
     /* Start DMA transfer */
@@ -322,6 +348,9 @@
     /* Disable DMA enable bit */
     SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
 
+    /* Disable Tx */
+    SAI_TxEnable(base, false);
+
     /* Set the handle state */
     handle->state = kSAI_Idle;
 }
@@ -336,6 +365,9 @@
     /* Disable DMA enable bit */
     SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
 
+    /* Disable Rx */
+    SAI_RxEnable(base, false);
+
     /* Set the handle state */
     handle->state = kSAI_Idle;
 }
@@ -353,7 +385,8 @@
     else
     {
         *count = (handle->transferSize[handle->queueDriver] -
-                  EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
 
     return status;
@@ -372,7 +405,8 @@
     else
     {
         *count = (handle->transferSize[handle->queueDriver] -
-                  EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
 
     return status;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,8 +38,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -53,6 +51,7 @@
 struct _sai_edma_handle
 {
     edma_handle_t *dmaHandle;                     /*!< DMA handler for SAI send */
+    uint8_t nbytes;                               /*!< eDMA minor byte transfer count initially configured. */
     uint8_t bytesPerFrame;                        /*!< Bytes in a frame */
     uint8_t channel;                              /*!< Which data channel */
     uint8_t count;                                /*!< The transfer data count in a DMA request */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,34 +1,28 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
- * Redistribution and use in source and binary forms, with or without
- * modification,
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this
- * list
+ * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
  *
- * o Redistributions in binary form must reproduce the above copyright notice,
- * this
+ * o Redistributions in binary form must reproduce the above copyright notice, this
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
@@ -42,12 +36,8 @@
 /*! @brief Clock setting */
 /* Max SD clock divisor from base clock */
 #define SDHC_MAX_DVS ((SDHC_SYSCTL_DVS_MASK >> SDHC_SYSCTL_DVS_SHIFT) + 1U)
-#define SDHC_INITIAL_DVS (1U)   /* Initial value of SD clock divisor */
-#define SDHC_INITIAL_CLKFS (2U) /* Initial value of SD clock frequency selector */
-#define SDHC_NEXT_DVS(x) ((x) += 1U)
 #define SDHC_PREV_DVS(x) ((x) -= 1U)
 #define SDHC_MAX_CLKFS ((SDHC_SYSCTL_SDCLKFS_MASK >> SDHC_SYSCTL_SDCLKFS_SHIFT) + 1U)
-#define SDHC_NEXT_CLKFS(x) ((x) <<= 1U)
 #define SDHC_PREV_CLKFS(x) ((x) >>= 1U)
 
 /* Typedef for interrupt handler. */
@@ -85,8 +75,9 @@
  * @param base SDHC peripheral base address.
  * @param command Command to be sent.
  * @param data Data to be transferred.
+ * @param DMA mode selection
  */
-static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data);
+static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode);
 
 /*!
  * @brief Receive command response
@@ -94,7 +85,7 @@
  * @param base SDHC peripheral base address.
  * @param command Command to be sent.
  */
-static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command);
+static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command);
 
 /*!
  * @brief Read DATAPORT when buffer enable bit is set.
@@ -230,8 +221,10 @@
 /*! @brief SDHC IRQ name array */
 static const IRQn_Type s_sdhcIRQ[] = SDHC_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief SDHC clock array name */
 static const clock_ip_name_t s_sdhcClock[] = SDHC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* SDHC ISR for transactional APIs. */
 static sdhc_isr_t s_sdhcIsr;
@@ -243,12 +236,12 @@
 {
     uint8_t instance = 0;
 
-    while ((instance < FSL_FEATURE_SOC_SDHC_COUNT) && (s_sdhcBase[instance] != base))
+    while ((instance < ARRAY_SIZE(s_sdhcBase)) && (s_sdhcBase[instance] != base))
     {
         instance++;
     }
 
-    assert(instance < FSL_FEATURE_SOC_SDHC_COUNT);
+    assert(instance < ARRAY_SIZE(s_sdhcBase));
 
     return instance;
 }
@@ -256,7 +249,6 @@
 static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal)
 {
     uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */
-    sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT);
     bool cardDetectDat3 = (bool)(base->PROCTL & SDHC_PROCTL_D3CD_MASK);
 
     /* Disable all interrupts */
@@ -267,23 +259,12 @@
     interruptEnabled =
         (kSDHC_CommandIndexErrorFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
          kSDHC_CommandTimeoutFlag | kSDHC_CommandCompleteFlag | kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag |
-         kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag);
+         kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag | kSDHC_BufferReadReadyFlag |
+         kSDHC_BufferWriteReadyFlag | kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag);
     if (cardDetectDat3)
     {
         interruptEnabled |= (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag);
     }
-    switch (dmaMode)
-    {
-        case kSDHC_DmaModeAdma1:
-        case kSDHC_DmaModeAdma2:
-            interruptEnabled |= (kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag);
-            break;
-        case kSDHC_DmaModeNo:
-            interruptEnabled |= (kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
-            break;
-        default:
-            break;
-    }
 
     SDHC_EnableInterruptStatus(base, interruptEnabled);
     if (usingInterruptSignal)
@@ -292,48 +273,47 @@
     }
 }
 
-static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data)
+static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode)
 {
     uint32_t flags = 0U;
     sdhc_transfer_config_t sdhcTransferConfig = {0};
-    sdhc_dma_mode_t dmaMode;
 
     /* Define the flag corresponding to each response type. */
     switch (command->responseType)
     {
-        case kSDHC_ResponseTypeNone:
+        case kCARD_ResponseTypeNone:
             break;
-        case kSDHC_ResponseTypeR1: /* Response 1 */
+        case kCARD_ResponseTypeR1: /* Response 1 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR1b: /* Response 1 with busy */
+        case kCARD_ResponseTypeR1b: /* Response 1 with busy */
             flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR2: /* Response 2 */
+        case kCARD_ResponseTypeR2: /* Response 2 */
             flags |= (kSDHC_ResponseLength136Flag | kSDHC_EnableCrcCheckFlag);
             break;
-        case kSDHC_ResponseTypeR3: /* Response 3 */
+        case kCARD_ResponseTypeR3: /* Response 3 */
             flags |= (kSDHC_ResponseLength48Flag);
             break;
-        case kSDHC_ResponseTypeR4: /* Response 4 */
+        case kCARD_ResponseTypeR4: /* Response 4 */
             flags |= (kSDHC_ResponseLength48Flag);
             break;
-        case kSDHC_ResponseTypeR5: /* Response 5 */
+        case kCARD_ResponseTypeR5: /* Response 5 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR5b: /* Response 5 with busy */
+        case kCARD_ResponseTypeR5b: /* Response 5 with busy */
             flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR6: /* Response 6 */
+        case kCARD_ResponseTypeR6: /* Response 6 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR7: /* Response 7 */
+        case kCARD_ResponseTypeR7: /* Response 7 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
         default:
             break;
     }
-    if (command->type == kSDHC_CommandTypeAbort)
+    if (command->type == kCARD_CommandTypeAbort)
     {
         flags |= kSDHC_CommandTypeAbortFlag;
     }
@@ -341,7 +321,7 @@
     if (data)
     {
         flags |= kSDHC_DataPresentFlag;
-        dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT);
+
         if (dmaMode != kSDHC_DmaModeNo)
         {
             flags |= kSDHC_EnableDmaFlag;
@@ -375,14 +355,14 @@
     SDHC_SetTransferConfig(base, &sdhcTransferConfig);
 }
 
-static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command)
+static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command)
 {
     uint32_t i;
 
-    if (command->responseType != kSDHC_ResponseTypeNone)
+    if (command->responseType != kCARD_ResponseTypeNone)
     {
         command->response[0U] = SDHC_GetCommandResponse(base, 0U);
-        if (command->responseType == kSDHC_ResponseTypeR2)
+        if (command->responseType == kCARD_ResponseTypeR2)
         {
             command->response[1U] = SDHC_GetCommandResponse(base, 1U);
             command->response[2U] = SDHC_GetCommandResponse(base, 2U);
@@ -401,6 +381,18 @@
             } while (i--);
         }
     }
+    /* check response error flag */
+    if ((command->responseErrorFlags != 0U) &&
+        ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
+         (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5)))
+    {
+        if (((command->responseErrorFlags) & (command->response[0U])) != 0U)
+        {
+            return kStatus_SDHC_SendCommandFailed;
+        }
+    }
+
+    return kStatus_Success;
 }
 
 static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords)
@@ -411,10 +403,10 @@
     uint32_t readWatermark = ((base->WML & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT);
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -458,10 +450,10 @@
     status_t error = kStatus_Success;
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -487,13 +479,12 @@
         {
             transferredWords = SDHC_ReadDataPort(base, data, transferredWords);
         }
-
-        /* Clear buffer enable flag to trigger transfer. Clear data error flag when SDHC encounter error */
-        SDHC_ClearInterruptStatusFlags(base, (kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag));
+        /* clear buffer ready and error */
+        SDHC_ClearInterruptStatusFlags(base, kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag);
     }
 
     /* Clear data complete flag after the last read operation. */
-    SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag);
+    SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag);
 
     return error;
 }
@@ -506,10 +497,10 @@
     uint32_t writeWatermark = ((base->WML & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT);
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -553,10 +544,10 @@
     status_t error = kStatus_Success;
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -598,6 +589,7 @@
             error = kStatus_Fail;
         }
     }
+
     SDHC_ClearInterruptStatusFlags(base, (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag));
 
     return error;
@@ -619,7 +611,7 @@
     /* Receive response when command completes successfully. */
     if (error == kStatus_Success)
     {
-        SDHC_ReceiveCommandResponse(base, command);
+        error = SDHC_ReceiveCommandResponse(base, command);
     }
 
     SDHC_ClearInterruptStatusFlags(base, (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag));
@@ -748,7 +740,11 @@
         {
             handle->transferredWords = SDHC_WriteDataPort(base, handle->data, handle->transferredWords);
         }
-        else if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete))
+        else
+        {
+        }
+
+        if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete))
         {
             handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
         }
@@ -787,8 +783,10 @@
     uint32_t proctl;
     uint32_t wml;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable SDHC clock. */
     CLOCK_EnableClock(s_sdhcClock[SDHC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset SDHC. */
     SDHC_Reset(base, kSDHC_ResetAll, 100);
@@ -822,8 +820,10 @@
 
 void SDHC_Deinit(SDHC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable clock. */
     CLOCK_DisableClock(s_sdhcClock[SDHC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout)
@@ -877,44 +877,83 @@
     assert(srcClock_Hz != 0U);
     assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz));
 
-    uint32_t divisor;
-    uint32_t prescaler;
-    uint32_t sysctl;
-    uint32_t nearestFrequency = 0;
+    uint32_t totalDiv = 0U;
+    uint32_t divisor = 0U;
+    uint32_t prescaler = 0U;
+    uint32_t sysctl = 0U;
+    uint32_t nearestFrequency = 0U;
+
+    /* calucate total divisor first */
+    totalDiv = srcClock_Hz / busClock_Hz;
+
+    if (totalDiv != 0U)
+    {
+        /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */
+        if ((srcClock_Hz / totalDiv) > busClock_Hz)
+        {
+            totalDiv++;
+        }
 
-    divisor = SDHC_INITIAL_DVS;
-    prescaler = SDHC_INITIAL_CLKFS;
+        /* divide the total divisor to div and prescaler */
+        if (totalDiv > SDHC_MAX_DVS)
+        {
+            prescaler = totalDiv / SDHC_MAX_DVS;
+            /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */
+            while (((SDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U))
+            {
+                prescaler++;
+            }
+            /* calucate the divisor */
+            divisor = totalDiv / prescaler;
+            /* fine tuning the divisor until divisor * prescaler >= totalDiv */
+            while ((divisor * prescaler) < totalDiv)
+            {
+                divisor++;
+            }
+            nearestFrequency = srcClock_Hz / divisor / prescaler;
+        }
+        else
+        {
+            divisor = totalDiv;
+            prescaler = 0U;
+            nearestFrequency = srcClock_Hz / divisor;
+        }
+    }
+    /* in this condition , srcClock_Hz = busClock_Hz, */
+    else
+    {
+        /* total divider = 1U */
+        divisor = 0U;
+        prescaler = 0U;
+        nearestFrequency = srcClock_Hz;
+    }
+
+    /* calucate the value write to register */
+    if (divisor != 0U)
+    {
+        SDHC_PREV_DVS(divisor);
+    }
+    /* calucate the value write to register */
+    if (prescaler != 0U)
+    {
+        SDHC_PREV_CLKFS(prescaler);
+    }
 
     /* Disable SD clock. It should be disabled before changing the SD clock frequency.*/
     base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
 
-    if (busClock_Hz > 0U)
-    {
-        while ((srcClock_Hz / prescaler / SDHC_MAX_DVS > busClock_Hz) && (prescaler < SDHC_MAX_CLKFS))
-        {
-            SDHC_NEXT_CLKFS(prescaler);
-        }
-        while ((srcClock_Hz / prescaler / divisor > busClock_Hz) && (divisor < SDHC_MAX_DVS))
-        {
-            SDHC_NEXT_DVS(divisor);
-        }
-        nearestFrequency = srcClock_Hz / prescaler / divisor;
-        SDHC_PREV_CLKFS(prescaler);
-        SDHC_PREV_DVS(divisor);
+    /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */
+    sysctl = base->SYSCTL;
+    sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK);
+    sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU));
+    base->SYSCTL = sysctl;
 
-        /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */
-        sysctl = base->SYSCTL;
-        sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK);
-        sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU));
-        base->SYSCTL = sysctl;
-
-        /* Wait until the SD clock is stable. */
-        while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK))
-        {
-        }
-        /* Enable the SD clock. */
-        base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
+    /* Wait until the SD clock is stable. */
+    while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK))
+    {
     }
+    /* Enable the SD clock. */
+    base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
 
     return nearestFrequency;
 }
@@ -1008,7 +1047,7 @@
     uint32_t mmcboot = 0U;
 
     mmcboot = (SDHC_MMCBOOT_DTOCVACK(config->ackTimeoutCount) | SDHC_MMCBOOT_BOOTMODE(config->bootMode) |
-              SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount));
+               SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount));
     if (config->enableBootAck)
     {
         mmcboot |= SDHC_MMCBOOT_BOOTACK_MASK;
@@ -1032,7 +1071,7 @@
                                  uint32_t dataBytes)
 {
     status_t error = kStatus_Success;
-    const uint32_t *startAddress;
+    const uint32_t *startAddress = data;
     uint32_t entries;
     uint32_t i;
 #if defined FSL_SDHC_ENABLE_ADMA1
@@ -1044,14 +1083,19 @@
         (!data) || (!dataBytes)
 #if !defined FSL_SDHC_ENABLE_ADMA1
         || (dmaMode == kSDHC_DmaModeAdma1)
-#else
-        /* Buffer address configured in ADMA1 descriptor must be 4KB aligned. */
-        || ((dmaMode == kSDHC_DmaModeAdma1) && (((uint32_t)data % SDHC_ADMA1_LENGTH_ALIGN) != 0U))
-#endif /* FSL_SDHC_ENABLE_ADMA1 */
+#endif
             )
     {
         error = kStatus_InvalidArgument;
     }
+    else if (((dmaMode == kSDHC_DmaModeAdma2) && (((uint32_t)startAddress % SDHC_ADMA2_LENGTH_ALIGN) != 0U))
+#if defined FSL_SDHC_ENABLE_ADMA1
+             || ((dmaMode == kSDHC_DmaModeAdma1) && (((uint32_t)startAddress % SDHC_ADMA1_LENGTH_ALIGN) != 0U))
+#endif
+                 )
+    {
+        error = kStatus_SDHC_DMADataBufferAddrNotAlign;
+    }
     else
     {
         switch (dmaMode)
@@ -1071,7 +1115,6 @@
                         sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */
                 }
 
-                startAddress = data;
                 /* Check if ADMA descriptor's number is enough. */
                 entries = ((dataBytes / SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
                 /* ADMA1 needs two descriptors to finish a transfer */
@@ -1113,22 +1156,24 @@
                     /* When use ADMA, disable simple DMA */
                     base->DSADDR = 0U;
                     base->ADSADDR = (uint32_t)table;
+                    /* disable the buffer ready flag in DMA mode */
+                    SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+                    SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
                 }
                 break;
 #endif /* FSL_SDHC_ENABLE_ADMA1 */
             case kSDHC_DmaModeAdma2:
                 /*
-                 * Add non aligned access support ,user need make sure your buffer size is big
-                 * enough to hold the data,in other words,user need make sure the buffer size
-                 * is 4 byte aligned
-                 */
+                * Add non aligned access support ,user need make sure your buffer size is big
+                * enough to hold the data,in other words,user need make sure the buffer size
+                * is 4 byte aligned
+                */
                 if (dataBytes % sizeof(uint32_t) != 0U)
                 {
                     dataBytes +=
                         sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */
                 }
 
-                startAddress = data;
                 /* Check if ADMA descriptor's number is enough. */
                 entries = ((dataBytes / SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
                 if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma2_descriptor_t)))
@@ -1165,6 +1210,9 @@
                     /* When use ADMA, disable simple DMA */
                     base->DSADDR = 0U;
                     base->ADSADDR = (uint32_t)table;
+                    /* disable the buffer read flag in DMA mode */
+                    SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+                    SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
                 }
                 break;
             default:
@@ -1187,44 +1235,53 @@
     /* make sure the cmd/block count is valid */
     if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT)))
     {
-        error = kStatus_InvalidArgument;
+        return kStatus_InvalidArgument;
+    }
+
+    /* Wait until command/data bus out of busy status. */
+    while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag)
+    {
+    }
+    while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))
+    {
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
+    if (data && (NULL != admaTable))
+    {
+        error =
+            SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
+                                    (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize));
+        /* in this situation , we disable the DMA instead of polling transfer mode */
+        if (error == kStatus_SDHC_DMADataBufferAddrNotAlign)
+        {
+            dmaMode = kSDHC_DmaModeNo;
+            SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+        }
+        else if (error != kStatus_Success)
+        {
+            return error;
+        }
+        else
+        {
+        }
+    }
+
+    /* Send command and receive data. */
+    SDHC_StartTransfer(base, command, data, dmaMode);
+    if (kStatus_Success != SDHC_SendCommandBlocking(base, command))
+    {
+        return kStatus_SDHC_SendCommandFailed;
+    }
+    else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data)))
+    {
+        return kStatus_SDHC_TransferDataFailed;
     }
     else
     {
-        /* Wait until command/data bus out of busy status. */
-        while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag)
-        {
-        }
-        while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))
-        {
-        }
-
-        /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
-        if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
-                                                                (data->rxData ? data->rxData : data->txData),
-                                                                (data->blockCount * data->blockSize))))
-        {
-            error = kStatus_SDHC_PrepareAdmaDescriptorFailed;
-        }
-        else
-        {
-            /* Send command and receive data. */
-            SDHC_StartTransfer(base, command, data);
-            if (kStatus_Success != SDHC_SendCommandBlocking(base, command))
-            {
-                error = kStatus_SDHC_SendCommandFailed;
-            }
-            else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data)))
-            {
-                error = kStatus_SDHC_TransferDataFailed;
-            }
-            else
-            {
-            }
-        }
     }
 
-    return error;
+    return kStatus_Success;
 }
 
 void SDHC_TransferCreateHandle(SDHC_Type *base,
@@ -1271,40 +1328,49 @@
     /* make sure cmd/block count is valid */
     if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT)))
     {
-        error = kStatus_InvalidArgument;
+        return kStatus_InvalidArgument;
     }
-    else
+
+    /* Wait until command/data bus out of busy status. */
+    if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) ||
+        (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)))
+    {
+        return kStatus_SDHC_BusyTransferring;
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
+    if (data && (NULL != admaTable))
     {
-        /* Wait until command/data bus out of busy status. */
-        if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) ||
-            (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)))
+        error =
+            SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
+                                    (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize));
+        /* in this situation , we disable the DMA instead of polling transfer mode */
+        if (error == kStatus_SDHC_DMADataBufferAddrNotAlign)
         {
-            error = kStatus_SDHC_BusyTransferring;
+            /* change to polling mode */
+            dmaMode = kSDHC_DmaModeNo;
+            SDHC_EnableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+            SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+        }
+        else if (error != kStatus_Success)
+        {
+            return error;
         }
         else
         {
-            /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
-            if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
-                                                                    (data->rxData ? data->rxData : data->txData),
-                                                                    (data->blockCount * data->blockSize))))
-            {
-                error = kStatus_SDHC_PrepareAdmaDescriptorFailed;
-            }
-            else
-            {
-                /* Save command and data into handle before transferring. */
-                handle->command = command;
-                handle->data = data;
-                handle->interruptFlags = 0U;
-                /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */
-                handle->transferredWords = 0U;
-
-                SDHC_StartTransfer(base, command, data);
-            }
         }
     }
 
-    return error;
+    /* Save command and data into handle before transferring. */
+    handle->command = command;
+    handle->data = data;
+    handle->interruptFlags = 0U;
+    /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */
+    handle->transferredWords = 0U;
+
+    SDHC_StartTransfer(base, command, data, dmaMode);
+
+    return kStatus_Success;
 }
 
 void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -43,8 +43,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.1.2. */
-#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U))
+/*! @brief Driver version 2.1.5. */
+#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 5U))
 /*@}*/
 
 /*! @brief Maximum block count can be set one time */
@@ -57,6 +57,8 @@
     kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */
     kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U),           /*!< Send command failed */
     kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U),          /*!< Transfer data failed */
+    kStatus_SDHC_DMADataBufferAddrNotAlign =
+        MAKE_STATUS(kStatusGroup_SDHC, 4U), /*!< data buffer addr not align in DMA mode */
 };
 
 /*! @brief Host controller capabilities flag mask */
@@ -282,32 +284,32 @@
 } sdhc_boot_mode_t;
 
 /*! @brief The command type */
-typedef enum _sdhc_command_type
+typedef enum _sdhc_card_command_type
 {
-    kSDHC_CommandTypeNormal = 0U,  /*!< Normal command */
-    kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */
-    kSDHC_CommandTypeResume = 2U,  /*!< Resume command */
-    kSDHC_CommandTypeAbort = 3U,   /*!< Abort command */
-} sdhc_command_type_t;
+    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
+    kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
+    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
+    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
+} sdhc_card_command_type_t;
 
 /*!
  * @brief The command response type.
  *
  * Define the command response type from card to host controller.
  */
-typedef enum _sdhc_response_type
+typedef enum _sdhc_card_response_type
 {
-    kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */
-    kSDHC_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
-    kSDHC_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
-    kSDHC_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
-    kSDHC_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
-    kSDHC_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
-    kSDHC_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
-    kSDHC_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
-    kSDHC_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
-    kSDHC_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
-} sdhc_response_type_t;
+    kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
+    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
+    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
+    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
+    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
+    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
+    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
+    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
+    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
+    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
+} sdhc_card_response_type_t;
 
 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
 #define SDHC_ADMA1_ADDRESS_ALIGN (4096U)
@@ -477,7 +479,8 @@
  * @brief Card data descriptor
  *
  * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card
- * driver want to ignore the error event to read/write all the data not to stop read/write immediately when error event
+ * driver
+ * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
  * happen for example bus testing procedure for MMC card.
  */
 typedef struct _sdhc_data
@@ -497,11 +500,13 @@
  */
 typedef struct _sdhc_command
 {
-    uint32_t index;                    /*!< Command index */
-    uint32_t argument;                 /*!< Command argument */
-    sdhc_command_type_t type;          /*!< Command type */
-    sdhc_response_type_t responseType; /*!< Command response type */
-    uint32_t response[4U];             /*!< Response for this command */
+    uint32_t index;                         /*!< Command index */
+    uint32_t argument;                      /*!< Command argument */
+    sdhc_card_command_type_t type;          /*!< Command type */
+    sdhc_card_response_type_t responseType; /*!< Command response type */
+    uint32_t response[4U];                  /*!< Response for this command */
+    uint32_t responseErrorFlags;            /*!< response error flag, the flag which need to check
+                                                the command reponse*/
 } sdhc_command_t;
 
 /*! @brief Transfer state */
@@ -829,7 +834,8 @@
  * @brief Sets the card transfer-related configuration.
  *
  * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent
- * by SDHC after calling this function.
+ by
+ * SDHC after calling this function.
  *
  * Example:
    @code
@@ -929,7 +935,8 @@
  *
  * This function sets the card detection test level to indicate whether the card is inserted into the SDHC when DAT[3]/
  * CD pin is selected as a card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is
- * selected as the card detection pin.
+ * selected
+ * as the card detection pin.
  *
  * @param base SDHC peripheral base address.
  * @param high True to set the card detect level to high.
@@ -1007,7 +1014,10 @@
  * @brief Transfers the command/data using a blocking method.
  *
  * This function waits until the command response/data is received or the SDHC encounters an error by polling the status
- * flag. The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * flag.
+ * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode,
+ * the API will continue finish the transfer by polling IO directly
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  * the re-entry mechanism.
  *
  * @note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API.
@@ -1044,7 +1054,10 @@
  * @brief Transfers the command/data using an interrupt and an asynchronous method.
  *
  * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
- * error. The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * error.
+ * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode,
+ * the API will continue finish the transfer by polling IO directly
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  * the re-entry mechanism.
  *
  * @note Call the API 'SDHC_TransferCreateHandle' when calling this API.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
 /*! @brief Define macros for SDRAM driver. */
 #define SDRAMC_ONEMILLSEC_NANOSECONDS (1000000U)
 #define SDRAMC_ONESECOND_MILLISECONDS (1000U)
-#define SDRAMC_TIMEOUT_COUNT (0xFFFFU)
 
 /*******************************************************************************
  * Prototypes
@@ -53,8 +52,10 @@
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to SDRAMC clocks for each instance. */
-const clock_ip_name_t s_sdramClock[FSL_FEATURE_SOC_SDRAM_COUNT] = SDRAM_CLOCKS;
+static const clock_ip_name_t s_sdramClock[FSL_FEATURE_SOC_SDRAM_COUNT] = SDRAM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to SDRAMC bases for each instance. */
 static SDRAM_Type *const s_sdramcBases[] = SDRAM_BASE_PTRS;
@@ -67,7 +68,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_SDRAM_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_sdramcBases); instance++)
     {
         if (s_sdramcBases[instance] == base)
         {
@@ -75,7 +76,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_SDRAM_COUNT);
+    assert(instance < ARRAY_SIZE(s_sdramcBases));
 
     return instance;
 }
@@ -92,8 +93,10 @@
     uint32_t count;
     uint32_t index;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Un-gate sdram controller clock. */
     CLOCK_EnableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Initialize sdram Auto refresh timing. */
     count = refreshConfig->sdramRefreshRow * (refreshConfig->busClock_Hz / SDRAMC_ONESECOND_MILLISECONDS);
@@ -119,50 +122,23 @@
     SDRAMC_EnableOperateValid(base, kSDRAMC_Block0, false);
     SDRAMC_EnableOperateValid(base, kSDRAMC_Block1, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable SDRAM clock. */
     CLOCK_DisableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
-status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
+void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
 {
-    status_t result = kStatus_Success;
-    uint32_t count = SDRAMC_TIMEOUT_COUNT;
-
     switch (command)
     {
         /* Initiate mrs command. */
         case kSDRAMC_ImrsCommand:
             base->BLOCK[block].AC |= SDRAM_AC_IMRS_MASK;
-            while (count--)
-            {
-                if (!(base->BLOCK[block].AC & SDRAM_AC_IMRS_MASK))
-                {
-                    break;
-                }
-            }
-
-            if (!count)
-            {
-                /* Timeout the mrs command is unfinished. */
-                result = kStatus_Fail;
-            }
-            break;
+            break;            
         /* Initiate precharge command. */
         case kSDRAMC_PrechargeCommand:
             base->BLOCK[block].AC |= SDRAM_AC_IP_MASK;
-            while (count--)
-            {
-                if (!(base->BLOCK[block].AC & SDRAM_AC_IP_MASK))
-                {
-                    break;
-                }
-            }
-
-            /* Timeout the precharge command is unfinished. */
-            if (!count)
-            {
-                result = kStatus_Fail;
-            }
             break;
         /* Enable Auto refresh command. */
         case kSDRAMC_AutoRefreshEnableCommand:
@@ -183,5 +159,4 @@
         default:
             break;
     }
-    return result;
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SDRAMC driver version 2.0.0. */
-#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief SDRAMC driver version 2.1.0. */
+#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 /*! @brief SDRAM controller auto-refresh timing. */
@@ -60,14 +59,14 @@
 /*!
  * @brief Setting latency for SDRAM controller timing specifications.
  *
- * The latency setting will affects the following SDRAM timing specifications:
+ * The latency setting affects the following SDRAM timing specifications:
  *       - trcd: SRAS assertion to SCAS assertion \n
  *       - tcasl: SCAS assertion to data out \n
  *       - tras: ACTV command to Precharge command \n
  *       - trp: Precharge command to ACTV command \n
  *       - trwl, trdl: Last data input to Precharge command \n
  *       - tep: Last data out to Precharge command \n
- * the details of the latency setting and timing specifications are shown on the following table list: \n
+ * The details of the latency setting and timing specifications are shown in the following table list. \n
  *   latency      trcd:          tcasl         tras           trp        trwl,trdl        tep   \n
  *    0       1 bus clock    1 bus clock   2 bus clocks   1 bus clock   1 bus clock   1 bus clock  \n
  *    1       2 bus clock    2 bus clock   4 bus clocks   2 bus clock   1 bus clock   1 bus clock  \n
@@ -219,10 +218,10 @@
 
 /*!
  * @brief Sends the SDRAM command.
- * This function sends the command to SDRAM. There are precharge command, initialize MRS command,
+ * This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
  * auto-refresh enable/disable command, and self-refresh enter/exit commands.
- * Note the self-refresh enter/exit commands are all blocks setting and "block"
- * are ignored. Ensure to set the right "block" when send other commands.
+ * Note that the self-refresh enter/exit commands are all blocks setting and "block"
+ * is ignored. Ensure to set the correct "block" when send other commands.
  *
  * @param base SDRAM controller peripheral base address.
  * @param block The block selection.
@@ -233,13 +232,8 @@
  *        kSDRAMC_SelfrefreshExitCommand  -  Exit self-refresh command \n
  *        kSDRAMC_AutoRefreshEnableCommand  - Enable auto refresh command \n
  *        kSDRAMC_AutoRefreshDisableCommand  - Disable auto refresh command
- * @return Command execution status.
- * All commands except the "initialize MRS command" and "precharge command"
- * return kStatus_Success directly.
- * For "initialize MRS command" and "precharge command"
- * return kStatus_Success when the command success else return kStatus_Fail.
  */
-status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
+void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
 
 /*!
  * @brief Enables/disables the write protection.
@@ -261,11 +255,11 @@
 }
 
 /*!
- * @brief Enables/disables the operation valid.
+ * @brief Enables/disables the valid operation.
  *
  * @param base SDRAM peripheral base address.
  * @param block The block which is selected.
- * @param enable True enable the operation valid, false disable the operation valid.
+ * @param enable True enable the valid operation; false disable the valid operation.
  */
 static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
 {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_sim.h"
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _FSL_SIM_H_
 #define _FSL_SIM_H_
@@ -36,7 +36,6 @@
 /*! @addtogroup sim */
 /*! @{*/
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -90,10 +89,10 @@
  * @brief Sets the USB voltage regulator setting.
  *
  * This function configures whether the USB voltage regulator is enabled in
- * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations
- * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable
+ * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations
+ * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable
  * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode,
- * please use:
+ * use:
  *
  * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower);
  *
@@ -103,16 +102,16 @@
 #endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
 
 /*!
- * @brief Get the unique identification register value.
+ * @brief Gets the unique identification register value.
  *
  * @param uid Pointer to the structure to save the UID value.
  */
 void SIM_GetUniqueId(sim_uid_t *uid);
 
 /*!
- * @brief Set the flash enable mode.
+ * @brief Sets the flash enable mode.
  *
- * @param mode The mode to set, see \ref _sim_flash_mode for mode details.
+ * @param mode The mode to set; see \ref _sim_flash_mode for mode details.
  */
 static inline void SIM_SetFlashMode(uint8_t mode)
 {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -29,6 +29,7 @@
  */
 
 #include "fsl_smc.h"
+#include "fsl_flash.h"
 
 #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
 void SMC_GetParam(SMC_Type *base, smc_param_t *param)
@@ -41,6 +42,39 @@
 }
 #endif /* FSL_FEATURE_SMC_HAS_PARAM */
 
+void SMC_PreEnterStopModes(void)
+{
+    flash_prefetch_speculation_status_t speculationStatus =
+    {
+        kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/
+        kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/
+    };
+
+    __disable_irq();
+    __ISB();
+
+    /*
+     * Before enter stop modes, the flash cache prefetch should be disabled.
+     * Otherwise the prefetch might be interrupted by stop, then the data and
+     * and instruction from flash are wrong.
+     */
+    FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
+}
+
+void SMC_PostExitStopModes(void)
+{
+    flash_prefetch_speculation_status_t speculationStatus =
+    {
+        kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/
+        kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/
+    };
+
+    FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
+
+    __enable_irq();
+    __ISB();
+}
+
 status_t SMC_SetPowerModeRun(SMC_Type *base)
 {
     uint8_t reg;
@@ -73,7 +107,9 @@
 {
     /* configure Normal Wait mode */
     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
     __WFI();
+    __ISB();
 
     return kStatus_Success;
 }
@@ -101,7 +137,9 @@
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter Stop mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -148,16 +186,12 @@
 
 status_t SMC_SetPowerModeVlpw(SMC_Type *base)
 {
-    /* Power mode transaction to VLPW can only happen in VLPR mode */
-    if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base))
-    {
-        return kStatus_Fail;
-    }
-
     /* configure VLPW mode */
     /* Set the SLEEPDEEP bit to enable deep sleep mode */
     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
     __WFI();
+    __ISB();
 
     return kStatus_Success;
 }
@@ -177,7 +211,9 @@
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter VLPS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -231,7 +267,9 @@
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter LLS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -345,7 +383,9 @@
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter LLS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -36,7 +36,6 @@
 /*! @addtogroup smc */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -44,8 +43,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SMC driver version 2.0.1. */
-#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief SMC driver version 2.0.3. */
+#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 /*!
@@ -54,14 +53,14 @@
 typedef enum _smc_power_mode_protection
 {
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
-    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */
 #endif
 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
-    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode.      */
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode.      */
 #endif                                             /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
-    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode.        */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode.        */
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
-    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode.        */
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode.        */
 #endif                                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
     kSMC_AllowPowerModeAll = (0U
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
@@ -107,10 +106,10 @@
  */
 typedef enum _smc_run_mode
 {
-    kSMC_RunNormal = 0U, /*!< normal RUN mode.             */
-    kSMC_RunVlpr = 2U,   /*!< Very-Low-Power RUN mode.     */
+    kSMC_RunNormal = 0U, /*!< Normal RUN mode.             */
+    kSMC_RunVlpr = 2U,   /*!< Very-low-power RUN mode.     */
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
-    kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
+    kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */
 #endif              /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
 } smc_run_mode_t;
 
@@ -120,12 +119,12 @@
 typedef enum _smc_stop_mode
 {
     kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
-    kSMC_StopVlps = 2U,   /*!< Very-Low-Power STOP mode.   */
+    kSMC_StopVlps = 2U,   /*!< Very-low-power STOP mode.   */
 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
-    kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode.      */
+    kSMC_StopLls = 3U, /*!< Low-leakage Stop mode.      */
 #endif                 /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
-    kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */
+    kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */
 #endif
 } smc_stop_mode_t;
 
@@ -155,7 +154,7 @@
 } smc_partial_stop_option_t;
 
 /*!
- * @brief SMC configuration status
+ * @brief SMC configuration status.
  */
 enum _smc_status
 {
@@ -190,7 +189,7 @@
 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
 /*!
- * @brief SMC Low-Leakage Stop power mode config
+ * @brief SMC Low-Leakage Stop power mode configuration.
  */
 typedef struct _smc_power_mode_lls_config
 {
@@ -205,7 +204,7 @@
 
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
 /*!
- * @brief SMC Very Low-Leakage Stop power mode config
+ * @brief SMC Very Low-Leakage Stop power mode configuration.
  */
 typedef struct _smc_power_mode_vlls_config
 {
@@ -242,10 +241,10 @@
  * @brief Gets the SMC version ID.
  *
  * This function gets the SMC version ID, including major version number,
- * minor version number and feature specification number.
+ * minor version number, and feature specification number.
  *
  * @param base SMC peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     Pointer to the version ID structure.
  */
 static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
 {
@@ -257,10 +256,10 @@
 /*!
  * @brief Gets the SMC parameter.
  *
- * This function gets the SMC parameter, including the enabled power mdoes.
+ * This function gets the SMC parameter including the enabled power mdoes.
  *
  * @param base SMC peripheral base address.
- * @param param         Pointer to SMC param structure.
+ * @param param         Pointer to the SMC param structure.
  */
 void SMC_GetParam(SMC_Type *base, smc_param_t *param);
 #endif
@@ -274,7 +273,7 @@
  * system level initialization stage. See the reference manual for details.
  * This register can only write once after the power reset.
  *
- * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * The allowed modes are passed as bit map. For example, to allow LLS and VLLS,
  * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps).
  * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
  *
@@ -289,13 +288,13 @@
 /*!
  * @brief Gets the current power mode status.
  *
- * This function  returns the current power mode stat. Once application
- * switches the power mode, it should always check the stat to check whether it
- * runs into the specified mode or not. An application  should  check
+ * This function  returns the current power mode status. After the application
+ * switches the power mode, it should always check the status to check whether it
+ * runs into the specified mode or not. The application  should  check
  * this mode before switching to a different mode. The system  requires that
  * only certain modes can switch to other specific modes. See the
  * reference manual for details and the smc_power_state_t for information about
- * the power stat.
+ * the power status.
  *
  * @param base SMC peripheral base address.
  * @return Current power mode status.
@@ -306,7 +305,45 @@
 }
 
 /*!
- * @brief Configure the system to RUN power mode.
+ * @brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with @ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void);
+
+/*!
+ * @brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+static inline void SMC_PreEnterWaitModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with @ref SMC_PreEnterWaitModes.
+ */
+static inline void SMC_PostExitWaitModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Configures the system to RUN power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -315,7 +352,7 @@
 
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
 /*!
- * @brief Configure the system to HSRUN power mode.
+ * @brief Configures the system to HSRUN power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -324,7 +361,7 @@
 #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
 
 /*!
- * @brief Configure the system to WAIT power mode.
+ * @brief Configures the system to WAIT power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -332,7 +369,7 @@
 status_t SMC_SetPowerModeWait(SMC_Type *base);
 
 /*!
- * @brief Configure the system to Stop power mode.
+ * @brief Configures the system to Stop power mode.
  *
  * @param base SMC peripheral base address.
  * @param  option Partial Stop mode option.
@@ -342,7 +379,7 @@
 
 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
 /*!
- * @brief Configure the system to VLPR power mode.
+ * @brief Configures the system to VLPR power mode.
  *
  * @param base SMC peripheral base address.
  * @param  wakeupMode Enter Normal Run mode if true, else stay in VLPR mode.
@@ -351,7 +388,7 @@
 status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode);
 #else
 /*!
- * @brief Configure the system to VLPR power mode.
+ * @brief Configures the system to VLPR power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -360,7 +397,7 @@
 #endif /* FSL_FEATURE_SMC_HAS_LPWUI */
 
 /*!
- * @brief Configure the system to VLPW power mode.
+ * @brief Configures the system to VLPW power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -368,7 +405,7 @@
 status_t SMC_SetPowerModeVlpw(SMC_Type *base);
 
 /*!
- * @brief Configure the system to VLPS power mode.
+ * @brief Configures the system to VLPS power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -379,7 +416,7 @@
 #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
      (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
 /*!
- * @brief Configure the system to LLS power mode.
+ * @brief Configures the system to LLS power mode.
  *
  * @param base SMC peripheral base address.
  * @param  config The LLS power mode configuration structure
@@ -388,7 +425,7 @@
 status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config);
 #else
 /*!
- * @brief Configure the system to LLS power mode.
+ * @brief Configures the system to LLS power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -399,7 +436,7 @@
 
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
 /*!
- * @brief Configure the system to VLLS power mode.
+ * @brief Configures the system to VLLS power mode.
  *
  * @param base SMC peripheral base address.
  * @param  config The VLLS power mode configuration structure.

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sysmpu.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config)
+{
+    assert(config);
+    uint8_t count;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Un-gate SYSMPU clock */
+    CLOCK_EnableClock(g_sysmpuClock[0]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Initializes the regions. */
+    for (count = 1; count < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; count++)
+    {
+        base->WORD[count][3] = 0; /* VLD/VID+PID. */
+        base->WORD[count][0] = 0; /* Start address. */
+        base->WORD[count][1] = 0; /* End address. */
+        base->WORD[count][2] = 0; /* Access rights. */
+        base->RGDAAC[count] = 0;  /* Alternate access rights. */
+    }
+
+    /* SYSMPU configure. */
+    while (config)
+    {
+        SYSMPU_SetRegionConfig(base, &(config->regionConfig));
+        config = config->next;
+    }
+    /* Enable SYSMPU. */
+    SYSMPU_Enable(base, true);
+}
+
+void SYSMPU_Deinit(SYSMPU_Type *base)
+{
+    /* Disable SYSMPU. */
+    SYSMPU_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the clock. */
+    CLOCK_DisableClock(g_sysmpuClock[0]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform)
+{
+    assert(hardwareInform);
+
+    uint32_t cesReg = base->CESR;
+
+    hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT;
+    hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT;
+    hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT);
+}
+
+void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig)
+{
+    assert(regionConfig);
+    assert(regionConfig->regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+
+    uint32_t wordReg = 0;
+    uint8_t msPortNum;
+    uint8_t regNumber = regionConfig->regionNum;
+
+    /* The start and end address of the region descriptor. */
+    base->WORD[regNumber][0] = regionConfig->startAddress;
+    base->WORD[regNumber][1] = regionConfig->endAddress;
+
+    /* Set the privilege rights for master 0 ~ master 3. */
+    for (msPortNum = 0; msPortNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum++)
+    {
+        wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER(
+            msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
+                        (uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
+
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+        wordReg |=
+            SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+    }
+
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT
+    /* Set the normal read write rights for master 4 ~ master 7. */
+    for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT;
+         msPortNum++)
+    {
+        wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum,
+            ((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U |
+            (uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable));
+    }
+#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */
+
+    /* Set region descriptor access rights. */
+    base->WORD[regNumber][2] = wordReg;
+
+    wordReg = SYSMPU_WORD_VLD(1);
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    wordReg |= SYSMPU_WORD_PID(regionConfig->processIdentifier) | SYSMPU_WORD_PIDMASK(regionConfig->processIdMask);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+
+    base->WORD[regNumber][3] = wordReg;
+}
+
+void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
+{
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+
+    base->WORD[regionNum][0] = startAddr;
+    base->WORD[regionNum][1] = endAddr;
+}
+
+void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const sysmpu_rwxrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+    assert(masterNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
+
+    uint32_t mask = SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    mask |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
+#endif
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |= SYSMPU_REGION_RWXRIGHTS_MASTER(
+        masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    right |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
+void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const sysmpu_rwrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+    assert(masterNum >= SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
+    assert(masterNum <= (FSL_FEATURE_SYSMPU_MASTER_COUNT - 1));
+
+    uint32_t mask = SYSMPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |=
+        SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
+
+bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum)
+{
+    uint8_t sperr;
+
+    sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1));
+
+    return (sperr != 0) ? true : false;
+}
+
+void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform)
+{
+    assert(errInform);
+
+    uint16_t value;
+    uint32_t cesReg;
+
+    /* Error address. */
+    errInform->address = base->SP[slaveNum].EAR;
+
+    /* Error detail information. */
+    value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT;
+    if (!value)
+    {
+        errInform->accessControl = kSYSMPU_NoRegionHit;
+    }
+    else if (!(value & (uint16_t)(value - 1)))
+    {
+        errInform->accessControl = kSYSMPU_NoneOverlappRegion;
+    }
+    else
+    {
+        errInform->accessControl = kSYSMPU_OverlappRegion;
+    }
+
+    value = base->SP[slaveNum].EDR;
+    errInform->master = (uint32_t)((value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT);
+    errInform->attributes = (sysmpu_err_attributes_t)((value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT);
+    errInform->accessType = (sysmpu_err_access_type_t)((value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT);
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_SHIFT);
+#endif
+
+    /* Clears error slave port bit. */
+    cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT);
+    base->CESR = cesReg;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SYSMPU_H_
+#define _FSL_SYSMPU_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sysmpu
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SYSMPU driver version 2.2.0. */
+#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief define the start master port with read and write attributes. */
+#define SYSMPU_MASTER_RWATTRIBUTE_START_PORT (4)
+
+/*! @brief SYSMPU the bit shift for masters with privilege rights: read write and execute. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
+
+/*! @brief SYSMPU masters with read, write and execute rights bit mask. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights bit width. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
+
+/*! @brief SYSMPU masters with read, write and execute rights priority setting. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable bit shift. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH)
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable bit mask. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable setting. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
+
+/*! @brief SYSMPU masters with normal read write permission bit shift. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24)
+
+/*! @brief SYSMPU masters with normal read write rights bit mask. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief SYSMPU masters with normal read write rights priority setting. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n))
+
+
+/*! @brief Describes the number of SYSMPU regions. */
+typedef enum _sysmpu_region_total_num
+{
+    kSYSMPU_8Regions = 0x0U,  /*!< SYSMPU supports 8 regions.  */
+    kSYSMPU_12Regions = 0x1U, /*!< SYSMPU supports 12 regions. */
+    kSYSMPU_16Regions = 0x2U  /*!< SYSMPU supports 16 regions. */
+} sysmpu_region_total_num_t;
+
+/*! @brief SYSMPU slave port number. */
+typedef enum _sysmpu_slave
+{
+    kSYSMPU_Slave0 = 0U, /*!< SYSMPU slave port 0. */
+    kSYSMPU_Slave1 = 1U, /*!< SYSMPU slave port 1. */
+    kSYSMPU_Slave2 = 2U, /*!< SYSMPU slave port 2. */
+    kSYSMPU_Slave3 = 3U, /*!< SYSMPU slave port 3. */
+    kSYSMPU_Slave4 = 4U, /*!< SYSMPU slave port 4. */
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 5
+    kSYSMPU_Slave5 = 5U, /*!< SYSMPU slave port 5. */
+#endif
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 6
+    kSYSMPU_Slave6 = 6U, /*!< SYSMPU slave port 6. */
+#endif
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 7
+    kSYSMPU_Slave7 = 7U, /*!< SYSMPU slave port 7. */
+#endif
+} sysmpu_slave_t;
+
+/*! @brief SYSMPU error access control detail. */
+typedef enum _sysmpu_err_access_control
+{
+    kSYSMPU_NoRegionHit = 0U,        /*!< No region hit error. */
+    kSYSMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
+    kSYSMPU_OverlappRegion = 2U      /*!< Access overlapping region error. */
+} sysmpu_err_access_control_t;
+
+/*! @brief SYSMPU error access type. */
+typedef enum _sysmpu_err_access_type
+{
+    kSYSMPU_ErrTypeRead = 0U, /*!< SYSMPU error access type --- read.  */
+    kSYSMPU_ErrTypeWrite = 1U /*!< SYSMPU error access type --- write. */
+} sysmpu_err_access_type_t;
+
+/*! @brief SYSMPU access error attributes.*/
+typedef enum _sysmpu_err_attributes
+{
+    kSYSMPU_InstructionAccessInUserMode = 0U,       /*!< Access instruction error in user mode. */
+    kSYSMPU_DataAccessInUserMode = 1U,              /*!< Access data error in user mode. */
+    kSYSMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
+    kSYSMPU_DataAccessInSupervisorMode = 3U         /*!< Access data error in supervisor mode. */
+} sysmpu_err_attributes_t;
+
+/*! @brief SYSMPU access rights in supervisor mode for bus master 0 ~ 3. */
+typedef enum _sysmpu_supervisor_access_rights
+{
+    kSYSMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorReadExecute = 1U,      /*!< Read and execute operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorReadWrite = 2U,        /*!< Read write operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorEqualToUsermode = 3U   /*!< Access permission equal to user mode. */
+} sysmpu_supervisor_access_rights_t;
+
+/*! @brief SYSMPU access rights in user mode for bus master 0 ~ 3. */
+typedef enum _sysmpu_user_access_rights
+{
+    kSYSMPU_UserNoAccessRights = 0U,  /*!< No access allowed in user mode.  */
+    kSYSMPU_UserExecute = 1U,         /*!< Execute operation is allowed in user mode. */
+    kSYSMPU_UserWrite = 2U,           /*!< Write operation is allowed in user mode. */
+    kSYSMPU_UserWriteExecute = 3U,    /*!< Write and execute operations are allowed in user mode. */
+    kSYSMPU_UserRead = 4U,            /*!< Read is allowed in user mode. */
+    kSYSMPU_UserReadExecute = 5U,     /*!< Read and execute operations are allowed in user mode. */
+    kSYSMPU_UserReadWrite = 6U,       /*!< Read and write operations are allowed in user mode. */
+    kSYSMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
+} sysmpu_user_access_rights_t;
+
+/*! @brief SYSMPU hardware basic information. */
+typedef struct _sysmpu_hardware_info
+{
+    uint8_t hardwareRevisionLevel;         /*!< Specifies the SYSMPU's hardware and definition reversion level. */
+    uint8_t slavePortsNumbers;             /*!< Specifies the number of slave ports connected to SYSMPU. */
+    sysmpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
+} sysmpu_hardware_info_t;
+
+/*! @brief SYSMPU detail error access information. */
+typedef struct _sysmpu_access_err_info
+{
+    uint32_t master;                        /*!< Access error master. */
+    sysmpu_err_attributes_t attributes;        /*!< Access error attributes. */
+    sysmpu_err_access_type_t accessType;       /*!< Access error type. */
+    sysmpu_err_access_control_t accessControl; /*!< Access error control. */
+    uint32_t address;                       /*!< Access error address. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processorIdentification; /*!< Access error processor identification. */
+#endif                               /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_access_err_info_t;
+
+/*! @brief SYSMPU read/write/execute rights control for bus master 0 ~ 3. */
+typedef struct _sysmpu_rwxrights_master_access_control
+{
+    sysmpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
+    sysmpu_user_access_rights_t userAccessRights;        /*!< Master access rights in user mode. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    bool processIdentifierEnable; /*!< Enables or disables process identifier. */
+#endif                            /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_rwxrights_master_access_control_t;
+
+/*! @brief SYSMPU read/write access control for bus master 4 ~ 7. */
+typedef struct _sysmpu_rwrights_master_access_control
+{
+    bool writeEnable; /*!< Enables or disables write permission. */
+    bool readEnable;  /*!< Enables or disables read permission.  */
+} sysmpu_rwrights_master_access_control_t;
+
+/*!
+ * @brief SYSMPU region configuration structure.
+ *
+ * This structure is used to configure the regionNum region.
+ * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
+ * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
+ * are used to configure the high master 4 ~ 7 with the normal read write permission.
+ * The master port assignment is the chip configuration. Normally, the core is the
+ * master 0, debugger is the master 1.
+ * Note that the SYSMPU assigns a priority scheme where the debugger is treated as the highest
+ * priority master followed by the core and then all the remaining masters.
+ * SYSMPU protection does not allow writes from the core to affect the "regionNum 0" start
+ * and end address nor the permissions associated with the debugger. It can only write
+ * the permission fields associated with the other masters. This protection guarantees that
+ * the debugger always has access to the entire address space and those rights can't
+ * be changed by the core or any other bus master. Prepare
+ * the region configuration when regionNum is 0.
+ */
+typedef struct _sysmpu_region_config
+{
+    uint32_t regionNum;    /*!< SYSMPU region number, range form 0 ~ FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. */
+    uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by SYSMPU. The actual
+                              start address is 0-modulo-32 byte address.  */
+    uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. The actual end
+                          address is 31-modulo-32 byte address. */
+    sysmpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
+    sysmpu_rwrights_master_access_control_t accessRights2[4];  /*!< Masters with normal read write rights setting. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
+    uint8_t
+        processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
+#endif                 /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_region_config_t;
+
+/*!
+ * @brief The configuration structure for the SYSMPU initialization.
+ *
+ * This structure is used when calling the SYSMPU_Init function.
+ */
+typedef struct _sysmpu_config
+{
+    sysmpu_region_config_t regionConfig; /*!< Region access permission. */
+    struct _sysmpu_config *next;         /*!< Pointer to the next structure. */
+} sysmpu_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SYSMPU with the user configuration structure.
+ *
+ * This function configures the SYSMPU module with the user-defined configuration.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ */
+void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config);
+
+/*!
+ * @brief Deinitializes the SYSMPU regions.
+ *
+ * @param base     SYSMPU peripheral base address.
+ */
+void SYSMPU_Deinit(SYSMPU_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the SYSMPU globally.
+ *
+ * Call this API to enable or disable the SYSMPU module.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param enable   True enable SYSMPU, false disable SYSMPU.
+ */
+static inline void SYSMPU_Enable(SYSMPU_Type *base, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the SYSMPU globally. */
+        base->CESR |= SYSMPU_CESR_VLD_MASK;
+    }
+    else
+    { /* Disable the SYSMPU globally. */
+        base->CESR &= ~SYSMPU_CESR_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the SYSMPU for a special region.
+ *
+ * When SYSMPU is enabled, call this API to disable an unused region
+ * of an enabled SYSMPU. Call this API to minimize the power dissipation.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param number   SYSMPU region number.
+ * @param enable   True enable the special region SYSMPU, false disable the special region SYSMPU.
+ */
+static inline void SYSMPU_RegionEnable(SYSMPU_Type *base, uint32_t number, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the #number region SYSMPU. */
+        base->WORD[number][3] |= SYSMPU_WORD_VLD_MASK;
+    }
+    else
+    { /* Disable the #number region SYSMPU. */
+        base->WORD[number][3] &= ~SYSMPU_WORD_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Gets the SYSMPU basic hardware information.
+ *
+ * @param base           SYSMPU peripheral base address.
+ * @param hardwareInform The pointer to the SYSMPU hardware information structure. See "sysmpu_hardware_info_t".
+ */
+void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform);
+
+/*!
+ * @brief Sets the SYSMPU region.
+ *
+ * Note: Due to the SYSMPU protection, the region number 0 does not allow writes from
+ * core to affect the start and end address nor the permissions associated with
+ * the debugger. It can only write the permission fields associated
+ * with the other masters.
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionConfig  The pointer to the SYSMPU user configuration structure. See "sysmpu_region_config_t".
+ */
+void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig);
+
+/*!
+ * @brief Sets the region start and end address.
+ *
+ * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by SYSMPU.
+ * The actual start address by SYSMPU is 0-modulo-32 byte address.
+ * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU.
+ * The end address used by the SYSMPU is 31-modulo-32 byte address.
+ * Note: Due to the SYSMPU protection, the startAddr and endAddr can't be
+ * changed by the core when regionNum is 0.
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. The range is from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param startAddr     Region start address.
+ * @param endAddr       Region end address.
+ */
+void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
+
+/*!
+ * @brief Sets the SYSMPU region access rights for masters with read, write, and execute rights.
+ * The SYSMPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The privilege rights masters have the read, write, and execute access rights.
+ * Except the normal read and write rights, the execute rights are also
+ * allowed for these masters. The privilege rights masters normally range from
+ * bus masters 0 - 3. However, the maximum master number is device-specific.
+ * See the "SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
+ * The normal rights masters access rights control see
+ * "SYSMPU_SetRegionRwMasterAccessRights()".
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. Should range from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     SYSMPU bus master number. Should range from 0 to
+ * SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
+ * @param accessRights  The pointer to the SYSMPU access rights configuration. See "sysmpu_rwxrights_master_access_control_t".
+ */
+void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const sysmpu_rwxrights_master_access_control_t *accessRights);
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
+/*!
+ * @brief Sets the SYSMPU region access rights for masters with read and write rights.
+ * The SYSMPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The normal rights masters only have the read and write access permissions.
+ * The privilege rights access control see "SYSMPU_SetRegionRwxMasterAccessRights".
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. The range is from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     SYSMPU bus master number. Should range from SYSMPU_MASTER_RWATTRIBUTE_START_PORT
+ * to ~ FSL_FEATURE_SYSMPU_MASTER_COUNT - 1.
+ * @param accessRights  The pointer to the SYSMPU access rights configuration. See "sysmpu_rwrights_master_access_control_t".
+ */
+void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const sysmpu_rwrights_master_access_control_t *accessRights);
+#endif  /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
+/*!
+ * @brief Gets the numbers of slave ports where errors occur.
+ *
+ * @param base       SYSMPU peripheral base address.
+ * @param slaveNum   SYSMPU slave port number.
+ * @return The slave ports error status.
+ *         true  - error happens in this slave port.
+ *         false - error didn't happen in this slave port.
+ */
+bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum);
+
+/*!
+ * @brief Gets the SYSMPU detailed error access information.
+ *
+ * @param base       SYSMPU peripheral base address.
+ * @param slaveNum   SYSMPU slave port number.
+ * @param errInform  The pointer to the SYSMPU access error information. See "sysmpu_access_err_info_t".
+ */
+void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SYSMPU_H_ */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -53,8 +53,10 @@
 /*! @brief Pointers to TPM bases for each instance. */
 static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to TPM clocks for each instance. */
 static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -82,8 +84,10 @@
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the module clock */
     CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
     /* TPM reset is available on certain SoC's */
@@ -118,8 +122,10 @@
 {
     /* Stop the counter */
     base->SC &= ~TPM_SC_CMOD_MASK;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the TPM clock */
     CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void TPM_GetDefaultConfig(tpm_config_t *config)
@@ -162,6 +168,12 @@
     assert(pwmFreq_Hz);
     assert(numOfChnls);
     assert(srcClock_Hz);
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if(mode == kTPM_CombinedPwm)
+    {
+        assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
+    }
+#endif
 
     uint32_t mod;
     uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK)));
@@ -169,8 +181,12 @@
     uint8_t i;
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
-    base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
+    {
+        /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
 #endif
 
     switch (mode)
@@ -351,6 +367,12 @@
                             uint8_t dutyCyclePercent)
 {
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if(currentPwmMode == kTPM_CombinedPwm)
+    {
+        assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
+    }
+#endif
 
     uint16_t cnv, mod;
 
@@ -401,7 +423,7 @@
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlNumber].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -424,16 +446,24 @@
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode for channel 0 or 1*/
-    if ((chnlNumber == 0) || (chnlNumber == 1))
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if ((chnlNumber == 0) || (chnlNumber == 1))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
-    /* Clear the combine bit for chnlNumber */
-    base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2));
+        /* The TPM's COMBINE register required to be effective */
+    if( FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base) )
+    {
+        /* Clear the combine bit for chnlNumber */
+        base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2));
+    }
 #endif
 
     /* When switching mode, disable channel first  */
@@ -464,10 +494,14 @@
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode for channel 0 or 1 */
-    if ((chnlNumber == 0) || (chnlNumber == 1))
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1 */
+        if ((chnlNumber == 0) || (chnlNumber == 1))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
@@ -502,13 +536,19 @@
 {
     assert(edgeParam);
     assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2);
+    assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
 
     uint32_t reg;
-/* Clear quadrature Decoder mode for channel 0 or 1*/
+
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    if (chnlPairNumber == 0)
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if (chnlPairNumber == 0)
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
@@ -518,7 +558,7 @@
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlPairNumber * 2].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -527,7 +567,7 @@
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -589,6 +629,7 @@
 {
     assert(phaseAParams);
     assert(phaseBParams);
+    assert(FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base));
 
     base->CONTROLS[0].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,8 +37,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -526,6 +524,47 @@
 /*! @}*/
 
 /*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the MOD register.
+ *
+ * @note
+ * 1. This API allows the user to use the TPM module as a timer. Do not mix usage
+ *    of this API with TPM's PWM setup API's.
+ * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base TPM peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)
+{
+    base->MOD = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)
+{
+    return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT);
+}
+
+/*!
  * @name Timer Start and Stop
  * @{
  */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -36,7 +36,9 @@
     bool is_module_enabled = false;
     bool is_int_enabled = false;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Tsi0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     if (base->GENCS & TSI_GENCS_TSIEN_MASK)
     {
         is_module_enabled = true;
@@ -47,18 +49,31 @@
         is_int_enabled = true;
         TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable);
     }
-
-    TSI_SetHighThreshold(base, config->thresh);
-    TSI_SetLowThreshold(base, config->thresl);
-    TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
-    TSI_SetReferenceChargeCurrent(base, config->refchrg);
-    TSI_SetElectrodeChargeCurrent(base, config->extchrg);
-    TSI_SetNumberOfScans(base, config->nscn);
-    TSI_SetAnalogMode(base, config->mode);
-    TSI_SetOscVoltageRails(base, config->dvolt);
-    TSI_SetElectrodeSeriesResistor(base, config->resistor);
-    TSI_SetFilterBits(base, config->filter);
-
+    
+    if(config->mode == kTSI_AnalogModeSel_Capacitive)
+    {
+      TSI_SetHighThreshold(base, config->thresh);
+      TSI_SetLowThreshold(base, config->thresl);
+      TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
+      TSI_SetReferenceChargeCurrent(base, config->refchrg);
+      TSI_SetElectrodeChargeCurrent(base, config->extchrg);
+      TSI_SetNumberOfScans(base, config->nscn);
+      TSI_SetAnalogMode(base, config->mode);
+      TSI_SetOscVoltageRails(base, config->dvolt);   
+    }
+    else /* For noise modes */
+    {  
+      TSI_SetHighThreshold(base, config->thresh);
+      TSI_SetLowThreshold(base, config->thresl);
+      TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
+      TSI_SetReferenceChargeCurrent(base, config->refchrg);
+      TSI_SetNumberOfScans(base, config->nscn);
+      TSI_SetAnalogMode(base, config->mode);
+      TSI_SetOscVoltageRails(base, config->dvolt);
+      TSI_SetElectrodeSeriesResistor(base, config->resistor);
+      TSI_SetFilterBits(base, config->filter);  
+    }
+     
     if (is_module_enabled)
     {
         TSI_EnableModule(base, true);
@@ -74,7 +89,9 @@
     base->GENCS = 0U;
     base->DATA = 0U;
     base->TSHD = 0U;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(kCLOCK_Tsi0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig)
@@ -82,13 +99,11 @@
     userConfig->thresh = 0U;
     userConfig->thresl = 0U;
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_3;
 }
 
 void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig)
@@ -96,13 +111,11 @@
     userConfig->thresh = 400U;
     userConfig->thresl = 0U;
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_3;
 }
 
 void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff)
@@ -135,44 +148,56 @@
 
 void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_GlobalInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_TSIIEN_MASK;
+        regValue |= TSI_GENCS_TSIIEN_MASK;
     }
     if (mask & kTSI_OutOfRangeInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_ESOR_MASK;
+        regValue &= (~TSI_GENCS_ESOR_MASK);
     }
     if (mask & kTSI_EndOfScanInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_ESOR_MASK;
+        regValue |= TSI_GENCS_ESOR_MASK;
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }
 
 void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_GlobalInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_TSIIEN_MASK;
+        regValue &= (~TSI_GENCS_TSIIEN_MASK);
     }
     if (mask & kTSI_OutOfRangeInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_ESOR_MASK;
+        regValue |= TSI_GENCS_ESOR_MASK;
     }
     if (mask & kTSI_EndOfScanInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_ESOR_MASK;
+        regValue &= (~TSI_GENCS_ESOR_MASK);
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }
 
 void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_EndOfScanFlag)
     {
-        base->GENCS = (base->GENCS & ~(TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)) | TSI_GENCS_EOSF_MASK;
+        regValue |= TSI_GENCS_EOSF_MASK;
     }
     if (mask & kTSI_OutOfRangeFlag)
     {
-        base->GENCS = (base->GENCS & ~(TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)) | TSI_GENCS_OUTRGF_MASK;
+        regValue |= TSI_GENCS_OUTRGF_MASK;
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,10 +44,13 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief TSI driver version 2.0.0. */
-#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief TSI driver version */
+#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
 /*@}*/
 
+/*! @brief TSI status flags macro collection */
+#define ALL_FLAGS_MASK  (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)
+
 /*! @brief resistor bit shift in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT TSI_GENCS_EXTCHRG_SHIFT
 
@@ -57,11 +59,11 @@
 
 /*! @brief macro of clearing the resistor bit in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR \
-    ((uint32_t)((~TSI_GENCS_EXTCHRG_MASK) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
 
 /*! @brief macro of clearing the filter bits in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_FILTER_BITS_CLEAR \
-    ((uint32_t)((~TSI_GENCS_EXTCHRG_MASK) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
 
 /*!
  * @brief TSI number of scan intervals for each electrode.
@@ -286,13 +288,11 @@
  * The user configure is set to these values:
  * @code
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_1;
     userConfig->thresh = 0U;
     userConfig->thresl = 0U;
    @endcode
@@ -308,13 +308,11 @@
  * The user configure is set to these values:
  * @code
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_1;
     userConfig->thresh = 400U;
     userConfig->thresl = 0U;
    @endcode
@@ -417,7 +415,7 @@
 */
 static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_osc_prescaler_t prescaler)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_PS_MASK) | (TSI_GENCS_PS(prescaler));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_PS_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_PS(prescaler));
 }
 
 /*!
@@ -429,7 +427,7 @@
 */
 static inline void TSI_SetNumberOfScans(TSI_Type *base, tsi_n_consecutive_scans_t number)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_NSCN_MASK) | (TSI_GENCS_NSCN(number));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_NSCN_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_NSCN(number));
 }
 
 /*!
@@ -445,11 +443,11 @@
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_TSIEN_MASK; /* Enable module */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_TSIEN_MASK;    /* Enable module */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_TSIEN_MASK; /* Disable module */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_TSIEN_MASK); /* Disable module */
     }
 }
 
@@ -467,11 +465,11 @@
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_STPE_MASK; /* Module enabled in low power stop modes */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STPE_MASK;    /* Module enabled in low power stop modes */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_STPE_MASK; /* Module disabled in low power stop modes */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STPE_MASK); /* Module disabled in low power stop modes */
     }
 }
 
@@ -488,11 +486,11 @@
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_STM_MASK; /* Enable hardware trigger scan */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STM_MASK;    /* Enable hardware trigger scan */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_STM_MASK; /* Enable software trigger scan */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STM_MASK); /* Enable software trigger scan */
     }
 }
 
@@ -567,12 +565,12 @@
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
     }
     else
     {
-        base->GENCS &=
-            ~TSI_GENCS_EOSDMEO_MASK; /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
+        base->GENCS =
+            (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_EOSDMEO_MASK); /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
     }
 }
 #endif /* End of (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)*/
@@ -625,7 +623,7 @@
 */
 static inline void TSI_SetAnalogMode(TSI_Type *base, tsi_analog_mode_t mode)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_MODE_MASK) | (TSI_GENCS_MODE(mode));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_MODE_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_MODE(mode));
 }
 
 /*!
@@ -648,7 +646,7 @@
 */
 static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_osc_charge_current_t current)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_REFCHRG_MASK) | (TSI_GENCS_REFCHRG(current));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_REFCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_REFCHRG(current));
 }
 
 /*!
@@ -660,7 +658,7 @@
 */
 static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_osc_charge_current_t current)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_EXTCHRG_MASK) | (TSI_GENCS_EXTCHRG(current));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_EXTCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_EXTCHRG(current));
 }
 
 /*!
@@ -672,7 +670,7 @@
 */
 static inline void TSI_SetOscVoltageRails(TSI_Type *base, tsi_osc_voltage_rails_t dvolt)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_DVOLT_MASK) | (TSI_GENCS_DVOLT(dvolt));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_DVOLT_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_DVOLT(dvolt));
 }
 
 /*!

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,10 +37,12 @@
 /* UART transfer state. */
 enum _uart_tansfer_states
 {
-    kUART_TxIdle, /* TX idle. */
-    kUART_TxBusy, /* TX busy. */
-    kUART_RxIdle, /* RX idle. */
-    kUART_RxBusy  /* RX busy. */
+    kUART_TxIdle,         /* TX idle. */
+    kUART_TxBusy,         /* TX busy. */
+    kUART_RxIdle,         /* RX idle. */
+    kUART_RxBusy,         /* RX busy. */
+    kUART_RxFramingError, /* Rx framing error */
+    kUART_RxParityError   /* Rx parity error */
 };
 
 /* Typedef for interrupt handler. */
@@ -138,8 +140,10 @@
 
 /* Array of UART IRQ number. */
 static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of UART clock name. */
 static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* UART ISR for transactional APIs. */
 static uart_isr_t s_uartIsr;
@@ -169,6 +173,8 @@
 
 static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
 {
+    assert(handle);
+
     size_t size;
 
     if (handle->rxRingBufferTail > handle->rxRingBufferHead)
@@ -185,6 +191,8 @@
 
 static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
 {
+    assert(handle);
+
     bool full;
 
     if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
@@ -199,36 +207,72 @@
     return full;
 }
 
-void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
 {
     assert(config);
+    assert(config->baudRate_Bps);
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
     assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
     assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
 #endif
 
-    uint16_t sbr;
-    uint8_t temp;
+    uint16_t sbr = 0;
+    uint8_t temp = 0;
+    uint32_t baudDiff = 0;
+
+    /* Calculate the baud rate modulo divisor, sbr*/
+    sbr = srcClock_Hz / (config->baudRate_Bps * 16);
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0)
+    {
+        sbr = 1;
+    }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* Determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    uint32_t tempBaud = 0;
+
+    uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr;
 
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+    baudDiff =
+        (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
+
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+    {
+        baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+        sbr++;
+    }
+#endif
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable uart clock */
     CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Disable UART TX RX before setting. */
     base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
 
-    /* Calculate the baud rate modulo divisor, sbr*/
-    sbr = srcClock_Hz / (config->baudRate_Bps * 16);
-
     /* Write the sbr value to the BDH and BDL registers*/
     base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
     base->BDL = (uint8_t)sbr;
 
 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
-    /* Determine if a fractional divider is needed to fine tune closer to the
-     * desired baud, each value of brfa is in 1/32 increments,
-     * hence the multiply-by-32. */
-    uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr;
-
     /* Write the brfa value to the register*/
     base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
 #endif
@@ -274,6 +318,8 @@
     }
 
     base->C2 = temp;
+
+    return kStatus_Success;
 }
 
 void UART_Deinit(UART_Type *base)
@@ -292,8 +338,10 @@
     /* Disable the module. */
     base->C2 = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable uart clock */
     CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void UART_GetDefaultConfig(uart_config_t *config)
@@ -313,61 +361,101 @@
     config->enableRx = false;
 }
 
-void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
-    uint16_t sbr;
-    uint8_t oldCtrl;
+    assert(baudRate_Bps);
 
-    /* Store C2 before disable Tx and Rx */
-    oldCtrl = base->C2;
-
-    /* Disable UART TX RX before setting. */
-    base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+    uint16_t sbr = 0;
+    uint32_t baudDiff = 0;
+    uint8_t oldCtrl;
 
     /* Calculate the baud rate modulo divisor, sbr*/
     sbr = srcClock_Hz / (baudRate_Bps * 16);
-
-    /* Write the sbr value to the BDH and BDL registers*/
-    base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
-    base->BDL = (uint8_t)sbr;
-
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0)
+    {
+        sbr = 1;
+    }
 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
     /* Determine if a fractional divider is needed to fine tune closer to the
      * desired baud, each value of brfa is in 1/32 increments,
      * hence the multiply-by-32. */
-    uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr;
+    uint32_t tempBaud = 0;
+
+    uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr;
 
-    /* Write the brfa value to the register*/
-    base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+    baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+    {
+        baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+        sbr++;
+    }
 #endif
 
-    /* Restore C2. */
-    base->C2 = oldCtrl;
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff < ((baudRate_Bps / 100) * 3))
+    {
+        /* Store C2 before disable Tx and Rx */
+        oldCtrl = base->C2;
+
+        /* Disable UART TX RX before setting. */
+        base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+
+        /* Write the sbr value to the BDH and BDL registers*/
+        base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+        base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+        /* Write the brfa value to the register*/
+        base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
+#endif
+        /* Restore C2. */
+        base->C2 = oldCtrl;
+
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
 }
 
 void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
 {
+    mask &= kUART_AllInterruptsEnable;
+
     /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
      */
-    base->BDH |= (mask & 0xFF);
-    base->C2 |= ((mask >> 8) & 0xFF);
-    base->C3 |= ((mask >> 16) & 0xFF);
+    base->BDH |= mask;
+    base->C2 |= (mask >> 8);
+    base->C3 |= (mask >> 16);
 
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    base->CFIFO |= ((mask >> 24) & 0xFF);
+    base->CFIFO |= (mask >> 24);
 #endif
 }
 
 void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
 {
+    mask &= kUART_AllInterruptsEnable;
+
     /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
      */
-    base->BDH &= ~(mask & 0xFF);
-    base->C2 &= ~((mask >> 8) & 0xFF);
-    base->C3 &= ~((mask >> 16) & 0xFF);
+    base->BDH &= ~mask;
+    base->C2 &= ~(mask >> 8);
+    base->C3 &= ~(mask >> 16);
 
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    base->CFIFO &= ~((mask >> 24) & 0xFF);
+    base->CFIFO &= ~(mask >> 24);
 #endif
 }
 
@@ -381,7 +469,7 @@
     temp |= ((uint32_t)(base->CFIFO) << 24);
 #endif
 
-    return temp;
+    return temp & kUART_AllInterruptsEnable;
 }
 
 uint32_t UART_GetStatusFlags(UART_Type *base)
@@ -418,14 +506,24 @@
     base->SFIFO = (uint8_t)(mask >> 24);
 #endif
 
-    if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag |
-                kUART_ParityErrorFlag))
+    if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag))
     {
         /* Read base->D to clear the flags. */
         (void)base->S1;
         (void)base->D;
     }
 
+    if (mask & kUART_RxOverrunFlag)
+    {
+        /* Read base->D to clear the flags and Flush all data in FIFO. */
+        (void)base->S1;
+        (void)base->D;
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+    }
+
     /* If some flags still pending. */
     if (mask & UART_GetStatusFlags(base))
     {
@@ -457,6 +555,8 @@
 
 static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking write data API assume user have ensured there is enough space in
@@ -469,6 +569,8 @@
 
 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     uint32_t statusFlag;
 
     while (length--)
@@ -509,6 +611,8 @@
 
 static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking read data API assume user have ensured there is enough space in
@@ -558,7 +662,6 @@
     s_uartHandle[instance] = handle;
 
     s_uartIsr = UART_TransferHandleIRQ;
-
     /* Enable interrupt in NVIC. */
     EnableIRQ(s_uartIRQ[instance]);
 }
@@ -566,17 +669,21 @@
 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
 {
     assert(handle);
+    assert(ringBuffer);
 
     /* Setup the ringbuffer address */
-    if (ringBuffer)
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    UART_EnableInterrupts(
+        base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable);
+    /* Enable parity error interrupt when parity mode is enable*/
+    if (UART_C1_PE_MASK & base->C1)
     {
-        handle->rxRingBuffer = ringBuffer;
-        handle->rxRingBufferSize = ringBufferSize;
-        handle->rxRingBufferHead = 0U;
-        handle->rxRingBufferTail = 0U;
-
-        /* Enable the interrupt to accept the data when user need the ring buffer. */
-        UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+        UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
     }
 }
 
@@ -586,7 +693,13 @@
 
     if (handle->rxState == kUART_RxIdle)
     {
-        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
     }
 
     handle->rxRingBuffer = NULL;
@@ -597,13 +710,12 @@
 
 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
 {
-    status_t status;
+    assert(handle);
+    assert(xfer);
+    assert(xfer->dataSize);
+    assert(xfer->data);
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
+    status_t status;
 
     /* Return error if current TX busy. */
     if (kUART_TxBusy == handle->txState)
@@ -628,6 +740,8 @@
 
 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable);
 
     handle->txDataSize = 0;
@@ -636,16 +750,14 @@
 
 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->txDataSizeAll - handle->txDataSize;
 
     return kStatus_Success;
@@ -656,6 +768,11 @@
                                          uart_transfer_t *xfer,
                                          size_t *receivedBytes)
 {
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
     uint32_t i;
     status_t status;
     /* How many bytes to copy from ring buffer to user memory. */
@@ -664,13 +781,6 @@
     size_t bytesToReceive;
     /* How many bytes currently have received. */
     size_t bytesCurrentReceived;
-    uint32_t regPrimask = 0U;
-
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
 
     /* How to get data:
        1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
@@ -694,8 +804,8 @@
         /* If RX ring buffer is used. */
         if (handle->rxRingBuffer)
         {
-            /* Disable IRQ, protect ring buffer. */
-            regPrimask = DisableGlobalIRQ();
+            /* Disable UART RX IRQ, protect ring buffer. */
+            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
 
             /* How many bytes in RX ring buffer currently. */
             bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
@@ -733,8 +843,8 @@
                 handle->rxState = kUART_RxBusy;
             }
 
-            /* Enable IRQ if previously enabled. */
-            EnableGlobalIRQ(regPrimask);
+            /* Enable UART RX IRQ if previously enabled. */
+            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
 
             /* Call user callback since all data are received. */
             if (0 == bytesToReceive)
@@ -753,8 +863,14 @@
             handle->rxDataSizeAll = bytesToReceive;
             handle->rxState = kUART_RxBusy;
 
-            /* Enable RX interrupt. */
-            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+            /* Enable RX/Rx overrun/framing error interrupt. */
+            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                            kUART_FramingErrorInterruptEnable);
+            /* Enable parity error interrupt when parity mode is enable*/
+            if (UART_C1_PE_MASK & base->C1)
+            {
+                UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
+            }
         }
 
         /* Return the how many bytes have read. */
@@ -771,11 +887,19 @@
 
 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
     if (!handle->rxRingBuffer)
     {
         /* Disable RX interrupt. */
-        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
     }
 
     handle->rxDataSize = 0U;
@@ -784,6 +908,9 @@
 
 status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
@@ -801,17 +928,67 @@
 
 void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     uint8_t count;
     uint8_t tempCount;
 
-    assert(handle);
+    /* If RX framing error */
+    if (UART_S1_FE_MASK & base->S1)
+    {
+        /* Read base->D to clear framing error flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState = kUART_RxFramingError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
+        }
+    }
+
+    /* If RX parity error */
+    if (UART_S1_PF_MASK & base->S1)
+    {
+        /* Read base->D to clear parity error flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState = kUART_RxParityError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
+        }
+    }
 
     /* If RX overrun. */
     if (UART_S1_OR_MASK & base->S1)
     {
-        /* Read base->D, otherwise the RX does not work. */
-        (void)base->D;
-
+        /* Read base->D to clear overrun flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
         /* Trigger callback. */
         if (handle->callback)
         {
@@ -898,16 +1075,38 @@
                 }
             }
         }
-        /* If no receive requst pending, stop RX interrupt. */
+
         else if (!handle->rxDataSize)
         {
-            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+            /* Disable RX interrupt/overrun interrupt/fram error interrupt */
+            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                             kUART_FramingErrorInterruptEnable);
+
+            /* Disable parity error interrupt when parity mode is enable*/
+            if (UART_C1_PE_MASK & base->C1)
+            {
+                UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+            }
         }
         else
         {
         }
     }
 
+    /* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */
+    if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) &&
+        (!handle->rxRingBuffer))
+    {
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
+    }
+
     /* Send data register empty and the interrupt is enabled. */
     if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK))
     {
@@ -952,7 +1151,7 @@
 
 void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
 {
-    /* TODO: To be implemented. */
+    /* To be implemented by User. */
 }
 
 #if defined(UART0)
@@ -992,7 +1191,6 @@
 {
     UART2_DriverIRQHandler();
 }
-
 #endif
 
 #if defined(UART3)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,16 +37,14 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief UART driver version 2.1.0. */
-#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief UART driver version 2.1.4. */
+#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
 /*@}*/
 
 /*! @brief Error codes for the UART driver. */
@@ -66,6 +64,8 @@
     kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10),         /*!< UART noise error. */
     kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11),       /*!< UART framing error. */
     kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12),        /*!< UART parity error. */
+    kStatus_UART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */
 };
 
 /*! @brief UART parity mode. */
@@ -103,10 +103,23 @@
     kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16),        /*!< Framing error flag interrupt. */
     kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16),         /*!< Parity error flag interrupt. */
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24),  /*!< TX FIFO overflow interrupt. */
-    kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24),  /*!< RX FIFO underflow interrupt. */
+    kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24),  /*!< RX FIFO overflow interrupt. */
+    kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24),  /*!< TX FIFO overflow interrupt. */
     kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
 #endif
+    kUART_AllInterruptsEnable =
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+        kUART_LinBreakInterruptEnable |
+#endif
+        kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable |
+        kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable |
+        kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable |
+        kUART_ParityErrorInterruptEnable
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        |
+        kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable | kUART_RxFifoUnderflowInterruptEnable
+#endif
+    ,
 };
 
 /*!
@@ -128,13 +141,16 @@
     kUART_ParityErrorFlag = (UART_S1_PF_MASK),          /*!< If parity enabled, sets upon parity error detection */
 #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
     kUART_LinBreakFlag =
-        (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when
-                                                           LIN break char detected and LIN circuit enabled */
+        (UART_S2_LBKDIF_MASK
+         << 8), /*!< LIN break detect interrupt flag, sets when
+                                                       LIN break char detected and LIN circuit enabled */
 #endif
-    kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,
-                                                                                 sets when active edge detected */
-    kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8),         /*!< Receiver Active Flag (RAF),
-                                                                                 sets at beginning of valid start bit */
+    kUART_RxActiveEdgeFlag =
+        (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,
+                                                                            sets when active edge detected */
+    kUART_RxActiveFlag =
+        (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF),
+                                                                        sets at beginning of valid start bit */
 #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
     kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16),    /*!< Noisy bit, sets if noise detected. */
     kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */
@@ -213,11 +229,11 @@
  */
 
 /*!
- * @brief Initializes a UART instance with user configuration structure and peripheral clock.
+ * @brief Initializes a UART instance with a user configuration structure and peripheral clock.
  *
  * This function configures the UART module with the user-defined settings. The user can configure the configuration
  * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
- * Example below shows how to use this API to configure UART.
+ * The example below shows how to use this API to configure UART.
  * @code
  *  uart_config_t uartConfig;
  *  uartConfig.baudRate_Bps = 115200U;
@@ -229,10 +245,12 @@
  * @endcode
  *
  * @param base UART peripheral base address.
- * @param config Pointer to user-defined configuration structure.
+ * @param config Pointer to the user-defined configuration structure.
  * @param srcClock_Hz UART clock source frequency in HZ.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Status UART initialize succeed
  */
-void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
 
 /*!
  * @brief Deinitializes a UART instance.
@@ -247,7 +265,7 @@
  * @brief Gets the default configuration structure.
  *
  * This function initializes the UART configuration structure to a default value. The default
- * values are:
+ * values are as follows.
  *   uartConfig->baudRate_Bps = 115200U;
  *   uartConfig->bitCountPerChar = kUART_8BitsPerChar;
  *   uartConfig->parityMode = kUART_ParityDisabled;
@@ -272,9 +290,11 @@
  *
  * @param base UART peripheral base address.
  * @param baudRate_Bps UART baudrate to be set.
- * @param srcClock_Hz UART clock source freqency in HZ.
+ * @param srcClock_Hz UART clock source freqency in Hz.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
  */
-void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
 
 /* @} */
 
@@ -284,12 +304,12 @@
  */
 
 /*!
- * @brief Get UART status flags.
+ * @brief Gets UART status flags.
  *
- * This function get all UART status flags, the flags are returned as the logical
- * OR value of the enumerators @ref _uart_flags. To check specific status,
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _uart_flags. To check a specific status,
  * compare the return value with enumerators in @ref _uart_flags.
- * For example, to check whether the TX is empty:
+ * For example, to check whether the TX is empty, do the following.
  * @code
  *     if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
  *     {
@@ -305,19 +325,19 @@
 /*!
  * @brief Clears status flags with the provided mask.
  *
- * This function clears UART status flags with a provided mask. Automatically cleared flag
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
  * can't be cleared by this function.
- * Some flags can only be cleared or set by hardware itself. These flags are:
+ * These flags can only be cleared or set by hardware.
  *    kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
  *    kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
  *    kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
- * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
  *
  * @param base UART peripheral base address.
- * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags.
+ * @param mask The status flags to be cleared; it is logical OR value of @ref _uart_flags.
  * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
  *         it is cleared automatically by hardware.
- * @retval kStatus_Success Status in the mask are cleared.
+ * @retval kStatus_Success Status in the mask is cleared.
  */
 status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
 
@@ -333,7 +353,7 @@
  *
  * This function enables the UART interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
- * For example, to enable TX empty interrupt and RX full interrupt:
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
  * @code
  *     UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
  * @endcode
@@ -348,7 +368,7 @@
  *
  * This function disables the UART interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
- * For example, to disable TX empty interrupt and RX full interrupt:
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
  * @code
  *     UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
  * @endcode
@@ -363,9 +383,9 @@
  *
  * This function gets the enabled UART interrupts. The enabled interrupts are returned
  * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check
- * specific interrupts enable status, compare the return value with enumerators
+ * a specific interrupts enable status, compare the return value with enumerators
  * in @ref _uart_interrupt_enable.
- * For example, to check whether TX empty interrupt is enabled:
+ * For example, to check whether TX empty interrupt is enabled, do the following.
  * @code
  *     uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
  *
@@ -394,7 +414,7 @@
  * This function returns the UART data register address, which is mainly used by DMA/eDMA.
  *
  * @param base UART peripheral base address.
- * @return UART data register address which are used both by transmitter and receiver.
+ * @return UART data register addresses which are used both by the transmitter and the receiver.
  */
 static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base)
 {
@@ -526,7 +546,7 @@
 /*!
  * @brief Reads the RX register directly.
  *
- * This function reads data from the TX register directly. The upper layer must
+ * This function reads data from the RX register directly. The upper layer must
  * ensure that the RX register is full or that the TX FIFO has data before calling this function.
  *
  * @param base UART peripheral base address.
@@ -543,7 +563,7 @@
  * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
  * to have room and writes data to the TX buffer.
  *
- * @note This function does not check whether all the data has been sent out to the bus.
+ * @note This function does not check whether all data is sent out to the bus.
  * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is
  * finished.
  *
@@ -557,15 +577,15 @@
  * @brief Read RX data register using a blocking method.
  *
  * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
- * have data and read data from the TX register.
+ * have data, and reads data from the TX register.
  *
  * @param base UART peripheral base address.
  * @param data Start address of the buffer to store the received data.
  * @param length Size of the buffer.
- * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data.
- * @retval kStatus_UART_NoiseError Noise error happened while receiving data.
- * @retval kStatus_UART_FramingError Framing error happened while receiving data.
- * @retval kStatus_UART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * @retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * @retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * @retval kStatus_UART_ParityError A parity error occurred while receiving data.
  * @retval kStatus_Success Successfully received all data.
  */
 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length);
@@ -600,16 +620,16 @@
  * This function sets up the RX ring buffer to a specific UART handle.
  *
  * When the RX ring buffer is used, data received are stored into the ring buffer even when the
- * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
  * in the ring buffer, the user can get the received data from the ring buffer directly.
  *
  * @note When using the RX ring buffer, one byte is reserved for internal use. In other
- * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
- * @param ringBufferSize size of the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
  */
 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
 
@@ -632,23 +652,23 @@
  * function and passes the @ref kStatus_UART_TxIdle as status parameter.
  *
  * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
- * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
  * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param xfer UART transfer structure. See  #uart_transfer_t.
  * @retval kStatus_Success Successfully start the data transmission.
- * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
 
 /*!
- * @brief Aborts the interrupt driven data transmit.
+ * @brief Aborts the interrupt-driven data transmit.
  *
- * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out
- * how many bytes are still not sent out.
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
@@ -656,16 +676,16 @@
 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to UART TX register.
+ * @brief Gets the number of bytes written to the UART TX register.
  *
- * This function gets the number of bytes that have been written to UART TX
- * register by interrupt method.
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param count Send bytes count.
  * @retval kStatus_NoTransferInProgress No send in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_InvalidArgument The parameter is invalid.
  * @retval kStatus_Success Get successfully through the parameter \p count;
  */
 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
@@ -690,7 +710,7 @@
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
- * @param xfer UART transfer structure, refer to #uart_transfer_t.
+ * @param xfer UART transfer structure, see #uart_transfer_t.
  * @param receivedBytes Bytes received from the ring buffer directly.
  * @retval kStatus_Success Successfully queue the transfer into transmit queue.
  * @retval kStatus_UART_RxBusy Previous receive request is not finished.
@@ -705,7 +725,7 @@
  * @brief Aborts the interrupt-driven data receiving.
  *
  * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
- * how many bytes not received yet.
+ * how many bytes are not received yet.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
@@ -713,7 +733,7 @@
 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of bytes that have been received.
  *
  * This function gets the number of bytes that have been received.
  *
@@ -739,7 +759,7 @@
 /*!
  * @brief UART Error IRQ handle function.
  *
- * This function handle the UART error IRQ request.
+ * This function handles the UART error IRQ request.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -125,6 +125,8 @@
 
 static void UART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
 
     /* Avoid the warning for unused variables. */
@@ -145,6 +147,8 @@
 
 static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
 
     /* Avoid warning for unused parameters. */
@@ -165,11 +169,11 @@
 }
 
 void UART_TransferCreateHandleEDMA(UART_Type *base,
-                           uart_edma_handle_t *handle,
-                           uart_edma_transfer_callback_t callback,
-                           void *userData,
-                           edma_handle_t *txEdmaHandle,
-                           edma_handle_t *rxEdmaHandle)
+                                   uart_edma_handle_t *handle,
+                                   uart_edma_transfer_callback_t callback,
+                                   void *userData,
+                                   edma_handle_t *txEdmaHandle,
+                                   edma_handle_t *rxEdmaHandle)
 {
     assert(handle);
 
@@ -219,17 +223,15 @@
 
 status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous TX not finished. */
     if (kUART_TxBusy == handle->txState)
     {
@@ -244,6 +246,9 @@
         EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base),
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+        /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->txEdmaHandle);
@@ -259,17 +264,15 @@
 
 status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous RX not finished. */
     if (kUART_RxBusy == handle->rxState)
     {
@@ -284,6 +287,9 @@
         EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
 
+        /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->rxEdmaHandle);
@@ -299,6 +305,7 @@
 
 void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
 
     /* Disable UART TX EDMA. */
@@ -312,6 +319,7 @@
 
 void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
 
     /* Disable UART RX EDMA. */
@@ -325,38 +333,36 @@
 
 status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(count);
 
     if (kUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+    *count = handle->rxDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
 
     return kStatus_Success;
 }
 
 status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(count);
 
     if (kUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+    *count = handle->txDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
 
     return kStatus_Success;
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,8 +39,6 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -67,6 +65,8 @@
     edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
     edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
 
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
     volatile uint8_t txState; /*!< TX transfer state. */
     volatile uint8_t rxState; /*!< RX transfer state */
 };
@@ -87,18 +87,18 @@
 /*!
  * @brief Initializes the UART handle which is used in transactional functions.
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  * @param callback UART callback, NULL means no callback.
  * @param userData User callback function data.
- * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
- * @param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * @param rxEdmaHandle User-requested DMA handle for RX DMA transfer.
+ * @param txEdmaHandle User-requested DMA handle for TX DMA transfer.
  */
 void UART_TransferCreateHandleEDMA(UART_Type *base,
-                           uart_edma_handle_t *handle,
-                           uart_edma_transfer_callback_t callback,
-                           void *userData,
-                           edma_handle_t *txEdmaHandle,
-                           edma_handle_t *rxEdmaHandle);
+                                   uart_edma_handle_t *handle,
+                                   uart_edma_transfer_callback_t callback,
+                                   void *userData,
+                                   edma_handle_t *txEdmaHandle,
+                                   edma_handle_t *rxEdmaHandle);
 
 /*!
  * @brief Sends data using eDMA.
@@ -109,23 +109,23 @@
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_UART_TxBusy Previous transfer on going.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_TxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
 
 /*!
- * @brief Receive data using eDMA.
+ * @brief Receives data using eDMA.
  *
  * This function receives data using eDMA. This is a non-blocking function, which returns
  * right away. When all data is received, the receive callback function is called.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_UART_RxBusy Previous transfer on going.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_RxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
@@ -136,7 +136,7 @@
  * This function aborts sent data using eDMA.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  */
 void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle);
 
@@ -146,12 +146,12 @@
  * This function aborts receive data using eDMA.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  */
 void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to UART TX register.
+ * @brief Gets the number of bytes that have been written to UART TX register.
  *
  * This function gets the number of bytes that have been written to UART TX
  * register by DMA.
@@ -166,9 +166,9 @@
 status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of received bytes.
  *
- * This function gets the number of bytes that have been received.
+ * This function gets the number of received bytes.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -50,8 +50,10 @@
 /*! @brief Pointers to VREF bases for each instance. */
 static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to VREF clocks for each instance. */
 static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -62,7 +64,7 @@
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
     {
         if (s_vrefBases[instance] == base)
         {
@@ -70,7 +72,7 @@
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_VREF_COUNT);
+    assert(instance < ARRAY_SIZE(s_vrefBases));
 
     return instance;
 }
@@ -81,15 +83,24 @@
 
     uint8_t reg = 0U;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock for VREF */
     CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* Configure VREF to a known state */
 #if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
     /* Set chop oscillator bit */
     base->TRM |= VREF_TRM_CHOPEN_MASK;
 #endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
+    /* Get current SC register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFH_SC;
+#else
     reg = base->SC;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    /* Clear old buffer mode selection bits */
+    reg &= ~VREF_SC_MODE_LV_MASK;
     /* Set buffer Mode selection and Regulator enable bit */
     reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
 #if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
@@ -99,30 +110,51 @@
     /* Enable VREF module */
     reg |= VREF_SC_VREFEN(1U);
     /* Update bit-field from value to Status and Control register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    base->VREFH_SC = reg;
+#else
     base->SC = reg;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
     reg = base->VREFL_TRM;
-    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/
+    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
     reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK);
     /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
     reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
     base->VREFL_TRM = reg;
 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
 
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    reg = base->TRM4;
+    /* Clear old select internal voltage reference bit (2.1V) */
+    reg &= ~VREF_TRM4_VREF2V1_EN_MASK;
+    /* Select internal voltage reference (2.1V) */
+    reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
+    base->TRM4 = reg;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
     /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
     while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
     {
     }
 }
 
 void VREF_Deinit(VREF_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate clock for VREF */
     CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void VREF_GetDefaultConfig(vref_config_t *config)
 {
+    assert(config);
+
 /* Set High power buffer mode in */
 #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
     config->bufferMode = kVREF_ModeHighPowerBuffer;
@@ -136,6 +168,11 @@
     /* Set VREFL (0.4 V) reference buffer disable */
     config->enableLowRef = false;
 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    /* Disable internal voltage reference (2.1V) */
+    config->enable2V1VoltRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
 }
 
 void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
@@ -147,10 +184,30 @@
     reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
     base->TRM = reg;
     /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference (2V1) */
+    reg = base->TRM4;
+    reg = ((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
+    base->TRM4 = reg;
+    /* Wait until internal voltage stable */
     while ((base->SC & VREF_SC_VREFST_MASK) == 0)
     {
     }
 }
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
 
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
 void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
@@ -165,7 +222,8 @@
     reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
     base->VREFL_TRM = reg;
     /* Wait until internal voltage stable */
-    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
     {
     }
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /******************************************************************************
  * Definitions
@@ -46,12 +45,11 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
 /*@}*/
 
 /* Those macros below defined to support SoC family which have VREFL (0.4V) reference */
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
-#define SC VREFH_SC
 #define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV
 #define VREF_SC_REGEN VREF_VREFH_SC_REGEN
 #define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN
@@ -80,8 +78,8 @@
 {
     kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */
 #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
-    kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */
-    kVREF_ModeLowPowerBuffer = 2U   /*!< Low power buffer mode enabled */
+    kVREF_ModeHighPowerBuffer = 1U, /*!< High-power buffer mode enabled */
+    kVREF_ModeLowPowerBuffer = 2U   /*!< Low-power buffer mode enabled */
 #else
     kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */
 #endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
@@ -97,6 +95,9 @@
     bool enableLowRef;          /*!< Set VREFL (0.4 V) reference buffer enable or disable */
     bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */
 #endif                          /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    bool enable2V1VoltRef; /*!< Enable Internal Voltage Reference (2.1V) */
+#endif                     /* FSL_FEATURE_VREF_HAS_TRM4 */
 } vref_config_t;
 
 /******************************************************************************
@@ -115,11 +116,11 @@
 /*!
  * @brief Enables the clock gate and configures the VREF module according to the configuration structure.
  *
- * This function must be called before calling all the other VREF driver functions,
+ * This function must be called before calling all other VREF driver functions,
  * read/write registers, and configurations with user-defined settings.
  * The example below shows how to set up  vref_config_t parameters and
- * how to call the VREF_Init function by passing in these parameters:
- * Example:
+ * how to call the VREF_Init function by passing in these parameters.
+ * This is an example.
  * @code
  *   vref_config_t vrefConfig;
  *   vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
@@ -137,7 +138,7 @@
  * @brief Stops and disables the clock for the VREF module.
  *
  * This function should be called to shut down the module.
- * Example:
+ * This is an example.
  * @code
  *   vref_config_t vrefUserConfig;
  *   VREF_Init(VREF);
@@ -153,8 +154,8 @@
 /*!
  * @brief Initializes the VREF configuration structure.
  *
- * This function initializes the VREF configuration structure to a default value.
- * Example:
+ * This function initializes the VREF configuration structure to default values.
+ * This is an example.
  * @code
  *   vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
  *   vrefConfig->enableExternalVoltRef = false;
@@ -166,9 +167,9 @@
 void VREF_GetDefaultConfig(vref_config_t *config);
 
 /*!
- * @brief Sets a TRIM value for reference voltage.
+ * @brief Sets a TRIM value for the reference voltage.
  *
- * This function sets a TRIM value for reference voltage.
+ * This function sets a TRIM value for the reference voltage.
  * Note that the TRIM value maximum is 0x3F.
  *
  * @param base VREF peripheral address.
@@ -188,13 +189,40 @@
 {
     return (base->TRM & VREF_TRM_TRIM_MASK);
 }
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+/*!
+ * @brief Sets a TRIM value for the reference voltage (2V1).
+ *
+ * This function sets a TRIM value for the reference voltage (2V1).
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage (2V1).
+ *
+ * This function gets the TRIM value from the VREF_TRM4 register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrim2V1Val(VREF_Type *base)
+{
+    return (base->TRM4 & VREF_TRM4_TRIM2V1_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
 
 /*!
- * @brief Sets the TRIM value for low voltage reference.
+ * @brief Sets the TRIM value for the low voltage reference.
  *
  * This function sets the TRIM value for low reference voltage.
- * NOTE:
+ * Note the following.
  *      - The TRIM value maximum is 0x05U
  *      - The values 111b and 110b are not valid/allowed.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h	Wed Oct 11 12:45:49 2017 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup wdog_driver
+ * @addtogroup wdog
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -136,7 +135,7 @@
  */
 enum _wdog_interrupt_enable_t
 {
-    kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout will generate interrupt before reset*/
+    kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout generates an interrupt before reset*/
 };
 
 /*!
@@ -164,10 +163,10 @@
  */
 
 /*!
- * @brief Initializes WDOG configure sturcture.
+ * @brief Initializes the WDOG configuration sturcture.
  *
- * This function initializes the WDOG configure structure to default value. The default
- * value are:
+ * This function initializes the WDOG configuration structure to default values. The default
+ * values are as follows.
  * @code
  *   wdogConfig->enableWdog = true;
  *   wdogConfig->clockSource = kWDOG_LpoClockSource;
@@ -182,7 +181,7 @@
  *   wdogConfig->timeoutValue = 0xFFFFU;
  * @endcode
  *
- * @param config Pointer to WDOG config structure.
+ * @param config Pointer to the WDOG configuration structure.
  * @see wdog_config_t
  */
 void WDOG_GetDefaultConfig(wdog_config_t *config);
@@ -191,10 +190,10 @@
  * @brief Initializes the WDOG.
  *
  * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
- * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true
- * in configuration.
+ * To reconfigure WDOG without forcing a reset first, enableUpdate must be set to true
+ * in the configuration.
  *
- * Example:
+ * This is an example.
  * @code
  *   wdog_config_t config;
  *   WDOG_GetDefaultConfig(&config);
@@ -212,18 +211,18 @@
  * @brief Shuts down the WDOG.
  *
  * This function shuts down the WDOG.
- * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which indicates that the register update is enabled.
  */
 void WDOG_Deinit(WDOG_Type *base);
 
 /*!
- * @brief Configures WDOG functional test.
+ * @brief Configures the WDOG functional test.
  *
  * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode
  * and runs according to the configuration.
- * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
  *
- * Example:
+ * This is an example.
  * @code
  *   wdog_test_config_t test_config;
  *   test_config.testMode = kWDOG_QuickTest;
@@ -259,9 +258,9 @@
 /*!
  * @brief Disables the WDOG module.
  *
- * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to disable the WDOG. It is a write-once register.
+ * Ensure that the WCT window is still open and that register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  */
@@ -271,15 +270,15 @@
 }
 
 /*!
- * @brief Enable WDOG interrupt.
+ * @brief Enables the WDOG interrupt.
  *
- * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to enable the WDOG interrupt. It is a write-once register.
+ * Ensure that the WCT window is still open and the register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param mask The interrupts to enable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined.
  *        @arg kWDOG_InterruptEnable
  */
 static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask)
@@ -288,15 +287,15 @@
 }
 
 /*!
- * @brief Disable WDOG interrupt.
+ * @brief Disables the WDOG interrupt.
  *
- * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to disable the WDOG interrupt. It is a write-once register.
+ * Ensure that the WCT window is still open and the register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param mask The interrupts to disable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined.
  *        @arg kWDOG_InterruptEnable
  */
 static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask)
@@ -305,50 +304,50 @@
 }
 
 /*!
- * @brief Gets WDOG all status flags.
+ * @brief Gets the WDOG all status flags.
  *
  * This function gets all status flags.
  *
- * Example for getting Running Flag:
+ * This is an example for getting the Running Flag.
  * @code
  *   uint32_t status;
- *   status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag;
+ *   status = WDOG_GetStatusFlags (wdog_base) & kWDOG_RunningFlag;
  * @endcode
  * @param base        WDOG peripheral base address
  * @return            State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t
- *                    - true: related status flag has been set.
- *                    - false: related status flag is not set.
+ *                    - true: a related status flag has been set.
+ *                    - false: a related status flag is not set.
  */
 uint32_t WDOG_GetStatusFlags(WDOG_Type *base);
 
 /*!
- * @brief Clear WDOG flag.
+ * @brief Clears the WDOG flag.
  *
- * This function clears WDOG status flag.
+ * This function clears the WDOG status flag.
  *
- * Example for clearing timeout(interrupt) flag:
+ * This is an example for clearing the timeout (interrupt) flag.
  * @code
  *   WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag);
  * @endcode
  * @param base        WDOG peripheral base address
  * @param mask        The status flags to clear.
- *                    The parameter could be any combination of the following values:
+ *                    The parameter could be any combination of the following values.
  *                    kWDOG_TimeoutFlag
  */
 void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
 
 /*!
- * @brief Set the WDOG timeout value.
+ * @brief Sets the WDOG timeout value.
  *
  * This function sets the timeout value.
  * It should be ensured that the time-out value for the WDOG is always greater than
  * 2xWCT time + 20 bus clock cycles.
- * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once.
- * Make sure the WCT window is still open and these two registers have not been written in this WCT
- * while this function is called.
+ * This function writes a value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once.
+ * Ensure the WCT window is still open and the two registers have not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
- * @param timeoutCount WDOG timeout value, count of WDOG clock tick.
+ * @param timeoutCount WDOG timeout value; count of WDOG clock tick.
  */
 static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount)
 {
@@ -360,9 +359,9 @@
  * @brief Sets the WDOG window value.
  *
  * This function sets the WDOG window value.
- * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once.
- * Make sure the WCT window is still open and these two registers have not been written in this WCT
- * while this function is called.
+ * This function writes a value into WDOG_WINH and WDOG_WINL registers which are wirte-once.
+ * Ensure the WCT window is still open and the two registers have not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param windowValue WDOG window value.
@@ -378,7 +377,7 @@
  *
  * This function unlocks the WDOG register written.
  * Before starting the unlock sequence and following congfiguration, disable the global interrupts.
- * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire,
+ * Otherwise, an interrupt may invalidate the unlocking sequence and the WCT may expire.
  * After the configuration finishes, re-enable the global interrupts.
  *
  * @param base WDOG peripheral base address
@@ -393,7 +392,7 @@
  * @brief Refreshes the WDOG timer.
  *
  * This function feeds the WDOG.
- * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted.
+ * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
  *
  * @param base WDOG peripheral base address
  */
@@ -405,7 +404,7 @@
  * This function gets the WDOG reset count value.
  *
  * @param base WDOG peripheral base address
- * @return     WDOG reset count value
+ * @return     WDOG reset count value.
  */
 static inline uint16_t WDOG_GetResetCount(WDOG_Type *base)
 {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -122,13 +122,17 @@
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
-    for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
-        char in = spi_master_write(obj, out);
-        if (i < rx_length) {
-            rx_buffer[i] = in;
-        }
-    }
+    // Default write is done in each and every call, in future can create HAL API instead
+    DSPI_SetDummyData(spi_address[obj->instance], write_fill);
+
+    DSPI_MasterTransferBlocking(spi_address[obj->instance], &(dspi_transfer_t){
+          .txData = (uint8_t *)tx_buffer,
+          .rxData = (uint8_t *)rx_buffer,
+          .dataSize = total,
+          .configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
+    });
+
+    DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
 
     return total;
 }

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -57,9 +57,6 @@
 
 void rtc_write(time_t t)
 {
-    if (t == 0) {
-        t = 1;
-    }
     RTC_StopTimer(RTC);
     RTC->TSR = t;
     RTC_StartTimer(RTC);

--- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -151,7 +151,7 @@
                         cfg.pull = NRF_GPIO_PIN_NOPULL;
                     break;
                 }
-                nrf_drv_gpiote_in_init(pin, &cfg, NULL);
+                nrf_gpio_cfg_input(pin,cfg.pull);
             }
         }
         else {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/cmsis_nvic.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+extern uint32_t Image$$VECTOR_RAM$$Base[];
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+extern uint32_t __VECTOR_RAM[];
+#endif
+
+/* Symbols defined by the linker script */
+#define NVIC_NUM_VECTORS        (16 + 40)         // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
+
+#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    OSC32KCLK = 0,
-} RTCName;
-
-typedef enum {
-    UART_0 = Flexcomm0,
-    UART_1 = Flexcomm4
-} UARTName;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-typedef enum {
-    I2C_0 = Flexcomm1,
-    I2C_1 = Flexcomm2
-} I2CName;
-
-#define TPM_SHIFT   8
-typedef enum {
-    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
-    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
-    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
-    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
-    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
-    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
-    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
-    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
-    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
-    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
-    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
-    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
-    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
-    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
-    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
-    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
-    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
-    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
-    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
-    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
-    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
-    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
-    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
-    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
-    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
-    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
-    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
-    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
-    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
-    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
-    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
-    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
-} PWMName;
-
-#define ADC_INSTANCE_SHIFT           8
-#define ADC_B_CHANNEL_SHIFT        5
-
-typedef enum {
-    ADC0_SE0  = 0,
-    ADC0_SE1  = 1,
-    ADC0_SE2  = 2,
-    ADC0_SE3  = 3,
-    ADC0_SE4  = 4,
-    ADC0_SE5  = 5,
-    ADC0_SE6  = 6,
-    ADC0_SE7  = 7,
-    ADC0_SE8  = 8,
-    ADC0_SE9  = 9,
-    ADC0_SE10 = 10,
-    ADC0_SE11 = 11,
-} ADCName;
-
-typedef enum {
-    CAN_0 = 0,
-    CAN_1 = 1
-} CANName;
-
-typedef enum {
-    SPI_0 = Flexcomm3,
-    SPI_1 = Flexcomm9
-} SPIName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "PeripheralPins.h"
-
-/************RTC***************/
-const PinMap PinMap_RTC[] = {
-    {NC, OSC32KCLK, 0},
-};
-
-/************ADC***************/
-const PinMap PinMap_ADC[] = {
-    {P0_16, ADC0_SE4,  0},
-    {P0_31, ADC0_SE5,  0},
-    {P1_0,  ADC0_SE6,  0},
-    {P2_0,  ADC0_SE7,  0},
-    {NC   , NC      ,  0}
-};
-
-/************CAN***************/
-const PinMap PinMap_CAN_TD[] = {
-    {P3_18, CAN_0,  4},
-    {P1_17, CAN_1,  5},
-    {NC   , NC   ,  0}
-};
-
-const PinMap PinMap_CAN_RD[] = {
-    {P3_19, CAN_0,  4},
-    {P1_18, CAN_1,  5},
-    {NC   , NC   ,  0}
-};
-
-
-/************DAC***************/
-const PinMap PinMap_DAC[] = {
-    {NC      , NC   , 0}
-};
-
-/************I2C***************/
-const PinMap PinMap_I2C_SDA[] = {
-    {P0_13, I2C_0, 1},
-    {P3_23, I2C_1, 1},
-    {NC   , NC   , 0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {P0_14, I2C_0, 1},
-    {P3_24, I2C_1, 1},
-    {NC   , NC   , 0}
-};
-
-/************UART***************/
-const PinMap PinMap_UART_TX[] = {
-    {P0_30, UART_0, 1},
-    {P3_27, UART_1, 1},
-    {NC   ,  NC   , 0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {P0_29, UART_0, 1},
-    {P3_26, UART_1, 1},
-    {NC   ,  NC   , 0}
-};
-
-const PinMap PinMap_UART_CTS[] = {
-    {P3_28, UART_1, 1},
-    {NC   , NC    , 0}
-};
-
-const PinMap PinMap_UART_RTS[] = {
-    {P3_29, UART_1, 1},
-    {NC   , NC    , 0}
-};
-
-/************SPI***************/
-const PinMap PinMap_SPI_SCLK[] = {
-    {P0_0,  SPI_0, 2},
-    {P3_20, SPI_1, 1},
-    {NC   , NC   , 0}
-};
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {P0_3,  SPI_0, 1},
-    {P3_21, SPI_1, 1},
-    {NC   , NC   , 0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {P0_2,  SPI_0, 1},
-    {P3_22, SPI_1, 1},
-    {NC   , NC   , 0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {P0_1,  SPI_0, 2},
-    {P3_30, SPI_1, 1},
-    {P4_6,  SPI_1, 2},
-    {NC  ,  NC   , 0}
-};
-
-/************PWM***************/
-const PinMap PinMap_PWM[] = {
-    {NC   , NC    , 0}
-};

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,245 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  5
-
-typedef enum {
-    P0_0 = (0 << PORT_SHIFT | 0),
-    P0_1 = (0 << PORT_SHIFT | 1),
-    P0_2 = (0 << PORT_SHIFT | 2),
-    P0_3 = (0 << PORT_SHIFT | 3),
-    P0_4 = (0 << PORT_SHIFT | 4),
-    P0_5 = (0 << PORT_SHIFT | 5),
-    P0_6 = (0 << PORT_SHIFT | 6),
-    P0_7 = (0 << PORT_SHIFT | 7),
-    P0_8 = (0 << PORT_SHIFT | 8),
-    P0_9 = (0 << PORT_SHIFT | 9),
-    P0_10 = (0 << PORT_SHIFT | 10),
-    P0_11 = (0 << PORT_SHIFT | 11),
-    P0_12 = (0 << PORT_SHIFT | 12),
-    P0_13 = (0 << PORT_SHIFT | 13),
-    P0_14 = (0 << PORT_SHIFT | 14),
-    P0_15 = (0 << PORT_SHIFT | 15),
-    P0_16 = (0 << PORT_SHIFT | 16),
-    P0_17 = (0 << PORT_SHIFT | 17),
-    P0_18 = (0 << PORT_SHIFT | 18),
-    P0_19 = (0 << PORT_SHIFT | 19),
-    P0_20 = (0 << PORT_SHIFT | 20),
-    P0_21 = (0 << PORT_SHIFT | 21),
-    P0_22 = (0 << PORT_SHIFT | 22),
-    P0_23 = (0 << PORT_SHIFT | 23),
-    P0_24 = (0 << PORT_SHIFT | 24),
-    P0_25 = (0 << PORT_SHIFT | 25),
-    P0_26 = (0 << PORT_SHIFT | 26),
-    P0_27 = (0 << PORT_SHIFT | 27),
-    P0_28 = (0 << PORT_SHIFT | 28),
-    P0_29 = (0 << PORT_SHIFT | 29),
-    P0_30 = (0 << PORT_SHIFT | 30),
-    P0_31 = (0 << PORT_SHIFT | 31),
-
-    P1_0 = (1 << PORT_SHIFT | 0),
-    P1_1 = (1 << PORT_SHIFT | 1),
-    P1_2 = (1 << PORT_SHIFT | 2),
-    P1_3 = (1 << PORT_SHIFT | 3),
-    P1_4 = (1 << PORT_SHIFT | 4),
-    P1_5 = (1 << PORT_SHIFT | 5),
-    P1_6 = (1 << PORT_SHIFT | 6),
-    P1_7 = (1 << PORT_SHIFT | 7),
-    P1_8 = (1 << PORT_SHIFT | 8),
-    P1_9 = (1 << PORT_SHIFT | 9),
-    P1_10 = (1 << PORT_SHIFT | 10),
-    P1_11 = (1 << PORT_SHIFT | 11),
-    P1_12 = (1 << PORT_SHIFT | 12),
-    P1_13 = (1 << PORT_SHIFT | 13),
-    P1_14 = (1 << PORT_SHIFT | 14),
-    P1_15 = (1 << PORT_SHIFT | 15),
-    P1_16 = (1 << PORT_SHIFT | 16),
-    P1_17 = (1 << PORT_SHIFT | 17),
-    P1_18 = (1 << PORT_SHIFT | 18),
-    P1_19 = (1 << PORT_SHIFT | 19),
-    P1_20 = (1 << PORT_SHIFT | 20),
-    P1_21 = (1 << PORT_SHIFT | 21),
-    P1_22 = (1 << PORT_SHIFT | 22),
-    P1_23 = (1 << PORT_SHIFT | 23),
-    P1_24 = (1 << PORT_SHIFT | 24),
-    P1_25 = (1 << PORT_SHIFT | 25),
-    P1_26 = (1 << PORT_SHIFT | 26),
-    P1_27 = (1 << PORT_SHIFT | 27),
-    P1_28 = (1 << PORT_SHIFT | 28),
-    P1_29 = (1 << PORT_SHIFT | 29),
-    P1_30 = (1 << PORT_SHIFT | 30),
-    P1_31 = (1 << PORT_SHIFT | 31),
-
-    P2_0 = (2 <<  PORT_SHIFT | 0),
-    P2_1 = (2 <<  PORT_SHIFT | 1),
-    P2_2 = (2 <<  PORT_SHIFT | 2),
-    P2_3 = (2 <<  PORT_SHIFT | 3),
-    P2_4 = (2 <<  PORT_SHIFT | 4),
-    P2_5 = (2 <<  PORT_SHIFT | 5),
-    P2_6 = (2 <<  PORT_SHIFT | 6),
-    P2_7 = (2 <<  PORT_SHIFT | 7),
-    P2_8 = (2 <<  PORT_SHIFT | 8),
-    P2_9 = (2 <<  PORT_SHIFT | 9),
-    P2_10 = (2 <<  PORT_SHIFT | 10),
-    P2_11 = (2 <<  PORT_SHIFT | 11),
-    P2_12 = (2 <<  PORT_SHIFT | 12),
-    P2_13 = (2 <<  PORT_SHIFT | 13),
-    P2_14 = (2 <<  PORT_SHIFT | 14),
-    P2_15 = (2 <<  PORT_SHIFT | 15),
-    P2_16 = (2 <<  PORT_SHIFT | 16),
-    P2_17 = (2 <<  PORT_SHIFT | 17),
-    P2_18 = (2 <<  PORT_SHIFT | 18),
-    P2_19 = (2 <<  PORT_SHIFT | 19),
-    P2_20 = (2 <<  PORT_SHIFT | 20),
-    P2_21 = (2 <<  PORT_SHIFT | 21),
-    P2_22 = (2 <<  PORT_SHIFT | 22),
-    P2_23 = (2 <<  PORT_SHIFT | 23),
-    P2_24 = (2 <<  PORT_SHIFT | 24),
-    P2_25 = (2 <<  PORT_SHIFT | 25),
-    P2_26 = (2 <<  PORT_SHIFT | 26),
-    P2_27 = (2 <<  PORT_SHIFT | 27),
-    P2_28 = (2 <<  PORT_SHIFT | 28),
-    P2_29 = (2 <<  PORT_SHIFT | 29),
-    P2_30 = (2 <<  PORT_SHIFT | 30),
-    P2_31 = (2 <<  PORT_SHIFT | 31),
-
-    P3_0 = (3 <<  PORT_SHIFT | 0),
-    P3_1 = (3 <<  PORT_SHIFT | 1),
-    P3_2 = (3 <<  PORT_SHIFT | 2),
-    P3_3 = (3 <<  PORT_SHIFT | 3),
-    P3_4 = (3 <<  PORT_SHIFT | 4),
-    P3_5 = (3 <<  PORT_SHIFT | 5),
-    P3_6 = (3 <<  PORT_SHIFT | 6),
-    P3_7 = (3 <<  PORT_SHIFT | 7),
-    P3_8 = (3 <<  PORT_SHIFT | 8),
-    P3_9 = (3 <<  PORT_SHIFT | 9),
-    P3_10 = (3 <<  PORT_SHIFT | 10),
-    P3_11 = (3 <<  PORT_SHIFT | 11),
-    P3_12 = (3 <<  PORT_SHIFT | 12),
-    P3_13 = (3 <<  PORT_SHIFT | 13),
-    P3_14 = (3 <<  PORT_SHIFT | 14),
-    P3_15 = (3 <<  PORT_SHIFT | 15),
-    P3_16 = (3 <<  PORT_SHIFT | 16),
-    P3_17 = (3 <<  PORT_SHIFT | 17),
-    P3_18 = (3 <<  PORT_SHIFT | 18),
-    P3_19 = (3 <<  PORT_SHIFT | 19),
-    P3_20 = (3 <<  PORT_SHIFT | 20),
-    P3_21 = (3 <<  PORT_SHIFT | 21),
-    P3_22 = (3 <<  PORT_SHIFT | 22),
-    P3_23 = (3 <<  PORT_SHIFT | 23),
-    P3_24 = (3 <<  PORT_SHIFT | 24),
-    P3_25 = (3 <<  PORT_SHIFT | 25),
-    P3_26 = (3 <<  PORT_SHIFT | 26),
-    P3_27 = (3 <<  PORT_SHIFT | 27),
-    P3_28 = (3 <<  PORT_SHIFT | 28),
-    P3_29 = (3 <<  PORT_SHIFT | 29),
-    P3_30 = (3 <<  PORT_SHIFT | 30),
-    P3_31 = (3 <<  PORT_SHIFT | 31),
-
-    P4_0 = (4 <<  PORT_SHIFT | 0),
-    P4_1 = (4 <<  PORT_SHIFT | 1),
-    P4_2 = (4 <<  PORT_SHIFT | 2),
-    P4_3 = (4 <<  PORT_SHIFT | 3),
-    P4_4 = (4 <<  PORT_SHIFT | 4),
-    P4_5 = (4 <<  PORT_SHIFT | 5),
-    P4_6 = (4 <<  PORT_SHIFT | 6),
-    P4_7 = (4 <<  PORT_SHIFT | 7),
-    P4_8 = (4 <<  PORT_SHIFT | 8),
-    P4_9 = (4 <<  PORT_SHIFT | 9),
-    P4_10 = (4 <<  PORT_SHIFT | 10),
-    P4_11 = (4 <<  PORT_SHIFT | 11),
-    P4_12 = (4 <<  PORT_SHIFT | 12),
-    P4_13 = (4 <<  PORT_SHIFT | 13),
-    P4_14 = (4 <<  PORT_SHIFT | 14),
-    P4_15 = (4 <<  PORT_SHIFT | 15),
-    P4_16 = (4 <<  PORT_SHIFT | 16),
-
-    LED_RED   = P2_2,
-
-    // mbed original LED naming
-    LED1 = LED_RED,
-    LED2 = P3_3,
-    LED3 = P3_14,
-    LED4 = LED_RED,
-
-    //Push buttons
-    SW2 = P0_6,
-    SW3 = P0_5,
-    SW4 = P0_4,
-    SW5 = P1_1,
-
-    // USB Pins
-    USBTX = P0_30,
-    USBRX = P0_29,
-
-    // Arduino Headers
-    D0 = P3_26,
-    D1 = P3_27,
-    D2 = P3_2,
-    D3 = P4_5,
-    D4 = P3_10,
-    D5 = P3_14,
-    D6 = P3_1,
-    D7 = P1_22,
-    D8 = P4_7,
-    D9 = P2_1,
-    D10 = P3_30,
-    D11 = P3_21,
-    D12 = P3_22,
-    D13 = P3_20,
-    D14 = P3_23,
-    D15 = P3_24,
-
-    I2C_SCL = D15,
-    I2C_SDA = D14,
-
-    A0 = P0_16,
-    A1 = P0_31,
-    A2 = P1_0,
-    A3 = P2_0,
-    A4 = P3_4,
-    A5 = P1_1,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-
-typedef enum {
-    PullNone = 0,
-    PullDown = 1,
-    PullUp   = 2,
-    PullDefault = PullUp
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * How to set up clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Setup voltage for the fastest of the clock outputs
- *
- * 3. Set up wait states of the flash.
- *
- * 4. Set up all dividers.
- *
- * 5. Set up all selectors to provide selected clocks.
- */
-
-/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
-!!ClocksProfile
-product: Clocks v1.0
-processor: LPC54608J512
-package_id: LPC54608J512ET180
-mcu_data: ksdk2_0
-processor_version: 0.0.0
-board: LPCXpresso54608
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
-
-#include "fsl_power.h"
-#include "fsl_clock.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockFRO12M ***********************
- ******************************************************************************/
-/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: System_clock.outFreq, value: 12 MHz}
-settings:
-- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Set up the clock sources */
-    /*!< Set up FRO */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-    CLOCK_AttachClk(
-        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
-                                   being below the voltage for current speed */
-    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
-    POWER_SetVoltageForFreq(
-        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
-    /*!< Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockFROHF48M ***********************
- ******************************************************************************/
-/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Set up the clock sources */
-    /*!< Set up FRO */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-    CLOCK_AttachClk(
-        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
-                                   being below the voltage for current speed */
-    POWER_SetVoltageForFreq(
-        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
-
-    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-    /*!< Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockFROHF96M **********************
- ******************************************************************************/
-/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
-!!Configuration
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF96M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF96M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF96M(void)
-{
-    /*!< Set up the clock sources */
-    /*!< Set up FRO */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-    CLOCK_AttachClk(
-        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
-                                   being below the voltage for current speed */
-    POWER_SetVoltageForFreq(
-        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-    /*!< Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockPLL180M **********************
- ******************************************************************************/
-/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
-!!Configuration
-name: BOARD_BootClockPLL180M
-outputs:
-- {id: FRO12M_clock.outFreq, value: 12 MHz}
-- {id: FROHF_clock.outFreq, value: 48 MHz}
-- {id: SYSPLL_clock.outFreq, value: 180 MHz}
-- {id: System_clock.outFreq, value: 180 MHz}
-settings:
-- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
-- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
-- {id: SYSCON.PDEC.scale, value: '2', locked: true}
-- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
-sources:
-- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL180M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL180M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL180M(void)
-{
-    /*!< Set up the clock sources */
-    /*!< Set up FRO */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-    CLOCK_AttachClk(
-        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
-                                   being below the voltage for current speed */
-    POWER_SetVoltageForFreq(
-        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
-
-    /*!< Set up SYS PLL */
-    const pll_setup_t pllSetup = {
-        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
-        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
-        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
-        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
-        .pllRate = 180000000U,
-        .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
-    CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */
-    CLOCK_SetPLLFreq(&pllSetup);          /*!< Configure PLL to the desired value */
-    POWER_SetVoltageForFreq(
-        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-    CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
-    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK);         /*!< Switch System clock to SYS PLL 180MHz */
-
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
-
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockFRO12M ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK   12000000U    /*!< Core clock frequency:12000000Hz */
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockFROHF48M ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK   48000000U    /*!< Core clock frequency:48000000Hz */
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockFROHF96M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF96M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK   96000000U    /*!< Core clock frequency:96000000Hz */
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF96M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF96M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockPLL180M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL180M configuration
- ******************************************************************************/
-#define BOARD_BootClockPLL180M_CORE_CLOCK   180000000U    /*!< Core clock frequency:180000000Hz */
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL180M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL180M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-#endif /* _CLOCK_CONFIG_H_ */
-

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
-// Check the 'features' section of the target description in 'targets.json' for more details.
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define NUMBER_OF_GPIO_INTS    8
-
-#define APP_EXCLUDE_FROM_DEEPSLEEP                                                                        \
-    (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK |  SYSCON_PDRUNCFG_PDEN_SRAMX_MASK |                               \
-     SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
-
-/* Defines used by the sleep code */
-#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M
-#define LPC_CLOCK_RUN          BOARD_BootClockFROHF48M
-
-#define DEVICE_ID_LENGTH       24
-
-
-
-
-
-#include "objects.h"
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "clock_config.h"
-#include "fsl_emc.h"
-#include "fsl_power.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/* The SDRAM timing. */
-#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
-#define SDRAM_TRP_NS (18u)
-#define SDRAM_TRAS_NS (42u)
-#define SDRAM_TSREX_NS (67u)
-#define SDRAM_TAPR_NS (18u)
-#define SDRAM_TWRDELT_NS (6u)
-#define SDRAM_TRC_NS (60u)
-#define SDRAM_RFC_NS (60u)
-#define SDRAM_XSR_NS (67u)
-#define SDRAM_RRD_NS (12u)
-#define SDRAM_MRD_NCLK (2u)
-#define SDRAM_RAS_NCLK (2u)
-#define SDRAM_MODEREG_VALUE (0x23u)
-#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
-
-// called before main
-void mbed_sdk_init()
-{
-    BOARD_BootClockFROHF48M();
-}
-
-// Change the NMI pin to an input. This allows NMI pin to
-//  be used as a low power mode wakeup.  The application will
-//  need to change the pin back to NMI_b or wakeup only occurs once!
-void NMI_Handler(void)
-{
-    //gpio_t gpio;
-    //gpio_init_in(&gpio, PTA4);
-}
-
-// Enable the RTC oscillator if available on the board
-void rtc_setup_oscillator(void)
-{
-    /* Enable the RTC 32K Oscillator */
-    SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
-}
-
-void ADC_ClockPower_Configuration(void)
-{
-    /* SYSCON power. */
-    POWER_DisablePD(kPDRUNCFG_PD_VDDA);    /* Power on VDDA. */
-    POWER_DisablePD(kPDRUNCFG_PD_ADC0);    /* Power on the ADC converter. */
-    POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */
-    POWER_DisablePD(kPDRUNCFG_PD_VREFP);   /* Power on the reference voltage source. */
-    POWER_DisablePD(kPDRUNCFG_PD_TS);      /* Power on the temperature sensor. */
-
-    /* Enable the clock. */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
-
-    /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
-    /* Sync clock source is not used. Using sync clock source and would be divided by 2.
-     * The divider would be set when configuring the converter.
-     */
-    CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */
-}
-
-/* Initialize the external memory. */
-void BOARD_InitSDRAM(void)
-{
-    emc_basic_config_t basicConfig;
-    emc_dynamic_timing_config_t dynTiming;
-    emc_dynamic_chip_config_t dynChipConfig;
-
-    /* Basic configuration. */
-    basicConfig.endian = kEMC_LittleEndian;
-    basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
-    /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
-     * If you change the divide to 0 and EMC clock is larger than 100M
-     * please take refer to emc.dox to adjust EMC clock delay.
-     */
-    basicConfig.emcClkDiv = 1;
-    /* Dynamic memory timing configuration. */
-    dynTiming.readConfig = kEMC_Cmddelay;
-    dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
-    dynTiming.tRp_Ns = SDRAM_TRP_NS;
-    dynTiming.tRas_Ns = SDRAM_TRAS_NS;
-    dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
-    dynTiming.tApr_Ns = SDRAM_TAPR_NS;
-    dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
-    dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
-    dynTiming.tRc_Ns = SDRAM_TRC_NS;
-    dynTiming.tRfc_Ns = SDRAM_RFC_NS;
-    dynTiming.tXsr_Ns = SDRAM_XSR_NS;
-    dynTiming.tRrd_Ns = SDRAM_RRD_NS;
-    dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
-    /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
-    dynChipConfig.chipIndex = 0;
-    dynChipConfig.dynamicDevice = kEMC_Sdram;
-    dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
-    dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
-    dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
-    dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
-    /* EMC Basic configuration. */
-    EMC_Init(EMC, &basicConfig);
-    /* EMC Dynamc memory configuration. */
-    EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,12371 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
-**
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**                          MCUXpresso Compiler
-**
-**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b170214
-**
-**     Abstract:
-**         CMSIS Peripheral Access Layer for LPC54608
-**
-**     Copyright 1997-2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2016-08-12)
-**         Initial version.
-**     - rev. 1.1 (2016-11-25)
-**         Update CANFD and Classic CAN register.
-**         Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54608.h
- * @version 1.1
- * @date 2016-11-25
- * @brief CMSIS Peripheral Access Layer for LPC54608
- *
- * CMSIS Peripheral Access Layer for LPC54608
- */
-
-#ifndef _LPC54608_H_
-#define _LPC54608_H_                             /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100U
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
-
-
-/* ----------------------------------------------------------------------------
-   -- Interrupt vector numbers
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-#define NUMBER_OF_INT_VECTORS 73                 /**< Number of interrupts in the Vector table */
-
-typedef enum IRQn {
-  /* Auxiliary constants */
-  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
-
-  /* Core interrupts */
-  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
-  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
-  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
-  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
-  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
-  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
-  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
-  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
-  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
-
-  /* Device specific interrupts */
-  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
-  DMA0_IRQn                    = 1,                /**< DMA controller */
-  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
-  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
-  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
-  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
-  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
-  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
-  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
-  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
-  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
-  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
-  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
-  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
-  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
-  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
-  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
-  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
-  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
-  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
-  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
-  USB0_IRQn                    = 28,               /**< USB device */
-  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
-  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
-  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
-  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
-  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
-  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
-  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
-  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
-  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
-  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
-  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
-  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
-  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
-  SDIO_IRQn                    = 42,               /**< SD/MMC  */
-  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
-  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
-  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
-  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
-  USB1_IRQn                    = 47,               /**< USB1 interrupt */
-  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
-  ETHERNET_IRQn                = 49,               /**< Ethernet */
-  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
-  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
-  EEPROM_IRQn                  = 52,               /**< EEPROM interrupt */
-  LCD_IRQn                     = 53,               /**< LCD interrupt */
-  SHA_IRQn                     = 54,               /**< SHA interrupt */
-  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
-  SMARTCARD1_IRQn              = 56                /**< Smart card 1 interrupt */
-} IRQn_Type;
-
-/*!
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
-   -- Cortex M4 Core Configuration
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
-#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
-
-#include "core_cm4.h"                  /* Core Peripheral Access Layer */
-#include "system_LPC54608.h"           /* Device specific configuration file */
-
-/*!
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
-   -- Mapping Information
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Mapping_Information Mapping Information
- * @{
- */
-
-/** Mapping Information */
-
-/*!
- * @}
- */ /* end of group Mapping_Information */
-
-
-/* ----------------------------------------------------------------------------
-   -- Device Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
-  #pragma push
-  #pragma anon_unions
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma language=extended
-#else
-  #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
-   -- ADC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
-  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
-  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
-  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
-       uint8_t RESERVED_0[8];
-  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
-  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
-  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
-  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
-  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
-  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
-  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
-  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
-  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
-  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- ADC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
-#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
-#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
-#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
-#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
-#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
-#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
-#define ADC_CTRL_RESOL_MASK                      (0x600U)
-#define ADC_CTRL_RESOL_SHIFT                     (9U)
-#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
-#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
-#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
-#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
-#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
-#define ADC_CTRL_TSAMP_SHIFT                     (12U)
-#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
-
-/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
-#define ADC_INSEL_SEL_MASK                       (0x3U)
-#define ADC_INSEL_SEL_SHIFT                      (0U)
-#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
-
-/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
-#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
-#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
-#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
-#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
-#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
-#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
-#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
-#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
-#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
-#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
-#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
-#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
-#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
-#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
-#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
-#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
-#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
-#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
-#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
-#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
-#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
-#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
-#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
-#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
-#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
-#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
-#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
-#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
-#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
-#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
-
-/* The count of ADC_SEQ_CTRL */
-#define ADC_SEQ_CTRL_COUNT                       (2U)
-
-/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
-#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
-#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
-#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
-#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
-#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
-#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
-#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
-#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
-#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
-#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
-#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
-#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
-#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
-#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
-#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
-#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
-#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
-#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
-
-/* The count of ADC_SEQ_GDAT */
-#define ADC_SEQ_GDAT_COUNT                       (2U)
-
-/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
-#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
-#define ADC_DAT_RESULT_SHIFT                     (4U)
-#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
-#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
-#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
-#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
-#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
-#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
-#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
-#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
-#define ADC_DAT_CHANNEL_SHIFT                    (26U)
-#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
-#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
-#define ADC_DAT_OVERRUN_SHIFT                    (30U)
-#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
-#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
-#define ADC_DAT_DATAVALID_SHIFT                  (31U)
-#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
-
-/* The count of ADC_DAT */
-#define ADC_DAT_COUNT                            (12U)
-
-/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
-#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
-#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
-#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
-
-/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
-#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
-#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
-#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
-
-/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
-#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
-#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
-#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
-
-/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
-#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
-#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
-#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
-
-/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
-#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
-#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
-#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
-#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
-#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
-#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
-#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
-#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
-#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
-#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
-#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
-#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
-#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
-#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
-#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
-#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
-#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
-#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
-#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
-#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
-#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
-#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
-#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
-#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
-#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
-
-/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
-#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
-#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
-#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
-#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
-#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
-#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
-#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
-#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
-#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
-#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
-#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
-#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
-#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
-#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
-#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
-#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
-#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
-#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
-#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
-#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
-#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
-#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
-#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
-#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
-#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
-#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
-#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
-#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
-#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
-#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
-#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
-#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
-#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
-#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
-#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
-#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
-#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
-#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
-#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
-#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
-#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
-#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
-#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
-#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
-#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
-
-/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
-#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
-#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
-#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
-#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
-#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
-#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
-#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
-#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
-#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
-#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
-#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
-#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
-#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
-#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
-#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
-#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
-#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
-#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
-#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
-#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
-#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
-#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
-#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
-#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
-#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
-#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
-#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
-#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
-#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
-#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
-#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
-#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
-#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
-#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
-#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
-#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
-#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
-#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
-#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
-#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
-#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
-#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
-#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
-#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
-#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
-#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
-#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
-#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
-#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
-#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
-#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
-#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
-#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
-#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
-#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
-#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
-#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
-#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
-#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
-#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
-#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
-#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
-#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
-#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
-#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
-#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
-#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
-#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
-#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
-#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
-#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
-#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
-#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
-#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
-#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
-#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
-#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
-#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
-#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
-#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
-#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
-#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
-#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
-#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
-#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
-#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
-#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
-#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
-#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
-#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
-
-/*! @name STARTUP - ADC Startup register. */
-#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
-#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
-#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
-#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
-#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
-#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
-
-/*! @name CALIB - ADC Calibration register. */
-#define ADC_CALIB_CALIB_MASK                     (0x1U)
-#define ADC_CALIB_CALIB_SHIFT                    (0U)
-#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
-#define ADC_CALIB_CALREQD_MASK                   (0x2U)
-#define ADC_CALIB_CALREQD_SHIFT                  (1U)
-#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
-#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
-#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
-#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
-
-
-/*!
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE                                (0x400A0000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0                                     ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS                           { ADC0_BASE }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS                            { ADC0 }
-/** Interrupt vectors for the ADC peripheral type */
-#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
-#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
-
-/*!
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- ASYNC_SYSCON Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
- * @{
- */
-
-/** ASYNC_SYSCON - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
-  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
-  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
-  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
-  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
-} ASYNC_SYSCON_Type;
-
-/* ----------------------------------------------------------------------------
-   -- ASYNC_SYSCON Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
- * @{
- */
-
-/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
-
-/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
-
-/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
-
-/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
-
-/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
-
-/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
-
-/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
-
-
-/*!
- * @}
- */ /* end of group ASYNC_SYSCON_Register_Masks */
-
-
-/* ASYNC_SYSCON - Peripheral instance base addresses */
-/** Peripheral ASYNC_SYSCON base address */
-#define ASYNC_SYSCON_BASE                        (0x40040000u)
-/** Peripheral ASYNC_SYSCON base pointer */
-#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
-/** Array initializer of ASYNC_SYSCON peripheral base addresses */
-#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
-/** Array initializer of ASYNC_SYSCON peripheral base pointers */
-#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
-
-/*!
- * @}
- */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- CAN Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
- * @{
- */
-
-/** CAN - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[16];
-  __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
-  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
-  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
-  __IO uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
-  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
-  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
-       uint8_t RESERVED_2[16];
-  __I  uint32_t ECR;                               /**< Error Counter Register, offset: 0x40 */
-  __I  uint32_t PSR;                               /**< Protocol Status Register, offset: 0x44 */
-  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator Register, offset: 0x48 */
-       uint8_t RESERVED_3[4];
-  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x50 */
-  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
-  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
-  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
-       uint8_t RESERVED_4[32];
-  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
-  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
-  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
-       uint8_t RESERVED_5[4];
-  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
-  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
-  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
-  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
-  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
-  __IO uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
-  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
-  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
-  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
-  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
-  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
-  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
-  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
-  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
-  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
-  __IO uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
-  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
-  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
-  __IO uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
-  __IO uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
-  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
-  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
-       uint8_t RESERVED_6[8];
-  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
-  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
-  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
-       uint8_t RESERVED_7[260];
-  __IO uint32_t MRBA;                              /**< CAN Message RAM Base Address, offset: 0x200 */
-       uint8_t RESERVED_8[508];
-  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
-       uint8_t RESERVED_9[508];
-  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
-} CAN_Type;
-
-/* ----------------------------------------------------------------------------
-   -- CAN Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Masks CAN Register Masks
- * @{
- */
-
-/*! @name TEST - Test Register */
-#define CAN_TEST_LBCK_MASK                       (0x10U)
-#define CAN_TEST_LBCK_SHIFT                      (4U)
-#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
-#define CAN_TEST_TX_MASK                         (0x60U)
-#define CAN_TEST_TX_SHIFT                        (5U)
-#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
-#define CAN_TEST_RX_MASK                         (0x80U)
-#define CAN_TEST_RX_SHIFT                        (7U)
-#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
-
-/*! @name CCCR - CC Control Register */
-#define CAN_CCCR_INIT_MASK                       (0x1U)
-#define CAN_CCCR_INIT_SHIFT                      (0U)
-#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
-#define CAN_CCCR_CCE_MASK                        (0x2U)
-#define CAN_CCCR_CCE_SHIFT                       (1U)
-#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
-#define CAN_CCCR_ASM_MASK                        (0x4U)
-#define CAN_CCCR_ASM_SHIFT                       (2U)
-#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
-#define CAN_CCCR_CSA_MASK                        (0x8U)
-#define CAN_CCCR_CSA_SHIFT                       (3U)
-#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
-#define CAN_CCCR_CSR_MASK                        (0x10U)
-#define CAN_CCCR_CSR_SHIFT                       (4U)
-#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
-#define CAN_CCCR_MON_MASK                        (0x20U)
-#define CAN_CCCR_MON_SHIFT                       (5U)
-#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
-#define CAN_CCCR_DAR_MASK                        (0x40U)
-#define CAN_CCCR_DAR_SHIFT                       (6U)
-#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
-#define CAN_CCCR_TEST_MASK                       (0x80U)
-#define CAN_CCCR_TEST_SHIFT                      (7U)
-#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
-#define CAN_CCCR_PXHD_MASK                       (0x1000U)
-#define CAN_CCCR_PXHD_SHIFT                      (12U)
-#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
-#define CAN_CCCR_EFBI_MASK                       (0x2000U)
-#define CAN_CCCR_EFBI_SHIFT                      (13U)
-#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
-#define CAN_CCCR_TXP_MASK                        (0x4000U)
-#define CAN_CCCR_TXP_SHIFT                       (14U)
-#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
-
-/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
-#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
-#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
-#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
-#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
-#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
-#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
-#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
-#define CAN_NBTP_NBRP_SHIFT                      (16U)
-#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
-#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
-#define CAN_NBTP_NSJW_SHIFT                      (25U)
-#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
-
-/*! @name TSCC - Timestamp Counter Configuration */
-#define CAN_TSCC_TSS_MASK                        (0x3U)
-#define CAN_TSCC_TSS_SHIFT                       (0U)
-#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
-#define CAN_TSCC_TCP_MASK                        (0xF0000U)
-#define CAN_TSCC_TCP_SHIFT                       (16U)
-#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
-
-/*! @name TSCV - Timestamp Counter Value */
-#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
-#define CAN_TSCV_TSC_SHIFT                       (0U)
-#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
-
-/*! @name TOCC - Timeout Counter Configuration */
-#define CAN_TOCC_ETOC_MASK                       (0x1U)
-#define CAN_TOCC_ETOC_SHIFT                      (0U)
-#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
-#define CAN_TOCC_TOS_MASK                        (0x6U)
-#define CAN_TOCC_TOS_SHIFT                       (1U)
-#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
-#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
-#define CAN_TOCC_TOP_SHIFT                       (16U)
-#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
-
-/*! @name TOCV - Timeout Counter Value */
-#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
-#define CAN_TOCV_TOC_SHIFT                       (0U)
-#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
-
-/*! @name ECR - Error Counter Register */
-#define CAN_ECR_TEC_MASK                         (0xFFU)
-#define CAN_ECR_TEC_SHIFT                        (0U)
-#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
-#define CAN_ECR_REC_MASK                         (0x7F00U)
-#define CAN_ECR_REC_SHIFT                        (8U)
-#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
-#define CAN_ECR_RP_MASK                          (0x8000U)
-#define CAN_ECR_RP_SHIFT                         (15U)
-#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
-#define CAN_ECR_CEL_MASK                         (0xFF0000U)
-#define CAN_ECR_CEL_SHIFT                        (16U)
-#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
-
-/*! @name PSR - Protocol Status Register */
-#define CAN_PSR_LEC_MASK                         (0x7U)
-#define CAN_PSR_LEC_SHIFT                        (0U)
-#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
-#define CAN_PSR_ACT_MASK                         (0x18U)
-#define CAN_PSR_ACT_SHIFT                        (3U)
-#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
-#define CAN_PSR_EP_MASK                          (0x20U)
-#define CAN_PSR_EP_SHIFT                         (5U)
-#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
-#define CAN_PSR_EW_MASK                          (0x40U)
-#define CAN_PSR_EW_SHIFT                         (6U)
-#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
-#define CAN_PSR_BO_MASK                          (0x80U)
-#define CAN_PSR_BO_SHIFT                         (7U)
-#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
-#define CAN_PSR_PXE_MASK                         (0x4000U)
-#define CAN_PSR_PXE_SHIFT                        (14U)
-#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
-#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
-#define CAN_PSR_TDCV_SHIFT                       (16U)
-#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
-
-/*! @name TDCR - Transmitter Delay Compensator Register */
-#define CAN_TDCR_TDCF_MASK                       (0x7FU)
-#define CAN_TDCR_TDCF_SHIFT                      (0U)
-#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
-#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
-#define CAN_TDCR_TDCO_SHIFT                      (8U)
-#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
-
-/*! @name IR - Interrupt Register */
-#define CAN_IR_RF0N_MASK                         (0x1U)
-#define CAN_IR_RF0N_SHIFT                        (0U)
-#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
-#define CAN_IR_RF0W_MASK                         (0x2U)
-#define CAN_IR_RF0W_SHIFT                        (1U)
-#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
-#define CAN_IR_RF0F_MASK                         (0x4U)
-#define CAN_IR_RF0F_SHIFT                        (2U)
-#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
-#define CAN_IR_RF0L_MASK                         (0x8U)
-#define CAN_IR_RF0L_SHIFT                        (3U)
-#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
-#define CAN_IR_RF1N_MASK                         (0x10U)
-#define CAN_IR_RF1N_SHIFT                        (4U)
-#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
-#define CAN_IR_RF1W_MASK                         (0x20U)
-#define CAN_IR_RF1W_SHIFT                        (5U)
-#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
-#define CAN_IR_RF1F_MASK                         (0x40U)
-#define CAN_IR_RF1F_SHIFT                        (6U)
-#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
-#define CAN_IR_RF1L_MASK                         (0x80U)
-#define CAN_IR_RF1L_SHIFT                        (7U)
-#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
-#define CAN_IR_HPM_MASK                          (0x100U)
-#define CAN_IR_HPM_SHIFT                         (8U)
-#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
-#define CAN_IR_TC_MASK                           (0x200U)
-#define CAN_IR_TC_SHIFT                          (9U)
-#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
-#define CAN_IR_TCF_MASK                          (0x400U)
-#define CAN_IR_TCF_SHIFT                         (10U)
-#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
-#define CAN_IR_TFE_MASK                          (0x800U)
-#define CAN_IR_TFE_SHIFT                         (11U)
-#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
-#define CAN_IR_TEFN_MASK                         (0x1000U)
-#define CAN_IR_TEFN_SHIFT                        (12U)
-#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
-#define CAN_IR_TEFW_MASK                         (0x2000U)
-#define CAN_IR_TEFW_SHIFT                        (13U)
-#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
-#define CAN_IR_TEFF_MASK                         (0x4000U)
-#define CAN_IR_TEFF_SHIFT                        (14U)
-#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
-#define CAN_IR_TEFL_MASK                         (0x8000U)
-#define CAN_IR_TEFL_SHIFT                        (15U)
-#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
-#define CAN_IR_TSW_MASK                          (0x10000U)
-#define CAN_IR_TSW_SHIFT                         (16U)
-#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
-#define CAN_IR_MRAF_MASK                         (0x20000U)
-#define CAN_IR_MRAF_SHIFT                        (17U)
-#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
-#define CAN_IR_TOO_MASK                          (0x40000U)
-#define CAN_IR_TOO_SHIFT                         (18U)
-#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
-#define CAN_IR_DRX_MASK                          (0x80000U)
-#define CAN_IR_DRX_SHIFT                         (19U)
-#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
-#define CAN_IR_BEC_MASK                          (0x100000U)
-#define CAN_IR_BEC_SHIFT                         (20U)
-#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
-#define CAN_IR_BEU_MASK                          (0x200000U)
-#define CAN_IR_BEU_SHIFT                         (21U)
-#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
-#define CAN_IR_ELO_MASK                          (0x400000U)
-#define CAN_IR_ELO_SHIFT                         (22U)
-#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
-#define CAN_IR_EP_MASK                           (0x800000U)
-#define CAN_IR_EP_SHIFT                          (23U)
-#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
-#define CAN_IR_EW_MASK                           (0x1000000U)
-#define CAN_IR_EW_SHIFT                          (24U)
-#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
-#define CAN_IR_BO_MASK                           (0x2000000U)
-#define CAN_IR_BO_SHIFT                          (25U)
-#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
-#define CAN_IR_WDI_MASK                          (0x4000000U)
-#define CAN_IR_WDI_SHIFT                         (26U)
-#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
-#define CAN_IR_PEA_MASK                          (0x8000000U)
-#define CAN_IR_PEA_SHIFT                         (27U)
-#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
-#define CAN_IR_PED_MASK                          (0x10000000U)
-#define CAN_IR_PED_SHIFT                         (28U)
-#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
-#define CAN_IR_ARA_MASK                          (0x20000000U)
-#define CAN_IR_ARA_SHIFT                         (29U)
-#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
-
-/*! @name IE - Interrupt Enable */
-#define CAN_IE_RF0NE_MASK                        (0x1U)
-#define CAN_IE_RF0NE_SHIFT                       (0U)
-#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
-#define CAN_IE_RF0WE_MASK                        (0x2U)
-#define CAN_IE_RF0WE_SHIFT                       (1U)
-#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
-#define CAN_IE_RF0FE_MASK                        (0x4U)
-#define CAN_IE_RF0FE_SHIFT                       (2U)
-#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
-#define CAN_IE_RF0LE_MASK                        (0x8U)
-#define CAN_IE_RF0LE_SHIFT                       (3U)
-#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
-#define CAN_IE_RF1NE_MASK                        (0x10U)
-#define CAN_IE_RF1NE_SHIFT                       (4U)
-#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
-#define CAN_IE_RF1WE_MASK                        (0x20U)
-#define CAN_IE_RF1WE_SHIFT                       (5U)
-#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
-#define CAN_IE_RF1FE_MASK                        (0x40U)
-#define CAN_IE_RF1FE_SHIFT                       (6U)
-#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
-#define CAN_IE_RF1LE_MASK                        (0x80U)
-#define CAN_IE_RF1LE_SHIFT                       (7U)
-#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
-#define CAN_IE_HPME_MASK                         (0x100U)
-#define CAN_IE_HPME_SHIFT                        (8U)
-#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
-#define CAN_IE_TCE_MASK                          (0x200U)
-#define CAN_IE_TCE_SHIFT                         (9U)
-#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
-#define CAN_IE_TCFE_MASK                         (0x400U)
-#define CAN_IE_TCFE_SHIFT                        (10U)
-#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
-#define CAN_IE_TFEE_MASK                         (0x800U)
-#define CAN_IE_TFEE_SHIFT                        (11U)
-#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
-#define CAN_IE_TEFNE_MASK                        (0x1000U)
-#define CAN_IE_TEFNE_SHIFT                       (12U)
-#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
-#define CAN_IE_TEFWE_MASK                        (0x2000U)
-#define CAN_IE_TEFWE_SHIFT                       (13U)
-#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
-#define CAN_IE_TEFFE_MASK                        (0x4000U)
-#define CAN_IE_TEFFE_SHIFT                       (14U)
-#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
-#define CAN_IE_TEFLE_MASK                        (0x8000U)
-#define CAN_IE_TEFLE_SHIFT                       (15U)
-#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
-#define CAN_IE_TSWE_MASK                         (0x10000U)
-#define CAN_IE_TSWE_SHIFT                        (16U)
-#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
-#define CAN_IE_MRAFE_MASK                        (0x20000U)
-#define CAN_IE_MRAFE_SHIFT                       (17U)
-#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
-#define CAN_IE_TOOE_MASK                         (0x40000U)
-#define CAN_IE_TOOE_SHIFT                        (18U)
-#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
-#define CAN_IE_DRXE_MASK                         (0x80000U)
-#define CAN_IE_DRXE_SHIFT                        (19U)
-#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
-#define CAN_IE_BECE_MASK                         (0x100000U)
-#define CAN_IE_BECE_SHIFT                        (20U)
-#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
-#define CAN_IE_BEUE_MASK                         (0x200000U)
-#define CAN_IE_BEUE_SHIFT                        (21U)
-#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
-#define CAN_IE_ELOE_MASK                         (0x400000U)
-#define CAN_IE_ELOE_SHIFT                        (22U)
-#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
-#define CAN_IE_EPE_MASK                          (0x800000U)
-#define CAN_IE_EPE_SHIFT                         (23U)
-#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
-#define CAN_IE_EWE_MASK                          (0x1000000U)
-#define CAN_IE_EWE_SHIFT                         (24U)
-#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
-#define CAN_IE_BOE_MASK                          (0x2000000U)
-#define CAN_IE_BOE_SHIFT                         (25U)
-#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
-#define CAN_IE_WDIE_MASK                         (0x4000000U)
-#define CAN_IE_WDIE_SHIFT                        (26U)
-#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
-#define CAN_IE_PEAE_MASK                         (0x8000000U)
-#define CAN_IE_PEAE_SHIFT                        (27U)
-#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
-#define CAN_IE_PEDE_MASK                         (0x10000000U)
-#define CAN_IE_PEDE_SHIFT                        (28U)
-#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
-#define CAN_IE_ARAE_MASK                         (0x20000000U)
-#define CAN_IE_ARAE_SHIFT                        (29U)
-#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
-
-/*! @name ILS - Interrupt Line Select */
-#define CAN_ILS_RF0NL_MASK                       (0x1U)
-#define CAN_ILS_RF0NL_SHIFT                      (0U)
-#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
-#define CAN_ILS_RF0WL_MASK                       (0x2U)
-#define CAN_ILS_RF0WL_SHIFT                      (1U)
-#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
-#define CAN_ILS_RF0FL_MASK                       (0x4U)
-#define CAN_ILS_RF0FL_SHIFT                      (2U)
-#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
-#define CAN_ILS_RF0LL_MASK                       (0x8U)
-#define CAN_ILS_RF0LL_SHIFT                      (3U)
-#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
-#define CAN_ILS_RF1NL_MASK                       (0x10U)
-#define CAN_ILS_RF1NL_SHIFT                      (4U)
-#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
-#define CAN_ILS_RF1WL_MASK                       (0x20U)
-#define CAN_ILS_RF1WL_SHIFT                      (5U)
-#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
-#define CAN_ILS_RF1FL_MASK                       (0x40U)
-#define CAN_ILS_RF1FL_SHIFT                      (6U)
-#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
-#define CAN_ILS_RF1LL_MASK                       (0x80U)
-#define CAN_ILS_RF1LL_SHIFT                      (7U)
-#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
-#define CAN_ILS_HPML_MASK                        (0x100U)
-#define CAN_ILS_HPML_SHIFT                       (8U)
-#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
-#define CAN_ILS_TCL_MASK                         (0x200U)
-#define CAN_ILS_TCL_SHIFT                        (9U)
-#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
-#define CAN_ILS_TCFL_MASK                        (0x400U)
-#define CAN_ILS_TCFL_SHIFT                       (10U)
-#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
-#define CAN_ILS_TFEL_MASK                        (0x800U)
-#define CAN_ILS_TFEL_SHIFT                       (11U)
-#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
-#define CAN_ILS_TEFNL_MASK                       (0x1000U)
-#define CAN_ILS_TEFNL_SHIFT                      (12U)
-#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
-#define CAN_ILS_TEFWL_MASK                       (0x2000U)
-#define CAN_ILS_TEFWL_SHIFT                      (13U)
-#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
-#define CAN_ILS_TEFFL_MASK                       (0x4000U)
-#define CAN_ILS_TEFFL_SHIFT                      (14U)
-#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
-#define CAN_ILS_TEFLL_MASK                       (0x8000U)
-#define CAN_ILS_TEFLL_SHIFT                      (15U)
-#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
-#define CAN_ILS_TSWL_MASK                        (0x10000U)
-#define CAN_ILS_TSWL_SHIFT                       (16U)
-#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
-#define CAN_ILS_MRAFL_MASK                       (0x20000U)
-#define CAN_ILS_MRAFL_SHIFT                      (17U)
-#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
-#define CAN_ILS_TOOL_MASK                        (0x40000U)
-#define CAN_ILS_TOOL_SHIFT                       (18U)
-#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
-#define CAN_ILS_DRXL_MASK                        (0x80000U)
-#define CAN_ILS_DRXL_SHIFT                       (19U)
-#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
-#define CAN_ILS_BECL_MASK                        (0x100000U)
-#define CAN_ILS_BECL_SHIFT                       (20U)
-#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
-#define CAN_ILS_BEUL_MASK                        (0x200000U)
-#define CAN_ILS_BEUL_SHIFT                       (21U)
-#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
-#define CAN_ILS_ELOL_MASK                        (0x400000U)
-#define CAN_ILS_ELOL_SHIFT                       (22U)
-#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
-#define CAN_ILS_EPL_MASK                         (0x800000U)
-#define CAN_ILS_EPL_SHIFT                        (23U)
-#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
-#define CAN_ILS_EWL_MASK                         (0x1000000U)
-#define CAN_ILS_EWL_SHIFT                        (24U)
-#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
-#define CAN_ILS_BOL_MASK                         (0x2000000U)
-#define CAN_ILS_BOL_SHIFT                        (25U)
-#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
-#define CAN_ILS_WDIL_MASK                        (0x4000000U)
-#define CAN_ILS_WDIL_SHIFT                       (26U)
-#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
-#define CAN_ILS_PEAL_MASK                        (0x8000000U)
-#define CAN_ILS_PEAL_SHIFT                       (27U)
-#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
-#define CAN_ILS_PEDL_MASK                        (0x10000000U)
-#define CAN_ILS_PEDL_SHIFT                       (28U)
-#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
-#define CAN_ILS_ARAL_MASK                        (0x20000000U)
-#define CAN_ILS_ARAL_SHIFT                       (29U)
-#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
-
-/*! @name ILE - Interrupt Line Enable */
-#define CAN_ILE_EINT0_MASK                       (0x1U)
-#define CAN_ILE_EINT0_SHIFT                      (0U)
-#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
-#define CAN_ILE_EINT1_MASK                       (0x2U)
-#define CAN_ILE_EINT1_SHIFT                      (1U)
-#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
-
-/*! @name GFC - Global Filter Configuration */
-#define CAN_GFC_RRFE_MASK                        (0x1U)
-#define CAN_GFC_RRFE_SHIFT                       (0U)
-#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
-#define CAN_GFC_RRFS_MASK                        (0x2U)
-#define CAN_GFC_RRFS_SHIFT                       (1U)
-#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
-#define CAN_GFC_ANFE_MASK                        (0xCU)
-#define CAN_GFC_ANFE_SHIFT                       (2U)
-#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
-#define CAN_GFC_ANFS_MASK                        (0x30U)
-#define CAN_GFC_ANFS_SHIFT                       (4U)
-#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
-
-/*! @name SIDFC - Standard ID Filter Configuration */
-#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
-#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
-#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
-#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
-#define CAN_SIDFC_LSS_SHIFT                      (16U)
-#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
-
-/*! @name XIDFC - Extended ID Filter Configuration */
-#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
-#define CAN_XIDFC_FLESA_SHIFT                    (2U)
-#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
-#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
-#define CAN_XIDFC_LSE_SHIFT                      (16U)
-#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
-
-/*! @name XIDAM - Extended ID AND Mask */
-#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
-#define CAN_XIDAM_EIDM_SHIFT                     (0U)
-#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
-
-/*! @name HPMS - High Priority Message Status */
-#define CAN_HPMS_BIDX_MASK                       (0x3FU)
-#define CAN_HPMS_BIDX_SHIFT                      (0U)
-#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
-#define CAN_HPMS_MSI_MASK                        (0xC0U)
-#define CAN_HPMS_MSI_SHIFT                       (6U)
-#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
-#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
-#define CAN_HPMS_FIDX_SHIFT                      (8U)
-#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
-#define CAN_HPMS_FLST_MASK                       (0x8000U)
-#define CAN_HPMS_FLST_SHIFT                      (15U)
-#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
-
-/*! @name NDAT1 - New Data 1 */
-#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
-#define CAN_NDAT1_ND_SHIFT                       (0U)
-#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
-
-/*! @name NDAT2 - New Data 2 */
-#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
-#define CAN_NDAT2_ND_SHIFT                       (0U)
-#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
-
-/*! @name RXF0C - Rx FIFO 0 Configuration */
-#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
-#define CAN_RXF0C_F0SA_SHIFT                     (2U)
-#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
-#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
-#define CAN_RXF0C_F0S_SHIFT                      (16U)
-#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
-#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
-#define CAN_RXF0C_F0WM_SHIFT                     (24U)
-#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
-#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
-#define CAN_RXF0C_F0OM_SHIFT                     (31U)
-#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
-
-/*! @name RXF0S - Rx FIFO 0 Status */
-#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
-#define CAN_RXF0S_F0FL_SHIFT                     (0U)
-#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
-#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
-#define CAN_RXF0S_F0GI_SHIFT                     (8U)
-#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
-#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
-#define CAN_RXF0S_F0PI_SHIFT                     (16U)
-#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
-#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
-#define CAN_RXF0S_F0F_SHIFT                      (24U)
-#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
-#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
-#define CAN_RXF0S_RF0L_SHIFT                     (25U)
-#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
-
-/*! @name RXF0A - Rx FIFO 0 Acknowledge */
-#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
-#define CAN_RXF0A_F0AI_SHIFT                     (0U)
-#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
-
-/*! @name RXBC - Rx Buffer Configuration */
-#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
-#define CAN_RXBC_RBSA_SHIFT                      (2U)
-#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
-
-/*! @name RXF1C - Rx FIFO 1 Configuration */
-#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
-#define CAN_RXF1C_F1SA_SHIFT                     (2U)
-#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
-#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
-#define CAN_RXF1C_F1S_SHIFT                      (16U)
-#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
-#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
-#define CAN_RXF1C_F1WM_SHIFT                     (24U)
-#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
-#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
-#define CAN_RXF1C_F1OM_SHIFT                     (31U)
-#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
-
-/*! @name RXF1S - Rx FIFO 1 Status */
-#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
-#define CAN_RXF1S_F1FL_SHIFT                     (0U)
-#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
-#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
-#define CAN_RXF1S_F1GI_SHIFT                     (8U)
-#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
-#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
-#define CAN_RXF1S_F1PI_SHIFT                     (16U)
-#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
-#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
-#define CAN_RXF1S_F1F_SHIFT                      (24U)
-#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
-#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
-#define CAN_RXF1S_RF1L_SHIFT                     (25U)
-#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
-
-/*! @name RXF1A - Rx FIFO 1 Acknowledge */
-#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
-#define CAN_RXF1A_F1AI_SHIFT                     (0U)
-#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
-
-/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
-#define CAN_RXESC_F0DS_MASK                      (0x7U)
-#define CAN_RXESC_F0DS_SHIFT                     (0U)
-#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
-#define CAN_RXESC_F1DS_MASK                      (0x70U)
-#define CAN_RXESC_F1DS_SHIFT                     (4U)
-#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
-#define CAN_RXESC_RBDS_MASK                      (0x700U)
-#define CAN_RXESC_RBDS_SHIFT                     (8U)
-#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
-
-/*! @name TXBC - Tx Buffer Configuration */
-#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
-#define CAN_TXBC_TBSA_SHIFT                      (2U)
-#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
-#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
-#define CAN_TXBC_NDTB_SHIFT                      (16U)
-#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
-#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
-#define CAN_TXBC_TFQS_SHIFT                      (24U)
-#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
-#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
-#define CAN_TXBC_TFQM_SHIFT                      (30U)
-#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
-
-/*! @name TXFQS - Tx FIFO/Queue Status */
-#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
-#define CAN_TXFQS_TFGI_SHIFT                     (8U)
-#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
-#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
-#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
-#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
-#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
-#define CAN_TXFQS_TFQF_SHIFT                     (21U)
-#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
-
-/*! @name TXESC - Tx Buffer Element Size Configuration */
-#define CAN_TXESC_TBDS_MASK                      (0x7U)
-#define CAN_TXESC_TBDS_SHIFT                     (0U)
-#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
-
-/*! @name TXBRP - Tx Buffer Request Pending */
-#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
-#define CAN_TXBRP_TRP_SHIFT                      (0U)
-#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
-
-/*! @name TXBAR - Tx Buffer Add Request */
-#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
-#define CAN_TXBAR_AR_SHIFT                       (0U)
-#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
-
-/*! @name TXBCR - Tx Buffer Cancellation Request */
-#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
-#define CAN_TXBCR_CR_SHIFT                       (0U)
-#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
-
-/*! @name TXBTO - Tx Buffer Transmission Occurred */
-#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
-#define CAN_TXBTO_TO_SHIFT                       (0U)
-#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
-
-/*! @name TXBCF - Tx Buffer Cancellation Finished */
-#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
-#define CAN_TXBCF_TO_SHIFT                       (0U)
-#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
-
-/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
-#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
-#define CAN_TXBTIE_TIE_SHIFT                     (0U)
-#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
-
-/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
-#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
-#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
-#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
-
-/*! @name TXEFC - Tx Event FIFO Configuration */
-#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
-#define CAN_TXEFC_EFSA_SHIFT                     (2U)
-#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
-#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
-#define CAN_TXEFC_EFS_SHIFT                      (16U)
-#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
-#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
-#define CAN_TXEFC_EFWM_SHIFT                     (24U)
-#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
-
-/*! @name TXEFS - Tx Event FIFO Status */
-#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
-#define CAN_TXEFS_EFFL_SHIFT                     (0U)
-#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
-#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
-#define CAN_TXEFS_EFGI_SHIFT                     (8U)
-#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
-#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
-#define CAN_TXEFS_EFPI_SHIFT                     (16U)
-#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
-#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
-#define CAN_TXEFS_EFF_SHIFT                      (24U)
-#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
-#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
-#define CAN_TXEFS_TEFL_SHIFT                     (25U)
-#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
-
-/*! @name TXEFA - Tx Event FIFO Acknowledge */
-#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
-#define CAN_TXEFA_EFAI_SHIFT                     (0U)
-#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
-
-/*! @name MRBA - CAN Message RAM Base Address */
-#define CAN_MRBA_BA_MASK                         (0xFFFFFFFFU)
-#define CAN_MRBA_BA_SHIFT                        (0U)
-#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
-
-/*! @name ETSCC - External Timestamp Counter Configuration */
-#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
-#define CAN_ETSCC_ETCP_SHIFT                     (0U)
-#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
-#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
-#define CAN_ETSCC_ETCE_SHIFT                     (31U)
-#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
-
-/*! @name ETSCV - External Timestamp Counter Value */
-#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
-#define CAN_ETSCV_ETSC_SHIFT                     (0U)
-#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
-
-
-/*!
- * @}
- */ /* end of group CAN_Register_Masks */
-
-
-/* CAN - Peripheral instance base addresses */
-/** Peripheral CAN0 base address */
-#define CAN0_BASE                                (0x4009D000u)
-/** Peripheral CAN0 base pointer */
-#define CAN0                                     ((CAN_Type *)CAN0_BASE)
-/** Peripheral CAN1 base address */
-#define CAN1_BASE                                (0x4009E000u)
-/** Peripheral CAN1 base pointer */
-#define CAN1                                     ((CAN_Type *)CAN1_BASE)
-/** Array initializer of CAN peripheral base addresses */
-#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
-/** Array initializer of CAN peripheral base pointers */
-#define CAN_BASE_PTRS                            { CAN0, CAN1 }
-/** Interrupt vectors for the CAN peripheral type */
-#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
-
-/*!
- * @}
- */ /* end of group CAN_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- CRC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
-  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
-  union {                                          /* offset: 0x8 */
-    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
-    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
-  };
-} CRC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- CRC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/*! @name MODE - CRC mode register */
-#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
-#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
-#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
-#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
-#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
-#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
-#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
-#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
-#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
-#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
-#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
-#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
-#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
-#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
-#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
-
-/*! @name SEED - CRC seed register */
-#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
-#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
-#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
-
-/*! @name SUM - CRC checksum register */
-#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
-#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
-#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
-
-/*! @name WR_DATA - CRC data register */
-#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
-#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
-#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
-
-
-/*!
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC_ENGINE base address */
-#define CRC_ENGINE_BASE                          (0x40095000u)
-/** Peripheral CRC_ENGINE base pointer */
-#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS                            { CRC_ENGINE }
-
-/*!
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- CTIMER Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
- * @{
- */
-
-/** CTIMER - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
-  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
-  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
-  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
-  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
-  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
-  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
-  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
-  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
-  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
-       uint8_t RESERVED_0[48];
-  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
-  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
-  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
-} CTIMER_Type;
-
-/* ----------------------------------------------------------------------------
-   -- CTIMER Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
- * @{
- */
-
-/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-#define CTIMER_IR_MR0INT_MASK                    (0x1U)
-#define CTIMER_IR_MR0INT_SHIFT                   (0U)
-#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
-#define CTIMER_IR_MR1INT_MASK                    (0x2U)
-#define CTIMER_IR_MR1INT_SHIFT                   (1U)
-#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
-#define CTIMER_IR_MR2INT_MASK                    (0x4U)
-#define CTIMER_IR_MR2INT_SHIFT                   (2U)
-#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
-#define CTIMER_IR_MR3INT_MASK                    (0x8U)
-#define CTIMER_IR_MR3INT_SHIFT                   (3U)
-#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
-#define CTIMER_IR_CR0INT_MASK                    (0x10U)
-#define CTIMER_IR_CR0INT_SHIFT                   (4U)
-#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
-#define CTIMER_IR_CR1INT_MASK                    (0x20U)
-#define CTIMER_IR_CR1INT_SHIFT                   (5U)
-#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
-#define CTIMER_IR_CR2INT_MASK                    (0x40U)
-#define CTIMER_IR_CR2INT_SHIFT                   (6U)
-#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
-#define CTIMER_IR_CR3INT_MASK                    (0x80U)
-#define CTIMER_IR_CR3INT_SHIFT                   (7U)
-#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
-
-/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-#define CTIMER_TCR_CEN_MASK                      (0x1U)
-#define CTIMER_TCR_CEN_SHIFT                     (0U)
-#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
-#define CTIMER_TCR_CRST_MASK                     (0x2U)
-#define CTIMER_TCR_CRST_SHIFT                    (1U)
-#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
-
-/*! @name TC - Timer Counter */
-#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
-#define CTIMER_TC_TCVAL_SHIFT                    (0U)
-#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
-
-/*! @name PR - Prescale Register */
-#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
-#define CTIMER_PR_PRVAL_SHIFT                    (0U)
-#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
-
-/*! @name PC - Prescale Counter */
-#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
-#define CTIMER_PC_PCVAL_SHIFT                    (0U)
-#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
-
-/*! @name MCR - Match Control Register */
-#define CTIMER_MCR_MR0I_MASK                     (0x1U)
-#define CTIMER_MCR_MR0I_SHIFT                    (0U)
-#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
-#define CTIMER_MCR_MR0R_MASK                     (0x2U)
-#define CTIMER_MCR_MR0R_SHIFT                    (1U)
-#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
-#define CTIMER_MCR_MR0S_MASK                     (0x4U)
-#define CTIMER_MCR_MR0S_SHIFT                    (2U)
-#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
-#define CTIMER_MCR_MR1I_MASK                     (0x8U)
-#define CTIMER_MCR_MR1I_SHIFT                    (3U)
-#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
-#define CTIMER_MCR_MR1R_MASK                     (0x10U)
-#define CTIMER_MCR_MR1R_SHIFT                    (4U)
-#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
-#define CTIMER_MCR_MR1S_MASK                     (0x20U)
-#define CTIMER_MCR_MR1S_SHIFT                    (5U)
-#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
-#define CTIMER_MCR_MR2I_MASK                     (0x40U)
-#define CTIMER_MCR_MR2I_SHIFT                    (6U)
-#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
-#define CTIMER_MCR_MR2R_MASK                     (0x80U)
-#define CTIMER_MCR_MR2R_SHIFT                    (7U)
-#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
-#define CTIMER_MCR_MR2S_MASK                     (0x100U)
-#define CTIMER_MCR_MR2S_SHIFT                    (8U)
-#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
-#define CTIMER_MCR_MR3I_MASK                     (0x200U)
-#define CTIMER_MCR_MR3I_SHIFT                    (9U)
-#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
-#define CTIMER_MCR_MR3R_MASK                     (0x400U)
-#define CTIMER_MCR_MR3R_SHIFT                    (10U)
-#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
-#define CTIMER_MCR_MR3S_MASK                     (0x800U)
-#define CTIMER_MCR_MR3S_SHIFT                    (11U)
-#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
-#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
-#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
-#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
-#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
-#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
-#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
-#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
-#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
-#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
-#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
-#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
-#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
-
-/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
-#define CTIMER_MR_MATCH_SHIFT                    (0U)
-#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
-
-/* The count of CTIMER_MR */
-#define CTIMER_MR_COUNT                          (4U)
-
-/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
-#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
-#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
-#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
-#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
-#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
-#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
-#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
-#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
-#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
-#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
-#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
-#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
-#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
-#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
-#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
-#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
-#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
-#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
-#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
-#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
-#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
-#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
-#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
-#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
-#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
-#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
-#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
-#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
-#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
-#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
-#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
-#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
-#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
-#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
-#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
-
-/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
-#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
-#define CTIMER_CR_CAP_SHIFT                      (0U)
-#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
-
-/* The count of CTIMER_CR */
-#define CTIMER_CR_COUNT                          (4U)
-
-/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
-#define CTIMER_EMR_EM0_MASK                      (0x1U)
-#define CTIMER_EMR_EM0_SHIFT                     (0U)
-#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
-#define CTIMER_EMR_EM1_MASK                      (0x2U)
-#define CTIMER_EMR_EM1_SHIFT                     (1U)
-#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
-#define CTIMER_EMR_EM2_MASK                      (0x4U)
-#define CTIMER_EMR_EM2_SHIFT                     (2U)
-#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
-#define CTIMER_EMR_EM3_MASK                      (0x8U)
-#define CTIMER_EMR_EM3_SHIFT                     (3U)
-#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
-#define CTIMER_EMR_EMC0_MASK                     (0x30U)
-#define CTIMER_EMR_EMC0_SHIFT                    (4U)
-#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
-#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
-#define CTIMER_EMR_EMC1_SHIFT                    (6U)
-#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
-#define CTIMER_EMR_EMC2_MASK                     (0x300U)
-#define CTIMER_EMR_EMC2_SHIFT                    (8U)
-#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
-#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
-#define CTIMER_EMR_EMC3_SHIFT                    (10U)
-#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
-
-/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
-#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
-#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
-#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
-#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
-#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
-#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
-#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
-#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
-#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
-#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
-#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
-
-/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
-#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
-#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
-#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
-#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
-#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
-#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
-#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
-#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
-#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
-#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
-#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
-#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
-
-/*! @name MSR - Match Shadow Register */
-#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
-#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
-#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
-
-/* The count of CTIMER_MSR */
-#define CTIMER_MSR_COUNT                         (4U)
-
-
-/*!
- * @}
- */ /* end of group CTIMER_Register_Masks */
-
-
-/* CTIMER - Peripheral instance base addresses */
-/** Peripheral CTIMER0 base address */
-#define CTIMER0_BASE                             (0x40008000u)
-/** Peripheral CTIMER0 base pointer */
-#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
-/** Peripheral CTIMER1 base address */
-#define CTIMER1_BASE                             (0x40009000u)
-/** Peripheral CTIMER1 base pointer */
-#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
-/** Peripheral CTIMER2 base address */
-#define CTIMER2_BASE                             (0x40028000u)
-/** Peripheral CTIMER2 base pointer */
-#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
-/** Peripheral CTIMER3 base address */
-#define CTIMER3_BASE                             (0x40048000u)
-/** Peripheral CTIMER3 base pointer */
-#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
-/** Peripheral CTIMER4 base address */
-#define CTIMER4_BASE                             (0x40049000u)
-/** Peripheral CTIMER4 base pointer */
-#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
-/** Array initializer of CTIMER peripheral base addresses */
-#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
-/** Array initializer of CTIMER peripheral base pointers */
-#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
-/** Interrupt vectors for the CTIMER peripheral type */
-#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
-
-/*!
- * @}
- */ /* end of group CTIMER_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- DMA Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
-  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
-  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
-       uint8_t RESERVED_0[20];
-  struct {                                         /* offset: 0x20, array step: 0x5C */
-    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
-         uint8_t RESERVED_0[4];
-    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
-         uint8_t RESERVED_1[4];
-    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
-         uint8_t RESERVED_2[4];
-    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
-         uint8_t RESERVED_3[4];
-    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
-         uint8_t RESERVED_4[4];
-    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
-         uint8_t RESERVED_5[4];
-    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
-         uint8_t RESERVED_6[4];
-    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
-         uint8_t RESERVED_7[4];
-    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
-         uint8_t RESERVED_8[4];
-    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
-         uint8_t RESERVED_9[4];
-    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
-         uint8_t RESERVED_10[4];
-    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
-  } COMMON[1];
-       uint8_t RESERVED_1[900];
-  struct {                                         /* offset: 0x400, array step: 0x10 */
-    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
-    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
-    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
-         uint8_t RESERVED_0[4];
-  } CHANNEL[30];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
-   -- DMA Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/*! @name CTRL - DMA control. */
-#define DMA_CTRL_ENABLE_MASK                     (0x1U)
-#define DMA_CTRL_ENABLE_SHIFT                    (0U)
-#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
-
-/*! @name INTSTAT - Interrupt status. */
-#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
-#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
-#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
-#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
-#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
-#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
-
-/*! @name SRAMBASE - SRAM address of the channel configuration table. */
-#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
-#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
-#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
-
-/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
-#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
-#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
-
-/* The count of DMA_COMMON_ENABLESET */
-#define DMA_COMMON_ENABLESET_COUNT               (1U)
-
-/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
-#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
-#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
-
-/* The count of DMA_COMMON_ENABLECLR */
-#define DMA_COMMON_ENABLECLR_COUNT               (1U)
-
-/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
-#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
-#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
-#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
-
-/* The count of DMA_COMMON_ACTIVE */
-#define DMA_COMMON_ACTIVE_COUNT                  (1U)
-
-/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
-#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
-#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
-#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
-
-/* The count of DMA_COMMON_BUSY */
-#define DMA_COMMON_BUSY_COUNT                    (1U)
-
-/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
-#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
-#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
-#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
-
-/* The count of DMA_COMMON_ERRINT */
-#define DMA_COMMON_ERRINT_COUNT                  (1U)
-
-/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
-#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
-#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
-#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
-
-/* The count of DMA_COMMON_INTENSET */
-#define DMA_COMMON_INTENSET_COUNT                (1U)
-
-/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
-#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
-#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
-#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
-
-/* The count of DMA_COMMON_INTENCLR */
-#define DMA_COMMON_INTENCLR_COUNT                (1U)
-
-/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
-#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
-#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
-#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
-
-/* The count of DMA_COMMON_INTA */
-#define DMA_COMMON_INTA_COUNT                    (1U)
-
-/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
-#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
-#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
-#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
-
-/* The count of DMA_COMMON_INTB */
-#define DMA_COMMON_INTB_COUNT                    (1U)
-
-/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
-#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
-#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
-#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
-
-/* The count of DMA_COMMON_SETVALID */
-#define DMA_COMMON_SETVALID_COUNT                (1U)
-
-/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
-#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
-#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
-#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
-
-/* The count of DMA_COMMON_SETTRIG */
-#define DMA_COMMON_SETTRIG_COUNT                 (1U)
-
-/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
-#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
-#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
-#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
-
-/* The count of DMA_COMMON_ABORT */
-#define DMA_COMMON_ABORT_COUNT                   (1U)
-
-/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
-#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
-#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
-#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
-#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
-#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
-#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
-#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
-#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
-#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
-#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
-#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
-#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
-#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
-#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
-#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
-#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
-#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
-#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
-#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
-#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
-
-/* The count of DMA_CHANNEL_CFG */
-#define DMA_CHANNEL_CFG_COUNT                    (30U)
-
-/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
-#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
-#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
-#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
-
-/* The count of DMA_CHANNEL_CTLSTAT */
-#define DMA_CHANNEL_CTLSTAT_COUNT                (30U)
-
-/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
-#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
-#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
-#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
-#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
-#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
-#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
-#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
-#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
-#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
-#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
-#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
-#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
-#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
-#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
-#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
-#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
-#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
-#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
-#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
-#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
-
-/* The count of DMA_CHANNEL_XFERCFG */
-#define DMA_CHANNEL_XFERCFG_COUNT                (30U)
-
-
-/*!
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA0 base address */
-#define DMA0_BASE                                (0x40082000u)
-/** Peripheral DMA0 base pointer */
-#define DMA0                                     ((DMA_Type *)DMA0_BASE)
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS                           { DMA0_BASE }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS                            { DMA0 }
-/** Interrupt vectors for the DMA peripheral type */
-#define DMA_IRQS                                 { DMA0_IRQn }
-
-/*!
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- DMIC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
- * @{
- */
-
-/** DMIC - Register Layout Typedef */
-typedef struct {
-  struct {                                         /* offset: 0x0, array step: 0x100 */
-    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
-    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
-    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
-    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
-    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
-         uint8_t RESERVED_0[108];
-    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
-    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
-    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
-    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
-    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
-         uint8_t RESERVED_1[108];
-  } CHANNEL[2];
-       uint8_t RESERVED_0[3328];
-  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
-       uint8_t RESERVED_1[8];
-  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
-  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
-       uint8_t RESERVED_2[108];
-  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
-  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
-  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
-  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
-  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
-  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
-  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
-       uint8_t RESERVED_3[96];
-  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
-} DMIC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- DMIC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMIC_Register_Masks DMIC Register Masks
- * @{
- */
-
-/*! @name CHANNEL_OSR - Oversample Rate register 0 */
-#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
-#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
-#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
-
-/* The count of DMIC_CHANNEL_OSR */
-#define DMIC_CHANNEL_OSR_COUNT                   (2U)
-
-/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
-
-/* The count of DMIC_CHANNEL_DIVHFCLK */
-#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
-
-/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
-
-/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
-#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
-
-/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
-
-/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
-#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
-
-/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
-#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
-#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
-#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
-
-/* The count of DMIC_CHANNEL_GAINSHIFT */
-#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
-
-/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_CTRL */
-#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
-
-/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
-#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
-#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
-#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_STATUS */
-#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
-
-/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
-#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
-#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
-#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_DATA */
-#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
-
-/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
-
-/* The count of DMIC_CHANNEL_PHY_CTRL */
-#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
-
-/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
-
-/* The count of DMIC_CHANNEL_DC_CTRL */
-#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
-
-/*! @name CHANEN - Channel Enable register */
-#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
-#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
-#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
-#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
-#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
-#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
-
-/*! @name IOCFG - I/O Configuration register */
-#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
-#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
-#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
-#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
-#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
-#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
-#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
-#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
-#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
-
-/*! @name USE2FS - Use 2FS register */
-#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
-#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
-#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
-
-/*! @name HWVADGAIN - HWVAD input gain register */
-#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
-#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
-#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
-
-/*! @name HWVADHPFS - HWVAD filter control register */
-#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
-#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
-#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
-
-/*! @name HWVADST10 - HWVAD control register */
-#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
-#define DMIC_HWVADST10_ST10_SHIFT                (0U)
-#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
-
-/*! @name HWVADRSTT - HWVAD filter reset register */
-#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
-#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
-#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
-
-/*! @name HWVADTHGN - HWVAD noise estimator gain register */
-#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
-#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
-#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
-
-/*! @name HWVADTHGS - HWVAD signal estimator gain register */
-#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
-#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
-#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
-
-/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
-#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
-#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
-#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
-
-/*! @name ID - Module Identification register */
-#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
-#define DMIC_ID_ID_SHIFT                         (0U)
-#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group DMIC_Register_Masks */
-
-
-/* DMIC - Peripheral instance base addresses */
-/** Peripheral DMIC0 base address */
-#define DMIC0_BASE                               (0x40090000u)
-/** Peripheral DMIC0 base pointer */
-#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
-/** Array initializer of DMIC peripheral base addresses */
-#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
-/** Array initializer of DMIC peripheral base pointers */
-#define DMIC_BASE_PTRS                           { DMIC0 }
-/** Interrupt vectors for the DMIC peripheral type */
-#define DMIC_IRQS                                { DMIC0_IRQn }
-#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
-
-/*!
- * @}
- */ /* end of group DMIC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- EEPROM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
- * @{
- */
-
-/** EEPROM - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CMD;                               /**< EEPROM command register, offset: 0x0 */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t RWSTATE;                           /**< EEPROM read wait state register, offset: 0x8 */
-  __IO uint32_t AUTOPROG;                          /**< EEPROM auto programming register, offset: 0xC */
-  __IO uint32_t WSTATE;                            /**< EEPROM wait state register, offset: 0x10 */
-  __IO uint32_t CLKDIV;                            /**< EEPROM clock divider register, offset: 0x14 */
-  __IO uint32_t PWRDWN;                            /**< EEPROM power-down register, offset: 0x18 */
-       uint8_t RESERVED_1[4028];
-  __O  uint32_t INTENCLR;                          /**< EEPROM interrupt enable clear, offset: 0xFD8 */
-  __O  uint32_t INTENSET;                          /**< EEPROM interrupt enable set, offset: 0xFDC */
-  __I  uint32_t INTSTAT;                           /**< EEPROM interrupt status, offset: 0xFE0 */
-  __I  uint32_t INTEN;                             /**< EEPROM interrupt enable, offset: 0xFE4 */
-  __O  uint32_t INTSTATCLR;                        /**< EEPROM interrupt status clear, offset: 0xFE8 */
-  __O  uint32_t INTSTATSET;                        /**< EEPROM interrupt status set, offset: 0xFEC */
-} EEPROM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- EEPROM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
- * @{
- */
-
-/*! @name CMD - EEPROM command register */
-#define EEPROM_CMD_CMD_MASK                      (0x7U)
-#define EEPROM_CMD_CMD_SHIFT                     (0U)
-#define EEPROM_CMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
-
-/*! @name RWSTATE - EEPROM read wait state register */
-#define EEPROM_RWSTATE_RPHASE2_MASK              (0xFFU)
-#define EEPROM_RWSTATE_RPHASE2_SHIFT             (0U)
-#define EEPROM_RWSTATE_RPHASE2(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
-#define EEPROM_RWSTATE_RPHASE1_MASK              (0xFF00U)
-#define EEPROM_RWSTATE_RPHASE1_SHIFT             (8U)
-#define EEPROM_RWSTATE_RPHASE1(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
-
-/*! @name AUTOPROG - EEPROM auto programming register */
-#define EEPROM_AUTOPROG_AUTOPROG_MASK            (0x3U)
-#define EEPROM_AUTOPROG_AUTOPROG_SHIFT           (0U)
-#define EEPROM_AUTOPROG_AUTOPROG(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
-
-/*! @name WSTATE - EEPROM wait state register */
-#define EEPROM_WSTATE_PHASE3_MASK                (0xFFU)
-#define EEPROM_WSTATE_PHASE3_SHIFT               (0U)
-#define EEPROM_WSTATE_PHASE3(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
-#define EEPROM_WSTATE_PHASE2_MASK                (0xFF00U)
-#define EEPROM_WSTATE_PHASE2_SHIFT               (8U)
-#define EEPROM_WSTATE_PHASE2(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
-#define EEPROM_WSTATE_PHASE1_MASK                (0xFF0000U)
-#define EEPROM_WSTATE_PHASE1_SHIFT               (16U)
-#define EEPROM_WSTATE_PHASE1(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
-#define EEPROM_WSTATE_LCK_PARWEP_MASK            (0x80000000U)
-#define EEPROM_WSTATE_LCK_PARWEP_SHIFT           (31U)
-#define EEPROM_WSTATE_LCK_PARWEP(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
-
-/*! @name CLKDIV - EEPROM clock divider register */
-#define EEPROM_CLKDIV_CLKDIV_MASK                (0xFFFFU)
-#define EEPROM_CLKDIV_CLKDIV_SHIFT               (0U)
-#define EEPROM_CLKDIV_CLKDIV(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
-
-/*! @name PWRDWN - EEPROM power-down register */
-#define EEPROM_PWRDWN_PWRDWN_MASK                (0x1U)
-#define EEPROM_PWRDWN_PWRDWN_SHIFT               (0U)
-#define EEPROM_PWRDWN_PWRDWN(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
-
-/*! @name INTENCLR - EEPROM interrupt enable clear */
-#define EEPROM_INTENCLR_PROG_CLR_EN_MASK         (0x4U)
-#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT        (2U)
-#define EEPROM_INTENCLR_PROG_CLR_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
-
-/*! @name INTENSET - EEPROM interrupt enable set */
-#define EEPROM_INTENSET_PROG_SET_EN_MASK         (0x4U)
-#define EEPROM_INTENSET_PROG_SET_EN_SHIFT        (2U)
-#define EEPROM_INTENSET_PROG_SET_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
-
-/*! @name INTSTAT - EEPROM interrupt status */
-#define EEPROM_INTSTAT_END_OF_PROG_MASK          (0x4U)
-#define EEPROM_INTSTAT_END_OF_PROG_SHIFT         (2U)
-#define EEPROM_INTSTAT_END_OF_PROG(x)            (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
-
-/*! @name INTEN - EEPROM interrupt enable */
-#define EEPROM_INTEN_EE_PROG_DONE_MASK           (0x4U)
-#define EEPROM_INTEN_EE_PROG_DONE_SHIFT          (2U)
-#define EEPROM_INTEN_EE_PROG_DONE(x)             (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
-
-/*! @name INTSTATCLR - EEPROM interrupt status clear */
-#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK       (0x4U)
-#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT      (2U)
-#define EEPROM_INTSTATCLR_PROG_CLR_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
-
-/*! @name INTSTATSET - EEPROM interrupt status set */
-#define EEPROM_INTSTATSET_PROG_SET_ST_MASK       (0x4U)
-#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT      (2U)
-#define EEPROM_INTSTATSET_PROG_SET_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
-
-
-/*!
- * @}
- */ /* end of group EEPROM_Register_Masks */
-
-
-/* EEPROM - Peripheral instance base addresses */
-/** Peripheral EEPROM base address */
-#define EEPROM_BASE                              (0x40014000u)
-/** Peripheral EEPROM base pointer */
-#define EEPROM                                   ((EEPROM_Type *)EEPROM_BASE)
-/** Array initializer of EEPROM peripheral base addresses */
-#define EEPROM_BASE_ADDRS                        { EEPROM_BASE }
-/** Array initializer of EEPROM peripheral base pointers */
-#define EEPROM_BASE_PTRS                         { EEPROM }
-/** Interrupt vectors for the EEPROM peripheral type */
-#define EEPROM_IRQS                              { EEPROM_IRQn }
-
-/*!
- * @}
- */ /* end of group EEPROM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- EMC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
- * @{
- */
-
-/** EMC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
-  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
-  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
-       uint8_t RESERVED_0[20];
-  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
-  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
-  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
-  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
-  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
-  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
-  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
-  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
-  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
-  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
-  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
-  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
-  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
-       uint8_t RESERVED_2[36];
-  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
-       uint8_t RESERVED_3[124];
-  struct {                                         /* offset: 0x100, array step: 0x20 */
-    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
-    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
-         uint8_t RESERVED_0[24];
-  } DYNAMIC[4];
-       uint8_t RESERVED_4[128];
-  struct {                                         /* offset: 0x200, array step: 0x20 */
-    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
-    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
-    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
-    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
-    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
-    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
-    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
-         uint8_t RESERVED_0[4];
-  } STATIC[4];
-} EMC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- EMC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EMC_Register_Masks EMC Register Masks
- * @{
- */
-
-/*! @name CONTROL - Controls operation of the memory controller */
-#define EMC_CONTROL_E_MASK                       (0x1U)
-#define EMC_CONTROL_E_SHIFT                      (0U)
-#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
-#define EMC_CONTROL_M_MASK                       (0x2U)
-#define EMC_CONTROL_M_SHIFT                      (1U)
-#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
-#define EMC_CONTROL_L_MASK                       (0x4U)
-#define EMC_CONTROL_L_SHIFT                      (2U)
-#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
-
-/*! @name STATUS - Provides EMC status information */
-#define EMC_STATUS_B_MASK                        (0x1U)
-#define EMC_STATUS_B_SHIFT                       (0U)
-#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
-#define EMC_STATUS_S_MASK                        (0x2U)
-#define EMC_STATUS_S_SHIFT                       (1U)
-#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
-#define EMC_STATUS_SA_MASK                       (0x4U)
-#define EMC_STATUS_SA_SHIFT                      (2U)
-#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
-
-/*! @name CONFIG - Configures operation of the memory controller */
-#define EMC_CONFIG_EM_MASK                       (0x1U)
-#define EMC_CONFIG_EM_SHIFT                      (0U)
-#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
-#define EMC_CONFIG_CLKR_MASK                     (0x100U)
-#define EMC_CONFIG_CLKR_SHIFT                    (8U)
-#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
-
-/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
-#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
-#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
-#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
-#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
-#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
-#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
-#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
-#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
-#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
-#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
-#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
-#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
-#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
-#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
-#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
-
-/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
-#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
-#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
-#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
-
-/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
-#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
-#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
-#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
-
-/*! @name DYNAMICRP - Precharge command period */
-#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
-#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
-#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
-
-/*! @name DYNAMICRAS - Active to precharge command period */
-#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
-#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
-#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
-
-/*! @name DYNAMICSREX - Self-refresh exit time */
-#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
-#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
-#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
-
-/*! @name DYNAMICAPR - Last-data-out to active command time */
-#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
-#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
-#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
-
-/*! @name DYNAMICDAL - Data-in to active command time */
-#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
-#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
-#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
-
-/*! @name DYNAMICWR - Write recovery time */
-#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
-#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
-#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
-
-/*! @name DYNAMICRC - Selects the active to active command period */
-#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
-#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
-#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
-
-/*! @name DYNAMICRFC - Selects the auto-refresh period */
-#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
-#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
-#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
-
-/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
-#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
-#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
-#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
-
-/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
-#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
-#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
-#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
-
-/*! @name DYNAMICMRD - Time for load mode register to active command */
-#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
-#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
-#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
-
-/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
-
-/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
-
-/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
-#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
-
-/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
-
-/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
-#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
-
-/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
-#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
-#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
-#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
-#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
-#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
-#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
-#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
-#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
-#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
-#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
-#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
-#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
-#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
-#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
-#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
-#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
-#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
-#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
-#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
-#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
-#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
-
-/* The count of EMC_STATIC_STATICCONFIG */
-#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
-
-/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
-#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
-#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
-#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITWEN */
-#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
-
-/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
-#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
-#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
-#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITOEN */
-#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
-
-/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
-#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
-#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
-#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
-
-/* The count of EMC_STATIC_STATICWAITRD */
-#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
-
-/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
-
-/* The count of EMC_STATIC_STATICWAITPAGE */
-#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
-
-/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
-#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
-#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
-#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
-
-/* The count of EMC_STATIC_STATICWAITWR */
-#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
-
-/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
-#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
-#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
-#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITTURN */
-#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
-
-
-/*!
- * @}
- */ /* end of group EMC_Register_Masks */
-
-
-/* EMC - Peripheral instance base addresses */
-/** Peripheral EMC base address */
-#define EMC_BASE                                 (0x40081000u)
-/** Peripheral EMC base pointer */
-#define EMC                                      ((EMC_Type *)EMC_BASE)
-/** Array initializer of EMC peripheral base addresses */
-#define EMC_BASE_ADDRS                           { EMC_BASE }
-/** Array initializer of EMC peripheral base pointers */
-#define EMC_BASE_PTRS                            { EMC }
-
-/*!
- * @}
- */ /* end of group EMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- ENET Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
- * @{
- */
-
-/** ENET - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t MAC_CONFIG;                        /**< MAC configuration register, offset: 0x0 */
-  __IO uint32_t MAC_EXT_CONFIG;                    /**< , offset: 0x4 */
-  __IO uint32_t MAC_FRAME_FILTER;                  /**< MAC frame filter register, offset: 0x8 */
-  __IO uint32_t MAC_WD_TIMEROUT;                   /**< MAC watchdog Timeout register, offset: 0xC */
-       uint8_t RESERVED_0[64];
-  __IO uint32_t MAC_VLAN_TAG;                      /**< MAC vlan tag register, offset: 0x50 */
-       uint8_t RESERVED_1[28];
-  __IO uint32_t MAC_TX_FLOW_CTRL_Q[2];             /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
-       uint8_t RESERVED_2[24];
-  __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< Receive flow control register, offset: 0x90 */
-       uint8_t RESERVED_3[4];
-  __IO uint32_t MAC_TXQ_PRIO_MAP;                  /**< , offset: 0x98 */
-       uint8_t RESERVED_4[4];
-  __IO uint32_t MAC_RXQ_CTRL[3];                   /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
-       uint8_t RESERVED_5[4];
-  __I  uint32_t MAC_INTR_STAT;                     /**< Interrupt status register 0x0000, offset: 0xB0 */
-  __IO uint32_t MAC_INTR_EN;                       /**< Interrupt enable register 0x0000, offset: 0xB4 */
-  __I  uint32_t MAC_RXTX_STAT;                     /**< Receive Transmit Status register, offset: 0xB8 */
-       uint8_t RESERVED_6[4];
-  __IO uint32_t MAC_PMT_CRTL_STAT;                 /**< , offset: 0xC0 */
-  __IO uint32_t MAC_RWAKE_FRFLT;                   /**< Remote wake-up frame filter, offset: 0xC4 */
-       uint8_t RESERVED_7[8];
-  __IO uint32_t MAC_LPI_CTRL_STAT;                 /**< LPI Control and Status Register, offset: 0xD0 */
-  __IO uint32_t MAC_LPI_TIMER_CTRL;                /**< LPI Timers Control register, offset: 0xD4 */
-  __IO uint32_t MAC_LPI_ENTR_TIMR;                 /**< LPI entry Timer register, offset: 0xD8 */
-  __IO uint32_t MAC_1US_TIC_COUNTR;                /**< , offset: 0xDC */
-       uint8_t RESERVED_8[48];
-  __IO uint32_t MAC_VERSION;                       /**< MAC version register, offset: 0x110 */
-  __I  uint32_t MAC_DBG;                           /**< MAC debug register, offset: 0x114 */
-       uint8_t RESERVED_9[4];
-  __IO uint32_t MAC_HW_FEAT[3];                    /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
-       uint8_t RESERVED_10[216];
-  __IO uint32_t MAC_MDIO_ADDR;                     /**< MIDO address Register, offset: 0x200 */
-  __IO uint32_t MAC_MDIO_DATA;                     /**< MDIO Data register, offset: 0x204 */
-       uint8_t RESERVED_11[248];
-  __IO uint32_t MAC_ADDR_HIGH;                     /**< MAC address0 high register, offset: 0x300 */
-  __IO uint32_t MAC_ADDR_LOW;                      /**< MAC address0 low register, offset: 0x304 */
-       uint8_t RESERVED_12[2040];
-  __IO uint32_t MAC_TIMESTAMP_CTRL;                /**< Time stamp control register, offset: 0xB00 */
-  __IO uint32_t MAC_SUB_SCND_INCR;                 /**< Sub-second increment register, offset: 0xB04 */
-  __I  uint32_t MAC_SYS_TIME_SCND;                 /**< System time seconds register, offset: 0xB08 */
-  __I  uint32_t MAC_SYS_TIME_NSCND;                /**< System time nanoseconds register, offset: 0xB0C */
-  __IO uint32_t MAC_SYS_TIME_SCND_UPD;             /**< , offset: 0xB10 */
-  __IO uint32_t MAC_SYS_TIME_NSCND_UPD;            /**< , offset: 0xB14 */
-  __IO uint32_t MAC_SYS_TIMESTMP_ADDEND;           /**< Time stamp addend register, offset: 0xB18 */
-  __IO uint32_t MAC_SYS_TIME_HWORD_SCND;           /**< , offset: 0xB1C */
-  __I  uint32_t MAC_SYS_TIMESTMP_STAT;             /**< Time stamp status register, offset: 0xB20 */
-       uint8_t RESERVED_13[12];
-  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
-  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Tx timestamp status seconds, offset: 0xB34 */
-       uint8_t RESERVED_14[32];
-  __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
-  __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
-       uint8_t RESERVED_15[160];
-  __IO uint32_t MTL_OP_MODE;                       /**< MTL Operation Mode Register, offset: 0xC00 */
-       uint8_t RESERVED_16[28];
-  __I  uint32_t MTL_INTR_STAT;                     /**< MTL Interrupt Status register, offset: 0xC20 */
-       uint8_t RESERVED_17[12];
-  __IO uint32_t MTL_RXQ_DMA_MAP;                   /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
-       uint8_t RESERVED_18[204];
-  struct {                                         /* offset: 0xD00, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_OP_MODE;                  /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
-    __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
-    __I  uint32_t MTL_TXQX_DBG;                      /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
-         uint8_t RESERVED_0[4];
-    __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_ETS_STAT;                 /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< , array offset: 0xD18, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
-    __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
-         uint8_t RESERVED_1[4];
-    __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< , array offset: 0xD2C, array step: 0x40 */
-    __IO uint32_t MTL_RXQX_OP_MODE;                  /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
-    __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
-    __IO uint32_t MTL_RXQX_DBG;                      /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
-    __IO uint32_t MTL_RXQX_CTRL;                     /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
-  } MTL_QUEUE[2];
-       uint8_t RESERVED_19[640];
-  __IO uint32_t DMA_MODE;                          /**< DMA mode register, offset: 0x1000 */
-  __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus mode, offset: 0x1004 */
-  __IO uint32_t DMA_INTR_STAT;                     /**< DMA Interrupt status, offset: 0x1008 */
-  __IO uint32_t DMA_DBG_STAT;                      /**< DMA Debug Status, offset: 0x100C */
-       uint8_t RESERVED_20[240];
-  struct {                                         /* offset: 0x1100, array step: 0x80 */
-    __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
-    __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
-    __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
-         uint8_t RESERVED_0[8];
-    __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< , array offset: 0x1114, array step: 0x80 */
-         uint8_t RESERVED_1[4];
-    __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< , array offset: 0x111C, array step: 0x80 */
-    __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< , array offset: 0x1120, array step: 0x80 */
-         uint8_t RESERVED_2[4];
-    __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< , array offset: 0x1128, array step: 0x80 */
-    __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< , array offset: 0x112C, array step: 0x80 */
-    __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
-    __IO uint32_t DMA_CHX_INT_EN;                    /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
-    __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
-    __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
-         uint8_t RESERVED_3[4];
-    __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
-         uint8_t RESERVED_4[4];
-    __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< , array offset: 0x114C, array step: 0x80 */
-         uint8_t RESERVED_5[4];
-    __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< , array offset: 0x1154, array step: 0x80 */
-         uint8_t RESERVED_6[4];
-    __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
-    __IO uint32_t DMA_CHX_STAT;                      /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
-         uint8_t RESERVED_7[28];
-  } DMA_CH[2];
-} ENET_Type;
-
-/* ----------------------------------------------------------------------------
-   -- ENET Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Masks ENET Register Masks
- * @{
- */
-
-/*! @name MAC_CONFIG - MAC configuration register */
-#define ENET_MAC_CONFIG_RE_MASK                  (0x1U)
-#define ENET_MAC_CONFIG_RE_SHIFT                 (0U)
-#define ENET_MAC_CONFIG_RE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
-#define ENET_MAC_CONFIG_TE_MASK                  (0x2U)
-#define ENET_MAC_CONFIG_TE_SHIFT                 (1U)
-#define ENET_MAC_CONFIG_TE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
-#define ENET_MAC_CONFIG_PRELEN_MASK              (0xCU)
-#define ENET_MAC_CONFIG_PRELEN_SHIFT             (2U)
-#define ENET_MAC_CONFIG_PRELEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
-#define ENET_MAC_CONFIG_DC_MASK                  (0x10U)
-#define ENET_MAC_CONFIG_DC_SHIFT                 (4U)
-#define ENET_MAC_CONFIG_DC(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
-#define ENET_MAC_CONFIG_BL_MASK                  (0x60U)
-#define ENET_MAC_CONFIG_BL_SHIFT                 (5U)
-#define ENET_MAC_CONFIG_BL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
-#define ENET_MAC_CONFIG_DR_MASK                  (0x100U)
-#define ENET_MAC_CONFIG_DR_SHIFT                 (8U)
-#define ENET_MAC_CONFIG_DR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
-#define ENET_MAC_CONFIG_DCRS_MASK                (0x200U)
-#define ENET_MAC_CONFIG_DCRS_SHIFT               (9U)
-#define ENET_MAC_CONFIG_DCRS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
-#define ENET_MAC_CONFIG_DO_MASK                  (0x400U)
-#define ENET_MAC_CONFIG_DO_SHIFT                 (10U)
-#define ENET_MAC_CONFIG_DO(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
-#define ENET_MAC_CONFIG_ECRSFD_MASK              (0x800U)
-#define ENET_MAC_CONFIG_ECRSFD_SHIFT             (11U)
-#define ENET_MAC_CONFIG_ECRSFD(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
-#define ENET_MAC_CONFIG_LM_MASK                  (0x1000U)
-#define ENET_MAC_CONFIG_LM_SHIFT                 (12U)
-#define ENET_MAC_CONFIG_LM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
-#define ENET_MAC_CONFIG_DM_MASK                  (0x2000U)
-#define ENET_MAC_CONFIG_DM_SHIFT                 (13U)
-#define ENET_MAC_CONFIG_DM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
-#define ENET_MAC_CONFIG_FES_MASK                 (0x4000U)
-#define ENET_MAC_CONFIG_FES_SHIFT                (14U)
-#define ENET_MAC_CONFIG_FES(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
-#define ENET_MAC_CONFIG_PS_MASK                  (0x8000U)
-#define ENET_MAC_CONFIG_PS_SHIFT                 (15U)
-#define ENET_MAC_CONFIG_PS(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
-#define ENET_MAC_CONFIG_JE_MASK                  (0x10000U)
-#define ENET_MAC_CONFIG_JE_SHIFT                 (16U)
-#define ENET_MAC_CONFIG_JE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
-#define ENET_MAC_CONFIG_JD_MASK                  (0x20000U)
-#define ENET_MAC_CONFIG_JD_SHIFT                 (17U)
-#define ENET_MAC_CONFIG_JD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
-#define ENET_MAC_CONFIG_BE_MASK                  (0x40000U)
-#define ENET_MAC_CONFIG_BE_SHIFT                 (18U)
-#define ENET_MAC_CONFIG_BE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
-#define ENET_MAC_CONFIG_WD_MASK                  (0x80000U)
-#define ENET_MAC_CONFIG_WD_SHIFT                 (19U)
-#define ENET_MAC_CONFIG_WD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
-#define ENET_MAC_CONFIG_ACS_MASK                 (0x100000U)
-#define ENET_MAC_CONFIG_ACS_SHIFT                (20U)
-#define ENET_MAC_CONFIG_ACS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
-#define ENET_MAC_CONFIG_CST_MASK                 (0x200000U)
-#define ENET_MAC_CONFIG_CST_SHIFT                (21U)
-#define ENET_MAC_CONFIG_CST(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
-#define ENET_MAC_CONFIG_S2KP_MASK                (0x400000U)
-#define ENET_MAC_CONFIG_S2KP_SHIFT               (22U)
-#define ENET_MAC_CONFIG_S2KP(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
-#define ENET_MAC_CONFIG_GPSLCE_MASK              (0x800000U)
-#define ENET_MAC_CONFIG_GPSLCE_SHIFT             (23U)
-#define ENET_MAC_CONFIG_GPSLCE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
-#define ENET_MAC_CONFIG_IPG_MASK                 (0x7000000U)
-#define ENET_MAC_CONFIG_IPG_SHIFT                (24U)
-#define ENET_MAC_CONFIG_IPG(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
-#define ENET_MAC_CONFIG_IPC_MASK                 (0x8000000U)
-#define ENET_MAC_CONFIG_IPC_SHIFT                (27U)
-#define ENET_MAC_CONFIG_IPC(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
-
-/*! @name MAC_EXT_CONFIG -  */
-#define ENET_MAC_EXT_CONFIG_GPSL_MASK            (0x3FFFU)
-#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT           (0U)
-#define ENET_MAC_EXT_CONFIG_GPSL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
-#define ENET_MAC_EXT_CONFIG_DCRCC_MASK           (0x10000U)
-#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT          (16U)
-#define ENET_MAC_EXT_CONFIG_DCRCC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
-#define ENET_MAC_EXT_CONFIG_SPEN_MASK            (0x20000U)
-#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT           (17U)
-#define ENET_MAC_EXT_CONFIG_SPEN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
-#define ENET_MAC_EXT_CONFIG_USP_MASK             (0x40000U)
-#define ENET_MAC_EXT_CONFIG_USP_SHIFT            (18U)
-#define ENET_MAC_EXT_CONFIG_USP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
-
-/*! @name MAC_FRAME_FILTER - MAC frame filter register */
-#define ENET_MAC_FRAME_FILTER_PR_MASK            (0x1U)
-#define ENET_MAC_FRAME_FILTER_PR_SHIFT           (0U)
-#define ENET_MAC_FRAME_FILTER_PR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
-#define ENET_MAC_FRAME_FILTER_DAIF_MASK          (0x8U)
-#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT         (3U)
-#define ENET_MAC_FRAME_FILTER_DAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
-#define ENET_MAC_FRAME_FILTER_PM_MASK            (0x10U)
-#define ENET_MAC_FRAME_FILTER_PM_SHIFT           (4U)
-#define ENET_MAC_FRAME_FILTER_PM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
-#define ENET_MAC_FRAME_FILTER_DBF_MASK           (0x20U)
-#define ENET_MAC_FRAME_FILTER_DBF_SHIFT          (5U)
-#define ENET_MAC_FRAME_FILTER_DBF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
-#define ENET_MAC_FRAME_FILTER_PCF_MASK           (0xC0U)
-#define ENET_MAC_FRAME_FILTER_PCF_SHIFT          (6U)
-#define ENET_MAC_FRAME_FILTER_PCF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
-#define ENET_MAC_FRAME_FILTER_SAIF_MASK          (0x100U)
-#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT         (8U)
-#define ENET_MAC_FRAME_FILTER_SAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
-#define ENET_MAC_FRAME_FILTER_SAF_MASK           (0x200U)
-#define ENET_MAC_FRAME_FILTER_SAF_SHIFT          (9U)
-#define ENET_MAC_FRAME_FILTER_SAF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
-#define ENET_MAC_FRAME_FILTER_RA_MASK            (0x80000000U)
-#define ENET_MAC_FRAME_FILTER_RA_SHIFT           (31U)
-#define ENET_MAC_FRAME_FILTER_RA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
-
-/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
-#define ENET_MAC_WD_TIMEROUT_WTO_MASK            (0xFU)
-#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT           (0U)
-#define ENET_MAC_WD_TIMEROUT_WTO(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
-#define ENET_MAC_WD_TIMEROUT_PWE_MASK            (0x100U)
-#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT           (8U)
-#define ENET_MAC_WD_TIMEROUT_PWE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
-
-/*! @name MAC_VLAN_TAG - MAC vlan tag register */
-#define ENET_MAC_VLAN_TAG_VL_MASK                (0xFFFFU)
-#define ENET_MAC_VLAN_TAG_VL_SHIFT               (0U)
-#define ENET_MAC_VLAN_TAG_VL(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
-#define ENET_MAC_VLAN_TAG_ETV_MASK               (0x10000U)
-#define ENET_MAC_VLAN_TAG_ETV_SHIFT              (16U)
-#define ENET_MAC_VLAN_TAG_ETV(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
-#define ENET_MAC_VLAN_TAG_VTIM_MASK              (0x20000U)
-#define ENET_MAC_VLAN_TAG_VTIM_SHIFT             (17U)
-#define ENET_MAC_VLAN_TAG_VTIM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
-#define ENET_MAC_VLAN_TAG_ESVL_MASK              (0x40000U)
-#define ENET_MAC_VLAN_TAG_ESVL_SHIFT             (18U)
-#define ENET_MAC_VLAN_TAG_ESVL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
-#define ENET_MAC_VLAN_TAG_ERSVLM_MASK            (0x80000U)
-#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT           (19U)
-#define ENET_MAC_VLAN_TAG_ERSVLM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
-#define ENET_MAC_VLAN_TAG_DOVLTC_MASK            (0x100000U)
-#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT           (20U)
-#define ENET_MAC_VLAN_TAG_DOVLTC(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
-#define ENET_MAC_VLAN_TAG_EVLS_MASK              (0x600000U)
-#define ENET_MAC_VLAN_TAG_EVLS_SHIFT             (21U)
-#define ENET_MAC_VLAN_TAG_EVLS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
-#define ENET_MAC_VLAN_TAG_EVLRXS_MASK            (0x1000000U)
-#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT           (24U)
-#define ENET_MAC_VLAN_TAG_EVLRXS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
-#define ENET_MAC_VLAN_TAG_VTHM_MASK              (0x2000000U)
-#define ENET_MAC_VLAN_TAG_VTHM_SHIFT             (25U)
-#define ENET_MAC_VLAN_TAG_VTHM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
-#define ENET_MAC_VLAN_TAG_EDVLP_MASK             (0x4000000U)
-#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT            (26U)
-#define ENET_MAC_VLAN_TAG_EDVLP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
-#define ENET_MAC_VLAN_TAG_ERIVLT_MASK            (0x8000000U)
-#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT           (27U)
-#define ENET_MAC_VLAN_TAG_ERIVLT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
-#define ENET_MAC_VLAN_TAG_EIVLS_MASK             (0x30000000U)
-#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT            (28U)
-#define ENET_MAC_VLAN_TAG_EIVLS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
-#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK           (0x80000000U)
-#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT          (31U)
-#define ENET_MAC_VLAN_TAG_EIVLRXS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
-
-/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK         (0x1U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT        (0U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK         (0x2U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT        (1U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK         (0x70U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT        (4U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK        (0x80U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT       (7U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK          (0xFFFF0000U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT         (16U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
-
-/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
-#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT            (2U)
-
-/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
-#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK           (0x1U)
-#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT          (0U)
-#define ENET_MAC_RX_FLOW_CTRL_RFE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
-#define ENET_MAC_RX_FLOW_CTRL_UP_MASK            (0x2U)
-#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT           (1U)
-#define ENET_MAC_RX_FLOW_CTRL_UP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
-
-/*! @name MAC_TXQ_PRIO_MAP -  */
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK         (0xFFU)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT        (0U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK         (0xFF00U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT        (8U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
-
-/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
-#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK            (0x3U)
-#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT           (0U)
-#define ENET_MAC_RXQ_CTRL_RXQ0EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK             (0xFFU)
-#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT            (0U)
-#define ENET_MAC_RXQ_CTRL_PSRQ0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
-#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK             (0x7U)
-#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT            (0U)
-#define ENET_MAC_RXQ_CTRL_AVCPQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK            (0xCU)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT           (2U)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK            (0x70U)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT           (4U)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK             (0xFF00U)
-#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT            (8U)
-#define ENET_MAC_RXQ_CTRL_PSRQ1(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
-#define ENET_MAC_RXQ_CTRL_UPQ_MASK               (0x7000U)
-#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT              (12U)
-#define ENET_MAC_RXQ_CTRL_UPQ(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK             (0xFF0000U)
-#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT            (16U)
-#define ENET_MAC_RXQ_CTRL_PSRQ2(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
-#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK             (0x70000U)
-#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT            (16U)
-#define ENET_MAC_RXQ_CTRL_MCBCQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK           (0x100000U)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT          (20U)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK             (0xFF000000U)
-#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT            (24U)
-#define ENET_MAC_RXQ_CTRL_PSRQ3(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
-
-/* The count of ENET_MAC_RXQ_CTRL */
-#define ENET_MAC_RXQ_CTRL_COUNT                  (3U)
-
-/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
-#define ENET_MAC_INTR_STAT_PHYIS_MASK            (0x8U)
-#define ENET_MAC_INTR_STAT_PHYIS_SHIFT           (3U)
-#define ENET_MAC_INTR_STAT_PHYIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
-#define ENET_MAC_INTR_STAT_PMTIS_MASK            (0x10U)
-#define ENET_MAC_INTR_STAT_PMTIS_SHIFT           (4U)
-#define ENET_MAC_INTR_STAT_PMTIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
-#define ENET_MAC_INTR_STAT_LPIIS_MASK            (0x20U)
-#define ENET_MAC_INTR_STAT_LPIIS_SHIFT           (5U)
-#define ENET_MAC_INTR_STAT_LPIIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
-#define ENET_MAC_INTR_STAT_TSIS_MASK             (0x1000U)
-#define ENET_MAC_INTR_STAT_TSIS_SHIFT            (12U)
-#define ENET_MAC_INTR_STAT_TSIS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
-#define ENET_MAC_INTR_STAT_TXSTSIS_MASK          (0x2000U)
-#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT         (13U)
-#define ENET_MAC_INTR_STAT_TXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
-#define ENET_MAC_INTR_STAT_RXSTSIS_MASK          (0x4000U)
-#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT         (14U)
-#define ENET_MAC_INTR_STAT_RXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
-
-/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
-#define ENET_MAC_INTR_EN_PHYIE_MASK              (0x8U)
-#define ENET_MAC_INTR_EN_PHYIE_SHIFT             (3U)
-#define ENET_MAC_INTR_EN_PHYIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
-#define ENET_MAC_INTR_EN_PMTIE_MASK              (0x10U)
-#define ENET_MAC_INTR_EN_PMTIE_SHIFT             (4U)
-#define ENET_MAC_INTR_EN_PMTIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
-#define ENET_MAC_INTR_EN_LPIIE_MASK              (0x20U)
-#define ENET_MAC_INTR_EN_LPIIE_SHIFT             (5U)
-#define ENET_MAC_INTR_EN_LPIIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
-#define ENET_MAC_INTR_EN_TSIE_MASK               (0x1000U)
-#define ENET_MAC_INTR_EN_TSIE_SHIFT              (12U)
-#define ENET_MAC_INTR_EN_TSIE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
-#define ENET_MAC_INTR_EN_TXSTSIE_MASK            (0x2000U)
-#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT           (13U)
-#define ENET_MAC_INTR_EN_TXSTSIE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
-#define ENET_MAC_INTR_EN_RXSTSIS_MASK            (0x4000U)
-#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT           (14U)
-#define ENET_MAC_INTR_EN_RXSTSIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
-
-/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
-#define ENET_MAC_RXTX_STAT_TJT_MASK              (0x1U)
-#define ENET_MAC_RXTX_STAT_TJT_SHIFT             (0U)
-#define ENET_MAC_RXTX_STAT_TJT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
-#define ENET_MAC_RXTX_STAT_NCARR_MASK            (0x2U)
-#define ENET_MAC_RXTX_STAT_NCARR_SHIFT           (1U)
-#define ENET_MAC_RXTX_STAT_NCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
-#define ENET_MAC_RXTX_STAT_LCARR_MASK            (0x4U)
-#define ENET_MAC_RXTX_STAT_LCARR_SHIFT           (2U)
-#define ENET_MAC_RXTX_STAT_LCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
-#define ENET_MAC_RXTX_STAT_EXDEF_MASK            (0x8U)
-#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT           (3U)
-#define ENET_MAC_RXTX_STAT_EXDEF(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
-#define ENET_MAC_RXTX_STAT_LCOL_MASK             (0x10U)
-#define ENET_MAC_RXTX_STAT_LCOL_SHIFT            (4U)
-#define ENET_MAC_RXTX_STAT_LCOL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
-#define ENET_MAC_RXTX_STAT_EXCOL_MASK            (0x20U)
-#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT           (5U)
-#define ENET_MAC_RXTX_STAT_EXCOL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
-#define ENET_MAC_RXTX_STAT_RWT_MASK              (0x100U)
-#define ENET_MAC_RXTX_STAT_RWT_SHIFT             (8U)
-#define ENET_MAC_RXTX_STAT_RWT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
-
-/*! @name MAC_PMT_CRTL_STAT -  */
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK       (0x1U)
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT      (0U)
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK     (0x2U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT    (1U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK     (0x4U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT    (2U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK     (0x20U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT    (5U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK     (0x40U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT    (6U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK    (0x200U)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT   (9U)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK       (0x400U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT      (10U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK       (0x1F000000U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT      (24U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK   (0x80000000U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT  (31U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
-
-/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
-#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK           (0xFFFFFFFFU)
-#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT          (0U)
-#define ENET_MAC_RWAKE_FRFLT_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
-
-/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK       (0x1U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT      (0U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK       (0x2U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT      (1U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK       (0x4U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT      (2U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK       (0x8U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT      (3U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK       (0x100U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT      (8U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK       (0x200U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT      (9U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK        (0x10000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT       (16U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK          (0x20000U)
-#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT         (17U)
-#define ENET_MAC_LPI_CTRL_STAT_PLS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK       (0x80000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT      (19U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK       (0x100000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT      (20U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK      (0x200000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT     (21U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
-
-/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
-#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK         (0xFFFFU)
-#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT        (0U)
-#define ENET_MAC_LPI_TIMER_CTRL_TWT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
-#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK         (0x3FF0000U)
-#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT        (16U)
-#define ENET_MAC_LPI_TIMER_CTRL_LST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
-
-/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK        (0xFFFF8U)
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT       (3U)
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
-
-/*! @name MAC_1US_TIC_COUNTR -  */
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
-
-/*! @name MAC_VERSION - MAC version register */
-#define ENET_MAC_VERSION_SNPVER_MASK             (0xFFU)
-#define ENET_MAC_VERSION_SNPVER_SHIFT            (0U)
-#define ENET_MAC_VERSION_SNPVER(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
-#define ENET_MAC_VERSION_USERVER_MASK            (0xFF00U)
-#define ENET_MAC_VERSION_USERVER_SHIFT           (8U)
-#define ENET_MAC_VERSION_USERVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
-
-/*! @name MAC_DBG - MAC debug register */
-#define ENET_MAC_DBG_REPESTS_MASK                (0x1U)
-#define ENET_MAC_DBG_REPESTS_SHIFT               (0U)
-#define ENET_MAC_DBG_REPESTS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
-#define ENET_MAC_DBG_RFCFCSTS_MASK               (0x6U)
-#define ENET_MAC_DBG_RFCFCSTS_SHIFT              (1U)
-#define ENET_MAC_DBG_RFCFCSTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
-#define ENET_MAC_DBG_TPESTS_MASK                 (0x10000U)
-#define ENET_MAC_DBG_TPESTS_SHIFT                (16U)
-#define ENET_MAC_DBG_TPESTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
-#define ENET_MAC_DBG_TFCSTS_MASK                 (0x60000U)
-#define ENET_MAC_DBG_TFCSTS_SHIFT                (17U)
-#define ENET_MAC_DBG_TFCSTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
-
-/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK         (0x1FU)
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT        (0U)
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
-#define ENET_MAC_HW_FEAT_RXQCNT_MASK             (0xFU)
-#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT            (0U)
-#define ENET_MAC_HW_FEAT_RXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
-#define ENET_MAC_HW_FEAT_MIISEL_MASK             (0x1U)
-#define ENET_MAC_HW_FEAT_MIISEL_SHIFT            (0U)
-#define ENET_MAC_HW_FEAT_MIISEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
-#define ENET_MAC_HW_FEAT_HDSEL_MASK              (0x4U)
-#define ENET_MAC_HW_FEAT_HDSEL_SHIFT             (2U)
-#define ENET_MAC_HW_FEAT_HDSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
-#define ENET_MAC_HW_FEAT_VLHASH_MASK             (0x10U)
-#define ENET_MAC_HW_FEAT_VLHASH_SHIFT            (4U)
-#define ENET_MAC_HW_FEAT_VLHASH(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
-#define ENET_MAC_HW_FEAT_SMASEL_MASK             (0x20U)
-#define ENET_MAC_HW_FEAT_SMASEL_SHIFT            (5U)
-#define ENET_MAC_HW_FEAT_SMASEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
-#define ENET_MAC_HW_FEAT_TXQCNT_MASK             (0x3C0U)
-#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT            (6U)
-#define ENET_MAC_HW_FEAT_TXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
-#define ENET_MAC_HW_FEAT_RWKSEL_MASK             (0x40U)
-#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT            (6U)
-#define ENET_MAC_HW_FEAT_RWKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK         (0x7C0U)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT        (6U)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
-#define ENET_MAC_HW_FEAT_MGKSEL_MASK             (0x80U)
-#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT            (7U)
-#define ENET_MAC_HW_FEAT_MGKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
-#define ENET_MAC_HW_FEAT_MMCSEL_MASK             (0x100U)
-#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT            (8U)
-#define ENET_MAC_HW_FEAT_MMCSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK          (0x200U)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT         (9U)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
-#define ENET_MAC_HW_FEAT_OSTEN_MASK              (0x800U)
-#define ENET_MAC_HW_FEAT_OSTEN_SHIFT             (11U)
-#define ENET_MAC_HW_FEAT_OSTEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
-#define ENET_MAC_HW_FEAT_RXCHCNT_MASK            (0xF000U)
-#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT           (12U)
-#define ENET_MAC_HW_FEAT_RXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
-#define ENET_MAC_HW_FEAT_TSSEL_MASK              (0x1000U)
-#define ENET_MAC_HW_FEAT_TSSEL_SHIFT             (12U)
-#define ENET_MAC_HW_FEAT_TSSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
-#define ENET_MAC_HW_FEAT_PTOEN_MASK              (0x1000U)
-#define ENET_MAC_HW_FEAT_PTOEN_SHIFT             (12U)
-#define ENET_MAC_HW_FEAT_PTOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
-#define ENET_MAC_HW_FEAT_EEESEL_MASK             (0x2000U)
-#define ENET_MAC_HW_FEAT_EEESEL_SHIFT            (13U)
-#define ENET_MAC_HW_FEAT_EEESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
-#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK          (0x2000U)
-#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT         (13U)
-#define ENET_MAC_HW_FEAT_ADVTHWORD(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
-#define ENET_MAC_HW_FEAT_ADDR64_MASK             (0xC000U)
-#define ENET_MAC_HW_FEAT_ADDR64_SHIFT            (14U)
-#define ENET_MAC_HW_FEAT_ADDR64(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
-#define ENET_MAC_HW_FEAT_TXCOESEL_MASK           (0x4000U)
-#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT          (14U)
-#define ENET_MAC_HW_FEAT_TXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
-#define ENET_MAC_HW_FEAT_DCBEN_MASK              (0x10000U)
-#define ENET_MAC_HW_FEAT_DCBEN_SHIFT             (16U)
-#define ENET_MAC_HW_FEAT_DCBEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
-#define ENET_MAC_HW_FEAT_RXCOESEL_MASK           (0x10000U)
-#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT          (16U)
-#define ENET_MAC_HW_FEAT_RXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
-#define ENET_MAC_HW_FEAT_SPEN_MASK               (0x20000U)
-#define ENET_MAC_HW_FEAT_SPEN_SHIFT              (17U)
-#define ENET_MAC_HW_FEAT_SPEN(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
-#define ENET_MAC_HW_FEAT_TXCHCNT_MASK            (0x3C0000U)
-#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT           (18U)
-#define ENET_MAC_HW_FEAT_TXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
-#define ENET_MAC_HW_FEAT_TSOEN_MASK              (0x40000U)
-#define ENET_MAC_HW_FEAT_TSOEN_SHIFT             (18U)
-#define ENET_MAC_HW_FEAT_TSOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
-#define ENET_MAC_HW_FEAT_DBGMEMA_MASK            (0x80000U)
-#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT           (19U)
-#define ENET_MAC_HW_FEAT_DBGMEMA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
-#define ENET_MAC_HW_FEAT_AVSEL_MASK              (0x100000U)
-#define ENET_MAC_HW_FEAT_AVSEL_SHIFT             (20U)
-#define ENET_MAC_HW_FEAT_AVSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
-#define ENET_MAC_HW_FEAT_LPMODEEN_MASK           (0x800000U)
-#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT          (23U)
-#define ENET_MAC_HW_FEAT_LPMODEEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK          (0x7000000U)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT         (24U)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK          (0x3000000U)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT         (24U)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
-#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK           (0x6000000U)
-#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT          (25U)
-#define ENET_MAC_HW_FEAT_TSSTSSEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK       (0x78000000U)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT      (27U)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK         (0x70000000U)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT        (28U)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK          (0x70000000U)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT         (28U)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
-
-/* The count of ENET_MAC_HW_FEAT */
-#define ENET_MAC_HW_FEAT_COUNT                   (3U)
-
-/*! @name MAC_MDIO_ADDR - MIDO address Register */
-#define ENET_MAC_MDIO_ADDR_MB_MASK               (0x1U)
-#define ENET_MAC_MDIO_ADDR_MB_SHIFT              (0U)
-#define ENET_MAC_MDIO_ADDR_MB(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
-#define ENET_MAC_MDIO_ADDR_MOC_MASK              (0xCU)
-#define ENET_MAC_MDIO_ADDR_MOC_SHIFT             (2U)
-#define ENET_MAC_MDIO_ADDR_MOC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
-#define ENET_MAC_MDIO_ADDR_CR_MASK               (0xF00U)
-#define ENET_MAC_MDIO_ADDR_CR_SHIFT              (8U)
-#define ENET_MAC_MDIO_ADDR_CR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
-#define ENET_MAC_MDIO_ADDR_NTC_MASK              (0x7000U)
-#define ENET_MAC_MDIO_ADDR_NTC_SHIFT             (12U)
-#define ENET_MAC_MDIO_ADDR_NTC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
-#define ENET_MAC_MDIO_ADDR_RDA_MASK              (0x1F0000U)
-#define ENET_MAC_MDIO_ADDR_RDA_SHIFT             (16U)
-#define ENET_MAC_MDIO_ADDR_RDA(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
-#define ENET_MAC_MDIO_ADDR_PA_MASK               (0x3E00000U)
-#define ENET_MAC_MDIO_ADDR_PA_SHIFT              (21U)
-#define ENET_MAC_MDIO_ADDR_PA(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
-#define ENET_MAC_MDIO_ADDR_BTB_MASK              (0x4000000U)
-#define ENET_MAC_MDIO_ADDR_BTB_SHIFT             (26U)
-#define ENET_MAC_MDIO_ADDR_BTB(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
-#define ENET_MAC_MDIO_ADDR_PSE_MASK              (0x8000000U)
-#define ENET_MAC_MDIO_ADDR_PSE_SHIFT             (27U)
-#define ENET_MAC_MDIO_ADDR_PSE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
-
-/*! @name MAC_MDIO_DATA - MDIO Data register */
-#define ENET_MAC_MDIO_DATA_MD_MASK               (0xFFFFU)
-#define ENET_MAC_MDIO_DATA_MD_SHIFT              (0U)
-#define ENET_MAC_MDIO_DATA_MD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
-
-/*! @name MAC_ADDR_HIGH - MAC address0 high register */
-#define ENET_MAC_ADDR_HIGH_A47_32_MASK           (0xFFFFU)
-#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT          (0U)
-#define ENET_MAC_ADDR_HIGH_A47_32(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
-#define ENET_MAC_ADDR_HIGH_DCS_MASK              (0x10000U)
-#define ENET_MAC_ADDR_HIGH_DCS_SHIFT             (16U)
-#define ENET_MAC_ADDR_HIGH_DCS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
-#define ENET_MAC_ADDR_HIGH_AE_MASK               (0x80000000U)
-#define ENET_MAC_ADDR_HIGH_AE_SHIFT              (31U)
-#define ENET_MAC_ADDR_HIGH_AE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
-
-/*! @name MAC_ADDR_LOW - MAC address0 low register */
-#define ENET_MAC_ADDR_LOW_A31_0_MASK             (0xFFFFFFFFU)
-#define ENET_MAC_ADDR_LOW_A31_0_SHIFT            (0U)
-#define ENET_MAC_ADDR_LOW_A31_0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
-
-/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK       (0x1U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT      (0U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK    (0x2U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT   (1U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK      (0x4U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT     (2U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK      (0x8U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT     (3U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK      (0x10U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT     (4U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK     (0x20U)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT    (5U)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK     (0x100U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT    (8U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK   (0x200U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT  (9U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK   (0x400U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT  (10U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK     (0x800U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT    (11U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK   (0x1000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT  (12U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK   (0x2000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT  (13U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK    (0x4000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT   (14U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK   (0x8000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT  (15U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK  (0x30000U)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK   (0x1000000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT  (24U)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
-
-/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
-#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK        (0xFF0000U)
-#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT       (16U)
-#define ENET_MAC_SUB_SCND_INCR_SSINC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
-
-/*! @name MAC_SYS_TIME_SCND - System time seconds register */
-#define ENET_MAC_SYS_TIME_SCND_TSS_MASK          (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT         (0U)
-#define ENET_MAC_SYS_TIME_SCND_TSS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
-
-/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
-#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK        (0x7FFFFFFFU)
-#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT       (0U)
-#define ENET_MAC_SYS_TIME_NSCND_TSSS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
-
-/*! @name MAC_SYS_TIME_SCND_UPD -  */
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK      (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT     (0U)
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
-
-/*! @name MAC_SYS_TIME_NSCND_UPD -  */
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK    (0x7FFFFFFFU)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT   (0U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK  (0x80000000U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
-
-/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK   (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT  (0U)
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
-
-/*! @name MAC_SYS_TIME_HWORD_SCND -  */
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK  (0xFFFFU)
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
-
-/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK   (0x1U)
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT  (0U)
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
-
-/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
-
-/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
-
-/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
-
-/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
-
-/*! @name MTL_OP_MODE - MTL Operation Mode Register */
-#define ENET_MTL_OP_MODE_DTXSTS_MASK             (0x2U)
-#define ENET_MTL_OP_MODE_DTXSTS_SHIFT            (1U)
-#define ENET_MTL_OP_MODE_DTXSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
-#define ENET_MTL_OP_MODE_RAA_MASK                (0x4U)
-#define ENET_MTL_OP_MODE_RAA_SHIFT               (2U)
-#define ENET_MTL_OP_MODE_RAA(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
-#define ENET_MTL_OP_MODE_SCHALG_MASK             (0x60U)
-#define ENET_MTL_OP_MODE_SCHALG_SHIFT            (5U)
-#define ENET_MTL_OP_MODE_SCHALG(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
-#define ENET_MTL_OP_MODE_CNTPRST_MASK            (0x100U)
-#define ENET_MTL_OP_MODE_CNTPRST_SHIFT           (8U)
-#define ENET_MTL_OP_MODE_CNTPRST(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
-#define ENET_MTL_OP_MODE_CNTCLR_MASK             (0x200U)
-#define ENET_MTL_OP_MODE_CNTCLR_SHIFT            (9U)
-#define ENET_MTL_OP_MODE_CNTCLR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
-
-/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
-#define ENET_MTL_INTR_STAT_Q0IS_MASK             (0x1U)
-#define ENET_MTL_INTR_STAT_Q0IS_SHIFT            (0U)
-#define ENET_MTL_INTR_STAT_Q0IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
-#define ENET_MTL_INTR_STAT_Q1IS_MASK             (0x2U)
-#define ENET_MTL_INTR_STAT_Q1IS_SHIFT            (1U)
-#define ENET_MTL_INTR_STAT_Q1IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
-
-/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK       (0x1U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT      (0U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK       (0x10U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT      (4U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK       (0x100U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT      (8U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK       (0x1000U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT      (12U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
-
-/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT    (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT    (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK  (0x6U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK  (0x8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK  (0x10U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK    (0x70000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT   (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT        (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT   (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT   (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT -  */
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT  (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK  (0x1FFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT    (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK  (0x1FFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT    (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT -  */
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT    (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK  (0x1U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK  (0x6U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK  (0x30U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK    (0x3FFF0000U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT   (16U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT        (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT       (2U)
-
-/*! @name DMA_MODE - DMA mode register */
-#define ENET_DMA_MODE_SWR_MASK                   (0x1U)
-#define ENET_DMA_MODE_SWR_SHIFT                  (0U)
-#define ENET_DMA_MODE_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
-#define ENET_DMA_MODE_DA_MASK                    (0x2U)
-#define ENET_DMA_MODE_DA_SHIFT                   (1U)
-#define ENET_DMA_MODE_DA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
-#define ENET_DMA_MODE_TAA_MASK                   (0x1CU)
-#define ENET_DMA_MODE_TAA_SHIFT                  (2U)
-#define ENET_DMA_MODE_TAA(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
-#define ENET_DMA_MODE_TXPR_MASK                  (0x800U)
-#define ENET_DMA_MODE_TXPR_SHIFT                 (11U)
-#define ENET_DMA_MODE_TXPR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
-#define ENET_DMA_MODE_PR_MASK                    (0x7000U)
-#define ENET_DMA_MODE_PR_SHIFT                   (12U)
-#define ENET_DMA_MODE_PR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
-
-/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
-#define ENET_DMA_SYSBUS_MODE_FB_MASK             (0x1U)
-#define ENET_DMA_SYSBUS_MODE_FB_SHIFT            (0U)
-#define ENET_DMA_SYSBUS_MODE_FB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
-#define ENET_DMA_SYSBUS_MODE_AAL_MASK            (0x1000U)
-#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT           (12U)
-#define ENET_DMA_SYSBUS_MODE_AAL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
-#define ENET_DMA_SYSBUS_MODE_MB_MASK             (0x4000U)
-#define ENET_DMA_SYSBUS_MODE_MB_SHIFT            (14U)
-#define ENET_DMA_SYSBUS_MODE_MB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
-#define ENET_DMA_SYSBUS_MODE_RB_MASK             (0x8000U)
-#define ENET_DMA_SYSBUS_MODE_RB_SHIFT            (15U)
-#define ENET_DMA_SYSBUS_MODE_RB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
-
-/*! @name DMA_INTR_STAT - DMA Interrupt status */
-#define ENET_DMA_INTR_STAT_DC0IS_MASK            (0x1U)
-#define ENET_DMA_INTR_STAT_DC0IS_SHIFT           (0U)
-#define ENET_DMA_INTR_STAT_DC0IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
-#define ENET_DMA_INTR_STAT_DC1IS_MASK            (0x2U)
-#define ENET_DMA_INTR_STAT_DC1IS_SHIFT           (1U)
-#define ENET_DMA_INTR_STAT_DC1IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
-#define ENET_DMA_INTR_STAT_MTLIS_MASK            (0x10000U)
-#define ENET_DMA_INTR_STAT_MTLIS_SHIFT           (16U)
-#define ENET_DMA_INTR_STAT_MTLIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
-#define ENET_DMA_INTR_STAT_MACIS_MASK            (0x20000U)
-#define ENET_DMA_INTR_STAT_MACIS_SHIFT           (17U)
-#define ENET_DMA_INTR_STAT_MACIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
-
-/*! @name DMA_DBG_STAT - DMA Debug Status */
-#define ENET_DMA_DBG_STAT_AHSTS_MASK             (0x1U)
-#define ENET_DMA_DBG_STAT_AHSTS_SHIFT            (0U)
-#define ENET_DMA_DBG_STAT_AHSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
-#define ENET_DMA_DBG_STAT_RPS0_MASK              (0xF00U)
-#define ENET_DMA_DBG_STAT_RPS0_SHIFT             (8U)
-#define ENET_DMA_DBG_STAT_RPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
-#define ENET_DMA_DBG_STAT_TPS0_MASK              (0xF000U)
-#define ENET_DMA_DBG_STAT_TPS0_SHIFT             (12U)
-#define ENET_DMA_DBG_STAT_TPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
-#define ENET_DMA_DBG_STAT_RPS1_MASK              (0xF0000U)
-#define ENET_DMA_DBG_STAT_RPS1_SHIFT             (16U)
-#define ENET_DMA_DBG_STAT_RPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
-#define ENET_DMA_DBG_STAT_TPS1_MASK              (0xF00000U)
-#define ENET_DMA_DBG_STAT_TPS1_SHIFT             (20U)
-#define ENET_DMA_DBG_STAT_TPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
-
-/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK      (0x10000U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT     (16U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK        (0x1C0000U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT       (18U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT           (2U)
-
-/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK      (0x1U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT     (0U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK     (0xEU)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT    (1U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK     (0x10U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT    (4U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK   (0x3F0000U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT  (16U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT        (2U)
-
-/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK      (0x1U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT     (0U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK    (0x7FF8U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT   (3U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK   (0x3F0000U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT  (16U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK     (0x80000000U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT    (31U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT        (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR -  */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR -  */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR -  */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR -  */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH -  */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK      (0x1U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT     (0U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK      (0x2U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT     (1U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK     (0x4U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT    (2U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK      (0x40U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT     (6U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK     (0x80U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT    (7U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK      (0x100U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT     (8U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK     (0x200U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT    (9U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK     (0x400U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT    (10U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK     (0x800U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT    (11U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK     (0x1000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT    (12U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK      (0x4000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT     (14U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK      (0x8000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT     (15U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
-#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT         (2U)
-
-/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC -  */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF -  */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT  (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT  (2U)
-
-/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
-#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK         (0x1U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT        (0U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK        (0x2U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT       (1U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK        (0x4U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT       (2U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK         (0x40U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT        (6U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK        (0x80U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT       (7U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK        (0x100U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT       (8U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK        (0x200U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT       (9U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK        (0x400U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT       (10U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK        (0x800U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT       (11U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK        (0x1000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT       (12U)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK        (0x4000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT       (14U)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK        (0x8000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT       (15U)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK         (0x70000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT        (16U)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_STAT */
-#define ENET_DMA_CH_DMA_CHX_STAT_COUNT           (2U)
-
-
-/*!
- * @}
- */ /* end of group ENET_Register_Masks */
-
-
-/* ENET - Peripheral instance base addresses */
-/** Peripheral ENET base address */
-#define ENET_BASE                                (0x40092000u)
-/** Peripheral ENET base pointer */
-#define ENET                                     ((ENET_Type *)ENET_BASE)
-/** Array initializer of ENET peripheral base addresses */
-#define ENET_BASE_ADDRS                          { ENET_BASE }
-/** Array initializer of ENET peripheral base pointers */
-#define ENET_BASE_PTRS                           { ENET }
-/** Interrupt vectors for the ENET peripheral type */
-#define ENET_IRQS                                { ETHERNET_IRQn }
-#define ENET_PMT_IRQS                            { ETHERNET_PMT_IRQn }
-#define ENET_MACLP_IRQS                          { ETHERNET_MACLP_IRQn }
-
-/*!
- * @}
- */ /* end of group ENET_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- FLEXCOMM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
- * @{
- */
-
-/** FLEXCOMM - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[4088];
-  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
-  __IO uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
-} FLEXCOMM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- FLEXCOMM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
- * @{
- */
-
-/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
-#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
-#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
-#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
-#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
-#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
-#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
-#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
-#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
-#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
-#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
-#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
-#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
-#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
-#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
-#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
-#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
-#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
-#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
-#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
-
-/*! @name PID - Peripheral identification register. */
-#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
-#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
-#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
-#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
-#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
-#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
-#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
-#define FLEXCOMM_PID_ID_SHIFT                    (16U)
-#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group FLEXCOMM_Register_Masks */
-
-
-/* FLEXCOMM - Peripheral instance base addresses */
-/** Peripheral FLEXCOMM0 base address */
-#define FLEXCOMM0_BASE                           (0x40086000u)
-/** Peripheral FLEXCOMM0 base pointer */
-#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
-/** Peripheral FLEXCOMM1 base address */
-#define FLEXCOMM1_BASE                           (0x40087000u)
-/** Peripheral FLEXCOMM1 base pointer */
-#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
-/** Peripheral FLEXCOMM2 base address */
-#define FLEXCOMM2_BASE                           (0x40088000u)
-/** Peripheral FLEXCOMM2 base pointer */
-#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
-/** Peripheral FLEXCOMM3 base address */
-#define FLEXCOMM3_BASE                           (0x40089000u)
-/** Peripheral FLEXCOMM3 base pointer */
-#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
-/** Peripheral FLEXCOMM4 base address */
-#define FLEXCOMM4_BASE                           (0x4008A000u)
-/** Peripheral FLEXCOMM4 base pointer */
-#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
-/** Peripheral FLEXCOMM5 base address */
-#define FLEXCOMM5_BASE                           (0x40096000u)
-/** Peripheral FLEXCOMM5 base pointer */
-#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
-/** Peripheral FLEXCOMM6 base address */
-#define FLEXCOMM6_BASE                           (0x40097000u)
-/** Peripheral FLEXCOMM6 base pointer */
-#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
-/** Peripheral FLEXCOMM7 base address */
-#define FLEXCOMM7_BASE                           (0x40098000u)
-/** Peripheral FLEXCOMM7 base pointer */
-#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
-/** Peripheral FLEXCOMM8 base address */
-#define FLEXCOMM8_BASE                           (0x40099000u)
-/** Peripheral FLEXCOMM8 base pointer */
-#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
-/** Peripheral FLEXCOMM9 base address */
-#define FLEXCOMM9_BASE                           (0x4009A000u)
-/** Peripheral FLEXCOMM9 base pointer */
-#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
-/** Array initializer of FLEXCOMM peripheral base addresses */
-#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }
-/** Array initializer of FLEXCOMM peripheral base pointers */
-#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }
-/** Interrupt vectors for the FLEXCOMM peripheral type */
-#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- FMC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t FCTR;                              /**< Control register, offset: 0x0 */
-       uint8_t RESERVED_0[12];
-  __IO uint32_t FBWST;                             /**< Wait state register, offset: 0x10 */
-       uint8_t RESERVED_1[12];
-  __IO uint32_t FMSSTART;                          /**< Signature start address register, offset: 0x20 */
-  __IO uint32_t FMSSTOP;                           /**< Signature stop-address register, offset: 0x24 */
-       uint8_t RESERVED_2[4];
-  __I  uint32_t FMSW[4];                           /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */
-       uint8_t RESERVED_3[4004];
-  __I  uint32_t FMSTAT;                            /**< Signature generation status register, offset: 0xFE0 */
-       uint8_t RESERVED_4[4];
-  __O  uint32_t FMSTATCLR;                         /**< Signature generation status clear register, offset: 0xFE8 */
-} FMC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- FMC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/*! @name FCTR - Control register */
-#define FMC_FCTR_FS_RD0_MASK                     (0x8U)
-#define FMC_FCTR_FS_RD0_SHIFT                    (3U)
-#define FMC_FCTR_FS_RD0(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)
-#define FMC_FCTR_FS_RD1_MASK                     (0x10U)
-#define FMC_FCTR_FS_RD1_SHIFT                    (4U)
-#define FMC_FCTR_FS_RD1(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)
-
-/*! @name FBWST - Wait state register */
-#define FMC_FBWST_WAITSTATES_MASK                (0xFFU)
-#define FMC_FBWST_WAITSTATES_SHIFT               (0U)
-#define FMC_FBWST_WAITSTATES(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)
-
-/*! @name FMSSTART - Signature start address register */
-#define FMC_FMSSTART_START_MASK                  (0x1FFFFU)
-#define FMC_FMSSTART_START_SHIFT                 (0U)
-#define FMC_FMSSTART_START(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)
-
-/*! @name FMSSTOP - Signature stop-address register */
-#define FMC_FMSSTOP_STOP_MASK                    (0x1FFFFU)
-#define FMC_FMSSTOP_STOP_SHIFT                   (0U)
-#define FMC_FMSSTOP_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)
-#define FMC_FMSSTOP_SIG_START_MASK               (0x20000U)
-#define FMC_FMSSTOP_SIG_START_SHIFT              (17U)
-#define FMC_FMSSTOP_SIG_START(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)
-
-/*! @name FMSW - Words of 128-bit signature word */
-#define FMC_FMSW_SW_MASK                         (0xFFFFFFFFU)
-#define FMC_FMSW_SW_SHIFT                        (0U)
-#define FMC_FMSW_SW(x)                           (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)
-
-/* The count of FMC_FMSW */
-#define FMC_FMSW_COUNT                           (4U)
-
-/*! @name FMSTAT - Signature generation status register */
-#define FMC_FMSTAT_SIG_DONE_MASK                 (0x4U)
-#define FMC_FMSTAT_SIG_DONE_SHIFT                (2U)
-#define FMC_FMSTAT_SIG_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)
-
-/*! @name FMSTATCLR - Signature generation status clear register */
-#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK          (0x4U)
-#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT         (2U)
-#define FMC_FMSTATCLR_SIG_DONE_CLR(x)            (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)
-
-
-/*!
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE                                 (0x40034000u)
-/** Peripheral FMC base pointer */
-#define FMC                                      ((FMC_Type *)FMC_BASE)
-/** Array initializer of FMC peripheral base addresses */
-#define FMC_BASE_ADDRS                           { FMC_BASE }
-/** Array initializer of FMC peripheral base pointers */
-#define FMC_BASE_PTRS                            { FMC }
-
-/*!
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- GINT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
- * @{
- */
-
-/** GINT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
-       uint8_t RESERVED_0[28];
-  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
-       uint8_t RESERVED_1[24];
-  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
-} GINT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- GINT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GINT_Register_Masks GINT Register Masks
- * @{
- */
-
-/*! @name CTRL - GPIO grouped interrupt control register */
-#define GINT_CTRL_INT_MASK                       (0x1U)
-#define GINT_CTRL_INT_SHIFT                      (0U)
-#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
-#define GINT_CTRL_COMB_MASK                      (0x2U)
-#define GINT_CTRL_COMB_SHIFT                     (1U)
-#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
-#define GINT_CTRL_TRIG_MASK                      (0x4U)
-#define GINT_CTRL_TRIG_SHIFT                     (2U)
-#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
-
-/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
-#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
-#define GINT_PORT_POL_POL_SHIFT                  (0U)
-#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
-
-/* The count of GINT_PORT_POL */
-#define GINT_PORT_POL_COUNT                      (2U)
-
-/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
-#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
-#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
-#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
-
-/* The count of GINT_PORT_ENA */
-#define GINT_PORT_ENA_COUNT                      (2U)
-
-
-/*!
- * @}
- */ /* end of group GINT_Register_Masks */
-
-
-/* GINT - Peripheral instance base addresses */
-/** Peripheral GINT0 base address */
-#define GINT0_BASE                               (0x40002000u)
-/** Peripheral GINT0 base pointer */
-#define GINT0                                    ((GINT_Type *)GINT0_BASE)
-/** Peripheral GINT1 base address */
-#define GINT1_BASE                               (0x40003000u)
-/** Peripheral GINT1 base pointer */
-#define GINT1                                    ((GINT_Type *)GINT1_BASE)
-/** Array initializer of GINT peripheral base addresses */
-#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
-/** Array initializer of GINT peripheral base pointers */
-#define GINT_BASE_PTRS                           { GINT0, GINT1 }
-/** Interrupt vectors for the GINT peripheral type */
-#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
-
-/*!
- * @}
- */ /* end of group GINT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- GPIO Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t B[6][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
-       uint8_t RESERVED_0[3904];
-  __IO uint32_t W[6][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
-       uint8_t RESERVED_1[3328];
-  __IO uint32_t DIR[6];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
-       uint8_t RESERVED_2[104];
-  __IO uint32_t MASK[6];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
-       uint8_t RESERVED_3[104];
-  __IO uint32_t PIN[6];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
-       uint8_t RESERVED_4[104];
-  __IO uint32_t MPIN[6];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
-       uint8_t RESERVED_5[104];
-  __IO uint32_t SET[6];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
-       uint8_t RESERVED_6[104];
-  __O  uint32_t CLR[6];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
-       uint8_t RESERVED_7[104];
-  __O  uint32_t NOT[6];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
-       uint8_t RESERVED_8[104];
-  __O  uint32_t DIRSET[6];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
-       uint8_t RESERVED_9[104];
-  __O  uint32_t DIRCLR[6];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
-       uint8_t RESERVED_10[104];
-  __O  uint32_t DIRNOT[6];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
-   -- GPIO Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
-#define GPIO_B_PBYTE_MASK                        (0x1U)
-#define GPIO_B_PBYTE_SHIFT                       (0U)
-#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
-
-/* The count of GPIO_B */
-#define GPIO_B_COUNT                             (6U)
-
-/* The count of GPIO_B */
-#define GPIO_B_COUNT2                            (32U)
-
-/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
-#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
-#define GPIO_W_PWORD_SHIFT                       (0U)
-#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
-
-/* The count of GPIO_W */
-#define GPIO_W_COUNT                             (6U)
-
-/* The count of GPIO_W */
-#define GPIO_W_COUNT2                            (32U)
-
-/*! @name DIR - Direction registers */
-#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
-#define GPIO_DIR_DIRP_SHIFT                      (0U)
-#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
-
-/* The count of GPIO_DIR */
-#define GPIO_DIR_COUNT                           (6U)
-
-/*! @name MASK - Mask register */
-#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
-#define GPIO_MASK_MASKP_SHIFT                    (0U)
-#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
-
-/* The count of GPIO_MASK */
-#define GPIO_MASK_COUNT                          (6U)
-
-/*! @name PIN - Port pin register */
-#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
-#define GPIO_PIN_PORT_SHIFT                      (0U)
-#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
-
-/* The count of GPIO_PIN */
-#define GPIO_PIN_COUNT                           (6U)
-
-/*! @name MPIN - Masked port register */
-#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
-#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
-#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
-
-/* The count of GPIO_MPIN */
-#define GPIO_MPIN_COUNT                          (6U)
-
-/*! @name SET - Write: Set register for port Read: output bits for port */
-#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
-#define GPIO_SET_SETP_SHIFT                      (0U)
-#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
-
-/* The count of GPIO_SET */
-#define GPIO_SET_COUNT                           (6U)
-
-/*! @name CLR - Clear port */
-#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
-#define GPIO_CLR_CLRP_SHIFT                      (0U)
-#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
-
-/* The count of GPIO_CLR */
-#define GPIO_CLR_COUNT                           (6U)
-
-/*! @name NOT - Toggle port */
-#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
-#define GPIO_NOT_NOTP_SHIFT                      (0U)
-#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
-
-/* The count of GPIO_NOT */
-#define GPIO_NOT_COUNT                           (6U)
-
-/*! @name DIRSET - Set pin direction bits for port */
-#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
-#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
-#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
-
-/* The count of GPIO_DIRSET */
-#define GPIO_DIRSET_COUNT                        (6U)
-
-/*! @name DIRCLR - Clear pin direction bits for port */
-#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
-#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
-#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
-
-/* The count of GPIO_DIRCLR */
-#define GPIO_DIRCLR_COUNT                        (6U)
-
-/*! @name DIRNOT - Toggle pin direction bits for port */
-#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
-#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
-#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
-
-/* The count of GPIO_DIRNOT */
-#define GPIO_DIRNOT_COUNT                        (6U)
-
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral GPIO base address */
-#define GPIO_BASE                                (0x4008C000u)
-/** Peripheral GPIO base pointer */
-#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS                          { GPIO_BASE }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS                           { GPIO }
-
-/*!
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- I2C Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[2048];
-  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
-  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
-  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
-  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
-  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
-  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
-  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
-  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
-  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
-       uint8_t RESERVED_2[20];
-  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
-  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
-  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
-  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
-       uint8_t RESERVED_3[36];
-  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
-       uint8_t RESERVED_4[1912];
-  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
-   -- I2C Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/*! @name CFG - Configuration for shared functions. */
-#define I2C_CFG_MSTEN_MASK                       (0x1U)
-#define I2C_CFG_MSTEN_SHIFT                      (0U)
-#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
-#define I2C_CFG_SLVEN_MASK                       (0x2U)
-#define I2C_CFG_SLVEN_SHIFT                      (1U)
-#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
-#define I2C_CFG_MONEN_MASK                       (0x4U)
-#define I2C_CFG_MONEN_SHIFT                      (2U)
-#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
-#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
-#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
-#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
-#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
-#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
-#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
-#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
-#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
-#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
-
-/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
-#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
-#define I2C_STAT_MSTPENDING_SHIFT                (0U)
-#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
-#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
-#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
-#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
-#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
-#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
-#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
-#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
-#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
-#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
-#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
-#define I2C_STAT_SLVPENDING_SHIFT                (8U)
-#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
-#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
-#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
-#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
-#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
-#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
-#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
-#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
-#define I2C_STAT_SLVIDX_SHIFT                    (12U)
-#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
-#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
-#define I2C_STAT_SLVSEL_SHIFT                    (14U)
-#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
-#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
-#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
-#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
-#define I2C_STAT_MONRDY_MASK                     (0x10000U)
-#define I2C_STAT_MONRDY_SHIFT                    (16U)
-#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
-#define I2C_STAT_MONOV_MASK                      (0x20000U)
-#define I2C_STAT_MONOV_SHIFT                     (17U)
-#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
-#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
-#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
-#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
-#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
-#define I2C_STAT_MONIDLE_SHIFT                   (19U)
-#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
-#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
-#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
-#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
-#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
-#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
-#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
-
-/*! @name INTENSET - Interrupt Enable Set and read register. */
-#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
-#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
-#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
-#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
-#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
-#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
-#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
-#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
-#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
-#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
-#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
-#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
-#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
-#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
-#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
-#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
-#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
-#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
-#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
-#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
-#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
-#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
-#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
-#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
-#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
-#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
-#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
-#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
-#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
-#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
-#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
-#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
-#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
-
-/*! @name INTENCLR - Interrupt Enable Clear register. */
-#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
-#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
-#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
-#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
-#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
-#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
-#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
-#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
-#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
-#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
-#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
-#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
-#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
-#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
-#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
-#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
-#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
-#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
-#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
-#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
-#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
-#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
-#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
-#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
-#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
-#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
-
-/*! @name TIMEOUT - Time-out value register. */
-#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
-#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
-#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
-#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
-#define I2C_TIMEOUT_TO_SHIFT                     (4U)
-#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
-
-/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
-#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
-#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
-#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
-
-/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
-#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
-#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
-#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
-#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
-#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
-#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
-#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
-#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
-#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
-#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
-#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
-#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
-#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
-#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
-#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
-#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
-#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
-#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
-#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
-#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
-#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
-#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
-#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
-#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
-#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
-#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
-#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
-#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
-#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
-#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
-#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
-#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
-#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
-
-/*! @name MSTCTL - Master control register. */
-#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
-#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
-#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
-#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
-#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
-#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
-#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
-#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
-#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
-#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
-#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
-#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
-
-/*! @name MSTTIME - Master timing configuration. */
-#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
-#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
-#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
-#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
-#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
-#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
-
-/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
-#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
-#define I2C_MSTDAT_DATA_SHIFT                    (0U)
-#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
-
-/*! @name SLVCTL - Slave control register. */
-#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
-#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
-#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
-#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
-#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
-#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
-#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
-#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
-#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
-#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
-#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
-#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
-#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
-#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
-#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
-
-/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
-#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
-#define I2C_SLVDAT_DATA_SHIFT                    (0U)
-#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
-
-/*! @name SLVADR - Slave address register. */
-#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
-#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
-#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
-#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
-#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
-#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
-#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
-#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
-#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
-
-/* The count of I2C_SLVADR */
-#define I2C_SLVADR_COUNT                         (4U)
-
-/*! @name SLVQUAL0 - Slave Qualification for address 0. */
-#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
-#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
-#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
-#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
-#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
-#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
-
-/*! @name MONRXDAT - Monitor receiver data register. */
-#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
-#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
-#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
-#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
-#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
-#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
-#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
-#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
-#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
-#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
-#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
-#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define I2C_ID_APERTURE_MASK                     (0xFFU)
-#define I2C_ID_APERTURE_SHIFT                    (0U)
-#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
-#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
-#define I2C_ID_MINOR_REV_SHIFT                   (8U)
-#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
-#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
-#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
-#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
-#define I2C_ID_ID_MASK                           (0xFFFF0000U)
-#define I2C_ID_ID_SHIFT                          (16U)
-#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE                                (0x40086000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0                                     ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE                                (0x40087000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1                                     ((I2C_Type *)I2C1_BASE)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE                                (0x40088000u)
-/** Peripheral I2C2 base pointer */
-#define I2C2                                     ((I2C_Type *)I2C2_BASE)
-/** Peripheral I2C3 base address */
-#define I2C3_BASE                                (0x40089000u)
-/** Peripheral I2C3 base pointer */
-#define I2C3                                     ((I2C_Type *)I2C3_BASE)
-/** Peripheral I2C4 base address */
-#define I2C4_BASE                                (0x4008A000u)
-/** Peripheral I2C4 base pointer */
-#define I2C4                                     ((I2C_Type *)I2C4_BASE)
-/** Peripheral I2C5 base address */
-#define I2C5_BASE                                (0x40096000u)
-/** Peripheral I2C5 base pointer */
-#define I2C5                                     ((I2C_Type *)I2C5_BASE)
-/** Peripheral I2C6 base address */
-#define I2C6_BASE                                (0x40097000u)
-/** Peripheral I2C6 base pointer */
-#define I2C6                                     ((I2C_Type *)I2C6_BASE)
-/** Peripheral I2C7 base address */
-#define I2C7_BASE                                (0x40098000u)
-/** Peripheral I2C7 base pointer */
-#define I2C7                                     ((I2C_Type *)I2C7_BASE)
-/** Peripheral I2C8 base address */
-#define I2C8_BASE                                (0x40099000u)
-/** Peripheral I2C8 base pointer */
-#define I2C8                                     ((I2C_Type *)I2C8_BASE)
-/** Peripheral I2C9 base address */
-#define I2C9_BASE                                (0x4009A000u)
-/** Peripheral I2C9 base pointer */
-#define I2C9                                     ((I2C_Type *)I2C9_BASE)
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
-/** Interrupt vectors for the I2C peripheral type */
-#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- I2S Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[32];
-  struct {                                         /* offset: 0x20, array step: 0x20 */
-    __IO uint32_t PCFG1;                             /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */
-    __IO uint32_t PCFG2;                             /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */
-    __IO uint32_t PSTAT;                             /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */
-         uint8_t RESERVED_0[20];
-  } SECCHANNEL[3];
-       uint8_t RESERVED_1[2944];
-  __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
-  __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
-  __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
-       uint8_t RESERVED_2[16];
-  __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
-       uint8_t RESERVED_3[480];
-  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
-  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
-  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
-       uint8_t RESERVED_4[4];
-  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
-  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
-  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
-       uint8_t RESERVED_5[4];
-  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
-  __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
-       uint8_t RESERVED_6[8];
-  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
-  __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
-       uint8_t RESERVED_7[8];
-  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
-  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
-       uint8_t RESERVED_8[4020];
-  __I  uint32_t ID;                                /**< I2S Module identification, offset: 0x1DFC */
-} I2S_Type;
-
-/* ----------------------------------------------------------------------------
-   -- I2S Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
-
-/* The count of I2S_SECCHANNEL_PCFG1 */
-#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)
-
-/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
-#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
-#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
-#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
-
-/* The count of I2S_SECCHANNEL_PCFG2 */
-#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)
-
-/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
-#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
-#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
-#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
-#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
-#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
-#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
-
-/* The count of I2S_SECCHANNEL_PSTAT */
-#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)
-
-/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
-#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
-#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
-#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
-#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
-#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
-#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
-#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
-#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
-#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
-#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
-#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
-#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
-#define I2S_CFG1_MODE_MASK                       (0xC0U)
-#define I2S_CFG1_MODE_SHIFT                      (6U)
-#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
-#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
-#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
-#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
-#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
-#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
-#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
-#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
-#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
-#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
-#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
-#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
-#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
-#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
-#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
-#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
-#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
-#define I2S_CFG1_WS_POL_SHIFT                    (13U)
-#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
-#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
-#define I2S_CFG1_DATALEN_SHIFT                   (16U)
-#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
-
-/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
-#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
-#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
-#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
-#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
-#define I2S_CFG2_POSITION_SHIFT                  (16U)
-#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
-
-/*! @name STAT - Status register for the primary channel pair. */
-#define I2S_STAT_BUSY_MASK                       (0x1U)
-#define I2S_STAT_BUSY_SHIFT                      (0U)
-#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
-#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
-#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
-#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
-#define I2S_STAT_LR_MASK                         (0x4U)
-#define I2S_STAT_LR_SHIFT                        (2U)
-#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
-#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
-#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
-#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
-
-/*! @name DIV - Clock divider, used by all channel pairs. */
-#define I2S_DIV_DIV_MASK                         (0xFFFU)
-#define I2S_DIV_DIV_SHIFT                        (0U)
-#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
-#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
-#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
-#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
-#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
-#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
-#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
-#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
-#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
-#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
-#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
-#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
-#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
-#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
-#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
-#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
-#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
-#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
-#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
-#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
-#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
-#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
-#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
-#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
-#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
-#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
-#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
-#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
-#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
-#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
-#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
-#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
-#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
-#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
-#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
-#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
-#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
-#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
-#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
-#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
-#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
-#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
-#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
-#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
-#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
-#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
-#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
-#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
-#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
-#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
-#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
-#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
-#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
-#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
-#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
-#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
-#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
-#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
-#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
-#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
-#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
-#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
-#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
-#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
-#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
-#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
-#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
-#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
-#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
-#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
-#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
-#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
-#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
-#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
-#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
-#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
-#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
-#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
-#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
-#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
-#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
-#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
-#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
-#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
-#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
-#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
-#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
-#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
-#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
-#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
-#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
-#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
-#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
-#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
-#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
-#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
-#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
-#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
-#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
-#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
-#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
-#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
-#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
-#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
-#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
-#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
-#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
-#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
-#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
-#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
-#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
-
-/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
-#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
-#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
-#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
-#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
-
-/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
-#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
-#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
-#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
-#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
-
-/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
-#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
-#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
-
-/*! @name ID - I2S Module identification */
-#define I2S_ID_Aperture_MASK                     (0xFFU)
-#define I2S_ID_Aperture_SHIFT                    (0U)
-#define I2S_ID_Aperture(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
-#define I2S_ID_Minor_Rev_MASK                    (0xF00U)
-#define I2S_ID_Minor_Rev_SHIFT                   (8U)
-#define I2S_ID_Minor_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
-#define I2S_ID_Major_Rev_MASK                    (0xF000U)
-#define I2S_ID_Major_Rev_SHIFT                   (12U)
-#define I2S_ID_Major_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
-#define I2S_ID_ID_MASK                           (0xFFFF0000U)
-#define I2S_ID_ID_SHIFT                          (16U)
-#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE                                (0x40097000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0                                     ((I2S_Type *)I2S0_BASE)
-/** Peripheral I2S1 base address */
-#define I2S1_BASE                                (0x40098000u)
-/** Peripheral I2S1 base pointer */
-#define I2S1                                     ((I2S_Type *)I2S1_BASE)
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS                            { I2S0, I2S1 }
-/** Interrupt vectors for the I2S peripheral type */
-#define I2S_IRQS                                 { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
-
-/*!
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- INPUTMUX Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
- * @{
- */
-
-/** INPUTMUX - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t SCT0_INMUX[7];                     /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
-       uint8_t RESERVED_0[164];
-  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
-  __IO uint32_t DMA_ITRIG_INMUX[30];               /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
-       uint8_t RESERVED_1[8];
-  __IO uint32_t DMA_OTRIG_INMUX[4];                /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
-       uint8_t RESERVED_2[16];
-  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
-  __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
-} INPUTMUX_Type;
-
-/* ----------------------------------------------------------------------------
-   -- INPUTMUX Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
- * @{
- */
-
-/*! @name SCT0_INMUX - Trigger select register for DMA channel */
-#define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x1FU)
-#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
-#define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
-
-/* The count of INPUTMUX_SCT0_INMUX */
-#define INPUTMUX_SCT0_INMUX_COUNT                (7U)
-
-/*! @name PINTSEL - Pin interrupt select register */
-#define INPUTMUX_PINTSEL_INTPIN_MASK             (0xFFU)
-#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
-#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
-
-/* The count of INPUTMUX_PINTSEL */
-#define INPUTMUX_PINTSEL_COUNT                   (8U)
-
-/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
-#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK        (0x1FU)
-#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT       (0U)
-#define INPUTMUX_DMA_ITRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
-
-/* The count of INPUTMUX_DMA_ITRIG_INMUX */
-#define INPUTMUX_DMA_ITRIG_INMUX_COUNT           (30U)
-
-/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
-#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK        (0x1FU)
-#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT       (0U)
-#define INPUTMUX_DMA_OTRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
-
-/* The count of INPUTMUX_DMA_OTRIG_INMUX */
-#define INPUTMUX_DMA_OTRIG_INMUX_COUNT           (4U)
-
-/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
-#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
-#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
-#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
-
-/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
-
-
-/*!
- * @}
- */ /* end of group INPUTMUX_Register_Masks */
-
-
-/* INPUTMUX - Peripheral instance base addresses */
-/** Peripheral INPUTMUX base address */
-#define INPUTMUX_BASE                            (0x40005000u)
-/** Peripheral INPUTMUX base pointer */
-#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
-/** Array initializer of INPUTMUX peripheral base addresses */
-#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
-/** Array initializer of INPUTMUX peripheral base pointers */
-#define INPUTMUX_BASE_PTRS                       { INPUTMUX }
-
-/*!
- * @}
- */ /* end of group INPUTMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- IOCON Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
- * @{
- */
-
-/** IOCON - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t PIO[6][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
-} IOCON_Type;
-
-/* ----------------------------------------------------------------------------
-   -- IOCON Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup IOCON_Register_Masks IOCON Register Masks
- * @{
- */
-
-/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
-#define IOCON_PIO_FUNC_MASK                      (0xFU)
-#define IOCON_PIO_FUNC_SHIFT                     (0U)
-#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
-#define IOCON_PIO_MODE_MASK                      (0x30U)
-#define IOCON_PIO_MODE_SHIFT                     (4U)
-#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
-#define IOCON_PIO_I2CSLEW_MASK                   (0x40U)
-#define IOCON_PIO_I2CSLEW_SHIFT                  (6U)
-#define IOCON_PIO_I2CSLEW(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
-#define IOCON_PIO_INVERT_MASK                    (0x80U)
-#define IOCON_PIO_INVERT_SHIFT                   (7U)
-#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
-#define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
-#define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
-#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
-#define IOCON_PIO_FILTEROFF_MASK                 (0x200U)
-#define IOCON_PIO_FILTEROFF_SHIFT                (9U)
-#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
-#define IOCON_PIO_I2CDRIVE_MASK                  (0x400U)
-#define IOCON_PIO_I2CDRIVE_SHIFT                 (10U)
-#define IOCON_PIO_I2CDRIVE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
-#define IOCON_PIO_SLEW_MASK                      (0x400U)
-#define IOCON_PIO_SLEW_SHIFT                     (10U)
-#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
-#define IOCON_PIO_OD_MASK                        (0x800U)
-#define IOCON_PIO_OD_SHIFT                       (11U)
-#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
-#define IOCON_PIO_I2CFILTER_MASK                 (0x800U)
-#define IOCON_PIO_I2CFILTER_SHIFT                (11U)
-#define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
-
-/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT                          (6U)
-
-/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT2                         (32U)
-
-
-/*!
- * @}
- */ /* end of group IOCON_Register_Masks */
-
-
-/* IOCON - Peripheral instance base addresses */
-/** Peripheral IOCON base address */
-#define IOCON_BASE                               (0x40001000u)
-/** Peripheral IOCON base pointer */
-#define IOCON                                    ((IOCON_Type *)IOCON_BASE)
-/** Array initializer of IOCON peripheral base addresses */
-#define IOCON_BASE_ADDRS                         { IOCON_BASE }
-/** Array initializer of IOCON peripheral base pointers */
-#define IOCON_BASE_PTRS                          { IOCON }
-
-/*!
- * @}
- */ /* end of group IOCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- LCD Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
- * @{
- */
-
-/** LCD - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t TIMH;                              /**< Horizontal Timing Control register, offset: 0x0 */
-  __IO uint32_t TIMV;                              /**< Vertical Timing Control register, offset: 0x4 */
-  __IO uint32_t POL;                               /**< Clock and Signal Polarity Control register, offset: 0x8 */
-  __IO uint32_t LE;                                /**< Line End Control register, offset: 0xC */
-  __IO uint32_t UPBASE;                            /**< Upper Panel Frame Base Address register, offset: 0x10 */
-  __IO uint32_t LPBASE;                            /**< Lower Panel Frame Base Address register, offset: 0x14 */
-  __IO uint32_t CTRL;                              /**< LCD Control register, offset: 0x18 */
-  __IO uint32_t INTMSK;                            /**< Interrupt Mask register, offset: 0x1C */
-  __I  uint32_t INTRAW;                            /**< Raw Interrupt Status register, offset: 0x20 */
-  __I  uint32_t INTSTAT;                           /**< Masked Interrupt Status register, offset: 0x24 */
-  __IO uint32_t INTCLR;                            /**< Interrupt Clear register, offset: 0x28 */
-  __I  uint32_t UPCURR;                            /**< Upper Panel Current Address Value register, offset: 0x2C */
-  __I  uint32_t LPCURR;                            /**< Lower Panel Current Address Value register, offset: 0x30 */
-       uint8_t RESERVED_0[460];
-  __IO uint32_t PAL[128];                          /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
-       uint8_t RESERVED_1[1024];
-  __IO uint32_t CRSR_IMG[256];                     /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
-  __IO uint32_t CRSR_CTRL;                         /**< Cursor Control register, offset: 0xC00 */
-  __IO uint32_t CRSR_CFG;                          /**< Cursor Configuration register, offset: 0xC04 */
-  __IO uint32_t CRSR_PAL0;                         /**< Cursor Palette register 0, offset: 0xC08 */
-  __IO uint32_t CRSR_PAL1;                         /**< Cursor Palette register 1, offset: 0xC0C */
-  __IO uint32_t CRSR_XY;                           /**< Cursor XY Position register, offset: 0xC10 */
-  __IO uint32_t CRSR_CLIP;                         /**< Cursor Clip Position register, offset: 0xC14 */
-       uint8_t RESERVED_2[8];
-  __IO uint32_t CRSR_INTMSK;                       /**< Cursor Interrupt Mask register, offset: 0xC20 */
-  __O  uint32_t CRSR_INTCLR;                       /**< Cursor Interrupt Clear register, offset: 0xC24 */
-  __I  uint32_t CRSR_INTRAW;                       /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
-  __I  uint32_t CRSR_INTSTAT;                      /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
-} LCD_Type;
-
-/* ----------------------------------------------------------------------------
-   -- LCD Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LCD_Register_Masks LCD Register Masks
- * @{
- */
-
-/*! @name TIMH - Horizontal Timing Control register */
-#define LCD_TIMH_PPL_MASK                        (0xFCU)
-#define LCD_TIMH_PPL_SHIFT                       (2U)
-#define LCD_TIMH_PPL(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
-#define LCD_TIMH_HSW_MASK                        (0xFF00U)
-#define LCD_TIMH_HSW_SHIFT                       (8U)
-#define LCD_TIMH_HSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
-#define LCD_TIMH_HFP_MASK                        (0xFF0000U)
-#define LCD_TIMH_HFP_SHIFT                       (16U)
-#define LCD_TIMH_HFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
-#define LCD_TIMH_HBP_MASK                        (0xFF000000U)
-#define LCD_TIMH_HBP_SHIFT                       (24U)
-#define LCD_TIMH_HBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
-
-/*! @name TIMV - Vertical Timing Control register */
-#define LCD_TIMV_LPP_MASK                        (0x3FFU)
-#define LCD_TIMV_LPP_SHIFT                       (0U)
-#define LCD_TIMV_LPP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
-#define LCD_TIMV_VSW_MASK                        (0xFC00U)
-#define LCD_TIMV_VSW_SHIFT                       (10U)
-#define LCD_TIMV_VSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
-#define LCD_TIMV_VFP_MASK                        (0xFF0000U)
-#define LCD_TIMV_VFP_SHIFT                       (16U)
-#define LCD_TIMV_VFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
-#define LCD_TIMV_VBP_MASK                        (0xFF000000U)
-#define LCD_TIMV_VBP_SHIFT                       (24U)
-#define LCD_TIMV_VBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
-
-/*! @name POL - Clock and Signal Polarity Control register */
-#define LCD_POL_PCD_LO_MASK                      (0x1FU)
-#define LCD_POL_PCD_LO_SHIFT                     (0U)
-#define LCD_POL_PCD_LO(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
-#define LCD_POL_ACB_MASK                         (0x7C0U)
-#define LCD_POL_ACB_SHIFT                        (6U)
-#define LCD_POL_ACB(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
-#define LCD_POL_IVS_MASK                         (0x800U)
-#define LCD_POL_IVS_SHIFT                        (11U)
-#define LCD_POL_IVS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
-#define LCD_POL_IHS_MASK                         (0x1000U)
-#define LCD_POL_IHS_SHIFT                        (12U)
-#define LCD_POL_IHS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
-#define LCD_POL_IPC_MASK                         (0x2000U)
-#define LCD_POL_IPC_SHIFT                        (13U)
-#define LCD_POL_IPC(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
-#define LCD_POL_IOE_MASK                         (0x4000U)
-#define LCD_POL_IOE_SHIFT                        (14U)
-#define LCD_POL_IOE(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
-#define LCD_POL_CPL_MASK                         (0x3FF0000U)
-#define LCD_POL_CPL_SHIFT                        (16U)
-#define LCD_POL_CPL(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
-#define LCD_POL_BCD_MASK                         (0x4000000U)
-#define LCD_POL_BCD_SHIFT                        (26U)
-#define LCD_POL_BCD(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
-#define LCD_POL_PCD_HI_MASK                      (0xF8000000U)
-#define LCD_POL_PCD_HI_SHIFT                     (27U)
-#define LCD_POL_PCD_HI(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
-
-/*! @name LE - Line End Control register */
-#define LCD_LE_LED_MASK                          (0x7FU)
-#define LCD_LE_LED_SHIFT                         (0U)
-#define LCD_LE_LED(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
-#define LCD_LE_LEE_MASK                          (0x10000U)
-#define LCD_LE_LEE_SHIFT                         (16U)
-#define LCD_LE_LEE(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
-
-/*! @name UPBASE - Upper Panel Frame Base Address register */
-#define LCD_UPBASE_LCDUPBASE_MASK                (0xFFFFFFF8U)
-#define LCD_UPBASE_LCDUPBASE_SHIFT               (3U)
-#define LCD_UPBASE_LCDUPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
-
-/*! @name LPBASE - Lower Panel Frame Base Address register */
-#define LCD_LPBASE_LCDLPBASE_MASK                (0xFFFFFFF8U)
-#define LCD_LPBASE_LCDLPBASE_SHIFT               (3U)
-#define LCD_LPBASE_LCDLPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
-
-/*! @name CTRL - LCD Control register */
-#define LCD_CTRL_LCDEN_MASK                      (0x1U)
-#define LCD_CTRL_LCDEN_SHIFT                     (0U)
-#define LCD_CTRL_LCDEN(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
-#define LCD_CTRL_LCDBPP_MASK                     (0xEU)
-#define LCD_CTRL_LCDBPP_SHIFT                    (1U)
-#define LCD_CTRL_LCDBPP(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
-#define LCD_CTRL_LCDBW_MASK                      (0x10U)
-#define LCD_CTRL_LCDBW_SHIFT                     (4U)
-#define LCD_CTRL_LCDBW(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
-#define LCD_CTRL_LCDTFT_MASK                     (0x20U)
-#define LCD_CTRL_LCDTFT_SHIFT                    (5U)
-#define LCD_CTRL_LCDTFT(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
-#define LCD_CTRL_LCDMONO8_MASK                   (0x40U)
-#define LCD_CTRL_LCDMONO8_SHIFT                  (6U)
-#define LCD_CTRL_LCDMONO8(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
-#define LCD_CTRL_LCDDUAL_MASK                    (0x80U)
-#define LCD_CTRL_LCDDUAL_SHIFT                   (7U)
-#define LCD_CTRL_LCDDUAL(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
-#define LCD_CTRL_BGR_MASK                        (0x100U)
-#define LCD_CTRL_BGR_SHIFT                       (8U)
-#define LCD_CTRL_BGR(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
-#define LCD_CTRL_BEBO_MASK                       (0x200U)
-#define LCD_CTRL_BEBO_SHIFT                      (9U)
-#define LCD_CTRL_BEBO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
-#define LCD_CTRL_BEPO_MASK                       (0x400U)
-#define LCD_CTRL_BEPO_SHIFT                      (10U)
-#define LCD_CTRL_BEPO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
-#define LCD_CTRL_LCDPWR_MASK                     (0x800U)
-#define LCD_CTRL_LCDPWR_SHIFT                    (11U)
-#define LCD_CTRL_LCDPWR(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
-#define LCD_CTRL_LCDVCOMP_MASK                   (0x3000U)
-#define LCD_CTRL_LCDVCOMP_SHIFT                  (12U)
-#define LCD_CTRL_LCDVCOMP(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
-#define LCD_CTRL_WATERMARK_MASK                  (0x10000U)
-#define LCD_CTRL_WATERMARK_SHIFT                 (16U)
-#define LCD_CTRL_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
-
-/*! @name INTMSK - Interrupt Mask register */
-#define LCD_INTMSK_FUFIM_MASK                    (0x2U)
-#define LCD_INTMSK_FUFIM_SHIFT                   (1U)
-#define LCD_INTMSK_FUFIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
-#define LCD_INTMSK_LNBUIM_MASK                   (0x4U)
-#define LCD_INTMSK_LNBUIM_SHIFT                  (2U)
-#define LCD_INTMSK_LNBUIM(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
-#define LCD_INTMSK_VCOMPIM_MASK                  (0x8U)
-#define LCD_INTMSK_VCOMPIM_SHIFT                 (3U)
-#define LCD_INTMSK_VCOMPIM(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
-#define LCD_INTMSK_BERIM_MASK                    (0x10U)
-#define LCD_INTMSK_BERIM_SHIFT                   (4U)
-#define LCD_INTMSK_BERIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
-
-/*! @name INTRAW - Raw Interrupt Status register */
-#define LCD_INTRAW_FUFRIS_MASK                   (0x2U)
-#define LCD_INTRAW_FUFRIS_SHIFT                  (1U)
-#define LCD_INTRAW_FUFRIS(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
-#define LCD_INTRAW_LNBURIS_MASK                  (0x4U)
-#define LCD_INTRAW_LNBURIS_SHIFT                 (2U)
-#define LCD_INTRAW_LNBURIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
-#define LCD_INTRAW_VCOMPRIS_MASK                 (0x8U)
-#define LCD_INTRAW_VCOMPRIS_SHIFT                (3U)
-#define LCD_INTRAW_VCOMPRIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
-#define LCD_INTRAW_BERRAW_MASK                   (0x10U)
-#define LCD_INTRAW_BERRAW_SHIFT                  (4U)
-#define LCD_INTRAW_BERRAW(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
-
-/*! @name INTSTAT - Masked Interrupt Status register */
-#define LCD_INTSTAT_FUFMIS_MASK                  (0x2U)
-#define LCD_INTSTAT_FUFMIS_SHIFT                 (1U)
-#define LCD_INTSTAT_FUFMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
-#define LCD_INTSTAT_LNBUMIS_MASK                 (0x4U)
-#define LCD_INTSTAT_LNBUMIS_SHIFT                (2U)
-#define LCD_INTSTAT_LNBUMIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
-#define LCD_INTSTAT_VCOMPMIS_MASK                (0x8U)
-#define LCD_INTSTAT_VCOMPMIS_SHIFT               (3U)
-#define LCD_INTSTAT_VCOMPMIS(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
-#define LCD_INTSTAT_BERMIS_MASK                  (0x10U)
-#define LCD_INTSTAT_BERMIS_SHIFT                 (4U)
-#define LCD_INTSTAT_BERMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
-
-/*! @name INTCLR - Interrupt Clear register */
-#define LCD_INTCLR_FUFIC_MASK                    (0x2U)
-#define LCD_INTCLR_FUFIC_SHIFT                   (1U)
-#define LCD_INTCLR_FUFIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
-#define LCD_INTCLR_LNBUIC_MASK                   (0x4U)
-#define LCD_INTCLR_LNBUIC_SHIFT                  (2U)
-#define LCD_INTCLR_LNBUIC(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
-#define LCD_INTCLR_VCOMPIC_MASK                  (0x8U)
-#define LCD_INTCLR_VCOMPIC_SHIFT                 (3U)
-#define LCD_INTCLR_VCOMPIC(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
-#define LCD_INTCLR_BERIC_MASK                    (0x10U)
-#define LCD_INTCLR_BERIC_SHIFT                   (4U)
-#define LCD_INTCLR_BERIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
-
-/*! @name UPCURR - Upper Panel Current Address Value register */
-#define LCD_UPCURR_LCDUPCURR_MASK                (0xFFFFFFFFU)
-#define LCD_UPCURR_LCDUPCURR_SHIFT               (0U)
-#define LCD_UPCURR_LCDUPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
-
-/*! @name LPCURR - Lower Panel Current Address Value register */
-#define LCD_LPCURR_LCDLPCURR_MASK                (0xFFFFFFFFU)
-#define LCD_LPCURR_LCDLPCURR_SHIFT               (0U)
-#define LCD_LPCURR_LCDLPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
-
-/*! @name PAL - 256x16-bit Color Palette registers */
-#define LCD_PAL_R04_0_MASK                       (0x1FU)
-#define LCD_PAL_R04_0_SHIFT                      (0U)
-#define LCD_PAL_R04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
-#define LCD_PAL_G04_0_MASK                       (0x3E0U)
-#define LCD_PAL_G04_0_SHIFT                      (5U)
-#define LCD_PAL_G04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
-#define LCD_PAL_B04_0_MASK                       (0x7C00U)
-#define LCD_PAL_B04_0_SHIFT                      (10U)
-#define LCD_PAL_B04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
-#define LCD_PAL_I0_MASK                          (0x8000U)
-#define LCD_PAL_I0_SHIFT                         (15U)
-#define LCD_PAL_I0(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
-#define LCD_PAL_R14_0_MASK                       (0x1F0000U)
-#define LCD_PAL_R14_0_SHIFT                      (16U)
-#define LCD_PAL_R14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
-#define LCD_PAL_G14_0_MASK                       (0x3E00000U)
-#define LCD_PAL_G14_0_SHIFT                      (21U)
-#define LCD_PAL_G14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
-#define LCD_PAL_B14_0_MASK                       (0x7C000000U)
-#define LCD_PAL_B14_0_SHIFT                      (26U)
-#define LCD_PAL_B14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
-#define LCD_PAL_I1_MASK                          (0x80000000U)
-#define LCD_PAL_I1_SHIFT                         (31U)
-#define LCD_PAL_I1(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
-
-/* The count of LCD_PAL */
-#define LCD_PAL_COUNT                            (128U)
-
-/*! @name CRSR_IMG - Cursor Image registers */
-#define LCD_CRSR_IMG_CRSR_IMG_MASK               (0xFFFFFFFFU)
-#define LCD_CRSR_IMG_CRSR_IMG_SHIFT              (0U)
-#define LCD_CRSR_IMG_CRSR_IMG(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
-
-/* The count of LCD_CRSR_IMG */
-#define LCD_CRSR_IMG_COUNT                       (256U)
-
-/*! @name CRSR_CTRL - Cursor Control register */
-#define LCD_CRSR_CTRL_CRSRON_MASK                (0x1U)
-#define LCD_CRSR_CTRL_CRSRON_SHIFT               (0U)
-#define LCD_CRSR_CTRL_CRSRON(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
-#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK            (0x30U)
-#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT           (4U)
-#define LCD_CRSR_CTRL_CRSRNUM1_0(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
-
-/*! @name CRSR_CFG - Cursor Configuration register */
-#define LCD_CRSR_CFG_CRSRSIZE_MASK               (0x1U)
-#define LCD_CRSR_CFG_CRSRSIZE_SHIFT              (0U)
-#define LCD_CRSR_CFG_CRSRSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
-#define LCD_CRSR_CFG_FRAMESYNC_MASK              (0x2U)
-#define LCD_CRSR_CFG_FRAMESYNC_SHIFT             (1U)
-#define LCD_CRSR_CFG_FRAMESYNC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
-
-/*! @name CRSR_PAL0 - Cursor Palette register 0 */
-#define LCD_CRSR_PAL0_RED_MASK                   (0xFFU)
-#define LCD_CRSR_PAL0_RED_SHIFT                  (0U)
-#define LCD_CRSR_PAL0_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
-#define LCD_CRSR_PAL0_GREEN_MASK                 (0xFF00U)
-#define LCD_CRSR_PAL0_GREEN_SHIFT                (8U)
-#define LCD_CRSR_PAL0_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
-#define LCD_CRSR_PAL0_BLUE_MASK                  (0xFF0000U)
-#define LCD_CRSR_PAL0_BLUE_SHIFT                 (16U)
-#define LCD_CRSR_PAL0_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
-
-/*! @name CRSR_PAL1 - Cursor Palette register 1 */
-#define LCD_CRSR_PAL1_RED_MASK                   (0xFFU)
-#define LCD_CRSR_PAL1_RED_SHIFT                  (0U)
-#define LCD_CRSR_PAL1_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
-#define LCD_CRSR_PAL1_GREEN_MASK                 (0xFF00U)
-#define LCD_CRSR_PAL1_GREEN_SHIFT                (8U)
-#define LCD_CRSR_PAL1_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
-#define LCD_CRSR_PAL1_BLUE_MASK                  (0xFF0000U)
-#define LCD_CRSR_PAL1_BLUE_SHIFT                 (16U)
-#define LCD_CRSR_PAL1_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
-
-/*! @name CRSR_XY - Cursor XY Position register */
-#define LCD_CRSR_XY_CRSRX_MASK                   (0x3FFU)
-#define LCD_CRSR_XY_CRSRX_SHIFT                  (0U)
-#define LCD_CRSR_XY_CRSRX(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
-#define LCD_CRSR_XY_CRSRY_MASK                   (0x3FF0000U)
-#define LCD_CRSR_XY_CRSRY_SHIFT                  (16U)
-#define LCD_CRSR_XY_CRSRY(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
-
-/*! @name CRSR_CLIP - Cursor Clip Position register */
-#define LCD_CRSR_CLIP_CRSRCLIPX_MASK             (0x3FU)
-#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT            (0U)
-#define LCD_CRSR_CLIP_CRSRCLIPX(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
-#define LCD_CRSR_CLIP_CRSRCLIPY_MASK             (0x3F00U)
-#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT            (8U)
-#define LCD_CRSR_CLIP_CRSRCLIPY(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
-
-/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
-#define LCD_CRSR_INTMSK_CRSRIM_MASK              (0x1U)
-#define LCD_CRSR_INTMSK_CRSRIM_SHIFT             (0U)
-#define LCD_CRSR_INTMSK_CRSRIM(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
-
-/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
-#define LCD_CRSR_INTCLR_CRSRIC_MASK              (0x1U)
-#define LCD_CRSR_INTCLR_CRSRIC_SHIFT             (0U)
-#define LCD_CRSR_INTCLR_CRSRIC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
-
-/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
-#define LCD_CRSR_INTRAW_CRSRRIS_MASK             (0x1U)
-#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT            (0U)
-#define LCD_CRSR_INTRAW_CRSRRIS(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
-
-/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
-#define LCD_CRSR_INTSTAT_CRSRMIS_MASK            (0x1U)
-#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT           (0U)
-#define LCD_CRSR_INTSTAT_CRSRMIS(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
-
-
-/*!
- * @}
- */ /* end of group LCD_Register_Masks */
-
-
-/* LCD - Peripheral instance base addresses */
-/** Peripheral LCD base address */
-#define LCD_BASE                                 (0x40083000u)
-/** Peripheral LCD base pointer */
-#define LCD                                      ((LCD_Type *)LCD_BASE)
-/** Array initializer of LCD peripheral base addresses */
-#define LCD_BASE_ADDRS                           { LCD_BASE }
-/** Array initializer of LCD peripheral base pointers */
-#define LCD_BASE_PTRS                            { LCD }
-/** Interrupt vectors for the LCD peripheral type */
-#define LCD_IRQS                                 { LCD_IRQn }
-
-/*!
- * @}
- */ /* end of group LCD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- MRT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
- * @{
- */
-
-/** MRT - Register Layout Typedef */
-typedef struct {
-  struct {                                         /* offset: 0x0, array step: 0x10 */
-    __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
-    __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
-    __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
-    __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
-  } CHANNEL[4];
-       uint8_t RESERVED_0[176];
-  __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
-  __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
-  __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
-} MRT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MRT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MRT_Register_Masks MRT Register Masks
- * @{
- */
-
-/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
-#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
-#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
-#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
-#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
-#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
-#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
-
-/* The count of MRT_CHANNEL_INTVAL */
-#define MRT_CHANNEL_INTVAL_COUNT                 (4U)
-
-/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
-#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
-#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
-#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
-
-/* The count of MRT_CHANNEL_TIMER */
-#define MRT_CHANNEL_TIMER_COUNT                  (4U)
-
-/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
-#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
-#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
-#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
-#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
-#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
-#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
-
-/* The count of MRT_CHANNEL_CTRL */
-#define MRT_CHANNEL_CTRL_COUNT                   (4U)
-
-/*! @name CHANNEL_STAT - MRT Status register. */
-#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
-#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
-#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
-#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
-#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
-#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
-#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
-#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
-#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
-
-/* The count of MRT_CHANNEL_STAT */
-#define MRT_CHANNEL_STAT_COUNT                   (4U)
-
-/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
-#define MRT_MODCFG_NOC_MASK                      (0xFU)
-#define MRT_MODCFG_NOC_SHIFT                     (0U)
-#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
-#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
-#define MRT_MODCFG_NOB_SHIFT                     (4U)
-#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
-#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
-#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
-#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
-
-/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
-#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
-#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
-#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
-
-/*! @name IRQ_FLAG - Global interrupt flag register */
-#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
-#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
-#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
-#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
-#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
-#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
-#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
-#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
-#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
-#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
-#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
-#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
-
-
-/*!
- * @}
- */ /* end of group MRT_Register_Masks */
-
-
-/* MRT - Peripheral instance base addresses */
-/** Peripheral MRT0 base address */
-#define MRT0_BASE                                (0x4000D000u)
-/** Peripheral MRT0 base pointer */
-#define MRT0                                     ((MRT_Type *)MRT0_BASE)
-/** Array initializer of MRT peripheral base addresses */
-#define MRT_BASE_ADDRS                           { MRT0_BASE }
-/** Array initializer of MRT peripheral base pointers */
-#define MRT_BASE_PTRS                            { MRT0 }
-/** Interrupt vectors for the MRT peripheral type */
-#define MRT_IRQS                                 { MRT0_IRQn }
-
-/*!
- * @}
- */ /* end of group MRT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- OTPC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
- * @{
- */
-
-/** OTPC - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[16];
-  __I  uint32_t AESKEY[8];                         /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
-  __I  uint32_t ECRP;                              /**< ECRP options., offset: 0x30 */
-       uint8_t RESERVED_1[4];
-  __I  uint32_t USER0;                             /**< User application specific options., offset: 0x38 */
-  __I  uint32_t USER1;                             /**< User application specific options., offset: 0x3C */
-} OTPC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- OTPC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OTPC_Register_Masks OTPC Register Masks
- * @{
- */
-
-/*! @name AESKEY - Register for reading the AES key. */
-#define OTPC_AESKEY_KEY_MASK                     (0xFFFFFFFFU)
-#define OTPC_AESKEY_KEY_SHIFT                    (0U)
-#define OTPC_AESKEY_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
-
-/* The count of OTPC_AESKEY */
-#define OTPC_AESKEY_COUNT                        (8U)
-
-/*! @name ECRP - ECRP options. */
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK    (0x10U)
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT   (4U)
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK     (0x20U)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT    (5U)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK       (0x40U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT      (6U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK       (0x80U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT      (7U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
-#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK            (0x200U)
-#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT           (9U)
-#define OTPC_ECRP_CRP_ALLOW_ZERO(x)              (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
-#define OTPC_ECRP_JTAG_DISABLE_MASK              (0x80000000U)
-#define OTPC_ECRP_JTAG_DISABLE_SHIFT             (31U)
-#define OTPC_ECRP_JTAG_DISABLE(x)                (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
-
-/*! @name USER0 - User application specific options. */
-#define OTPC_USER0_USER0_MASK                    (0xFFFFFFFFU)
-#define OTPC_USER0_USER0_SHIFT                   (0U)
-#define OTPC_USER0_USER0(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
-
-/*! @name USER1 - User application specific options. */
-#define OTPC_USER1_USER1_MASK                    (0xFFFFFFFFU)
-#define OTPC_USER1_USER1_SHIFT                   (0U)
-#define OTPC_USER1_USER1(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
-
-
-/*!
- * @}
- */ /* end of group OTPC_Register_Masks */
-
-
-/* OTPC - Peripheral instance base addresses */
-/** Peripheral OTPC base address */
-#define OTPC_BASE                                (0x40015000u)
-/** Peripheral OTPC base pointer */
-#define OTPC                                     ((OTPC_Type *)OTPC_BASE)
-/** Array initializer of OTPC peripheral base addresses */
-#define OTPC_BASE_ADDRS                          { OTPC_BASE }
-/** Array initializer of OTPC peripheral base pointers */
-#define OTPC_BASE_PTRS                           { OTPC }
-
-/*!
- * @}
- */ /* end of group OTPC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- PINT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
- * @{
- */
-
-/** PINT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
-  __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
-  __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
-  __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
-  __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
-  __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
-  __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
-  __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
-  __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
-  __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
-  __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
-  __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
-  __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
-} PINT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- PINT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PINT_Register_Masks PINT Register Masks
- * @{
- */
-
-/*! @name ISEL - Pin Interrupt Mode register */
-#define PINT_ISEL_PMODE_MASK                     (0xFFU)
-#define PINT_ISEL_PMODE_SHIFT                    (0U)
-#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
-
-/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
-#define PINT_IENR_ENRL_MASK                      (0xFFU)
-#define PINT_IENR_ENRL_SHIFT                     (0U)
-#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
-
-/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
-#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
-#define PINT_SIENR_SETENRL_SHIFT                 (0U)
-#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
-
-/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
-#define PINT_CIENR_CENRL_MASK                    (0xFFU)
-#define PINT_CIENR_CENRL_SHIFT                   (0U)
-#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
-
-/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
-#define PINT_IENF_ENAF_MASK                      (0xFFU)
-#define PINT_IENF_ENAF_SHIFT                     (0U)
-#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
-
-/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
-#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
-#define PINT_SIENF_SETENAF_SHIFT                 (0U)
-#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
-
-/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
-#define PINT_CIENF_CENAF_MASK                    (0xFFU)
-#define PINT_CIENF_CENAF_SHIFT                   (0U)
-#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
-
-/*! @name RISE - Pin interrupt rising edge register */
-#define PINT_RISE_RDET_MASK                      (0xFFU)
-#define PINT_RISE_RDET_SHIFT                     (0U)
-#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
-
-/*! @name FALL - Pin interrupt falling edge register */
-#define PINT_FALL_FDET_MASK                      (0xFFU)
-#define PINT_FALL_FDET_SHIFT                     (0U)
-#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
-
-/*! @name IST - Pin interrupt status register */
-#define PINT_IST_PSTAT_MASK                      (0xFFU)
-#define PINT_IST_PSTAT_SHIFT                     (0U)
-#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
-
-/*! @name PMCTRL - Pattern match interrupt control register */
-#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
-#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
-#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
-#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
-#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
-#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
-#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
-#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
-#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
-
-/*! @name PMSRC - Pattern match interrupt bit-slice source register */
-#define PINT_PMSRC_SRC0_MASK                     (0x700U)
-#define PINT_PMSRC_SRC0_SHIFT                    (8U)
-#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
-#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
-#define PINT_PMSRC_SRC1_SHIFT                    (11U)
-#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
-#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
-#define PINT_PMSRC_SRC2_SHIFT                    (14U)
-#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
-#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
-#define PINT_PMSRC_SRC3_SHIFT                    (17U)
-#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
-#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
-#define PINT_PMSRC_SRC4_SHIFT                    (20U)
-#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
-#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
-#define PINT_PMSRC_SRC5_SHIFT                    (23U)
-#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
-#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
-#define PINT_PMSRC_SRC6_SHIFT                    (26U)
-#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
-#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
-#define PINT_PMSRC_SRC7_SHIFT                    (29U)
-#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
-
-/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
-#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
-#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
-#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
-#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
-#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
-#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
-#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
-#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
-#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
-#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
-#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
-#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
-#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
-#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
-#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
-#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
-#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
-#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
-#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
-#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
-#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
-#define PINT_PMCFG_CFG0_MASK                     (0x700U)
-#define PINT_PMCFG_CFG0_SHIFT                    (8U)
-#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
-#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
-#define PINT_PMCFG_CFG1_SHIFT                    (11U)
-#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
-#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
-#define PINT_PMCFG_CFG2_SHIFT                    (14U)
-#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
-#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
-#define PINT_PMCFG_CFG3_SHIFT                    (17U)
-#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
-#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
-#define PINT_PMCFG_CFG4_SHIFT                    (20U)
-#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
-#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
-#define PINT_PMCFG_CFG5_SHIFT                    (23U)
-#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
-#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
-#define PINT_PMCFG_CFG6_SHIFT                    (26U)
-#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
-#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
-#define PINT_PMCFG_CFG7_SHIFT                    (29U)
-#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
-
-
-/*!
- * @}
- */ /* end of group PINT_Register_Masks */
-
-
-/* PINT - Peripheral instance base addresses */
-/** Peripheral PINT base address */
-#define PINT_BASE                                (0x40004000u)
-/** Peripheral PINT base pointer */
-#define PINT                                     ((PINT_Type *)PINT_BASE)
-/** Array initializer of PINT peripheral base addresses */
-#define PINT_BASE_ADDRS                          { PINT_BASE }
-/** Array initializer of PINT peripheral base pointers */
-#define PINT_BASE_PTRS                           { PINT }
-/** Interrupt vectors for the PINT peripheral type */
-#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
-
-/*!
- * @}
- */ /* end of group PINT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- RIT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
- * @{
- */
-
-/** RIT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t COMPVAL;                           /**< Compare value LSB register, offset: 0x0 */
-  __IO uint32_t MASK;                              /**< Mask LSB register, offset: 0x4 */
-  __IO uint32_t CTRL;                              /**< Control register, offset: 0x8 */
-  __IO uint32_t COUNTER;                           /**< Counter LSB register, offset: 0xC */
-  __IO uint32_t COMPVAL_H;                         /**< Compare value MSB register, offset: 0x10 */
-  __IO uint32_t MASK_H;                            /**< Mask MSB register, offset: 0x14 */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t COUNTER_H;                         /**< Counter MSB register, offset: 0x1C */
-} RIT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- RIT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RIT_Register_Masks RIT Register Masks
- * @{
- */
-
-/*! @name COMPVAL - Compare value LSB register */
-#define RIT_COMPVAL_RICOMP_MASK                  (0xFFFFFFFFU)
-#define RIT_COMPVAL_RICOMP_SHIFT                 (0U)
-#define RIT_COMPVAL_RICOMP(x)                    (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
-
-/*! @name MASK - Mask LSB register */
-#define RIT_MASK_RIMASK_MASK                     (0xFFFFFFFFU)
-#define RIT_MASK_RIMASK_SHIFT                    (0U)
-#define RIT_MASK_RIMASK(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
-
-/*! @name CTRL - Control register */
-#define RIT_CTRL_RITINT_MASK                     (0x1U)
-#define RIT_CTRL_RITINT_SHIFT                    (0U)
-#define RIT_CTRL_RITINT(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
-#define RIT_CTRL_RITENCLR_MASK                   (0x2U)
-#define RIT_CTRL_RITENCLR_SHIFT                  (1U)
-#define RIT_CTRL_RITENCLR(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
-#define RIT_CTRL_RITENBR_MASK                    (0x4U)
-#define RIT_CTRL_RITENBR_SHIFT                   (2U)
-#define RIT_CTRL_RITENBR(x)                      (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
-#define RIT_CTRL_RITEN_MASK                      (0x8U)
-#define RIT_CTRL_RITEN_SHIFT                     (3U)
-#define RIT_CTRL_RITEN(x)                        (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
-
-/*! @name COUNTER - Counter LSB register */
-#define RIT_COUNTER_RICOUNTER_MASK               (0xFFFFFFFFU)
-#define RIT_COUNTER_RICOUNTER_SHIFT              (0U)
-#define RIT_COUNTER_RICOUNTER(x)                 (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
-
-/*! @name COMPVAL_H - Compare value MSB register */
-#define RIT_COMPVAL_H_RICOMP_MASK                (0xFFFFU)
-#define RIT_COMPVAL_H_RICOMP_SHIFT               (0U)
-#define RIT_COMPVAL_H_RICOMP(x)                  (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
-
-/*! @name MASK_H - Mask MSB register */
-#define RIT_MASK_H_RIMASK_MASK                   (0xFFFFU)
-#define RIT_MASK_H_RIMASK_SHIFT                  (0U)
-#define RIT_MASK_H_RIMASK(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
-
-/*! @name COUNTER_H - Counter MSB register */
-#define RIT_COUNTER_H_RICOUNTER_MASK             (0xFFFFU)
-#define RIT_COUNTER_H_RICOUNTER_SHIFT            (0U)
-#define RIT_COUNTER_H_RICOUNTER(x)               (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
-
-
-/*!
- * @}
- */ /* end of group RIT_Register_Masks */
-
-
-/* RIT - Peripheral instance base addresses */
-/** Peripheral RIT base address */
-#define RIT_BASE                                 (0x4002D000u)
-/** Peripheral RIT base pointer */
-#define RIT                                      ((RIT_Type *)RIT_BASE)
-/** Array initializer of RIT peripheral base addresses */
-#define RIT_BASE_ADDRS                           { RIT_BASE }
-/** Array initializer of RIT peripheral base pointers */
-#define RIT_BASE_PTRS                            { RIT }
-/** Interrupt vectors for the RIT peripheral type */
-#define RIT_IRQS                                 { RIT_IRQn }
-
-/*!
- * @}
- */ /* end of group RIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- RTC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
-  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
-  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
-  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
-       uint8_t RESERVED_0[48];
-  __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x40, array step: 0x4 */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- RTC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/*! @name CTRL - RTC control register */
-#define RTC_CTRL_SWRESET_MASK                    (0x1U)
-#define RTC_CTRL_SWRESET_SHIFT                   (0U)
-#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
-#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
-#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
-#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
-#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
-#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
-#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
-#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
-#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
-#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
-#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
-#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
-#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
-#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
-#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
-#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
-#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
-#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
-#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
-#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
-#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
-#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
-
-/*! @name MATCH - RTC match register */
-#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
-#define RTC_MATCH_MATVAL_SHIFT                   (0U)
-#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
-
-/*! @name COUNT - RTC counter register */
-#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
-#define RTC_COUNT_VAL_SHIFT                      (0U)
-#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
-
-/*! @name WAKE - High-resolution/wake-up timer control register */
-#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
-#define RTC_WAKE_VAL_SHIFT                       (0U)
-#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
-
-/*! @name GPREG - General Purpose register */
-#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
-#define RTC_GPREG_GPDATA_SHIFT                   (0U)
-#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
-
-/* The count of RTC_GPREG */
-#define RTC_GPREG_COUNT                          (8U)
-
-
-/*!
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE                                 (0x4002C000u)
-/** Peripheral RTC base pointer */
-#define RTC                                      ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS                           { RTC_BASE }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS                            { RTC }
-/** Interrupt vectors for the RTC peripheral type */
-#define RTC_IRQS                                 { RTC_IRQn }
-
-/*!
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SCT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
- * @{
- */
-
-/** SCT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
-  __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
-  __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
-  __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
-  __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
-  __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
-       uint8_t RESERVED_0[40];
-  __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
-  __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
-  __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
-  __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
-  __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
-  __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
-  __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
-  __IO uint32_t DMA0REQUEST;                       /**< SCT DMA request 0 register, offset: 0x5C */
-  __IO uint32_t DMA1REQUEST;                       /**< SCT DMA request 1 register, offset: 0x60 */
-       uint8_t RESERVED_1[140];
-  __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
-  __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
-  __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
-  __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
-  union {                                          /* offset: 0x100 */
-    __IO uint32_t SCTCAP[10];                        /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
-    __IO uint32_t SCTMATCH[10];                      /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
-  };
-       uint8_t RESERVED_2[216];
-  union {                                          /* offset: 0x200 */
-    __IO uint32_t SCTCAPCTRL[10];                    /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
-    __IO uint32_t SCTMATCHREL[10];                   /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
-  };
-       uint8_t RESERVED_3[216];
-  struct {                                         /* offset: 0x300, array step: 0x8 */
-    __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
-    __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
-  } EVENT[10];
-       uint8_t RESERVED_4[432];
-  struct {                                         /* offset: 0x500, array step: 0x8 */
-    __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
-    __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
-  } OUT[10];
-} SCT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SCT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SCT_Register_Masks SCT Register Masks
- * @{
- */
-
-/*! @name CONFIG - SCT configuration register */
-#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
-#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
-#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
-#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
-#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
-#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
-#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
-#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
-#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
-#define SCT_CONFIG_NORELAOD_L_MASK               (0x80U)
-#define SCT_CONFIG_NORELAOD_L_SHIFT              (7U)
-#define SCT_CONFIG_NORELAOD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
-#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
-#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
-#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
-#define SCT_CONFIG_INSYNC_MASK                   (0x1E00U)
-#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
-#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
-#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
-#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
-#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
-#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
-#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
-#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
-
-/*! @name CTRL - SCT control register */
-#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
-#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
-#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
-#define SCT_CTRL_STOP_L_MASK                     (0x2U)
-#define SCT_CTRL_STOP_L_SHIFT                    (1U)
-#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
-#define SCT_CTRL_HALT_L_MASK                     (0x4U)
-#define SCT_CTRL_HALT_L_SHIFT                    (2U)
-#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
-#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
-#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
-#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
-#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
-#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
-#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
-#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
-#define SCT_CTRL_PRE_L_SHIFT                     (5U)
-#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
-#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
-#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
-#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
-#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
-#define SCT_CTRL_STOP_H_SHIFT                    (17U)
-#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
-#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
-#define SCT_CTRL_HALT_H_SHIFT                    (18U)
-#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
-#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
-#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
-#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
-#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
-#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
-#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
-#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
-#define SCT_CTRL_PRE_H_SHIFT                     (21U)
-#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
-
-/*! @name LIMIT - SCT limit event select register */
-#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
-#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
-#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
-#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
-#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
-#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
-
-/*! @name HALT - SCT halt event select register */
-#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
-#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
-#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
-#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
-#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
-#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
-
-/*! @name STOP - SCT stop event select register */
-#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
-#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
-#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
-#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
-#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
-#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
-
-/*! @name START - SCT start event select register */
-#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
-#define SCT_START_STARTMSK_L_SHIFT               (0U)
-#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
-#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
-#define SCT_START_STARTMSK_H_SHIFT               (16U)
-#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
-
-/*! @name COUNT - SCT counter register */
-#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
-#define SCT_COUNT_CTR_L_SHIFT                    (0U)
-#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
-#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
-#define SCT_COUNT_CTR_H_SHIFT                    (16U)
-#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
-
-/*! @name STATE - SCT state register */
-#define SCT_STATE_STATE_L_MASK                   (0x1FU)
-#define SCT_STATE_STATE_L_SHIFT                  (0U)
-#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
-#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
-#define SCT_STATE_STATE_H_SHIFT                  (16U)
-#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
-
-/*! @name INPUT - SCT input register */
-#define SCT_INPUT_AIN0_MASK                      (0x1U)
-#define SCT_INPUT_AIN0_SHIFT                     (0U)
-#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
-#define SCT_INPUT_AIN1_MASK                      (0x2U)
-#define SCT_INPUT_AIN1_SHIFT                     (1U)
-#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
-#define SCT_INPUT_AIN2_MASK                      (0x4U)
-#define SCT_INPUT_AIN2_SHIFT                     (2U)
-#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
-#define SCT_INPUT_AIN3_MASK                      (0x8U)
-#define SCT_INPUT_AIN3_SHIFT                     (3U)
-#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
-#define SCT_INPUT_AIN4_MASK                      (0x10U)
-#define SCT_INPUT_AIN4_SHIFT                     (4U)
-#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
-#define SCT_INPUT_AIN5_MASK                      (0x20U)
-#define SCT_INPUT_AIN5_SHIFT                     (5U)
-#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
-#define SCT_INPUT_AIN6_MASK                      (0x40U)
-#define SCT_INPUT_AIN6_SHIFT                     (6U)
-#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
-#define SCT_INPUT_AIN7_MASK                      (0x80U)
-#define SCT_INPUT_AIN7_SHIFT                     (7U)
-#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
-#define SCT_INPUT_AIN8_MASK                      (0x100U)
-#define SCT_INPUT_AIN8_SHIFT                     (8U)
-#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
-#define SCT_INPUT_AIN9_MASK                      (0x200U)
-#define SCT_INPUT_AIN9_SHIFT                     (9U)
-#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
-#define SCT_INPUT_AIN10_MASK                     (0x400U)
-#define SCT_INPUT_AIN10_SHIFT                    (10U)
-#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
-#define SCT_INPUT_AIN11_MASK                     (0x800U)
-#define SCT_INPUT_AIN11_SHIFT                    (11U)
-#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
-#define SCT_INPUT_AIN12_MASK                     (0x1000U)
-#define SCT_INPUT_AIN12_SHIFT                    (12U)
-#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
-#define SCT_INPUT_AIN13_MASK                     (0x2000U)
-#define SCT_INPUT_AIN13_SHIFT                    (13U)
-#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
-#define SCT_INPUT_AIN14_MASK                     (0x4000U)
-#define SCT_INPUT_AIN14_SHIFT                    (14U)
-#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
-#define SCT_INPUT_AIN15_MASK                     (0x8000U)
-#define SCT_INPUT_AIN15_SHIFT                    (15U)
-#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
-#define SCT_INPUT_SIN0_MASK                      (0x10000U)
-#define SCT_INPUT_SIN0_SHIFT                     (16U)
-#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
-#define SCT_INPUT_SIN1_MASK                      (0x20000U)
-#define SCT_INPUT_SIN1_SHIFT                     (17U)
-#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
-#define SCT_INPUT_SIN2_MASK                      (0x40000U)
-#define SCT_INPUT_SIN2_SHIFT                     (18U)
-#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
-#define SCT_INPUT_SIN3_MASK                      (0x80000U)
-#define SCT_INPUT_SIN3_SHIFT                     (19U)
-#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
-#define SCT_INPUT_SIN4_MASK                      (0x100000U)
-#define SCT_INPUT_SIN4_SHIFT                     (20U)
-#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
-#define SCT_INPUT_SIN5_MASK                      (0x200000U)
-#define SCT_INPUT_SIN5_SHIFT                     (21U)
-#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
-#define SCT_INPUT_SIN6_MASK                      (0x400000U)
-#define SCT_INPUT_SIN6_SHIFT                     (22U)
-#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
-#define SCT_INPUT_SIN7_MASK                      (0x800000U)
-#define SCT_INPUT_SIN7_SHIFT                     (23U)
-#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
-#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
-#define SCT_INPUT_SIN8_SHIFT                     (24U)
-#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
-#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
-#define SCT_INPUT_SIN9_SHIFT                     (25U)
-#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
-#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
-#define SCT_INPUT_SIN10_SHIFT                    (26U)
-#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
-#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
-#define SCT_INPUT_SIN11_SHIFT                    (27U)
-#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
-#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
-#define SCT_INPUT_SIN12_SHIFT                    (28U)
-#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
-#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
-#define SCT_INPUT_SIN13_SHIFT                    (29U)
-#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
-#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
-#define SCT_INPUT_SIN14_SHIFT                    (30U)
-#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
-#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
-#define SCT_INPUT_SIN15_SHIFT                    (31U)
-#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
-
-/*! @name REGMODE - SCT match/capture mode register */
-#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
-#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
-#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
-#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
-#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
-#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
-
-/*! @name OUTPUT - SCT output register */
-#define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
-#define SCT_OUTPUT_OUT_SHIFT                     (0U)
-#define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
-
-/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
-#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
-#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
-#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
-#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
-#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
-#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
-#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
-#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
-#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
-#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
-#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
-#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
-#define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
-#define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
-#define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
-#define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
-#define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
-#define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
-
-/*! @name RES - SCT conflict resolution register */
-#define SCT_RES_O0RES_MASK                       (0x3U)
-#define SCT_RES_O0RES_SHIFT                      (0U)
-#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
-#define SCT_RES_O1RES_MASK                       (0xCU)
-#define SCT_RES_O1RES_SHIFT                      (2U)
-#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
-#define SCT_RES_O2RES_MASK                       (0x30U)
-#define SCT_RES_O2RES_SHIFT                      (4U)
-#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
-#define SCT_RES_O3RES_MASK                       (0xC0U)
-#define SCT_RES_O3RES_SHIFT                      (6U)
-#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
-#define SCT_RES_O4RES_MASK                       (0x300U)
-#define SCT_RES_O4RES_SHIFT                      (8U)
-#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
-#define SCT_RES_O5RES_MASK                       (0xC00U)
-#define SCT_RES_O5RES_SHIFT                      (10U)
-#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
-#define SCT_RES_O6RES_MASK                       (0x3000U)
-#define SCT_RES_O6RES_SHIFT                      (12U)
-#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
-#define SCT_RES_O7RES_MASK                       (0xC000U)
-#define SCT_RES_O7RES_SHIFT                      (14U)
-#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
-#define SCT_RES_O8RES_MASK                       (0x30000U)
-#define SCT_RES_O8RES_SHIFT                      (16U)
-#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
-#define SCT_RES_O9RES_MASK                       (0xC0000U)
-#define SCT_RES_O9RES_SHIFT                      (18U)
-#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
-#define SCT_RES_O10RES_MASK                      (0x300000U)
-#define SCT_RES_O10RES_SHIFT                     (20U)
-#define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
-#define SCT_RES_O11RES_MASK                      (0xC00000U)
-#define SCT_RES_O11RES_SHIFT                     (22U)
-#define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
-#define SCT_RES_O12RES_MASK                      (0x3000000U)
-#define SCT_RES_O12RES_SHIFT                     (24U)
-#define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
-#define SCT_RES_O13RES_MASK                      (0xC000000U)
-#define SCT_RES_O13RES_SHIFT                     (26U)
-#define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
-#define SCT_RES_O14RES_MASK                      (0x30000000U)
-#define SCT_RES_O14RES_SHIFT                     (28U)
-#define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
-#define SCT_RES_O15RES_MASK                      (0xC0000000U)
-#define SCT_RES_O15RES_SHIFT                     (30U)
-#define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
-
-/*! @name DMA0REQUEST - SCT DMA request 0 register */
-#define SCT_DMA0REQUEST_DEV_0_MASK               (0xFFFFU)
-#define SCT_DMA0REQUEST_DEV_0_SHIFT              (0U)
-#define SCT_DMA0REQUEST_DEV_0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
-#define SCT_DMA0REQUEST_DRL0_MASK                (0x40000000U)
-#define SCT_DMA0REQUEST_DRL0_SHIFT               (30U)
-#define SCT_DMA0REQUEST_DRL0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
-#define SCT_DMA0REQUEST_DRQ0_MASK                (0x80000000U)
-#define SCT_DMA0REQUEST_DRQ0_SHIFT               (31U)
-#define SCT_DMA0REQUEST_DRQ0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
-
-/*! @name DMA1REQUEST - SCT DMA request 1 register */
-#define SCT_DMA1REQUEST_DEV_1_MASK               (0xFFFFU)
-#define SCT_DMA1REQUEST_DEV_1_SHIFT              (0U)
-#define SCT_DMA1REQUEST_DEV_1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
-#define SCT_DMA1REQUEST_DRL1_MASK                (0x40000000U)
-#define SCT_DMA1REQUEST_DRL1_SHIFT               (30U)
-#define SCT_DMA1REQUEST_DRL1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
-#define SCT_DMA1REQUEST_DRQ1_MASK                (0x80000000U)
-#define SCT_DMA1REQUEST_DRQ1_SHIFT               (31U)
-#define SCT_DMA1REQUEST_DRQ1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
-
-/*! @name EVEN - SCT event interrupt enable register */
-#define SCT_EVEN_IEN_MASK                        (0xFFFFU)
-#define SCT_EVEN_IEN_SHIFT                       (0U)
-#define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
-
-/*! @name EVFLAG - SCT event flag register */
-#define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
-#define SCT_EVFLAG_FLAG_SHIFT                    (0U)
-#define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
-
-/*! @name CONEN - SCT conflict interrupt enable register */
-#define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
-#define SCT_CONEN_NCEN_SHIFT                     (0U)
-#define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
-
-/*! @name CONFLAG - SCT conflict flag register */
-#define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
-#define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
-#define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
-#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
-#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
-#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
-#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
-#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
-#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
-
-/*! @name SCTCAP - SCT capture register of capture channel */
-#define SCT_SCTCAP_CAPn_L_MASK                   (0xFFFFU)
-#define SCT_SCTCAP_CAPn_L_SHIFT                  (0U)
-#define SCT_SCTCAP_CAPn_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
-#define SCT_SCTCAP_CAPn_H_MASK                   (0xFFFF0000U)
-#define SCT_SCTCAP_CAPn_H_SHIFT                  (16U)
-#define SCT_SCTCAP_CAPn_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
-
-/* The count of SCT_SCTCAP */
-#define SCT_SCTCAP_COUNT                         (10U)
-
-/*! @name SCTMATCH - SCT match value register of match channels */
-#define SCT_SCTMATCH_MATCHn_L_MASK               (0xFFFFU)
-#define SCT_SCTMATCH_MATCHn_L_SHIFT              (0U)
-#define SCT_SCTMATCH_MATCHn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
-#define SCT_SCTMATCH_MATCHn_H_MASK               (0xFFFF0000U)
-#define SCT_SCTMATCH_MATCHn_H_SHIFT              (16U)
-#define SCT_SCTMATCH_MATCHn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
-
-/* The count of SCT_SCTMATCH */
-#define SCT_SCTMATCH_COUNT                       (10U)
-
-/*! @name SCTCAPCTRL - SCT capture control register */
-#define SCT_SCTCAPCTRL_CAPCONn_L_MASK            (0xFFFFU)
-#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT           (0U)
-#define SCT_SCTCAPCTRL_CAPCONn_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
-#define SCT_SCTCAPCTRL_CAPCONn_H_MASK            (0xFFFF0000U)
-#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT           (16U)
-#define SCT_SCTCAPCTRL_CAPCONn_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
-
-/* The count of SCT_SCTCAPCTRL */
-#define SCT_SCTCAPCTRL_COUNT                     (10U)
-
-/*! @name SCTMATCHREL - SCT match reload value register */
-#define SCT_SCTMATCHREL_RELOADn_L_MASK           (0xFFFFU)
-#define SCT_SCTMATCHREL_RELOADn_L_SHIFT          (0U)
-#define SCT_SCTMATCHREL_RELOADn_L(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
-#define SCT_SCTMATCHREL_RELOADn_H_MASK           (0xFFFF0000U)
-#define SCT_SCTMATCHREL_RELOADn_H_SHIFT          (16U)
-#define SCT_SCTMATCHREL_RELOADn_H(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
-
-/* The count of SCT_SCTMATCHREL */
-#define SCT_SCTMATCHREL_COUNT                    (10U)
-
-/*! @name EVENT_STATE - SCT event state register 0 */
-#define SCT_EVENT_STATE_STATEMSKn_MASK           (0xFFFFU)
-#define SCT_EVENT_STATE_STATEMSKn_SHIFT          (0U)
-#define SCT_EVENT_STATE_STATEMSKn(x)             (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
-
-/* The count of SCT_EVENT_STATE */
-#define SCT_EVENT_STATE_COUNT                    (10U)
-
-/*! @name EVENT_CTRL - SCT event control register 0 */
-#define SCT_EVENT_CTRL_MATCHSEL_MASK             (0xFU)
-#define SCT_EVENT_CTRL_MATCHSEL_SHIFT            (0U)
-#define SCT_EVENT_CTRL_MATCHSEL(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
-#define SCT_EVENT_CTRL_HEVENT_MASK               (0x10U)
-#define SCT_EVENT_CTRL_HEVENT_SHIFT              (4U)
-#define SCT_EVENT_CTRL_HEVENT(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
-#define SCT_EVENT_CTRL_OUTSEL_MASK               (0x20U)
-#define SCT_EVENT_CTRL_OUTSEL_SHIFT              (5U)
-#define SCT_EVENT_CTRL_OUTSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
-#define SCT_EVENT_CTRL_IOSEL_MASK                (0x3C0U)
-#define SCT_EVENT_CTRL_IOSEL_SHIFT               (6U)
-#define SCT_EVENT_CTRL_IOSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
-#define SCT_EVENT_CTRL_IOCOND_MASK               (0xC00U)
-#define SCT_EVENT_CTRL_IOCOND_SHIFT              (10U)
-#define SCT_EVENT_CTRL_IOCOND(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
-#define SCT_EVENT_CTRL_COMBMODE_MASK             (0x3000U)
-#define SCT_EVENT_CTRL_COMBMODE_SHIFT            (12U)
-#define SCT_EVENT_CTRL_COMBMODE(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
-#define SCT_EVENT_CTRL_STATELD_MASK              (0x4000U)
-#define SCT_EVENT_CTRL_STATELD_SHIFT             (14U)
-#define SCT_EVENT_CTRL_STATELD(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
-#define SCT_EVENT_CTRL_STATEV_MASK               (0xF8000U)
-#define SCT_EVENT_CTRL_STATEV_SHIFT              (15U)
-#define SCT_EVENT_CTRL_STATEV(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
-#define SCT_EVENT_CTRL_MATCHMEM_MASK             (0x100000U)
-#define SCT_EVENT_CTRL_MATCHMEM_SHIFT            (20U)
-#define SCT_EVENT_CTRL_MATCHMEM(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
-#define SCT_EVENT_CTRL_DIRECTION_MASK            (0x600000U)
-#define SCT_EVENT_CTRL_DIRECTION_SHIFT           (21U)
-#define SCT_EVENT_CTRL_DIRECTION(x)              (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
-
-/* The count of SCT_EVENT_CTRL */
-#define SCT_EVENT_CTRL_COUNT                     (10U)
-
-/*! @name OUT_SET - SCT output 0 set register */
-#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
-#define SCT_OUT_SET_SET_SHIFT                    (0U)
-#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
-
-/* The count of SCT_OUT_SET */
-#define SCT_OUT_SET_COUNT                        (10U)
-
-/*! @name OUT_CLR - SCT output 0 clear register */
-#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
-#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
-#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
-
-/* The count of SCT_OUT_CLR */
-#define SCT_OUT_CLR_COUNT                        (10U)
-
-
-/*!
- * @}
- */ /* end of group SCT_Register_Masks */
-
-
-/* SCT - Peripheral instance base addresses */
-/** Peripheral SCT0 base address */
-#define SCT0_BASE                                (0x40085000u)
-/** Peripheral SCT0 base pointer */
-#define SCT0                                     ((SCT_Type *)SCT0_BASE)
-/** Array initializer of SCT peripheral base addresses */
-#define SCT_BASE_ADDRS                           { SCT0_BASE }
-/** Array initializer of SCT peripheral base pointers */
-#define SCT_BASE_PTRS                            { SCT0 }
-/** Interrupt vectors for the SCT peripheral type */
-#define SCT_IRQS                                 { SCT0_IRQn }
-
-/*!
- * @}
- */ /* end of group SCT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SDIF Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
- * @{
- */
-
-/** SDIF - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
-  __IO uint32_t PWREN;                             /**< Power Enable register, offset: 0x4 */
-  __IO uint32_t CLKDIV;                            /**< Clock Divider register, offset: 0x8 */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t CLKENA;                            /**< Clock Enable register, offset: 0x10 */
-  __IO uint32_t TMOUT;                             /**< Time-out register, offset: 0x14 */
-  __IO uint32_t CTYPE;                             /**< Card Type register, offset: 0x18 */
-  __IO uint32_t BLKSIZ;                            /**< Block Size register, offset: 0x1C */
-  __IO uint32_t BYTCNT;                            /**< Byte Count register, offset: 0x20 */
-  __IO uint32_t INTMASK;                           /**< Interrupt Mask register, offset: 0x24 */
-  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x28 */
-  __IO uint32_t CMD;                               /**< Command register, offset: 0x2C */
-  __IO uint32_t RESP[4];                           /**< Response register, array offset: 0x30, array step: 0x4 */
-  __IO uint32_t MINTSTS;                           /**< Masked Interrupt Status register, offset: 0x40 */
-  __IO uint32_t RINTSTS;                           /**< Raw Interrupt Status register, offset: 0x44 */
-  __IO uint32_t STATUS;                            /**< Status register, offset: 0x48 */
-  __IO uint32_t FIFOTH;                            /**< FIFO Threshold Watermark register, offset: 0x4C */
-  __IO uint32_t CDETECT;                           /**< Card Detect register, offset: 0x50 */
-  __IO uint32_t WRTPRT;                            /**< Write Protect register, offset: 0x54 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t TCBCNT;                            /**< Transferred CIU Card Byte Count register, offset: 0x5C */
-  __IO uint32_t TBBCNT;                            /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
-  __IO uint32_t DEBNCE;                            /**< Debounce Count register, offset: 0x64 */
-       uint8_t RESERVED_2[16];
-  __IO uint32_t RST_N;                             /**< Hardware Reset, offset: 0x78 */
-       uint8_t RESERVED_3[4];
-  __IO uint32_t BMOD;                              /**< Bus Mode register, offset: 0x80 */
-  __IO uint32_t PLDMND;                            /**< Poll Demand register, offset: 0x84 */
-  __IO uint32_t DBADDR;                            /**< Descriptor List Base Address register, offset: 0x88 */
-  __IO uint32_t IDSTS;                             /**< Internal DMAC Status register, offset: 0x8C */
-  __IO uint32_t IDINTEN;                           /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
-  __IO uint32_t DSCADDR;                           /**< Current Host Descriptor Address register, offset: 0x94 */
-  __IO uint32_t BUFADDR;                           /**< Current Buffer Descriptor Address register, offset: 0x98 */
-       uint8_t RESERVED_4[100];
-  __IO uint32_t CARDTHRCTL;                        /**< Card Threshold Control, offset: 0x100 */
-  __IO uint32_t BACKENDPWR;                        /**< Power control, offset: 0x104 */
-       uint8_t RESERVED_5[248];
-  __IO uint32_t FIFO[64];                          /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
-} SDIF_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SDIF Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDIF_Register_Masks SDIF Register Masks
- * @{
- */
-
-/*! @name CTRL - Control register */
-#define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
-#define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
-#define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
-#define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
-#define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
-#define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
-#define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
-#define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
-#define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
-#define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
-#define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
-#define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
-#define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
-#define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
-#define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
-#define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
-#define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
-#define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
-#define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
-#define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
-#define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
-#define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
-#define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
-#define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
-#define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
-
-/*! @name PWREN - Power Enable register */
-#define SDIF_PWREN_POWER_ENABLE_MASK             (0x1U)
-#define SDIF_PWREN_POWER_ENABLE_SHIFT            (0U)
-#define SDIF_PWREN_POWER_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
-
-/*! @name CLKDIV - Clock Divider register */
-#define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
-#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
-#define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
-
-/*! @name CLKENA - Clock Enable register */
-#define SDIF_CLKENA_CCLK_ENABLE_MASK             (0x1U)
-#define SDIF_CLKENA_CCLK_ENABLE_SHIFT            (0U)
-#define SDIF_CLKENA_CCLK_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
-#define SDIF_CLKENA_CCLK_LOW_POWER_MASK          (0x10000U)
-#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT         (16U)
-#define SDIF_CLKENA_CCLK_LOW_POWER(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
-
-/*! @name TMOUT - Time-out register */
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
-#define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
-#define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
-#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
-#define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
-
-/*! @name CTYPE - Card Type register */
-#define SDIF_CTYPE_CARD_WIDTH0_MASK              (0x1U)
-#define SDIF_CTYPE_CARD_WIDTH0_SHIFT             (0U)
-#define SDIF_CTYPE_CARD_WIDTH0(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
-#define SDIF_CTYPE_CARD_WIDTH1_MASK              (0x10000U)
-#define SDIF_CTYPE_CARD_WIDTH1_SHIFT             (16U)
-#define SDIF_CTYPE_CARD_WIDTH1(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
-
-/*! @name BLKSIZ - Block Size register */
-#define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
-#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
-#define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
-
-/*! @name BYTCNT - Byte Count register */
-#define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
-#define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
-#define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
-
-/*! @name INTMASK - Interrupt Mask register */
-#define SDIF_INTMASK_CDET_MASK                   (0x1U)
-#define SDIF_INTMASK_CDET_SHIFT                  (0U)
-#define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
-#define SDIF_INTMASK_RE_MASK                     (0x2U)
-#define SDIF_INTMASK_RE_SHIFT                    (1U)
-#define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
-#define SDIF_INTMASK_CDONE_MASK                  (0x4U)
-#define SDIF_INTMASK_CDONE_SHIFT                 (2U)
-#define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
-#define SDIF_INTMASK_DTO_MASK                    (0x8U)
-#define SDIF_INTMASK_DTO_SHIFT                   (3U)
-#define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
-#define SDIF_INTMASK_TXDR_MASK                   (0x10U)
-#define SDIF_INTMASK_TXDR_SHIFT                  (4U)
-#define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
-#define SDIF_INTMASK_RXDR_MASK                   (0x20U)
-#define SDIF_INTMASK_RXDR_SHIFT                  (5U)
-#define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
-#define SDIF_INTMASK_RCRC_MASK                   (0x40U)
-#define SDIF_INTMASK_RCRC_SHIFT                  (6U)
-#define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
-#define SDIF_INTMASK_DCRC_MASK                   (0x80U)
-#define SDIF_INTMASK_DCRC_SHIFT                  (7U)
-#define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
-#define SDIF_INTMASK_RTO_MASK                    (0x100U)
-#define SDIF_INTMASK_RTO_SHIFT                   (8U)
-#define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
-#define SDIF_INTMASK_DRTO_MASK                   (0x200U)
-#define SDIF_INTMASK_DRTO_SHIFT                  (9U)
-#define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
-#define SDIF_INTMASK_HTO_MASK                    (0x400U)
-#define SDIF_INTMASK_HTO_SHIFT                   (10U)
-#define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
-#define SDIF_INTMASK_FRUN_MASK                   (0x800U)
-#define SDIF_INTMASK_FRUN_SHIFT                  (11U)
-#define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
-#define SDIF_INTMASK_HLE_MASK                    (0x1000U)
-#define SDIF_INTMASK_HLE_SHIFT                   (12U)
-#define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
-#define SDIF_INTMASK_SBE_MASK                    (0x2000U)
-#define SDIF_INTMASK_SBE_SHIFT                   (13U)
-#define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
-#define SDIF_INTMASK_ACD_MASK                    (0x4000U)
-#define SDIF_INTMASK_ACD_SHIFT                   (14U)
-#define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
-#define SDIF_INTMASK_EBE_MASK                    (0x8000U)
-#define SDIF_INTMASK_EBE_SHIFT                   (15U)
-#define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
-#define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
-#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
-#define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
-
-/*! @name CMDARG - Command Argument register */
-#define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
-#define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
-#define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
-
-/*! @name CMD - Command register */
-#define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
-#define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
-#define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
-#define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
-#define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
-#define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
-#define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
-#define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
-#define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
-#define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
-#define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
-#define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
-#define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
-#define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
-#define SDIF_CMD_READ_WRITE_SHIFT                (10U)
-#define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
-#define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
-#define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
-#define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
-#define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
-#define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
-#define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
-#define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
-#define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
-#define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
-#define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
-#define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
-#define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
-#define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
-#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
-#define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
-#define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
-#define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
-#define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
-#define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
-#define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
-#define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
-#define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
-#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
-#define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
-#define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
-#define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
-#define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
-#define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
-#define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
-#define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
-#define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
-#define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
-#define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
-#define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
-#define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
-#define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
-#define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
-#define SDIF_CMD_START_CMD_SHIFT                 (31U)
-#define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
-
-/*! @name RESP - Response register */
-#define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
-#define SDIF_RESP_RESPONSE_SHIFT                 (0U)
-#define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
-
-/* The count of SDIF_RESP */
-#define SDIF_RESP_COUNT                          (4U)
-
-/*! @name MINTSTS - Masked Interrupt Status register */
-#define SDIF_MINTSTS_CDET_MASK                   (0x1U)
-#define SDIF_MINTSTS_CDET_SHIFT                  (0U)
-#define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
-#define SDIF_MINTSTS_RE_MASK                     (0x2U)
-#define SDIF_MINTSTS_RE_SHIFT                    (1U)
-#define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
-#define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
-#define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
-#define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
-#define SDIF_MINTSTS_DTO_MASK                    (0x8U)
-#define SDIF_MINTSTS_DTO_SHIFT                   (3U)
-#define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
-#define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
-#define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
-#define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
-#define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
-#define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
-#define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
-#define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
-#define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
-#define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
-#define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
-#define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
-#define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
-#define SDIF_MINTSTS_RTO_MASK                    (0x100U)
-#define SDIF_MINTSTS_RTO_SHIFT                   (8U)
-#define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
-#define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
-#define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
-#define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
-#define SDIF_MINTSTS_HTO_MASK                    (0x400U)
-#define SDIF_MINTSTS_HTO_SHIFT                   (10U)
-#define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
-#define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
-#define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
-#define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
-#define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
-#define SDIF_MINTSTS_HLE_SHIFT                   (12U)
-#define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
-#define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
-#define SDIF_MINTSTS_SBE_SHIFT                   (13U)
-#define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
-#define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
-#define SDIF_MINTSTS_ACD_SHIFT                   (14U)
-#define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
-#define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
-#define SDIF_MINTSTS_EBE_SHIFT                   (15U)
-#define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
-#define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
-
-/*! @name RINTSTS - Raw Interrupt Status register */
-#define SDIF_RINTSTS_CDET_MASK                   (0x1U)
-#define SDIF_RINTSTS_CDET_SHIFT                  (0U)
-#define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
-#define SDIF_RINTSTS_RE_MASK                     (0x2U)
-#define SDIF_RINTSTS_RE_SHIFT                    (1U)
-#define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
-#define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
-#define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
-#define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
-#define SDIF_RINTSTS_DTO_MASK                    (0x8U)
-#define SDIF_RINTSTS_DTO_SHIFT                   (3U)
-#define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
-#define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
-#define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
-#define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
-#define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
-#define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
-#define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
-#define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
-#define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
-#define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
-#define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
-#define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
-#define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
-#define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
-#define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
-#define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
-#define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
-#define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
-#define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
-#define SDIF_RINTSTS_HTO_MASK                    (0x400U)
-#define SDIF_RINTSTS_HTO_SHIFT                   (10U)
-#define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
-#define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
-#define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
-#define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
-#define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
-#define SDIF_RINTSTS_HLE_SHIFT                   (12U)
-#define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
-#define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
-#define SDIF_RINTSTS_SBE_SHIFT                   (13U)
-#define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
-#define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
-#define SDIF_RINTSTS_ACD_SHIFT                   (14U)
-#define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
-#define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
-#define SDIF_RINTSTS_EBE_SHIFT                   (15U)
-#define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
-#define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
-
-/*! @name STATUS - Status register */
-#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
-#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
-#define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
-#define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
-#define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
-#define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
-#define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
-#define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
-#define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
-#define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
-#define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
-#define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
-#define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
-#define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
-#define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
-#define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
-#define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
-#define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
-#define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
-#define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
-#define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
-#define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
-#define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
-#define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
-#define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
-#define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
-#define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
-#define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
-#define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
-#define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
-
-/*! @name FIFOTH - FIFO Threshold Watermark register */
-#define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
-#define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
-#define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
-#define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
-#define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
-#define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
-#define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
-#define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
-#define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
-
-/*! @name CDETECT - Card Detect register */
-#define SDIF_CDETECT_CARD_DETECT_MASK            (0x1U)
-#define SDIF_CDETECT_CARD_DETECT_SHIFT           (0U)
-#define SDIF_CDETECT_CARD_DETECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
-
-/*! @name WRTPRT - Write Protect register */
-#define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
-#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
-#define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
-
-/*! @name TCBCNT - Transferred CIU Card Byte Count register */
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
-
-/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
-
-/*! @name DEBNCE - Debounce Count register */
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
-#define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
-
-/*! @name RST_N - Hardware Reset */
-#define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
-#define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
-#define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
-
-/*! @name BMOD - Bus Mode register */
-#define SDIF_BMOD_SWR_MASK                       (0x1U)
-#define SDIF_BMOD_SWR_SHIFT                      (0U)
-#define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
-#define SDIF_BMOD_FB_MASK                        (0x2U)
-#define SDIF_BMOD_FB_SHIFT                       (1U)
-#define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
-#define SDIF_BMOD_DSL_MASK                       (0x7CU)
-#define SDIF_BMOD_DSL_SHIFT                      (2U)
-#define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
-#define SDIF_BMOD_DE_MASK                        (0x80U)
-#define SDIF_BMOD_DE_SHIFT                       (7U)
-#define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
-#define SDIF_BMOD_PBL_MASK                       (0x700U)
-#define SDIF_BMOD_PBL_SHIFT                      (8U)
-#define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
-
-/*! @name PLDMND - Poll Demand register */
-#define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
-#define SDIF_PLDMND_PD_SHIFT                     (0U)
-#define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
-
-/*! @name DBADDR - Descriptor List Base Address register */
-#define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
-#define SDIF_DBADDR_SDL_SHIFT                    (0U)
-#define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
-
-/*! @name IDSTS - Internal DMAC Status register */
-#define SDIF_IDSTS_TI_MASK                       (0x1U)
-#define SDIF_IDSTS_TI_SHIFT                      (0U)
-#define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
-#define SDIF_IDSTS_RI_MASK                       (0x2U)
-#define SDIF_IDSTS_RI_SHIFT                      (1U)
-#define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
-#define SDIF_IDSTS_FBE_MASK                      (0x4U)
-#define SDIF_IDSTS_FBE_SHIFT                     (2U)
-#define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
-#define SDIF_IDSTS_DU_MASK                       (0x10U)
-#define SDIF_IDSTS_DU_SHIFT                      (4U)
-#define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
-#define SDIF_IDSTS_CES_MASK                      (0x20U)
-#define SDIF_IDSTS_CES_SHIFT                     (5U)
-#define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
-#define SDIF_IDSTS_NIS_MASK                      (0x100U)
-#define SDIF_IDSTS_NIS_SHIFT                     (8U)
-#define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
-#define SDIF_IDSTS_AIS_MASK                      (0x200U)
-#define SDIF_IDSTS_AIS_SHIFT                     (9U)
-#define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
-#define SDIF_IDSTS_EB_MASK                       (0x1C00U)
-#define SDIF_IDSTS_EB_SHIFT                      (10U)
-#define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
-#define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
-#define SDIF_IDSTS_FSM_SHIFT                     (13U)
-#define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
-
-/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
-#define SDIF_IDINTEN_TI_MASK                     (0x1U)
-#define SDIF_IDINTEN_TI_SHIFT                    (0U)
-#define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
-#define SDIF_IDINTEN_RI_MASK                     (0x2U)
-#define SDIF_IDINTEN_RI_SHIFT                    (1U)
-#define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
-#define SDIF_IDINTEN_FBE_MASK                    (0x4U)
-#define SDIF_IDINTEN_FBE_SHIFT                   (2U)
-#define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
-#define SDIF_IDINTEN_DU_MASK                     (0x10U)
-#define SDIF_IDINTEN_DU_SHIFT                    (4U)
-#define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
-#define SDIF_IDINTEN_CES_MASK                    (0x20U)
-#define SDIF_IDINTEN_CES_SHIFT                   (5U)
-#define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
-#define SDIF_IDINTEN_NIS_MASK                    (0x100U)
-#define SDIF_IDINTEN_NIS_SHIFT                   (8U)
-#define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
-#define SDIF_IDINTEN_AIS_MASK                    (0x200U)
-#define SDIF_IDINTEN_AIS_SHIFT                   (9U)
-#define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
-
-/*! @name DSCADDR - Current Host Descriptor Address register */
-#define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
-#define SDIF_DSCADDR_HDA_SHIFT                   (0U)
-#define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
-
-/*! @name BUFADDR - Current Buffer Descriptor Address register */
-#define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
-#define SDIF_BUFADDR_HBA_SHIFT                   (0U)
-#define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
-
-/*! @name CARDTHRCTL - Card Threshold Control */
-#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
-#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
-#define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
-
-/*! @name BACKENDPWR - Power control */
-#define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
-#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
-#define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
-
-/*! @name FIFO - SDIF FIFO */
-#define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
-#define SDIF_FIFO_DATA_SHIFT                     (0U)
-#define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
-
-/* The count of SDIF_FIFO */
-#define SDIF_FIFO_COUNT                          (64U)
-
-
-/*!
- * @}
- */ /* end of group SDIF_Register_Masks */
-
-
-/* SDIF - Peripheral instance base addresses */
-/** Peripheral SDIF base address */
-#define SDIF_BASE                                (0x4009B000u)
-/** Peripheral SDIF base pointer */
-#define SDIF                                     ((SDIF_Type *)SDIF_BASE)
-/** Array initializer of SDIF peripheral base addresses */
-#define SDIF_BASE_ADDRS                          { SDIF_BASE }
-/** Array initializer of SDIF peripheral base pointers */
-#define SDIF_BASE_PTRS                           { SDIF }
-/** Interrupt vectors for the SDIF peripheral type */
-#define SDIF_IRQS                                { SDIO_IRQn }
-
-/*!
- * @}
- */ /* end of group SDIF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SMARTCARD Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
- * @{
- */
-
-/** SMARTCARD - Register Layout Typedef */
-typedef struct {
-  union {                                          /* offset: 0x0 */
-    __IO uint32_t DLL;                               /**< Divisor Latch LSB, offset: 0x0 */
-    __I  uint32_t RBR;                               /**< Receiver Buffer Register, offset: 0x0 */
-    __O  uint32_t THR;                               /**< Transmit Holding Register, offset: 0x0 */
-  };
-  union {                                          /* offset: 0x4 */
-    __IO uint32_t DLM;                               /**< Divisor Latch MSB, offset: 0x4 */
-    __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x4 */
-  };
-  union {                                          /* offset: 0x8 */
-    __O  uint32_t FCR;                               /**< FIFO Control Register, offset: 0x8 */
-    __I  uint32_t IIR;                               /**< Interrupt ID Register, offset: 0x8 */
-  };
-  __IO uint32_t LCR;                               /**< Line Control Register, offset: 0xC */
-       uint8_t RESERVED_0[4];
-  __I  uint32_t LSR;                               /**< Line Status Register, offset: 0x14 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t SCR;                               /**< Scratch Pad Register, offset: 0x1C */
-       uint8_t RESERVED_2[12];
-  __IO uint32_t OSR;                               /**< Oversampling register, offset: 0x2C */
-       uint8_t RESERVED_3[24];
-  __IO uint32_t SCICTRL;                           /**< Smart Card Interface control register, offset: 0x48 */
-} SMARTCARD_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SMARTCARD Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
- * @{
- */
-
-/*! @name DLL - Divisor Latch LSB */
-#define SMARTCARD_DLL_DLLSB_MASK                 (0xFFU)
-#define SMARTCARD_DLL_DLLSB_SHIFT                (0U)
-#define SMARTCARD_DLL_DLLSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
-
-/*! @name RBR - Receiver Buffer Register */
-#define SMARTCARD_RBR_RBR_MASK                   (0xFFU)
-#define SMARTCARD_RBR_RBR_SHIFT                  (0U)
-#define SMARTCARD_RBR_RBR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
-
-/*! @name THR - Transmit Holding Register */
-#define SMARTCARD_THR_THR_MASK                   (0xFFU)
-#define SMARTCARD_THR_THR_SHIFT                  (0U)
-#define SMARTCARD_THR_THR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
-
-/*! @name DLM - Divisor Latch MSB */
-#define SMARTCARD_DLM_DLMSB_MASK                 (0xFFU)
-#define SMARTCARD_DLM_DLMSB_SHIFT                (0U)
-#define SMARTCARD_DLM_DLMSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
-
-/*! @name IER - Interrupt Enable Register */
-#define SMARTCARD_IER_RBRIE_MASK                 (0x1U)
-#define SMARTCARD_IER_RBRIE_SHIFT                (0U)
-#define SMARTCARD_IER_RBRIE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
-#define SMARTCARD_IER_THREIE_MASK                (0x2U)
-#define SMARTCARD_IER_THREIE_SHIFT               (1U)
-#define SMARTCARD_IER_THREIE(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
-#define SMARTCARD_IER_RXIE_MASK                  (0x4U)
-#define SMARTCARD_IER_RXIE_SHIFT                 (2U)
-#define SMARTCARD_IER_RXIE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
-
-/*! @name FCR - FIFO Control Register */
-#define SMARTCARD_FCR_FIFOEN_MASK                (0x1U)
-#define SMARTCARD_FCR_FIFOEN_SHIFT               (0U)
-#define SMARTCARD_FCR_FIFOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
-#define SMARTCARD_FCR_RXFIFORES_MASK             (0x2U)
-#define SMARTCARD_FCR_RXFIFORES_SHIFT            (1U)
-#define SMARTCARD_FCR_RXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
-#define SMARTCARD_FCR_TXFIFORES_MASK             (0x4U)
-#define SMARTCARD_FCR_TXFIFORES_SHIFT            (2U)
-#define SMARTCARD_FCR_TXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
-#define SMARTCARD_FCR_DMAMODE_MASK               (0x8U)
-#define SMARTCARD_FCR_DMAMODE_SHIFT              (3U)
-#define SMARTCARD_FCR_DMAMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
-#define SMARTCARD_FCR_RXTRIGLVL_MASK             (0xC0U)
-#define SMARTCARD_FCR_RXTRIGLVL_SHIFT            (6U)
-#define SMARTCARD_FCR_RXTRIGLVL(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
-
-/*! @name IIR - Interrupt ID Register */
-#define SMARTCARD_IIR_INTSTATUS_MASK             (0x1U)
-#define SMARTCARD_IIR_INTSTATUS_SHIFT            (0U)
-#define SMARTCARD_IIR_INTSTATUS(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
-#define SMARTCARD_IIR_INTID_MASK                 (0xEU)
-#define SMARTCARD_IIR_INTID_SHIFT                (1U)
-#define SMARTCARD_IIR_INTID(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
-#define SMARTCARD_IIR_FIFOENABLE_MASK            (0xC0U)
-#define SMARTCARD_IIR_FIFOENABLE_SHIFT           (6U)
-#define SMARTCARD_IIR_FIFOENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
-
-/*! @name LCR - Line Control Register */
-#define SMARTCARD_LCR_WLS_MASK                   (0x3U)
-#define SMARTCARD_LCR_WLS_SHIFT                  (0U)
-#define SMARTCARD_LCR_WLS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
-#define SMARTCARD_LCR_SBS_MASK                   (0x4U)
-#define SMARTCARD_LCR_SBS_SHIFT                  (2U)
-#define SMARTCARD_LCR_SBS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
-#define SMARTCARD_LCR_PE_MASK                    (0x8U)
-#define SMARTCARD_LCR_PE_SHIFT                   (3U)
-#define SMARTCARD_LCR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
-#define SMARTCARD_LCR_PS_MASK                    (0x30U)
-#define SMARTCARD_LCR_PS_SHIFT                   (4U)
-#define SMARTCARD_LCR_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
-#define SMARTCARD_LCR_DLAB_MASK                  (0x80U)
-#define SMARTCARD_LCR_DLAB_SHIFT                 (7U)
-#define SMARTCARD_LCR_DLAB(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
-
-/*! @name LSR - Line Status Register */
-#define SMARTCARD_LSR_RDR_MASK                   (0x1U)
-#define SMARTCARD_LSR_RDR_SHIFT                  (0U)
-#define SMARTCARD_LSR_RDR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
-#define SMARTCARD_LSR_OE_MASK                    (0x2U)
-#define SMARTCARD_LSR_OE_SHIFT                   (1U)
-#define SMARTCARD_LSR_OE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
-#define SMARTCARD_LSR_PE_MASK                    (0x4U)
-#define SMARTCARD_LSR_PE_SHIFT                   (2U)
-#define SMARTCARD_LSR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
-#define SMARTCARD_LSR_FE_MASK                    (0x8U)
-#define SMARTCARD_LSR_FE_SHIFT                   (3U)
-#define SMARTCARD_LSR_FE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
-#define SMARTCARD_LSR_THRE_MASK                  (0x20U)
-#define SMARTCARD_LSR_THRE_SHIFT                 (5U)
-#define SMARTCARD_LSR_THRE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
-#define SMARTCARD_LSR_TEMT_MASK                  (0x40U)
-#define SMARTCARD_LSR_TEMT_SHIFT                 (6U)
-#define SMARTCARD_LSR_TEMT(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
-#define SMARTCARD_LSR_RXFE_MASK                  (0x80U)
-#define SMARTCARD_LSR_RXFE_SHIFT                 (7U)
-#define SMARTCARD_LSR_RXFE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
-
-/*! @name SCR - Scratch Pad Register */
-#define SMARTCARD_SCR_PAD_MASK                   (0xFFU)
-#define SMARTCARD_SCR_PAD_SHIFT                  (0U)
-#define SMARTCARD_SCR_PAD(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
-
-/*! @name OSR - Oversampling register */
-#define SMARTCARD_OSR_OSFRAC_MASK                (0xEU)
-#define SMARTCARD_OSR_OSFRAC_SHIFT               (1U)
-#define SMARTCARD_OSR_OSFRAC(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
-#define SMARTCARD_OSR_OSINT_MASK                 (0xF0U)
-#define SMARTCARD_OSR_OSINT_SHIFT                (4U)
-#define SMARTCARD_OSR_OSINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
-#define SMARTCARD_OSR_FDINT_MASK                 (0x7F00U)
-#define SMARTCARD_OSR_FDINT_SHIFT                (8U)
-#define SMARTCARD_OSR_FDINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
-
-/*! @name SCICTRL - Smart Card Interface control register */
-#define SMARTCARD_SCICTRL_SCIEN_MASK             (0x1U)
-#define SMARTCARD_SCICTRL_SCIEN_SHIFT            (0U)
-#define SMARTCARD_SCICTRL_SCIEN(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
-#define SMARTCARD_SCICTRL_NACKDIS_MASK           (0x2U)
-#define SMARTCARD_SCICTRL_NACKDIS_SHIFT          (1U)
-#define SMARTCARD_SCICTRL_NACKDIS(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
-#define SMARTCARD_SCICTRL_PROTSEL_MASK           (0x4U)
-#define SMARTCARD_SCICTRL_PROTSEL_SHIFT          (2U)
-#define SMARTCARD_SCICTRL_PROTSEL(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
-#define SMARTCARD_SCICTRL_TXRETRY_MASK           (0xE0U)
-#define SMARTCARD_SCICTRL_TXRETRY_SHIFT          (5U)
-#define SMARTCARD_SCICTRL_TXRETRY(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
-#define SMARTCARD_SCICTRL_GUARDTIME_MASK         (0xFF00U)
-#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT        (8U)
-#define SMARTCARD_SCICTRL_GUARDTIME(x)           (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
-
-
-/*!
- * @}
- */ /* end of group SMARTCARD_Register_Masks */
-
-
-/* SMARTCARD - Peripheral instance base addresses */
-/** Peripheral SMARTCARD0 base address */
-#define SMARTCARD0_BASE                          (0x40036000u)
-/** Peripheral SMARTCARD0 base pointer */
-#define SMARTCARD0                               ((SMARTCARD_Type *)SMARTCARD0_BASE)
-/** Peripheral SMARTCARD1 base address */
-#define SMARTCARD1_BASE                          (0x40037000u)
-/** Peripheral SMARTCARD1 base pointer */
-#define SMARTCARD1                               ((SMARTCARD_Type *)SMARTCARD1_BASE)
-/** Array initializer of SMARTCARD peripheral base addresses */
-#define SMARTCARD_BASE_ADDRS                     { SMARTCARD0_BASE, SMARTCARD1_BASE }
-/** Array initializer of SMARTCARD peripheral base pointers */
-#define SMARTCARD_BASE_PTRS                      { SMARTCARD0, SMARTCARD1 }
-/** Interrupt vectors for the SMARTCARD peripheral type */
-#define SMARTCARD_IRQS                           { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
-
-/*!
- * @}
- */ /* end of group SMARTCARD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SPI Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[1024];
-  __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
-  __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
-  __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
-  __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
-  __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
-       uint8_t RESERVED_1[16];
-  __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
-  __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
-       uint8_t RESERVED_2[2516];
-  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
-  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
-  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
-       uint8_t RESERVED_3[4];
-  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
-  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
-  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
-       uint8_t RESERVED_4[4];
-  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
-       uint8_t RESERVED_5[12];
-  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
-       uint8_t RESERVED_6[12];
-  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
-       uint8_t RESERVED_7[440];
-  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SPI Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/*! @name CFG - SPI Configuration register */
-#define SPI_CFG_ENABLE_MASK                      (0x1U)
-#define SPI_CFG_ENABLE_SHIFT                     (0U)
-#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
-#define SPI_CFG_MASTER_MASK                      (0x4U)
-#define SPI_CFG_MASTER_SHIFT                     (2U)
-#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
-#define SPI_CFG_LSBF_MASK                        (0x8U)
-#define SPI_CFG_LSBF_SHIFT                       (3U)
-#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
-#define SPI_CFG_CPHA_MASK                        (0x10U)
-#define SPI_CFG_CPHA_SHIFT                       (4U)
-#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
-#define SPI_CFG_CPOL_MASK                        (0x20U)
-#define SPI_CFG_CPOL_SHIFT                       (5U)
-#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
-#define SPI_CFG_LOOP_MASK                        (0x80U)
-#define SPI_CFG_LOOP_SHIFT                       (7U)
-#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
-#define SPI_CFG_SPOL0_MASK                       (0x100U)
-#define SPI_CFG_SPOL0_SHIFT                      (8U)
-#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
-#define SPI_CFG_SPOL1_MASK                       (0x200U)
-#define SPI_CFG_SPOL1_SHIFT                      (9U)
-#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
-#define SPI_CFG_SPOL2_MASK                       (0x400U)
-#define SPI_CFG_SPOL2_SHIFT                      (10U)
-#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
-#define SPI_CFG_SPOL3_MASK                       (0x800U)
-#define SPI_CFG_SPOL3_SHIFT                      (11U)
-#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
-
-/*! @name DLY - SPI Delay register */
-#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
-#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
-#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
-#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
-#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
-#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
-#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
-#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
-#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
-#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
-#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
-#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
-
-/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
-#define SPI_STAT_SSA_MASK                        (0x10U)
-#define SPI_STAT_SSA_SHIFT                       (4U)
-#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
-#define SPI_STAT_SSD_MASK                        (0x20U)
-#define SPI_STAT_SSD_SHIFT                       (5U)
-#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
-#define SPI_STAT_STALLED_MASK                    (0x40U)
-#define SPI_STAT_STALLED_SHIFT                   (6U)
-#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
-#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
-#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
-#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
-#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
-#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
-#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
-
-/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
-#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
-#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
-#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
-#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
-#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
-#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
-#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
-#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
-#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
-
-/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
-#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
-#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
-#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
-#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
-#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
-#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
-#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
-#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
-#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
-
-/*! @name DIV - SPI clock Divider */
-#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
-#define SPI_DIV_DIVVAL_SHIFT                     (0U)
-#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
-
-/*! @name INTSTAT - SPI Interrupt Status */
-#define SPI_INTSTAT_SSA_MASK                     (0x10U)
-#define SPI_INTSTAT_SSA_SHIFT                    (4U)
-#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
-#define SPI_INTSTAT_SSD_MASK                     (0x20U)
-#define SPI_INTSTAT_SSD_SHIFT                    (5U)
-#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
-#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
-#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
-#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
-#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
-#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
-#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
-#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
-#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
-#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
-#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
-#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
-#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
-#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
-#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
-#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
-#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
-#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
-#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
-#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
-#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
-#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
-#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
-#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
-#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
-#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
-#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
-#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
-#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
-#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
-#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
-#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
-#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
-#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
-#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
-#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
-#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
-#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
-#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
-#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
-#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
-#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
-#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
-#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
-#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
-#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
-#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
-#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
-#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
-#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
-#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
-#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
-#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
-#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
-#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
-#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
-#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
-#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
-#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
-#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
-#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
-#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
-#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
-#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
-#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
-#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
-#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
-#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
-#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
-#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
-#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
-#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
-#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
-#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
-#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
-#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
-#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
-#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
-#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
-#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
-#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
-#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
-#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
-#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
-#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
-#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
-#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
-#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
-#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
-#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
-#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
-#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
-#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
-#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
-#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
-#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
-#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
-#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
-#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
-#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
-#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
-#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
-#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
-#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
-#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
-#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
-#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
-#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
-#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
-#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
-#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
-#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
-#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
-#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
-#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
-#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
-#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
-#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
-#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
-#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
-#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
-#define SPI_FIFOWR_EOT_SHIFT                     (20U)
-#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
-#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
-#define SPI_FIFOWR_EOF_SHIFT                     (21U)
-#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
-#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
-#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
-#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
-#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
-#define SPI_FIFOWR_LEN_SHIFT                     (24U)
-#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
-#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
-#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
-#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
-#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
-#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
-#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
-#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
-#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
-#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
-#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
-#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
-#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
-#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
-#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
-#define SPI_FIFORD_SOT_MASK                      (0x100000U)
-#define SPI_FIFORD_SOT_SHIFT                     (20U)
-#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
-#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
-#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
-#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
-#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
-#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
-#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
-#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
-#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define SPI_ID_APERTURE_MASK                     (0xFFU)
-#define SPI_ID_APERTURE_SHIFT                    (0U)
-#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
-#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
-#define SPI_ID_MINOR_REV_SHIFT                   (8U)
-#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
-#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
-#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
-#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
-#define SPI_ID_ID_MASK                           (0xFFFF0000U)
-#define SPI_ID_ID_SHIFT                          (16U)
-#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE                                (0x40086000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0                                     ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE                                (0x40087000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1                                     ((SPI_Type *)SPI1_BASE)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE                                (0x40088000u)
-/** Peripheral SPI2 base pointer */
-#define SPI2                                     ((SPI_Type *)SPI2_BASE)
-/** Peripheral SPI3 base address */
-#define SPI3_BASE                                (0x40089000u)
-/** Peripheral SPI3 base pointer */
-#define SPI3                                     ((SPI_Type *)SPI3_BASE)
-/** Peripheral SPI4 base address */
-#define SPI4_BASE                                (0x4008A000u)
-/** Peripheral SPI4 base pointer */
-#define SPI4                                     ((SPI_Type *)SPI4_BASE)
-/** Peripheral SPI5 base address */
-#define SPI5_BASE                                (0x40096000u)
-/** Peripheral SPI5 base pointer */
-#define SPI5                                     ((SPI_Type *)SPI5_BASE)
-/** Peripheral SPI6 base address */
-#define SPI6_BASE                                (0x40097000u)
-/** Peripheral SPI6 base pointer */
-#define SPI6                                     ((SPI_Type *)SPI6_BASE)
-/** Peripheral SPI7 base address */
-#define SPI7_BASE                                (0x40098000u)
-/** Peripheral SPI7 base pointer */
-#define SPI7                                     ((SPI_Type *)SPI7_BASE)
-/** Peripheral SPI8 base address */
-#define SPI8_BASE                                (0x40099000u)
-/** Peripheral SPI8 base pointer */
-#define SPI8                                     ((SPI_Type *)SPI8_BASE)
-/** Peripheral SPI9 base address */
-#define SPI9_BASE                                (0x4009A000u)
-/** Peripheral SPI9 base pointer */
-#define SPI9                                     ((SPI_Type *)SPI9_BASE)
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }
-/** Interrupt vectors for the SPI peripheral type */
-#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SPIFI Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
- * @{
- */
-
-/** SPIFI - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< SPIFI control register, offset: 0x0 */
-  __IO uint32_t CMD;                               /**< SPIFI command register, offset: 0x4 */
-  __IO uint32_t ADDR;                              /**< SPIFI address register, offset: 0x8 */
-  __IO uint32_t IDATA;                             /**< SPIFI intermediate data register, offset: 0xC */
-  __IO uint32_t CLIMIT;                            /**< SPIFI limit register, offset: 0x10 */
-  __IO uint32_t DATA;                              /**< SPIFI data register, offset: 0x14 */
-  __IO uint32_t MCMD;                              /**< SPIFI memory command register, offset: 0x18 */
-  __IO uint32_t STAT;                              /**< SPIFI status register, offset: 0x1C */
-} SPIFI_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SPIFI Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
- * @{
- */
-
-/*! @name CTRL - SPIFI control register */
-#define SPIFI_CTRL_TIMEOUT_MASK                  (0xFFFFU)
-#define SPIFI_CTRL_TIMEOUT_SHIFT                 (0U)
-#define SPIFI_CTRL_TIMEOUT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
-#define SPIFI_CTRL_CSHIGH_MASK                   (0xF0000U)
-#define SPIFI_CTRL_CSHIGH_SHIFT                  (16U)
-#define SPIFI_CTRL_CSHIGH(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
-#define SPIFI_CTRL_D_PRFTCH_DIS_MASK             (0x200000U)
-#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT            (21U)
-#define SPIFI_CTRL_D_PRFTCH_DIS(x)               (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
-#define SPIFI_CTRL_INTEN_MASK                    (0x400000U)
-#define SPIFI_CTRL_INTEN_SHIFT                   (22U)
-#define SPIFI_CTRL_INTEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
-#define SPIFI_CTRL_MODE3_MASK                    (0x800000U)
-#define SPIFI_CTRL_MODE3_SHIFT                   (23U)
-#define SPIFI_CTRL_MODE3(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
-#define SPIFI_CTRL_PRFTCH_DIS_MASK               (0x8000000U)
-#define SPIFI_CTRL_PRFTCH_DIS_SHIFT              (27U)
-#define SPIFI_CTRL_PRFTCH_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
-#define SPIFI_CTRL_DUAL_MASK                     (0x10000000U)
-#define SPIFI_CTRL_DUAL_SHIFT                    (28U)
-#define SPIFI_CTRL_DUAL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
-#define SPIFI_CTRL_RFCLK_MASK                    (0x20000000U)
-#define SPIFI_CTRL_RFCLK_SHIFT                   (29U)
-#define SPIFI_CTRL_RFCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
-#define SPIFI_CTRL_FBCLK_MASK                    (0x40000000U)
-#define SPIFI_CTRL_FBCLK_SHIFT                   (30U)
-#define SPIFI_CTRL_FBCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
-#define SPIFI_CTRL_DMAEN_MASK                    (0x80000000U)
-#define SPIFI_CTRL_DMAEN_SHIFT                   (31U)
-#define SPIFI_CTRL_DMAEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
-
-/*! @name CMD - SPIFI command register */
-#define SPIFI_CMD_DATALEN_MASK                   (0x3FFFU)
-#define SPIFI_CMD_DATALEN_SHIFT                  (0U)
-#define SPIFI_CMD_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
-#define SPIFI_CMD_POLL_MASK                      (0x4000U)
-#define SPIFI_CMD_POLL_SHIFT                     (14U)
-#define SPIFI_CMD_POLL(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
-#define SPIFI_CMD_DOUT_MASK                      (0x8000U)
-#define SPIFI_CMD_DOUT_SHIFT                     (15U)
-#define SPIFI_CMD_DOUT(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
-#define SPIFI_CMD_INTLEN_MASK                    (0x70000U)
-#define SPIFI_CMD_INTLEN_SHIFT                   (16U)
-#define SPIFI_CMD_INTLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
-#define SPIFI_CMD_FIELDFORM_MASK                 (0x180000U)
-#define SPIFI_CMD_FIELDFORM_SHIFT                (19U)
-#define SPIFI_CMD_FIELDFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
-#define SPIFI_CMD_FRAMEFORM_MASK                 (0xE00000U)
-#define SPIFI_CMD_FRAMEFORM_SHIFT                (21U)
-#define SPIFI_CMD_FRAMEFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
-#define SPIFI_CMD_OPCODE_MASK                    (0xFF000000U)
-#define SPIFI_CMD_OPCODE_SHIFT                   (24U)
-#define SPIFI_CMD_OPCODE(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
-
-/*! @name ADDR - SPIFI address register */
-#define SPIFI_ADDR_ADDRESS_MASK                  (0xFFFFFFFFU)
-#define SPIFI_ADDR_ADDRESS_SHIFT                 (0U)
-#define SPIFI_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
-
-/*! @name IDATA - SPIFI intermediate data register */
-#define SPIFI_IDATA_IDATA_MASK                   (0xFFFFFFFFU)
-#define SPIFI_IDATA_IDATA_SHIFT                  (0U)
-#define SPIFI_IDATA_IDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
-
-/*! @name CLIMIT - SPIFI limit register */
-#define SPIFI_CLIMIT_CLIMIT_MASK                 (0xFFFFFFFFU)
-#define SPIFI_CLIMIT_CLIMIT_SHIFT                (0U)
-#define SPIFI_CLIMIT_CLIMIT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
-
-/*! @name DATA - SPIFI data register */
-#define SPIFI_DATA_DATA_MASK                     (0xFFFFFFFFU)
-#define SPIFI_DATA_DATA_SHIFT                    (0U)
-#define SPIFI_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
-
-/*! @name MCMD - SPIFI memory command register */
-#define SPIFI_MCMD_POLL_MASK                     (0x4000U)
-#define SPIFI_MCMD_POLL_SHIFT                    (14U)
-#define SPIFI_MCMD_POLL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
-#define SPIFI_MCMD_DOUT_MASK                     (0x8000U)
-#define SPIFI_MCMD_DOUT_SHIFT                    (15U)
-#define SPIFI_MCMD_DOUT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
-#define SPIFI_MCMD_INTLEN_MASK                   (0x70000U)
-#define SPIFI_MCMD_INTLEN_SHIFT                  (16U)
-#define SPIFI_MCMD_INTLEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
-#define SPIFI_MCMD_FIELDFORM_MASK                (0x180000U)
-#define SPIFI_MCMD_FIELDFORM_SHIFT               (19U)
-#define SPIFI_MCMD_FIELDFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
-#define SPIFI_MCMD_FRAMEFORM_MASK                (0xE00000U)
-#define SPIFI_MCMD_FRAMEFORM_SHIFT               (21U)
-#define SPIFI_MCMD_FRAMEFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
-#define SPIFI_MCMD_OPCODE_MASK                   (0xFF000000U)
-#define SPIFI_MCMD_OPCODE_SHIFT                  (24U)
-#define SPIFI_MCMD_OPCODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
-
-/*! @name STAT - SPIFI status register */
-#define SPIFI_STAT_MCINIT_MASK                   (0x1U)
-#define SPIFI_STAT_MCINIT_SHIFT                  (0U)
-#define SPIFI_STAT_MCINIT(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
-#define SPIFI_STAT_CMD_MASK                      (0x2U)
-#define SPIFI_STAT_CMD_SHIFT                     (1U)
-#define SPIFI_STAT_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
-#define SPIFI_STAT_RESET_MASK                    (0x10U)
-#define SPIFI_STAT_RESET_SHIFT                   (4U)
-#define SPIFI_STAT_RESET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
-#define SPIFI_STAT_INTRQ_MASK                    (0x20U)
-#define SPIFI_STAT_INTRQ_SHIFT                   (5U)
-#define SPIFI_STAT_INTRQ(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
-
-
-/*!
- * @}
- */ /* end of group SPIFI_Register_Masks */
-
-
-/* SPIFI - Peripheral instance base addresses */
-/** Peripheral SPIFI0 base address */
-#define SPIFI0_BASE                              (0x40080000u)
-/** Peripheral SPIFI0 base pointer */
-#define SPIFI0                                   ((SPIFI_Type *)SPIFI0_BASE)
-/** Array initializer of SPIFI peripheral base addresses */
-#define SPIFI_BASE_ADDRS                         { SPIFI0_BASE }
-/** Array initializer of SPIFI peripheral base pointers */
-#define SPIFI_BASE_PTRS                          { SPIFI0 }
-/** Interrupt vectors for the SPIFI peripheral type */
-#define SPIFI_IRQS                               { SPIFI0_IRQn }
-
-/*!
- * @}
- */ /* end of group SPIFI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SYSCON Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
- * @{
- */
-
-/** SYSCON - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[16];
-  __IO uint32_t AHBMATPRIO;                        /**< AHB multilayer matrix priority control, offset: 0x10 */
-       uint8_t RESERVED_1[44];
-  __IO uint32_t SYSTCKCAL;                         /**< System tick counter calibration, offset: 0x40 */
-       uint8_t RESERVED_2[4];
-  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
-  __IO uint32_t ASYNCAPBCTRL;                      /**< Asynchronous APB Control, offset: 0x4C */
-       uint8_t RESERVED_3[112];
-  __I  uint32_t PIOPORCAP[2];                      /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
-       uint8_t RESERVED_4[8];
-  __I  uint32_t PIORESCAP[2];                      /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
-       uint8_t RESERVED_5[40];
-  __IO uint32_t PRESETCTRL[3];                     /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
-       uint8_t RESERVED_6[20];
-  __O  uint32_t PRESETCTRLSET[3];                  /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
-       uint8_t RESERVED_7[20];
-  __O  uint32_t PRESETCTRLCLR[3];                  /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
-       uint8_t RESERVED_8[164];
-  __IO uint32_t SYSRSTSTAT;                        /**< System reset status register, offset: 0x1F0 */
-       uint8_t RESERVED_9[12];
-  __IO uint32_t AHBCLKCTRL[3];                     /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
-       uint8_t RESERVED_10[20];
-  __O  uint32_t AHBCLKCTRLSET[3];                  /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
-       uint8_t RESERVED_11[20];
-  __O  uint32_t AHBCLKCTRLCLR[3];                  /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
-       uint8_t RESERVED_12[52];
-  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
-  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
-  __IO uint32_t CLKOUTSELA;                        /**< CLKOUT clock source select A, offset: 0x288 */
-       uint8_t RESERVED_13[4];
-  __IO uint32_t SYSPLLCLKSEL;                      /**< PLL clock source select, offset: 0x290 */
-       uint8_t RESERVED_14[4];
-  __IO uint32_t AUDPLLCLKSEL;                      /**< Audio PLL clock source select, offset: 0x298 */
-       uint8_t RESERVED_15[4];
-  __IO uint32_t SPIFICLKSEL;                       /**< SPIFI clock source select, offset: 0x2A0 */
-  __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
-  __IO uint32_t USB0CLKSEL;                        /**< USB0 clock source select, offset: 0x2A8 */
-  __IO uint32_t USB1CLKSEL;                        /**< USB1 clock source select, offset: 0x2AC */
-  __IO uint32_t FCLKSEL[10];                       /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
-       uint8_t RESERVED_16[8];
-  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
-       uint8_t RESERVED_17[4];
-  __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
-  __IO uint32_t DMICCLKSEL;                        /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
-  __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
-  __IO uint32_t LCDCLKSEL;                         /**< LCD clock source select, offset: 0x2F4 */
-  __IO uint32_t SDIOCLKSEL;                        /**< SDIO clock source select, offset: 0x2F8 */
-       uint8_t RESERVED_18[4];
-  __IO uint32_t SYSTICKCLKDIV;                     /**< SYSTICK clock divider, offset: 0x300 */
-  __IO uint32_t ARMTRACECLKDIV;                    /**< ARM Trace clock divider, offset: 0x304 */
-  __IO uint32_t CAN0CLKDIV;                        /**< MCAN0 clock divider, offset: 0x308 */
-  __IO uint32_t CAN1CLKDIV;                        /**< MCAN1 clock divider, offset: 0x30C */
-  __IO uint32_t SC0CLKDIV;                         /**< Smartcard0 clock divider, offset: 0x310 */
-  __IO uint32_t SC1CLKDIV;                         /**< Smartcard1 clock divider, offset: 0x314 */
-       uint8_t RESERVED_19[104];
-  __IO uint32_t AHBCLKDIV;                         /**< AHB clock divider, offset: 0x380 */
-  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
-  __IO uint32_t FROHFCLKDIV;                       /**< FROHF clock divider, offset: 0x388 */
-       uint8_t RESERVED_20[4];
-  __IO uint32_t SPIFICLKDIV;                       /**< SPIFI clock divider, offset: 0x390 */
-  __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
-  __IO uint32_t USB0CLKDIV;                        /**< USB0 clock divider, offset: 0x398 */
-  __IO uint32_t USB1CLKDIV;                        /**< USB1 clock divider, offset: 0x39C */
-  __IO uint32_t FRGCTRL;                           /**< Fractional rate divider, offset: 0x3A0 */
-       uint8_t RESERVED_21[4];
-  __IO uint32_t DMICCLKDIV;                        /**< DMIC clock divider, offset: 0x3A8 */
-  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
-  __IO uint32_t LCDCLKDIV;                         /**< LCD clock divider, offset: 0x3B0 */
-  __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
-  __IO uint32_t EMCCLKDIV;                         /**< EMC clock divider, offset: 0x3B8 */
-  __IO uint32_t SDIOCLKDIV;                        /**< SDIO clock divider, offset: 0x3BC */
-       uint8_t RESERVED_22[64];
-  __IO uint32_t FLASHCFG;                          /**< Flash wait states configuration, offset: 0x400 */
-       uint8_t RESERVED_23[8];
-  __IO uint32_t USB0CLKCTRL;                       /**< USB0 clock control, offset: 0x40C */
-  __IO uint32_t USB0CLKSTAT;                       /**< USB0 clock status, offset: 0x410 */
-       uint8_t RESERVED_24[4];
-  __IO uint32_t FREQMECTRL;                        /**< Frequency measure register, offset: 0x418 */
-       uint8_t RESERVED_25[4];
-  __IO uint32_t MCLKIO;                            /**< MCLK input/output control, offset: 0x420 */
-  __IO uint32_t USB1CLKCTRL;                       /**< USB1 clock control, offset: 0x424 */
-  __IO uint32_t USB1CLKSTAT;                       /**< USB1 clock status, offset: 0x428 */
-       uint8_t RESERVED_26[24];
-  __IO uint32_t EMCSYSCTRL;                        /**< EMC system control, offset: 0x444 */
-  __IO uint32_t EMCDLYCTRL;                        /**< EMC clock delay control, offset: 0x448 */
-  __IO uint32_t EMCDLYCAL;                         /**< EMC delay chain calibration control, offset: 0x44C */
-  __IO uint32_t ETHPHYSEL;                         /**< Ethernet PHY Selection, offset: 0x450 */
-  __IO uint32_t ETHSBDCTRL;                        /**< Ethernet SBD flow control, offset: 0x454 */
-       uint8_t RESERVED_27[8];
-  __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
-       uint8_t RESERVED_28[156];
-  __IO uint32_t FROCTRL;                           /**< FRO oscillator control, offset: 0x500 */
-  __IO uint32_t SYSOSCCTRL;                        /**< System oscillator control, offset: 0x504 */
-  __IO uint32_t WDTOSCCTRL;                        /**< Watchdog oscillator control, offset: 0x508 */
-  __IO uint32_t RTCOSCCTRL;                        /**< RTC oscillator 32 kHz output control, offset: 0x50C */
-       uint8_t RESERVED_29[12];
-  __IO uint32_t USBPLLCTRL;                        /**< USB PLL control, offset: 0x51C */
-  __IO uint32_t USBPLLSTAT;                        /**< USB PLL status, offset: 0x520 */
-       uint8_t RESERVED_30[92];
-  __IO uint32_t SYSPLLCTRL;                        /**< System PLL control, offset: 0x580 */
-  __IO uint32_t SYSPLLSTAT;                        /**< PLL status, offset: 0x584 */
-  __IO uint32_t SYSPLLNDEC;                        /**< PLL N divider, offset: 0x588 */
-  __IO uint32_t SYSPLLPDEC;                        /**< PLL P divider, offset: 0x58C */
-  __IO uint32_t SYSPLLMDEC;                        /**< System PLL M divider, offset: 0x590 */
-       uint8_t RESERVED_31[12];
-  __IO uint32_t AUDPLLCTRL;                        /**< Audio PLL control, offset: 0x5A0 */
-  __IO uint32_t AUDPLLSTAT;                        /**< Audio PLL status, offset: 0x5A4 */
-  __IO uint32_t AUDPLLNDEC;                        /**< Audio PLL N divider, offset: 0x5A8 */
-  __IO uint32_t AUDPLLPDEC;                        /**< Audio PLL P divider, offset: 0x5AC */
-  __IO uint32_t AUDPLLMDEC;                        /**< Audio PLL M divider, offset: 0x5B0 */
-  __IO uint32_t AUDPLLFRAC;                        /**< Audio PLL fractional divider control, offset: 0x5B4 */
-       uint8_t RESERVED_32[72];
-  __IO uint32_t PDSLEEPCFG[2];                     /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */
-       uint8_t RESERVED_33[8];
-  __IO uint32_t PDRUNCFG[2];                       /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */
-       uint8_t RESERVED_34[8];
-  __IO uint32_t PDRUNCFGSET[2];                    /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */
-       uint8_t RESERVED_35[8];
-  __IO uint32_t PDRUNCFGCLR[2];                    /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */
-       uint8_t RESERVED_36[72];
-  __IO uint32_t STARTER[2];                        /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
-       uint8_t RESERVED_37[24];
-  __O  uint32_t STARTERSET[2];                     /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
-       uint8_t RESERVED_38[24];
-  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
-       uint8_t RESERVED_39[184];
-  __IO uint32_t HWWAKE;                            /**< Configures special cases of hardware wake-up, offset: 0x780 */
-       uint8_t RESERVED_40[1664];
-  __IO uint32_t AUTOCGOR;                          /**< Auto Clock-Gate Override Register, offset: 0xE04 */
-       uint8_t RESERVED_41[492];
-  __I  uint32_t JTAGIDCODE;                        /**< JTAG ID code register, offset: 0xFF4 */
-  __I  uint32_t DEVICE_ID0;                        /**< Part ID register, offset: 0xFF8 */
-  __I  uint32_t DEVICE_ID1;                        /**< Boot ROM and die revision register, offset: 0xFFC */
-       uint8_t RESERVED_42[127044];
-  __IO uint32_t BODCTRL;                           /**< Brown-Out Detect control, offset: 0x20044 */
-} SYSCON_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SYSCON Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
- * @{
- */
-
-/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
-#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK         (0x3U)
-#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT        (0U)
-#define SYSCON_AHBMATPRIO_PRI_ICODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
-#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK         (0xCU)
-#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT        (2U)
-#define SYSCON_AHBMATPRIO_PRI_DCODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SYS_MASK           (0x30U)
-#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT          (4U)
-#define SYSCON_AHBMATPRIO_PRI_SYS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_DMA_MASK           (0x3C0U)
-#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT          (6U)
-#define SYSCON_AHBMATPRIO_PRI_DMA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
-#define SYSCON_AHBMATPRIO_PRI_ETH_MASK           (0xC00U)
-#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT          (10U)
-#define SYSCON_AHBMATPRIO_PRI_ETH(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
-#define SYSCON_AHBMATPRIO_PRI_LCD_MASK           (0x3000U)
-#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT          (12U)
-#define SYSCON_AHBMATPRIO_PRI_LCD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB0_MASK          (0xC000U)
-#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT         (14U)
-#define SYSCON_AHBMATPRIO_PRI_USB0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB1_MASK          (0x30000U)
-#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT         (16U)
-#define SYSCON_AHBMATPRIO_PRI_USB1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK          (0xC0000U)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT         (18U)
-#define SYSCON_AHBMATPRIO_PRI_SDIO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK         (0x300000U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT        (20U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK         (0xC00000U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT        (22U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SHA_MASK           (0x3000000U)
-#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT          (24U)
-#define SYSCON_AHBMATPRIO_PRI_SHA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)
-
-/*! @name SYSTCKCAL - System tick counter calibration */
-#define SYSCON_SYSTCKCAL_CAL_MASK                (0xFFFFFFU)
-#define SYSCON_SYSTCKCAL_CAL_SHIFT               (0U)
-#define SYSCON_SYSTCKCAL_CAL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
-#define SYSCON_SYSTCKCAL_SKEW_MASK               (0x1000000U)
-#define SYSCON_SYSTCKCAL_SKEW_SHIFT              (24U)
-#define SYSCON_SYSTCKCAL_SKEW(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
-#define SYSCON_SYSTCKCAL_NOREF_MASK              (0x2000000U)
-#define SYSCON_SYSTCKCAL_NOREF_SHIFT             (25U)
-#define SYSCON_SYSTCKCAL_NOREF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
-
-/*! @name NMISRC - NMI Source Select */
-#define SYSCON_NMISRC_IRQM4_MASK                 (0x3FU)
-#define SYSCON_NMISRC_IRQM4_SHIFT                (0U)
-#define SYSCON_NMISRC_IRQM4(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
-#define SYSCON_NMISRC_NMIENM4_MASK               (0x80000000U)
-#define SYSCON_NMISRC_NMIENM4_SHIFT              (31U)
-#define SYSCON_NMISRC_NMIENM4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
-
-/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
-#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK          (0x1U)
-#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT         (0U)
-#define SYSCON_ASYNCAPBCTRL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
-
-/*! @name PIOPORCAP - POR captured value of port n */
-#define SYSCON_PIOPORCAP_PIOPORCAP_MASK          (0xFFFFFFFFU)
-#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT         (0U)
-#define SYSCON_PIOPORCAP_PIOPORCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
-
-/* The count of SYSCON_PIOPORCAP */
-#define SYSCON_PIOPORCAP_COUNT                   (2U)
-
-/*! @name PIORESCAP - Reset captured value of port n */
-#define SYSCON_PIORESCAP_PIORESCAP_MASK          (0xFFFFFFFFU)
-#define SYSCON_PIORESCAP_PIORESCAP_SHIFT         (0U)
-#define SYSCON_PIORESCAP_PIORESCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
-
-/* The count of SYSCON_PIORESCAP */
-#define SYSCON_PIORESCAP_COUNT                   (2U)
-
-/*! @name PRESETCTRL - Peripheral reset control n */
-#define SYSCON_PRESETCTRL_MRT_RST_MASK           (0x1U)
-#define SYSCON_PRESETCTRL_MRT_RST_SHIFT          (0U)
-#define SYSCON_PRESETCTRL_MRT_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
-#define SYSCON_PRESETCTRL_SCT0_RST_MASK          (0x4U)
-#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT         (2U)
-#define SYSCON_PRESETCTRL_SCT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
-#define SYSCON_PRESETCTRL_LCD_RST_MASK           (0x4U)
-#define SYSCON_PRESETCTRL_LCD_RST_SHIFT          (2U)
-#define SYSCON_PRESETCTRL_LCD_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
-#define SYSCON_PRESETCTRL_SDIO_RST_MASK          (0x8U)
-#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT         (3U)
-#define SYSCON_PRESETCTRL_SDIO_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1H_RST_MASK         (0x10U)
-#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT        (4U)
-#define SYSCON_PRESETCTRL_USB1H_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1D_RST_MASK         (0x20U)
-#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT        (5U)
-#define SYSCON_PRESETCTRL_USB1D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK       (0x40U)
-#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT      (6U)
-#define SYSCON_PRESETCTRL_USB1RAM_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
-#define SYSCON_PRESETCTRL_EMC_RESET_MASK         (0x80U)
-#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT        (7U)
-#define SYSCON_PRESETCTRL_EMC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
-#define SYSCON_PRESETCTRL_FLASH_RST_MASK         (0x80U)
-#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT        (7U)
-#define SYSCON_PRESETCTRL_FLASH_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
-#define SYSCON_PRESETCTRL_MCAN0_RST_MASK         (0x80U)
-#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT        (7U)
-#define SYSCON_PRESETCTRL_MCAN0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
-#define SYSCON_PRESETCTRL_FMC_RST_MASK           (0x100U)
-#define SYSCON_PRESETCTRL_FMC_RST_SHIFT          (8U)
-#define SYSCON_PRESETCTRL_FMC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
-#define SYSCON_PRESETCTRL_ETH_RST_MASK           (0x100U)
-#define SYSCON_PRESETCTRL_ETH_RST_SHIFT          (8U)
-#define SYSCON_PRESETCTRL_ETH_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
-#define SYSCON_PRESETCTRL_MCAN1_RST_MASK         (0x100U)
-#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT        (8U)
-#define SYSCON_PRESETCTRL_MCAN1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO4_RST_MASK         (0x200U)
-#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT        (9U)
-#define SYSCON_PRESETCTRL_GPIO4_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
-#define SYSCON_PRESETCTRL_EEPROM_RST_MASK        (0x200U)
-#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT       (9U)
-#define SYSCON_PRESETCTRL_EEPROM_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO5_RST_MASK         (0x400U)
-#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT        (10U)
-#define SYSCON_PRESETCTRL_GPIO5_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
-#define SYSCON_PRESETCTRL_UTICK_RST_MASK         (0x400U)
-#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT        (10U)
-#define SYSCON_PRESETCTRL_UTICK_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
-#define SYSCON_PRESETCTRL_SPIFI_RST_MASK         (0x400U)
-#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT        (10U)
-#define SYSCON_PRESETCTRL_SPIFI_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
-#define SYSCON_PRESETCTRL_AES_RST_MASK           (0x800U)
-#define SYSCON_PRESETCTRL_AES_RST_SHIFT          (11U)
-#define SYSCON_PRESETCTRL_AES_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)
-#define SYSCON_PRESETCTRL_MUX_RST_MASK           (0x800U)
-#define SYSCON_PRESETCTRL_MUX_RST_SHIFT          (11U)
-#define SYSCON_PRESETCTRL_MUX_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
-#define SYSCON_PRESETCTRL_FC0_RST_MASK           (0x800U)
-#define SYSCON_PRESETCTRL_FC0_RST_SHIFT          (11U)
-#define SYSCON_PRESETCTRL_FC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
-#define SYSCON_PRESETCTRL_OTP_RST_MASK           (0x1000U)
-#define SYSCON_PRESETCTRL_OTP_RST_SHIFT          (12U)
-#define SYSCON_PRESETCTRL_OTP_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
-#define SYSCON_PRESETCTRL_FC1_RST_MASK           (0x1000U)
-#define SYSCON_PRESETCTRL_FC1_RST_SHIFT          (12U)
-#define SYSCON_PRESETCTRL_FC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
-#define SYSCON_PRESETCTRL_IOCON_RST_MASK         (0x2000U)
-#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT        (13U)
-#define SYSCON_PRESETCTRL_IOCON_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
-#define SYSCON_PRESETCTRL_RNG_RST_MASK           (0x2000U)
-#define SYSCON_PRESETCTRL_RNG_RST_SHIFT          (13U)
-#define SYSCON_PRESETCTRL_RNG_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
-#define SYSCON_PRESETCTRL_FC2_RST_MASK           (0x2000U)
-#define SYSCON_PRESETCTRL_FC2_RST_SHIFT          (13U)
-#define SYSCON_PRESETCTRL_FC2_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
-#define SYSCON_PRESETCTRL_FC8_RST_MASK           (0x4000U)
-#define SYSCON_PRESETCTRL_FC8_RST_SHIFT          (14U)
-#define SYSCON_PRESETCTRL_FC8_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
-#define SYSCON_PRESETCTRL_FC3_RST_MASK           (0x4000U)
-#define SYSCON_PRESETCTRL_FC3_RST_SHIFT          (14U)
-#define SYSCON_PRESETCTRL_FC3_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO0_RST_MASK         (0x4000U)
-#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT        (14U)
-#define SYSCON_PRESETCTRL_GPIO0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO1_RST_MASK         (0x8000U)
-#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT        (15U)
-#define SYSCON_PRESETCTRL_GPIO1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
-#define SYSCON_PRESETCTRL_FC9_RST_MASK           (0x8000U)
-#define SYSCON_PRESETCTRL_FC9_RST_SHIFT          (15U)
-#define SYSCON_PRESETCTRL_FC9_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
-#define SYSCON_PRESETCTRL_FC4_RST_MASK           (0x8000U)
-#define SYSCON_PRESETCTRL_FC4_RST_SHIFT          (15U)
-#define SYSCON_PRESETCTRL_FC4_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK       (0x10000U)
-#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT      (16U)
-#define SYSCON_PRESETCTRL_USB0HMR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO2_RST_MASK         (0x10000U)
-#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT        (16U)
-#define SYSCON_PRESETCTRL_GPIO2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
-#define SYSCON_PRESETCTRL_FC5_RST_MASK           (0x10000U)
-#define SYSCON_PRESETCTRL_FC5_RST_SHIFT          (16U)
-#define SYSCON_PRESETCTRL_FC5_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO3_RST_MASK         (0x20000U)
-#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT        (17U)
-#define SYSCON_PRESETCTRL_GPIO3_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
-#define SYSCON_PRESETCTRL_FC6_RST_MASK           (0x20000U)
-#define SYSCON_PRESETCTRL_FC6_RST_SHIFT          (17U)
-#define SYSCON_PRESETCTRL_FC6_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK       (0x20000U)
-#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT      (17U)
-#define SYSCON_PRESETCTRL_USB0HSL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
-#define SYSCON_PRESETCTRL_FC7_RST_MASK           (0x40000U)
-#define SYSCON_PRESETCTRL_FC7_RST_SHIFT          (18U)
-#define SYSCON_PRESETCTRL_FC7_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
-#define SYSCON_PRESETCTRL_SHA_RST_MASK           (0x40000U)
-#define SYSCON_PRESETCTRL_SHA_RST_SHIFT          (18U)
-#define SYSCON_PRESETCTRL_SHA_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
-#define SYSCON_PRESETCTRL_PINT_RST_MASK          (0x40000U)
-#define SYSCON_PRESETCTRL_PINT_RST_SHIFT         (18U)
-#define SYSCON_PRESETCTRL_PINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
-#define SYSCON_PRESETCTRL_DMIC_RST_MASK          (0x80000U)
-#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT         (19U)
-#define SYSCON_PRESETCTRL_DMIC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
-#define SYSCON_PRESETCTRL_SC0_RST_MASK           (0x80000U)
-#define SYSCON_PRESETCTRL_SC0_RST_SHIFT          (19U)
-#define SYSCON_PRESETCTRL_SC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
-#define SYSCON_PRESETCTRL_GINT_RST_MASK          (0x80000U)
-#define SYSCON_PRESETCTRL_GINT_RST_SHIFT         (19U)
-#define SYSCON_PRESETCTRL_GINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
-#define SYSCON_PRESETCTRL_SC1_RST_MASK           (0x100000U)
-#define SYSCON_PRESETCTRL_SC1_RST_SHIFT          (20U)
-#define SYSCON_PRESETCTRL_SC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
-#define SYSCON_PRESETCTRL_DMA0_RST_MASK          (0x100000U)
-#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT         (20U)
-#define SYSCON_PRESETCTRL_DMA0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
-#define SYSCON_PRESETCTRL_CRC_RST_MASK           (0x200000U)
-#define SYSCON_PRESETCTRL_CRC_RST_SHIFT          (21U)
-#define SYSCON_PRESETCTRL_CRC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK       (0x400000U)
-#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT      (22U)
-#define SYSCON_PRESETCTRL_CTIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
-#define SYSCON_PRESETCTRL_WWDT_RST_MASK          (0x400000U)
-#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT         (22U)
-#define SYSCON_PRESETCTRL_WWDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0D_RST_MASK         (0x2000000U)
-#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT        (25U)
-#define SYSCON_PRESETCTRL_USB0D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK       (0x4000000U)
-#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT      (26U)
-#define SYSCON_PRESETCTRL_CTIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
-#define SYSCON_PRESETCTRL_ADC0_RST_MASK          (0x8000000U)
-#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT         (27U)
-#define SYSCON_PRESETCTRL_ADC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK       (0x8000000U)
-#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT      (27U)
-#define SYSCON_PRESETCTRL_CTIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
-
-/* The count of SYSCON_PRESETCTRL */
-#define SYSCON_PRESETCTRL_COUNT                  (3U)
-
-/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
-#define SYSCON_PRESETCTRLSET_RST_SET_MASK        (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT       (0U)
-#define SYSCON_PRESETCTRLSET_RST_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
-
-/* The count of SYSCON_PRESETCTRLSET */
-#define SYSCON_PRESETCTRLSET_COUNT               (3U)
-
-/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
-#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK        (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT       (0U)
-#define SYSCON_PRESETCTRLCLR_RST_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
-
-/* The count of SYSCON_PRESETCTRLCLR */
-#define SYSCON_PRESETCTRLCLR_COUNT               (3U)
-
-/*! @name SYSRSTSTAT - System reset status register */
-#define SYSCON_SYSRSTSTAT_POR_MASK               (0x1U)
-#define SYSCON_SYSRSTSTAT_POR_SHIFT              (0U)
-#define SYSCON_SYSRSTSTAT_POR(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
-#define SYSCON_SYSRSTSTAT_EXTRST_MASK            (0x2U)
-#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT           (1U)
-#define SYSCON_SYSRSTSTAT_EXTRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
-#define SYSCON_SYSRSTSTAT_WDT_MASK               (0x4U)
-#define SYSCON_SYSRSTSTAT_WDT_SHIFT              (2U)
-#define SYSCON_SYSRSTSTAT_WDT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
-#define SYSCON_SYSRSTSTAT_BOD_MASK               (0x8U)
-#define SYSCON_SYSRSTSTAT_BOD_SHIFT              (3U)
-#define SYSCON_SYSRSTSTAT_BOD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
-#define SYSCON_SYSRSTSTAT_SYSRST_MASK            (0x10U)
-#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT           (4U)
-#define SYSCON_SYSRSTSTAT_SYSRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
-
-/*! @name AHBCLKCTRL - AHB Clock control n */
-#define SYSCON_AHBCLKCTRL_MRT_MASK               (0x1U)
-#define SYSCON_AHBCLKCTRL_MRT_SHIFT              (0U)
-#define SYSCON_AHBCLKCTRL_MRT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
-#define SYSCON_AHBCLKCTRL_RIT_MASK               (0x2U)
-#define SYSCON_AHBCLKCTRL_RIT_SHIFT              (1U)
-#define SYSCON_AHBCLKCTRL_RIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
-#define SYSCON_AHBCLKCTRL_ROM_MASK               (0x2U)
-#define SYSCON_AHBCLKCTRL_ROM_SHIFT              (1U)
-#define SYSCON_AHBCLKCTRL_ROM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
-#define SYSCON_AHBCLKCTRL_SCT0_MASK              (0x4U)
-#define SYSCON_AHBCLKCTRL_SCT0_SHIFT             (2U)
-#define SYSCON_AHBCLKCTRL_SCT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
-#define SYSCON_AHBCLKCTRL_LCD_MASK               (0x4U)
-#define SYSCON_AHBCLKCTRL_LCD_SHIFT              (2U)
-#define SYSCON_AHBCLKCTRL_LCD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM1_MASK             (0x8U)
-#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT            (3U)
-#define SYSCON_AHBCLKCTRL_SRAM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
-#define SYSCON_AHBCLKCTRL_SDIO_MASK              (0x8U)
-#define SYSCON_AHBCLKCTRL_SDIO_SHIFT             (3U)
-#define SYSCON_AHBCLKCTRL_SDIO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM2_MASK             (0x10U)
-#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT            (4U)
-#define SYSCON_AHBCLKCTRL_SRAM2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
-#define SYSCON_AHBCLKCTRL_USB1H_MASK             (0x10U)
-#define SYSCON_AHBCLKCTRL_USB1H_SHIFT            (4U)
-#define SYSCON_AHBCLKCTRL_USB1H(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM3_MASK             (0x20U)
-#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT            (5U)
-#define SYSCON_AHBCLKCTRL_SRAM3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
-#define SYSCON_AHBCLKCTRL_USB1D_MASK             (0x20U)
-#define SYSCON_AHBCLKCTRL_USB1D_SHIFT            (5U)
-#define SYSCON_AHBCLKCTRL_USB1D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
-#define SYSCON_AHBCLKCTRL_USB1RAM_MASK           (0x40U)
-#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT          (6U)
-#define SYSCON_AHBCLKCTRL_USB1RAM(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
-#define SYSCON_AHBCLKCTRL_FLASH_MASK             (0x80U)
-#define SYSCON_AHBCLKCTRL_FLASH_SHIFT            (7U)
-#define SYSCON_AHBCLKCTRL_FLASH(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
-#define SYSCON_AHBCLKCTRL_EMC_MASK               (0x80U)
-#define SYSCON_AHBCLKCTRL_EMC_SHIFT              (7U)
-#define SYSCON_AHBCLKCTRL_EMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
-#define SYSCON_AHBCLKCTRL_MCAN0_MASK             (0x80U)
-#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT            (7U)
-#define SYSCON_AHBCLKCTRL_MCAN0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
-#define SYSCON_AHBCLKCTRL_FMC_MASK               (0x100U)
-#define SYSCON_AHBCLKCTRL_FMC_SHIFT              (8U)
-#define SYSCON_AHBCLKCTRL_FMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
-#define SYSCON_AHBCLKCTRL_ETH_MASK               (0x100U)
-#define SYSCON_AHBCLKCTRL_ETH_SHIFT              (8U)
-#define SYSCON_AHBCLKCTRL_ETH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
-#define SYSCON_AHBCLKCTRL_MCAN1_MASK             (0x100U)
-#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT            (8U)
-#define SYSCON_AHBCLKCTRL_MCAN1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
-#define SYSCON_AHBCLKCTRL_EEPROM_MASK            (0x200U)
-#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT           (9U)
-#define SYSCON_AHBCLKCTRL_EEPROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO4_MASK             (0x200U)
-#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT            (9U)
-#define SYSCON_AHBCLKCTRL_GPIO4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO5_MASK             (0x400U)
-#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT            (10U)
-#define SYSCON_AHBCLKCTRL_GPIO5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
-#define SYSCON_AHBCLKCTRL_UTICK_MASK             (0x400U)
-#define SYSCON_AHBCLKCTRL_UTICK_SHIFT            (10U)
-#define SYSCON_AHBCLKCTRL_UTICK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
-#define SYSCON_AHBCLKCTRL_SPIFI_MASK             (0x400U)
-#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT            (10U)
-#define SYSCON_AHBCLKCTRL_SPIFI(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
-#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK          (0x800U)
-#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT         (11U)
-#define SYSCON_AHBCLKCTRL_INPUTMUX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
-#define SYSCON_AHBCLKCTRL_AES_MASK               (0x800U)
-#define SYSCON_AHBCLKCTRL_AES_SHIFT              (11U)
-#define SYSCON_AHBCLKCTRL_AES(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK         (0x800U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT        (11U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
-#define SYSCON_AHBCLKCTRL_OTP_MASK               (0x1000U)
-#define SYSCON_AHBCLKCTRL_OTP_SHIFT              (12U)
-#define SYSCON_AHBCLKCTRL_OTP(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK         (0x1000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT        (12U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
-#define SYSCON_AHBCLKCTRL_RNG_MASK               (0x2000U)
-#define SYSCON_AHBCLKCTRL_RNG_SHIFT              (13U)
-#define SYSCON_AHBCLKCTRL_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
-#define SYSCON_AHBCLKCTRL_IOCON_MASK             (0x2000U)
-#define SYSCON_AHBCLKCTRL_IOCON_SHIFT            (13U)
-#define SYSCON_AHBCLKCTRL_IOCON(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK         (0x2000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT        (13U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO0_MASK             (0x4000U)
-#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT            (14U)
-#define SYSCON_AHBCLKCTRL_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK         (0x4000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT        (14U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK         (0x4000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT        (14U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK         (0x8000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT        (15U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK         (0x8000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT        (15U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO1_MASK             (0x8000U)
-#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT            (15U)
-#define SYSCON_AHBCLKCTRL_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO2_MASK             (0x10000U)
-#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT            (16U)
-#define SYSCON_AHBCLKCTRL_GPIO2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
-#define SYSCON_AHBCLKCTRL_USB0HMR_MASK           (0x10000U)
-#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT          (16U)
-#define SYSCON_AHBCLKCTRL_USB0HMR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK         (0x10000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT        (16U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK         (0x20000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT        (17U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO3_MASK             (0x20000U)
-#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT            (17U)
-#define SYSCON_AHBCLKCTRL_GPIO3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
-#define SYSCON_AHBCLKCTRL_USB0HSL_MASK           (0x20000U)
-#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT          (17U)
-#define SYSCON_AHBCLKCTRL_USB0HSL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
-#define SYSCON_AHBCLKCTRL_PINT_MASK              (0x40000U)
-#define SYSCON_AHBCLKCTRL_PINT_SHIFT             (18U)
-#define SYSCON_AHBCLKCTRL_PINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
-#define SYSCON_AHBCLKCTRL_SHA0_MASK              (0x40000U)
-#define SYSCON_AHBCLKCTRL_SHA0_SHIFT             (18U)
-#define SYSCON_AHBCLKCTRL_SHA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK         (0x40000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT        (18U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
-#define SYSCON_AHBCLKCTRL_DMIC_MASK              (0x80000U)
-#define SYSCON_AHBCLKCTRL_DMIC_SHIFT             (19U)
-#define SYSCON_AHBCLKCTRL_DMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
-#define SYSCON_AHBCLKCTRL_GINT_MASK              (0x80000U)
-#define SYSCON_AHBCLKCTRL_GINT_SHIFT             (19U)
-#define SYSCON_AHBCLKCTRL_GINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
-#define SYSCON_AHBCLKCTRL_SC0_MASK               (0x80000U)
-#define SYSCON_AHBCLKCTRL_SC0_SHIFT              (19U)
-#define SYSCON_AHBCLKCTRL_SC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
-#define SYSCON_AHBCLKCTRL_SC1_MASK               (0x100000U)
-#define SYSCON_AHBCLKCTRL_SC1_SHIFT              (20U)
-#define SYSCON_AHBCLKCTRL_SC1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
-#define SYSCON_AHBCLKCTRL_DMA_MASK               (0x100000U)
-#define SYSCON_AHBCLKCTRL_DMA_SHIFT              (20U)
-#define SYSCON_AHBCLKCTRL_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
-#define SYSCON_AHBCLKCTRL_CRC_MASK               (0x200000U)
-#define SYSCON_AHBCLKCTRL_CRC_SHIFT              (21U)
-#define SYSCON_AHBCLKCTRL_CRC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
-#define SYSCON_AHBCLKCTRL_WWDT_MASK              (0x400000U)
-#define SYSCON_AHBCLKCTRL_WWDT_SHIFT             (22U)
-#define SYSCON_AHBCLKCTRL_WWDT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER2_MASK           (0x400000U)
-#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT          (22U)
-#define SYSCON_AHBCLKCTRL_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
-#define SYSCON_AHBCLKCTRL_RTC_MASK               (0x800000U)
-#define SYSCON_AHBCLKCTRL_RTC_SHIFT              (23U)
-#define SYSCON_AHBCLKCTRL_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
-#define SYSCON_AHBCLKCTRL_USB0D_MASK             (0x2000000U)
-#define SYSCON_AHBCLKCTRL_USB0D_SHIFT            (25U)
-#define SYSCON_AHBCLKCTRL_USB0D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER0_MASK           (0x4000000U)
-#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT          (26U)
-#define SYSCON_AHBCLKCTRL_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER1_MASK           (0x8000000U)
-#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT          (27U)
-#define SYSCON_AHBCLKCTRL_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
-#define SYSCON_AHBCLKCTRL_ADC0_MASK              (0x8000000U)
-#define SYSCON_AHBCLKCTRL_ADC0_SHIFT             (27U)
-#define SYSCON_AHBCLKCTRL_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
-
-/* The count of SYSCON_AHBCLKCTRL */
-#define SYSCON_AHBCLKCTRL_COUNT                  (3U)
-
-/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
-#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK        (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT       (0U)
-#define SYSCON_AHBCLKCTRLSET_CLK_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
-
-/* The count of SYSCON_AHBCLKCTRLSET */
-#define SYSCON_AHBCLKCTRLSET_COUNT               (3U)
-
-/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK        (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT       (0U)
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
-
-/* The count of SYSCON_AHBCLKCTRLCLR */
-#define SYSCON_AHBCLKCTRLCLR_COUNT               (3U)
-
-/*! @name MAINCLKSELA - Main clock source select A */
-#define SYSCON_MAINCLKSELA_SEL_MASK              (0x3U)
-#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
-#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
-
-/*! @name MAINCLKSELB - Main clock source select B */
-#define SYSCON_MAINCLKSELB_SEL_MASK              (0x3U)
-#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
-#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
-
-/*! @name CLKOUTSELA - CLKOUT clock source select A */
-#define SYSCON_CLKOUTSELA_SEL_MASK               (0x7U)
-#define SYSCON_CLKOUTSELA_SEL_SHIFT              (0U)
-#define SYSCON_CLKOUTSELA_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
-
-/*! @name SYSPLLCLKSEL - PLL clock source select */
-#define SYSCON_SYSPLLCLKSEL_SEL_MASK             (0x7U)
-#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT            (0U)
-#define SYSCON_SYSPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
-
-/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
-#define SYSCON_AUDPLLCLKSEL_SEL_MASK             (0x7U)
-#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT            (0U)
-#define SYSCON_AUDPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
-
-/*! @name SPIFICLKSEL - SPIFI clock source select */
-#define SYSCON_SPIFICLKSEL_SEL_MASK              (0x7U)
-#define SYSCON_SPIFICLKSEL_SEL_SHIFT             (0U)
-#define SYSCON_SPIFICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
-
-/*! @name ADCCLKSEL - ADC clock source select */
-#define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
-#define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
-#define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
-
-/*! @name USB0CLKSEL - USB0 clock source select */
-#define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
-#define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
-#define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
-
-/*! @name USB1CLKSEL - USB1 clock source select */
-#define SYSCON_USB1CLKSEL_SEL_MASK               (0x7U)
-#define SYSCON_USB1CLKSEL_SEL_SHIFT              (0U)
-#define SYSCON_USB1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
-
-/*! @name FCLKSEL - Flexcomm 0 clock source select */
-#define SYSCON_FCLKSEL_SEL_MASK                  (0x7U)
-#define SYSCON_FCLKSEL_SEL_SHIFT                 (0U)
-#define SYSCON_FCLKSEL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
-
-/* The count of SYSCON_FCLKSEL */
-#define SYSCON_FCLKSEL_COUNT                     (10U)
-
-/*! @name MCLKCLKSEL - MCLK clock source select */
-#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
-#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
-#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
-
-/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
-#define SYSCON_FRGCLKSEL_SEL_MASK                (0x7U)
-#define SYSCON_FRGCLKSEL_SEL_SHIFT               (0U)
-#define SYSCON_FRGCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
-
-/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
-#define SYSCON_DMICCLKSEL_SEL_MASK               (0x7U)
-#define SYSCON_DMICCLKSEL_SEL_SHIFT              (0U)
-#define SYSCON_DMICCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
-
-/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
-#define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
-#define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
-#define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
-
-/*! @name LCDCLKSEL - LCD clock source select */
-#define SYSCON_LCDCLKSEL_SEL_MASK                (0x3U)
-#define SYSCON_LCDCLKSEL_SEL_SHIFT               (0U)
-#define SYSCON_LCDCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
-
-/*! @name SDIOCLKSEL - SDIO clock source select */
-#define SYSCON_SDIOCLKSEL_SEL_MASK               (0x7U)
-#define SYSCON_SDIOCLKSEL_SEL_SHIFT              (0U)
-#define SYSCON_SDIOCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
-
-/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
-#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
-#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
-#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
-#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
-#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
-#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
-#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
-#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
-#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK        (0x80000000U)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT       (31U)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
-
-/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
-#define SYSCON_ARMTRACECLKDIV_DIV_MASK           (0xFFU)
-#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT          (0U)
-#define SYSCON_ARMTRACECLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
-#define SYSCON_ARMTRACECLKDIV_RESET_MASK         (0x20000000U)
-#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT        (29U)
-#define SYSCON_ARMTRACECLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
-#define SYSCON_ARMTRACECLKDIV_HALT_MASK          (0x40000000U)
-#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT         (30U)
-#define SYSCON_ARMTRACECLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK       (0x80000000U)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT      (31U)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
-
-/*! @name CAN0CLKDIV - MCAN0 clock divider */
-#define SYSCON_CAN0CLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_CAN0CLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_CAN0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
-#define SYSCON_CAN0CLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_CAN0CLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_CAN0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
-#define SYSCON_CAN0CLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_CAN0CLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_CAN0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
-#define SYSCON_CAN0CLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_CAN0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
-
-/*! @name CAN1CLKDIV - MCAN1 clock divider */
-#define SYSCON_CAN1CLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_CAN1CLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_CAN1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
-#define SYSCON_CAN1CLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_CAN1CLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_CAN1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
-#define SYSCON_CAN1CLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_CAN1CLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_CAN1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
-#define SYSCON_CAN1CLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_CAN1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
-
-/*! @name SC0CLKDIV - Smartcard0 clock divider */
-#define SYSCON_SC0CLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_SC0CLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_SC0CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
-#define SYSCON_SC0CLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_SC0CLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_SC0CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
-#define SYSCON_SC0CLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_SC0CLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_SC0CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
-#define SYSCON_SC0CLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_SC0CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
-
-/*! @name SC1CLKDIV - Smartcard1 clock divider */
-#define SYSCON_SC1CLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_SC1CLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_SC1CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
-#define SYSCON_SC1CLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_SC1CLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_SC1CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
-#define SYSCON_SC1CLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_SC1CLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_SC1CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
-#define SYSCON_SC1CLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_SC1CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
-
-/*! @name AHBCLKDIV - AHB clock divider */
-#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
-#define SYSCON_AHBCLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_AHBCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
-
-/*! @name CLKOUTDIV - CLKOUT clock divider */
-#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
-#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
-#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
-#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
-#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
-#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
-#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
-#define SYSCON_CLKOUTDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_CLKOUTDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
-
-/*! @name FROHFCLKDIV - FROHF clock divider */
-#define SYSCON_FROHFCLKDIV_DIV_MASK              (0xFFU)
-#define SYSCON_FROHFCLKDIV_DIV_SHIFT             (0U)
-#define SYSCON_FROHFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)
-#define SYSCON_FROHFCLKDIV_RESET_MASK            (0x20000000U)
-#define SYSCON_FROHFCLKDIV_RESET_SHIFT           (29U)
-#define SYSCON_FROHFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)
-#define SYSCON_FROHFCLKDIV_HALT_MASK             (0x40000000U)
-#define SYSCON_FROHFCLKDIV_HALT_SHIFT            (30U)
-#define SYSCON_FROHFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)
-#define SYSCON_FROHFCLKDIV_REQFLAG_MASK          (0x80000000U)
-#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT         (31U)
-#define SYSCON_FROHFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)
-
-/*! @name SPIFICLKDIV - SPIFI clock divider */
-#define SYSCON_SPIFICLKDIV_DIV_MASK              (0xFFU)
-#define SYSCON_SPIFICLKDIV_DIV_SHIFT             (0U)
-#define SYSCON_SPIFICLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
-#define SYSCON_SPIFICLKDIV_RESET_MASK            (0x20000000U)
-#define SYSCON_SPIFICLKDIV_RESET_SHIFT           (29U)
-#define SYSCON_SPIFICLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
-#define SYSCON_SPIFICLKDIV_HALT_MASK             (0x40000000U)
-#define SYSCON_SPIFICLKDIV_HALT_SHIFT            (30U)
-#define SYSCON_SPIFICLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
-#define SYSCON_SPIFICLKDIV_REQFLAG_MASK          (0x80000000U)
-#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT         (31U)
-#define SYSCON_SPIFICLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
-
-/*! @name ADCCLKDIV - ADC clock divider */
-#define SYSCON_ADCCLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
-#define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
-#define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
-#define SYSCON_ADCCLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_ADCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
-
-/*! @name USB0CLKDIV - USB0 clock divider */
-#define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
-#define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
-#define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
-#define SYSCON_USB0CLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_USB0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
-
-/*! @name USB1CLKDIV - USB1 clock divider */
-#define SYSCON_USB1CLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_USB1CLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_USB1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
-#define SYSCON_USB1CLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_USB1CLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_USB1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
-#define SYSCON_USB1CLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_USB1CLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_USB1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
-#define SYSCON_USB1CLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_USB1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
-
-/*! @name FRGCTRL - Fractional rate divider */
-#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
-#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
-#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
-#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
-#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
-#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
-
-/*! @name DMICCLKDIV - DMIC clock divider */
-#define SYSCON_DMICCLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_DMICCLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_DMICCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
-#define SYSCON_DMICCLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_DMICCLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_DMICCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
-#define SYSCON_DMICCLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_DMICCLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_DMICCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
-#define SYSCON_DMICCLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_DMICCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
-
-/*! @name MCLKDIV - I2S MCLK clock divider */
-#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
-#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
-#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
-#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
-#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
-#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
-#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
-#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
-#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
-#define SYSCON_MCLKDIV_REQFLAG_MASK              (0x80000000U)
-#define SYSCON_MCLKDIV_REQFLAG_SHIFT             (31U)
-#define SYSCON_MCLKDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
-
-/*! @name LCDCLKDIV - LCD clock divider */
-#define SYSCON_LCDCLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_LCDCLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_LCDCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
-#define SYSCON_LCDCLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_LCDCLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_LCDCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
-#define SYSCON_LCDCLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_LCDCLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_LCDCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
-#define SYSCON_LCDCLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_LCDCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
-
-/*! @name SCTCLKDIV - SCT/PWM clock divider */
-#define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
-#define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
-#define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
-#define SYSCON_SCTCLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_SCTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
-
-/*! @name EMCCLKDIV - EMC clock divider */
-#define SYSCON_EMCCLKDIV_DIV_MASK                (0xFFU)
-#define SYSCON_EMCCLKDIV_DIV_SHIFT               (0U)
-#define SYSCON_EMCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
-#define SYSCON_EMCCLKDIV_RESET_MASK              (0x20000000U)
-#define SYSCON_EMCCLKDIV_RESET_SHIFT             (29U)
-#define SYSCON_EMCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
-#define SYSCON_EMCCLKDIV_HALT_MASK               (0x40000000U)
-#define SYSCON_EMCCLKDIV_HALT_SHIFT              (30U)
-#define SYSCON_EMCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
-#define SYSCON_EMCCLKDIV_REQFLAG_MASK            (0x80000000U)
-#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT           (31U)
-#define SYSCON_EMCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
-
-/*! @name SDIOCLKDIV - SDIO clock divider */
-#define SYSCON_SDIOCLKDIV_DIV_MASK               (0xFFU)
-#define SYSCON_SDIOCLKDIV_DIV_SHIFT              (0U)
-#define SYSCON_SDIOCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
-#define SYSCON_SDIOCLKDIV_RESET_MASK             (0x20000000U)
-#define SYSCON_SDIOCLKDIV_RESET_SHIFT            (29U)
-#define SYSCON_SDIOCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
-#define SYSCON_SDIOCLKDIV_HALT_MASK              (0x40000000U)
-#define SYSCON_SDIOCLKDIV_HALT_SHIFT             (30U)
-#define SYSCON_SDIOCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
-#define SYSCON_SDIOCLKDIV_REQFLAG_MASK           (0x80000000U)
-#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT          (31U)
-#define SYSCON_SDIOCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
-
-/*! @name FLASHCFG - Flash wait states configuration */
-#define SYSCON_FLASHCFG_FETCHCFG_MASK            (0x3U)
-#define SYSCON_FLASHCFG_FETCHCFG_SHIFT           (0U)
-#define SYSCON_FLASHCFG_FETCHCFG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
-#define SYSCON_FLASHCFG_DATACFG_MASK             (0xCU)
-#define SYSCON_FLASHCFG_DATACFG_SHIFT            (2U)
-#define SYSCON_FLASHCFG_DATACFG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
-#define SYSCON_FLASHCFG_ACCEL_MASK               (0x10U)
-#define SYSCON_FLASHCFG_ACCEL_SHIFT              (4U)
-#define SYSCON_FLASHCFG_ACCEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
-#define SYSCON_FLASHCFG_PREFEN_MASK              (0x20U)
-#define SYSCON_FLASHCFG_PREFEN_SHIFT             (5U)
-#define SYSCON_FLASHCFG_PREFEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
-#define SYSCON_FLASHCFG_PREFOVR_MASK             (0x40U)
-#define SYSCON_FLASHCFG_PREFOVR_SHIFT            (6U)
-#define SYSCON_FLASHCFG_PREFOVR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
-#define SYSCON_FLASHCFG_FLASHTIM_MASK            (0xF000U)
-#define SYSCON_FLASHCFG_FLASHTIM_SHIFT           (12U)
-#define SYSCON_FLASHCFG_FLASHTIM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
-
-/*! @name USB0CLKCTRL - USB0 clock control */
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK       (0x10U)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT      (4U)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
-
-/*! @name USB0CLKSTAT - USB0 clock status */
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
-
-/*! @name FREQMECTRL - Frequency measure register */
-#define SYSCON_FREQMECTRL_CAPVAL_MASK            (0x3FFFU)
-#define SYSCON_FREQMECTRL_CAPVAL_SHIFT           (0U)
-#define SYSCON_FREQMECTRL_CAPVAL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
-#define SYSCON_FREQMECTRL_PROG_MASK              (0x80000000U)
-#define SYSCON_FREQMECTRL_PROG_SHIFT             (31U)
-#define SYSCON_FREQMECTRL_PROG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
-
-/*! @name MCLKIO - MCLK input/output control */
-#define SYSCON_MCLKIO_DIR_MASK                   (0x1U)
-#define SYSCON_MCLKIO_DIR_SHIFT                  (0U)
-#define SYSCON_MCLKIO_DIR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
-
-/*! @name USB1CLKCTRL - USB1 clock control */
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK  (0x10U)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
-
-/*! @name USB1CLKSTAT - USB1 clock status */
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
-
-/*! @name EMCSYSCTRL - EMC system control */
-#define SYSCON_EMCSYSCTRL_EMCSC_MASK             (0x1U)
-#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT            (0U)
-#define SYSCON_EMCSYSCTRL_EMCSC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
-#define SYSCON_EMCSYSCTRL_EMCRD_MASK             (0x2U)
-#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT            (1U)
-#define SYSCON_EMCSYSCTRL_EMCRD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
-#define SYSCON_EMCSYSCTRL_EMCBC_MASK             (0x4U)
-#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT            (2U)
-#define SYSCON_EMCSYSCTRL_EMCBC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK     (0x8U)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT    (3U)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
-
-/*! @name EMCDLYCTRL - EMC clock delay control */
-#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK         (0x1FU)
-#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT        (0U)
-#define SYSCON_EMCDLYCTRL_CMD_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK       (0x1F00U)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT      (8U)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)
-
-/*! @name EMCDLYCAL - EMC delay chain calibration control */
-#define SYSCON_EMCDLYCAL_CALVALUE_MASK           (0xFFU)
-#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT          (0U)
-#define SYSCON_EMCDLYCAL_CALVALUE(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)
-#define SYSCON_EMCDLYCAL_START_MASK              (0x4000U)
-#define SYSCON_EMCDLYCAL_START_SHIFT             (14U)
-#define SYSCON_EMCDLYCAL_START(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)
-#define SYSCON_EMCDLYCAL_DONE_MASK               (0x8000U)
-#define SYSCON_EMCDLYCAL_DONE_SHIFT              (15U)
-#define SYSCON_EMCDLYCAL_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)
-
-/*! @name ETHPHYSEL - Ethernet PHY Selection */
-#define SYSCON_ETHPHYSEL_PHY_SEL_MASK            (0x4U)
-#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT           (2U)
-#define SYSCON_ETHPHYSEL_PHY_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
-
-/*! @name ETHSBDCTRL - Ethernet SBD flow control */
-#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK          (0x3U)
-#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT         (0U)
-#define SYSCON_ETHSBDCTRL_SBD_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
-
-/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK   (0x3U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT  (0U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK     (0x80U)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT    (7U)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK   (0x1F0000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT  (16U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
-
-/*! @name FROCTRL - FRO oscillator control */
-#define SYSCON_FROCTRL_TRIM_MASK                 (0x3FFFU)
-#define SYSCON_FROCTRL_TRIM_SHIFT                (0U)
-#define SYSCON_FROCTRL_TRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
-#define SYSCON_FROCTRL_SEL_MASK                  (0x4000U)
-#define SYSCON_FROCTRL_SEL_SHIFT                 (14U)
-#define SYSCON_FROCTRL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
-#define SYSCON_FROCTRL_FREQTRIM_MASK             (0xFF0000U)
-#define SYSCON_FROCTRL_FREQTRIM_SHIFT            (16U)
-#define SYSCON_FROCTRL_FREQTRIM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
-#define SYSCON_FROCTRL_USBCLKADJ_MASK            (0x1000000U)
-#define SYSCON_FROCTRL_USBCLKADJ_SHIFT           (24U)
-#define SYSCON_FROCTRL_USBCLKADJ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
-#define SYSCON_FROCTRL_USBMODCHG_MASK            (0x2000000U)
-#define SYSCON_FROCTRL_USBMODCHG_SHIFT           (25U)
-#define SYSCON_FROCTRL_USBMODCHG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
-#define SYSCON_FROCTRL_HSPDCLK_MASK              (0x40000000U)
-#define SYSCON_FROCTRL_HSPDCLK_SHIFT             (30U)
-#define SYSCON_FROCTRL_HSPDCLK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
-#define SYSCON_FROCTRL_WRTRIM_MASK               (0x80000000U)
-#define SYSCON_FROCTRL_WRTRIM_SHIFT              (31U)
-#define SYSCON_FROCTRL_WRTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
-
-/*! @name SYSOSCCTRL - System oscillator control */
-#define SYSCON_SYSOSCCTRL_BYPASS_MASK            (0x1U)
-#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT           (0U)
-#define SYSCON_SYSOSCCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
-#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK         (0x2U)
-#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT        (1U)
-#define SYSCON_SYSOSCCTRL_FREQRANGE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
-
-/*! @name WDTOSCCTRL - Watchdog oscillator control */
-#define SYSCON_WDTOSCCTRL_DIVSEL_MASK            (0x1FU)
-#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT           (0U)
-#define SYSCON_WDTOSCCTRL_DIVSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
-#define SYSCON_WDTOSCCTRL_FREQSEL_MASK           (0x3E0U)
-#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT          (5U)
-#define SYSCON_WDTOSCCTRL_FREQSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
-
-/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
-#define SYSCON_RTCOSCCTRL_EN_MASK                (0x1U)
-#define SYSCON_RTCOSCCTRL_EN_SHIFT               (0U)
-#define SYSCON_RTCOSCCTRL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
-
-/*! @name USBPLLCTRL - USB PLL control */
-#define SYSCON_USBPLLCTRL_MSEL_MASK              (0xFFU)
-#define SYSCON_USBPLLCTRL_MSEL_SHIFT             (0U)
-#define SYSCON_USBPLLCTRL_MSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
-#define SYSCON_USBPLLCTRL_PSEL_MASK              (0x300U)
-#define SYSCON_USBPLLCTRL_PSEL_SHIFT             (8U)
-#define SYSCON_USBPLLCTRL_PSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
-#define SYSCON_USBPLLCTRL_NSEL_MASK              (0xC00U)
-#define SYSCON_USBPLLCTRL_NSEL_SHIFT             (10U)
-#define SYSCON_USBPLLCTRL_NSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
-#define SYSCON_USBPLLCTRL_DIRECT_MASK            (0x1000U)
-#define SYSCON_USBPLLCTRL_DIRECT_SHIFT           (12U)
-#define SYSCON_USBPLLCTRL_DIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
-#define SYSCON_USBPLLCTRL_BYPASS_MASK            (0x2000U)
-#define SYSCON_USBPLLCTRL_BYPASS_SHIFT           (13U)
-#define SYSCON_USBPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
-#define SYSCON_USBPLLCTRL_FBSEL_MASK             (0x4000U)
-#define SYSCON_USBPLLCTRL_FBSEL_SHIFT            (14U)
-#define SYSCON_USBPLLCTRL_FBSEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
-
-/*! @name USBPLLSTAT - USB PLL status */
-#define SYSCON_USBPLLSTAT_LOCK_MASK              (0x1U)
-#define SYSCON_USBPLLSTAT_LOCK_SHIFT             (0U)
-#define SYSCON_USBPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
-
-/*! @name SYSPLLCTRL - System PLL control */
-#define SYSCON_SYSPLLCTRL_SELR_MASK              (0xFU)
-#define SYSCON_SYSPLLCTRL_SELR_SHIFT             (0U)
-#define SYSCON_SYSPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
-#define SYSCON_SYSPLLCTRL_SELI_MASK              (0x3F0U)
-#define SYSCON_SYSPLLCTRL_SELI_SHIFT             (4U)
-#define SYSCON_SYSPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
-#define SYSCON_SYSPLLCTRL_SELP_MASK              (0x7C00U)
-#define SYSCON_SYSPLLCTRL_SELP_SHIFT             (10U)
-#define SYSCON_SYSPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
-#define SYSCON_SYSPLLCTRL_BYPASS_MASK            (0x8000U)
-#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT           (15U)
-#define SYSCON_SYSPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK          (0x20000U)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT         (17U)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
-#define SYSCON_SYSPLLCTRL_DIRECTI_MASK           (0x80000U)
-#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT          (19U)
-#define SYSCON_SYSPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
-#define SYSCON_SYSPLLCTRL_DIRECTO_MASK           (0x100000U)
-#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT          (20U)
-#define SYSCON_SYSPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
-
-/*! @name SYSPLLSTAT - PLL status */
-#define SYSCON_SYSPLLSTAT_LOCK_MASK              (0x1U)
-#define SYSCON_SYSPLLSTAT_LOCK_SHIFT             (0U)
-#define SYSCON_SYSPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
-
-/*! @name SYSPLLNDEC - PLL N divider */
-#define SYSCON_SYSPLLNDEC_NDEC_MASK              (0x3FFU)
-#define SYSCON_SYSPLLNDEC_NDEC_SHIFT             (0U)
-#define SYSCON_SYSPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
-#define SYSCON_SYSPLLNDEC_NREQ_MASK              (0x400U)
-#define SYSCON_SYSPLLNDEC_NREQ_SHIFT             (10U)
-#define SYSCON_SYSPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
-
-/*! @name SYSPLLPDEC - PLL P divider */
-#define SYSCON_SYSPLLPDEC_PDEC_MASK              (0x7FU)
-#define SYSCON_SYSPLLPDEC_PDEC_SHIFT             (0U)
-#define SYSCON_SYSPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
-#define SYSCON_SYSPLLPDEC_PREQ_MASK              (0x80U)
-#define SYSCON_SYSPLLPDEC_PREQ_SHIFT             (7U)
-#define SYSCON_SYSPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
-
-/*! @name SYSPLLMDEC - System PLL M divider */
-#define SYSCON_SYSPLLMDEC_MDEC_MASK              (0x1FFFFU)
-#define SYSCON_SYSPLLMDEC_MDEC_SHIFT             (0U)
-#define SYSCON_SYSPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
-#define SYSCON_SYSPLLMDEC_MREQ_MASK              (0x20000U)
-#define SYSCON_SYSPLLMDEC_MREQ_SHIFT             (17U)
-#define SYSCON_SYSPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
-
-/*! @name AUDPLLCTRL - Audio PLL control */
-#define SYSCON_AUDPLLCTRL_SELR_MASK              (0xFU)
-#define SYSCON_AUDPLLCTRL_SELR_SHIFT             (0U)
-#define SYSCON_AUDPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
-#define SYSCON_AUDPLLCTRL_SELI_MASK              (0x3F0U)
-#define SYSCON_AUDPLLCTRL_SELI_SHIFT             (4U)
-#define SYSCON_AUDPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
-#define SYSCON_AUDPLLCTRL_SELP_MASK              (0x7C00U)
-#define SYSCON_AUDPLLCTRL_SELP_SHIFT             (10U)
-#define SYSCON_AUDPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
-#define SYSCON_AUDPLLCTRL_BYPASS_MASK            (0x8000U)
-#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT           (15U)
-#define SYSCON_AUDPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK          (0x20000U)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT         (17U)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
-#define SYSCON_AUDPLLCTRL_DIRECTI_MASK           (0x80000U)
-#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT          (19U)
-#define SYSCON_AUDPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
-#define SYSCON_AUDPLLCTRL_DIRECTO_MASK           (0x100000U)
-#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT          (20U)
-#define SYSCON_AUDPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
-
-/*! @name AUDPLLSTAT - Audio PLL status */
-#define SYSCON_AUDPLLSTAT_LOCK_MASK              (0x1U)
-#define SYSCON_AUDPLLSTAT_LOCK_SHIFT             (0U)
-#define SYSCON_AUDPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
-
-/*! @name AUDPLLNDEC - Audio PLL N divider */
-#define SYSCON_AUDPLLNDEC_NDEC_MASK              (0x3FFU)
-#define SYSCON_AUDPLLNDEC_NDEC_SHIFT             (0U)
-#define SYSCON_AUDPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
-#define SYSCON_AUDPLLNDEC_NREQ_MASK              (0x400U)
-#define SYSCON_AUDPLLNDEC_NREQ_SHIFT             (10U)
-#define SYSCON_AUDPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
-
-/*! @name AUDPLLPDEC - Audio PLL P divider */
-#define SYSCON_AUDPLLPDEC_PDEC_MASK              (0x7FU)
-#define SYSCON_AUDPLLPDEC_PDEC_SHIFT             (0U)
-#define SYSCON_AUDPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
-#define SYSCON_AUDPLLPDEC_PREQ_MASK              (0x80U)
-#define SYSCON_AUDPLLPDEC_PREQ_SHIFT             (7U)
-#define SYSCON_AUDPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
-
-/*! @name AUDPLLMDEC - Audio PLL M divider */
-#define SYSCON_AUDPLLMDEC_MDEC_MASK              (0x1FFFFU)
-#define SYSCON_AUDPLLMDEC_MDEC_SHIFT             (0U)
-#define SYSCON_AUDPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
-#define SYSCON_AUDPLLMDEC_MREQ_MASK              (0x20000U)
-#define SYSCON_AUDPLLMDEC_MREQ_SHIFT             (17U)
-#define SYSCON_AUDPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
-
-/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
-#define SYSCON_AUDPLLFRAC_CTRL_MASK              (0x3FFFFFU)
-#define SYSCON_AUDPLLFRAC_CTRL_SHIFT             (0U)
-#define SYSCON_AUDPLLFRAC_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
-#define SYSCON_AUDPLLFRAC_REQ_MASK               (0x400000U)
-#define SYSCON_AUDPLLFRAC_REQ_SHIFT              (22U)
-#define SYSCON_AUDPLLFRAC_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
-#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK           (0x800000U)
-#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT          (23U)
-#define SYSCON_AUDPLLFRAC_SEL_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
-
-/*! @name PDSLEEPCFG - Power configuration register 0 */
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK     (0x1U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT    (0U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK     (0x2U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT    (1U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK      (0x4U)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT     (2U)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK       (0x8U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT      (3U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK          (0x10U)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT         (4U)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK       (0x20U)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT      (5U)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK           (0x40U)
-#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT          (6U)
-#define SYSCON_PDSLEEPCFG_PDEN_TS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK      (0x80U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT     (7U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK          (0x80U)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT         (7U)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK     (0x100U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT    (8U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK      (0x200U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT     (9U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK         (0x400U)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT        (10U)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK        (0x2000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT       (13U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK        (0x4000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT       (14U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK    (0x8000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT   (15U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK      (0x10000U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT     (16U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK          (0x20000U)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT         (17U)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK         (0x80000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT        (19U)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK      (0x100000U)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT     (20U)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK     (0x200000U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT    (21U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK      (0x400000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT     (22U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK        (0x800000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT       (23U)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK          (0x4000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT         (26U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK          (0x8000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT         (27U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK          (0x10000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT         (28U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK          (0x20000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT         (29U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDSLEEPCFG */
-#define SYSCON_PDSLEEPCFG_COUNT                  (2U)
-
-/*! @name PDRUNCFG - Power configuration register 0 */
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK       (0x1U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT      (0U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK       (0x2U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT      (1U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK        (0x4U)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT       (2U)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK         (0x8U)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT        (3U)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFG_PDEN_FRO_MASK            (0x10U)
-#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT           (4U)
-#define SYSCON_PDRUNCFG_PDEN_FRO(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK         (0x20U)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT        (5U)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_TS_MASK             (0x40U)
-#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT            (6U)
-#define SYSCON_PDRUNCFG_PDEN_TS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK        (0x80U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT       (7U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFG_PDEN_RNG_MASK            (0x80U)
-#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT           (7U)
-#define SYSCON_PDRUNCFG_PDEN_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK       (0x100U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT      (8U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK        (0x200U)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT       (9U)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK           (0x400U)
-#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT          (10U)
-#define SYSCON_PDRUNCFG_PDEN_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          (0x2000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT         (13U)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          (0x4000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT         (14U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK      (0x8000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT     (15U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK        (0x10000U)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT       (16U)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_ROM_MASK            (0x20000U)
-#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT           (17U)
-#define SYSCON_PDRUNCFG_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK           (0x80000U)
-#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT          (19U)
-#define SYSCON_PDRUNCFG_PDEN_VDDA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK        (0x100000U)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT       (20U)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK       (0x200000U)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT      (21U)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK        (0x400000U)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT       (22U)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK          (0x800000U)
-#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT         (23U)
-#define SYSCON_PDRUNCFG_PDEN_VREFP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD3_MASK            (0x4000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT           (26U)
-#define SYSCON_PDRUNCFG_PDEN_VD3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD4_MASK            (0x8000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT           (27U)
-#define SYSCON_PDRUNCFG_PDEN_VD4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD5_MASK            (0x10000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT           (28U)
-#define SYSCON_PDRUNCFG_PDEN_VD5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD6_MASK            (0x20000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT           (29U)
-#define SYSCON_PDRUNCFG_PDEN_VD6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFG */
-#define SYSCON_PDRUNCFG_COUNT                    (2U)
-
-/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK    (0x1U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT   (0U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK    (0x2U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT   (1U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK     (0x4U)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT    (2U)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK      (0x8U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT     (3U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK         (0x10U)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT        (4U)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK      (0x20U)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT     (5U)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK          (0x40U)
-#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT         (6U)
-#define SYSCON_PDRUNCFGSET_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK     (0x80U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT    (7U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK         (0x80U)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT        (7U)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK    (0x100U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT   (8U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK     (0x200U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT    (9U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK        (0x400U)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT       (10U)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK       (0x2000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT      (13U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK       (0x4000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT      (14U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK   (0x8000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT  (15U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK     (0x10000U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT    (16U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK         (0x20000U)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT        (17U)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK        (0x80000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT       (19U)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK     (0x100000U)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT    (20U)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK    (0x200000U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT   (21U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK     (0x400000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT    (22U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK       (0x800000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT      (23U)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK         (0x4000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT        (26U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK         (0x8000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT        (27U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK         (0x10000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT        (28U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK         (0x20000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT        (29U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFGSET */
-#define SYSCON_PDRUNCFGSET_COUNT                 (2U)
-
-/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK    (0x1U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT   (0U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK    (0x2U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT   (1U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK     (0x4U)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT    (2U)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK      (0x8U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT     (3U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK         (0x10U)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT        (4U)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK      (0x20U)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT     (5U)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK          (0x40U)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT         (6U)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK     (0x80U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT    (7U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK         (0x80U)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT        (7U)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK    (0x100U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT   (8U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK     (0x200U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT    (9U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK        (0x400U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT       (10U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK       (0x2000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT      (13U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK       (0x4000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT      (14U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK   (0x8000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT  (15U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK     (0x10000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT    (16U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK         (0x20000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT        (17U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK        (0x80000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT       (19U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK     (0x100000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT    (20U)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK    (0x200000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT   (21U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK     (0x400000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT    (22U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK       (0x800000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT      (23U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK         (0x4000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT        (26U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK         (0x8000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT        (27U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK         (0x10000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT        (28U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK         (0x20000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT        (29U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFGCLR */
-#define SYSCON_PDRUNCFGCLR_COUNT                 (2U)
-
-/*! @name STARTER - Start logic 0 wake-up enable register */
-#define SYSCON_STARTER_WDT_BOD_MASK              (0x1U)
-#define SYSCON_STARTER_WDT_BOD_SHIFT             (0U)
-#define SYSCON_STARTER_WDT_BOD(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
-#define SYSCON_STARTER_PINT4_MASK                (0x1U)
-#define SYSCON_STARTER_PINT4_SHIFT               (0U)
-#define SYSCON_STARTER_PINT4(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
-#define SYSCON_STARTER_PINT5_MASK                (0x2U)
-#define SYSCON_STARTER_PINT5_SHIFT               (1U)
-#define SYSCON_STARTER_PINT5(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
-#define SYSCON_STARTER_DMA_MASK                  (0x2U)
-#define SYSCON_STARTER_DMA_SHIFT                 (1U)
-#define SYSCON_STARTER_DMA(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
-#define SYSCON_STARTER_GINT0_MASK                (0x4U)
-#define SYSCON_STARTER_GINT0_SHIFT               (2U)
-#define SYSCON_STARTER_GINT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
-#define SYSCON_STARTER_PINT6_MASK                (0x4U)
-#define SYSCON_STARTER_PINT6_SHIFT               (2U)
-#define SYSCON_STARTER_PINT6(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
-#define SYSCON_STARTER_GINT1_MASK                (0x8U)
-#define SYSCON_STARTER_GINT1_SHIFT               (3U)
-#define SYSCON_STARTER_GINT1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
-#define SYSCON_STARTER_PINT7_MASK                (0x8U)
-#define SYSCON_STARTER_PINT7_SHIFT               (3U)
-#define SYSCON_STARTER_PINT7(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
-#define SYSCON_STARTER_CTIMER2_MASK              (0x10U)
-#define SYSCON_STARTER_CTIMER2_SHIFT             (4U)
-#define SYSCON_STARTER_CTIMER2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)
-#define SYSCON_STARTER_PIN_INT0_MASK             (0x10U)
-#define SYSCON_STARTER_PIN_INT0_SHIFT            (4U)
-#define SYSCON_STARTER_PIN_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
-#define SYSCON_STARTER_CTIMER4_MASK              (0x20U)
-#define SYSCON_STARTER_CTIMER4_SHIFT             (5U)
-#define SYSCON_STARTER_CTIMER4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)
-#define SYSCON_STARTER_PIN_INT1_MASK             (0x20U)
-#define SYSCON_STARTER_PIN_INT1_SHIFT            (5U)
-#define SYSCON_STARTER_PIN_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
-#define SYSCON_STARTER_PIN_INT2_MASK             (0x40U)
-#define SYSCON_STARTER_PIN_INT2_SHIFT            (6U)
-#define SYSCON_STARTER_PIN_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
-#define SYSCON_STARTER_PIN_INT3_MASK             (0x80U)
-#define SYSCON_STARTER_PIN_INT3_SHIFT            (7U)
-#define SYSCON_STARTER_PIN_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
-#define SYSCON_STARTER_SPIFI_MASK                (0x80U)
-#define SYSCON_STARTER_SPIFI_SHIFT               (7U)
-#define SYSCON_STARTER_SPIFI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)
-#define SYSCON_STARTER_FLEXCOMM8_MASK            (0x100U)
-#define SYSCON_STARTER_FLEXCOMM8_SHIFT           (8U)
-#define SYSCON_STARTER_FLEXCOMM8(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
-#define SYSCON_STARTER_UTICK_MASK                (0x100U)
-#define SYSCON_STARTER_UTICK_SHIFT               (8U)
-#define SYSCON_STARTER_UTICK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
-#define SYSCON_STARTER_MRT_MASK                  (0x200U)
-#define SYSCON_STARTER_MRT_SHIFT                 (9U)
-#define SYSCON_STARTER_MRT(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)
-#define SYSCON_STARTER_FLEXCOMM9_MASK            (0x200U)
-#define SYSCON_STARTER_FLEXCOMM9_SHIFT           (9U)
-#define SYSCON_STARTER_FLEXCOMM9(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
-#define SYSCON_STARTER_CTIMER0_MASK              (0x400U)
-#define SYSCON_STARTER_CTIMER0_SHIFT             (10U)
-#define SYSCON_STARTER_CTIMER0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)
-#define SYSCON_STARTER_CTIMER1_MASK              (0x800U)
-#define SYSCON_STARTER_CTIMER1_SHIFT             (11U)
-#define SYSCON_STARTER_CTIMER1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)
-#define SYSCON_STARTER_SCT0_MASK                 (0x1000U)
-#define SYSCON_STARTER_SCT0_SHIFT                (12U)
-#define SYSCON_STARTER_SCT0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)
-#define SYSCON_STARTER_CTIMER3_MASK              (0x2000U)
-#define SYSCON_STARTER_CTIMER3_SHIFT             (13U)
-#define SYSCON_STARTER_CTIMER3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)
-#define SYSCON_STARTER_FLEXCOMM0_MASK            (0x4000U)
-#define SYSCON_STARTER_FLEXCOMM0_SHIFT           (14U)
-#define SYSCON_STARTER_FLEXCOMM0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
-#define SYSCON_STARTER_FLEXCOMM1_MASK            (0x8000U)
-#define SYSCON_STARTER_FLEXCOMM1_SHIFT           (15U)
-#define SYSCON_STARTER_FLEXCOMM1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
-#define SYSCON_STARTER_USB1_MASK                 (0x8000U)
-#define SYSCON_STARTER_USB1_SHIFT                (15U)
-#define SYSCON_STARTER_USB1(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
-#define SYSCON_STARTER_FLEXCOMM2_MASK            (0x10000U)
-#define SYSCON_STARTER_FLEXCOMM2_SHIFT           (16U)
-#define SYSCON_STARTER_FLEXCOMM2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
-#define SYSCON_STARTER_USB1_ACT_MASK             (0x10000U)
-#define SYSCON_STARTER_USB1_ACT_SHIFT            (16U)
-#define SYSCON_STARTER_USB1_ACT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
-#define SYSCON_STARTER_ENET_INT1_MASK            (0x20000U)
-#define SYSCON_STARTER_ENET_INT1_SHIFT           (17U)
-#define SYSCON_STARTER_ENET_INT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)
-#define SYSCON_STARTER_FLEXCOMM3_MASK            (0x20000U)
-#define SYSCON_STARTER_FLEXCOMM3_SHIFT           (17U)
-#define SYSCON_STARTER_FLEXCOMM3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
-#define SYSCON_STARTER_ENET_INT2_MASK            (0x40000U)
-#define SYSCON_STARTER_ENET_INT2_SHIFT           (18U)
-#define SYSCON_STARTER_ENET_INT2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)
-#define SYSCON_STARTER_FLEXCOMM4_MASK            (0x40000U)
-#define SYSCON_STARTER_FLEXCOMM4_SHIFT           (18U)
-#define SYSCON_STARTER_FLEXCOMM4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
-#define SYSCON_STARTER_ENET_INT0_MASK            (0x80000U)
-#define SYSCON_STARTER_ENET_INT0_SHIFT           (19U)
-#define SYSCON_STARTER_ENET_INT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)
-#define SYSCON_STARTER_FLEXCOMM5_MASK            (0x80000U)
-#define SYSCON_STARTER_FLEXCOMM5_SHIFT           (19U)
-#define SYSCON_STARTER_FLEXCOMM5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
-#define SYSCON_STARTER_FLEXCOMM6_MASK            (0x100000U)
-#define SYSCON_STARTER_FLEXCOMM6_SHIFT           (20U)
-#define SYSCON_STARTER_FLEXCOMM6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
-#define SYSCON_STARTER_FLEXCOMM7_MASK            (0x200000U)
-#define SYSCON_STARTER_FLEXCOMM7_SHIFT           (21U)
-#define SYSCON_STARTER_FLEXCOMM7(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
-#define SYSCON_STARTER_ADC0_SEQA_MASK            (0x400000U)
-#define SYSCON_STARTER_ADC0_SEQA_SHIFT           (22U)
-#define SYSCON_STARTER_ADC0_SEQA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)
-#define SYSCON_STARTER_SMARTCARD0_MASK           (0x800000U)
-#define SYSCON_STARTER_SMARTCARD0_SHIFT          (23U)
-#define SYSCON_STARTER_SMARTCARD0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)
-#define SYSCON_STARTER_ADC0_SEQB_MASK            (0x800000U)
-#define SYSCON_STARTER_ADC0_SEQB_SHIFT           (23U)
-#define SYSCON_STARTER_ADC0_SEQB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)
-#define SYSCON_STARTER_ADC0_THCMP_MASK           (0x1000000U)
-#define SYSCON_STARTER_ADC0_THCMP_SHIFT          (24U)
-#define SYSCON_STARTER_ADC0_THCMP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)
-#define SYSCON_STARTER_SMARTCARD1_MASK           (0x1000000U)
-#define SYSCON_STARTER_SMARTCARD1_SHIFT          (24U)
-#define SYSCON_STARTER_SMARTCARD1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)
-#define SYSCON_STARTER_DMIC_MASK                 (0x2000000U)
-#define SYSCON_STARTER_DMIC_SHIFT                (25U)
-#define SYSCON_STARTER_DMIC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
-#define SYSCON_STARTER_HWVAD_MASK                (0x4000000U)
-#define SYSCON_STARTER_HWVAD_SHIFT               (26U)
-#define SYSCON_STARTER_HWVAD(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
-#define SYSCON_STARTER_USB0_NEEDCLK_MASK         (0x8000000U)
-#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT        (27U)
-#define SYSCON_STARTER_USB0_NEEDCLK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
-#define SYSCON_STARTER_USB0_MASK                 (0x10000000U)
-#define SYSCON_STARTER_USB0_SHIFT                (28U)
-#define SYSCON_STARTER_USB0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
-#define SYSCON_STARTER_RTC_MASK                  (0x20000000U)
-#define SYSCON_STARTER_RTC_SHIFT                 (29U)
-#define SYSCON_STARTER_RTC(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
-
-/* The count of SYSCON_STARTER */
-#define SYSCON_STARTER_COUNT                     (2U)
-
-/*! @name STARTERSET - Set bits in STARTER */
-#define SYSCON_STARTERSET_START_SET_MASK         (0xFFFFFFFFU)
-#define SYSCON_STARTERSET_START_SET_SHIFT        (0U)
-#define SYSCON_STARTERSET_START_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
-
-/* The count of SYSCON_STARTERSET */
-#define SYSCON_STARTERSET_COUNT                  (2U)
-
-/*! @name STARTERCLR - Clear bits in STARTER0 */
-#define SYSCON_STARTERCLR_START_CLR_MASK         (0xFFFFFFFFU)
-#define SYSCON_STARTERCLR_START_CLR_SHIFT        (0U)
-#define SYSCON_STARTERCLR_START_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
-
-/* The count of SYSCON_STARTERCLR */
-#define SYSCON_STARTERCLR_COUNT                  (2U)
-
-/*! @name HWWAKE - Configures special cases of hardware wake-up */
-#define SYSCON_HWWAKE_FORCEWAKE_MASK             (0x1U)
-#define SYSCON_HWWAKE_FORCEWAKE_SHIFT            (0U)
-#define SYSCON_HWWAKE_FORCEWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
-#define SYSCON_HWWAKE_FCWAKE_MASK                (0x2U)
-#define SYSCON_HWWAKE_FCWAKE_SHIFT               (1U)
-#define SYSCON_HWWAKE_FCWAKE(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
-#define SYSCON_HWWAKE_WAKEDMIC_MASK              (0x4U)
-#define SYSCON_HWWAKE_WAKEDMIC_SHIFT             (2U)
-#define SYSCON_HWWAKE_WAKEDMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
-#define SYSCON_HWWAKE_WAKEDMA_MASK               (0x8U)
-#define SYSCON_HWWAKE_WAKEDMA_SHIFT              (3U)
-#define SYSCON_HWWAKE_WAKEDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
-
-/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
-#define SYSCON_AUTOCGOR_RAM0X_MASK               (0x2U)
-#define SYSCON_AUTOCGOR_RAM0X_SHIFT              (1U)
-#define SYSCON_AUTOCGOR_RAM0X(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
-#define SYSCON_AUTOCGOR_RAM1_MASK                (0x4U)
-#define SYSCON_AUTOCGOR_RAM1_SHIFT               (2U)
-#define SYSCON_AUTOCGOR_RAM1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
-#define SYSCON_AUTOCGOR_RAM2_MASK                (0x8U)
-#define SYSCON_AUTOCGOR_RAM2_SHIFT               (3U)
-#define SYSCON_AUTOCGOR_RAM2(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
-#define SYSCON_AUTOCGOR_RAM3_MASK                (0x10U)
-#define SYSCON_AUTOCGOR_RAM3_SHIFT               (4U)
-#define SYSCON_AUTOCGOR_RAM3(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
-
-/*! @name JTAGIDCODE - JTAG ID code register */
-#define SYSCON_JTAGIDCODE_JTAGID_MASK            (0xFFFFFFFFU)
-#define SYSCON_JTAGIDCODE_JTAGID_SHIFT           (0U)
-#define SYSCON_JTAGIDCODE_JTAGID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
-
-/*! @name DEVICE_ID0 - Part ID register */
-#define SYSCON_DEVICE_ID0_PARTID_MASK            (0xFFFFFFFFU)
-#define SYSCON_DEVICE_ID0_PARTID_SHIFT           (0U)
-#define SYSCON_DEVICE_ID0_PARTID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
-
-/*! @name DEVICE_ID1 - Boot ROM and die revision register */
-#define SYSCON_DEVICE_ID1_REVID_MASK             (0xFFFFFFFFU)
-#define SYSCON_DEVICE_ID1_REVID_SHIFT            (0U)
-#define SYSCON_DEVICE_ID1_REVID(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
-
-/*! @name BODCTRL - Brown-Out Detect control */
-#define SYSCON_BODCTRL_BODRSTLEV_MASK            (0x3U)
-#define SYSCON_BODCTRL_BODRSTLEV_SHIFT           (0U)
-#define SYSCON_BODCTRL_BODRSTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
-#define SYSCON_BODCTRL_BODRSTENA_MASK            (0x4U)
-#define SYSCON_BODCTRL_BODRSTENA_SHIFT           (2U)
-#define SYSCON_BODCTRL_BODRSTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
-#define SYSCON_BODCTRL_BODINTLEV_MASK            (0x18U)
-#define SYSCON_BODCTRL_BODINTLEV_SHIFT           (3U)
-#define SYSCON_BODCTRL_BODINTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
-#define SYSCON_BODCTRL_BODINTENA_MASK            (0x20U)
-#define SYSCON_BODCTRL_BODINTENA_SHIFT           (5U)
-#define SYSCON_BODCTRL_BODINTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
-#define SYSCON_BODCTRL_BODRSTSTAT_MASK           (0x40U)
-#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT          (6U)
-#define SYSCON_BODCTRL_BODRSTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
-#define SYSCON_BODCTRL_BODINTSTAT_MASK           (0x80U)
-#define SYSCON_BODCTRL_BODINTSTAT_SHIFT          (7U)
-#define SYSCON_BODCTRL_BODINTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
-
-
-/*!
- * @}
- */ /* end of group SYSCON_Register_Masks */
-
-
-/* SYSCON - Peripheral instance base addresses */
-/** Peripheral SYSCON base address */
-#define SYSCON_BASE                              (0x40000000u)
-/** Peripheral SYSCON base pointer */
-#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
-/** Array initializer of SYSCON peripheral base addresses */
-#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
-/** Array initializer of SYSCON peripheral base pointers */
-#define SYSCON_BASE_PTRS                         { SYSCON }
-
-/*!
- * @}
- */ /* end of group SYSCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USART Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
- * @{
- */
-
-/** USART - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
-  __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
-  __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
-  __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
-  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
-       uint8_t RESERVED_0[12];
-  __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
-  __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
-  __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
-  __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
-       uint8_t RESERVED_1[3536];
-  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
-  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
-  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
-       uint8_t RESERVED_2[4];
-  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
-  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
-  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
-       uint8_t RESERVED_3[4];
-  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
-       uint8_t RESERVED_4[12];
-  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
-       uint8_t RESERVED_5[12];
-  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
-       uint8_t RESERVED_6[440];
-  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
-} USART_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USART Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USART_Register_Masks USART Register Masks
- * @{
- */
-
-/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
-#define USART_CFG_ENABLE_MASK                    (0x1U)
-#define USART_CFG_ENABLE_SHIFT                   (0U)
-#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
-#define USART_CFG_DATALEN_MASK                   (0xCU)
-#define USART_CFG_DATALEN_SHIFT                  (2U)
-#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
-#define USART_CFG_PARITYSEL_MASK                 (0x30U)
-#define USART_CFG_PARITYSEL_SHIFT                (4U)
-#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
-#define USART_CFG_STOPLEN_MASK                   (0x40U)
-#define USART_CFG_STOPLEN_SHIFT                  (6U)
-#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
-#define USART_CFG_MODE32K_MASK                   (0x80U)
-#define USART_CFG_MODE32K_SHIFT                  (7U)
-#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
-#define USART_CFG_LINMODE_MASK                   (0x100U)
-#define USART_CFG_LINMODE_SHIFT                  (8U)
-#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
-#define USART_CFG_CTSEN_MASK                     (0x200U)
-#define USART_CFG_CTSEN_SHIFT                    (9U)
-#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
-#define USART_CFG_SYNCEN_MASK                    (0x800U)
-#define USART_CFG_SYNCEN_SHIFT                   (11U)
-#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
-#define USART_CFG_CLKPOL_MASK                    (0x1000U)
-#define USART_CFG_CLKPOL_SHIFT                   (12U)
-#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
-#define USART_CFG_SYNCMST_MASK                   (0x4000U)
-#define USART_CFG_SYNCMST_SHIFT                  (14U)
-#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
-#define USART_CFG_LOOP_MASK                      (0x8000U)
-#define USART_CFG_LOOP_SHIFT                     (15U)
-#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
-#define USART_CFG_OETA_MASK                      (0x40000U)
-#define USART_CFG_OETA_SHIFT                     (18U)
-#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
-#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
-#define USART_CFG_AUTOADDR_SHIFT                 (19U)
-#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
-#define USART_CFG_OESEL_MASK                     (0x100000U)
-#define USART_CFG_OESEL_SHIFT                    (20U)
-#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
-#define USART_CFG_OEPOL_MASK                     (0x200000U)
-#define USART_CFG_OEPOL_SHIFT                    (21U)
-#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
-#define USART_CFG_RXPOL_MASK                     (0x400000U)
-#define USART_CFG_RXPOL_SHIFT                    (22U)
-#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
-#define USART_CFG_TXPOL_MASK                     (0x800000U)
-#define USART_CFG_TXPOL_SHIFT                    (23U)
-#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
-
-/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
-#define USART_CTL_TXBRKEN_MASK                   (0x2U)
-#define USART_CTL_TXBRKEN_SHIFT                  (1U)
-#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
-#define USART_CTL_ADDRDET_MASK                   (0x4U)
-#define USART_CTL_ADDRDET_SHIFT                  (2U)
-#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
-#define USART_CTL_TXDIS_MASK                     (0x40U)
-#define USART_CTL_TXDIS_SHIFT                    (6U)
-#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
-#define USART_CTL_CC_MASK                        (0x100U)
-#define USART_CTL_CC_SHIFT                       (8U)
-#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
-#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
-#define USART_CTL_CLRCCONRX_SHIFT                (9U)
-#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
-#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
-#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
-#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
-
-/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
-#define USART_STAT_RXIDLE_MASK                   (0x2U)
-#define USART_STAT_RXIDLE_SHIFT                  (1U)
-#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
-#define USART_STAT_TXIDLE_MASK                   (0x8U)
-#define USART_STAT_TXIDLE_SHIFT                  (3U)
-#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
-#define USART_STAT_CTS_MASK                      (0x10U)
-#define USART_STAT_CTS_SHIFT                     (4U)
-#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
-#define USART_STAT_DELTACTS_MASK                 (0x20U)
-#define USART_STAT_DELTACTS_SHIFT                (5U)
-#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
-#define USART_STAT_TXDISSTAT_MASK                (0x40U)
-#define USART_STAT_TXDISSTAT_SHIFT               (6U)
-#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
-#define USART_STAT_RXBRK_MASK                    (0x400U)
-#define USART_STAT_RXBRK_SHIFT                   (10U)
-#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
-#define USART_STAT_DELTARXBRK_MASK               (0x800U)
-#define USART_STAT_DELTARXBRK_SHIFT              (11U)
-#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
-#define USART_STAT_START_MASK                    (0x1000U)
-#define USART_STAT_START_SHIFT                   (12U)
-#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
-#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
-#define USART_STAT_FRAMERRINT_SHIFT              (13U)
-#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
-#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
-#define USART_STAT_PARITYERRINT_SHIFT            (14U)
-#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
-#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
-#define USART_STAT_RXNOISEINT_SHIFT              (15U)
-#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
-#define USART_STAT_ABERR_MASK                    (0x10000U)
-#define USART_STAT_ABERR_SHIFT                   (16U)
-#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
-
-/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
-#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
-#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
-#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
-#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
-#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
-#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
-#define USART_INTENSET_TXDISEN_MASK              (0x40U)
-#define USART_INTENSET_TXDISEN_SHIFT             (6U)
-#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
-#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
-#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
-#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
-#define USART_INTENSET_STARTEN_MASK              (0x1000U)
-#define USART_INTENSET_STARTEN_SHIFT             (12U)
-#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
-#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
-#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
-#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
-#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
-#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
-#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
-#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
-#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
-#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
-#define USART_INTENSET_ABERREN_MASK              (0x10000U)
-#define USART_INTENSET_ABERREN_SHIFT             (16U)
-#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
-
-/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
-#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
-#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
-#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
-#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
-#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
-#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
-#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
-#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
-#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
-#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
-#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
-#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
-#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
-#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
-#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
-#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
-#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
-#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
-#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
-#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
-#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
-#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
-#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
-#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
-#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
-#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
-#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
-
-/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
-#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
-#define USART_BRG_BRGVAL_SHIFT                   (0U)
-#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
-
-/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
-#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
-#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
-#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
-#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
-#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
-#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
-#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
-#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
-#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
-#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
-#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
-#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
-#define USART_INTSTAT_START_MASK                 (0x1000U)
-#define USART_INTSTAT_START_SHIFT                (12U)
-#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
-#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
-#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
-#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
-#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
-#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
-#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
-#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
-#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
-#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
-#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
-#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
-#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
-
-/*! @name OSR - Oversample selection register for asynchronous communication. */
-#define USART_OSR_OSRVAL_MASK                    (0xFU)
-#define USART_OSR_OSRVAL_SHIFT                   (0U)
-#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
-
-/*! @name ADDR - Address register for automatic address matching. */
-#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
-#define USART_ADDR_ADDRESS_SHIFT                 (0U)
-#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
-#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
-#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
-#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
-#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
-#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
-#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
-#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
-#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
-#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
-#define USART_FIFOCFG_DMATX_SHIFT                (12U)
-#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
-#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
-#define USART_FIFOCFG_DMARX_SHIFT                (13U)
-#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
-#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
-#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
-#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
-#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
-#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
-#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
-#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
-#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
-#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
-#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
-#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
-#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
-#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
-#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
-#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
-#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
-#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
-#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
-#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
-#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
-#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
-#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
-#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
-#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
-#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
-#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
-#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
-#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
-#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
-#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
-#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
-#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
-#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
-#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
-#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
-#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
-#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
-#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
-#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
-#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
-#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
-#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
-#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
-#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
-#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
-#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
-#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
-#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
-#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
-#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
-#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
-#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
-#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
-#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
-#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
-#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
-#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
-#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
-#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
-#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
-#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
-#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
-#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
-#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
-#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
-#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
-#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
-#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
-#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
-#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
-#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
-#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
-#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
-#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
-#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
-#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
-#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
-#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
-#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
-#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
-#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
-#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
-#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
-#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
-#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
-#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
-#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
-#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
-#define USART_FIFOWR_TXDATA_SHIFT                (0U)
-#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
-#define USART_FIFORD_RXDATA_SHIFT                (0U)
-#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
-#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
-#define USART_FIFORD_FRAMERR_SHIFT               (13U)
-#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
-#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
-#define USART_FIFORD_PARITYERR_SHIFT             (14U)
-#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
-#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
-#define USART_FIFORD_RXNOISE_SHIFT               (15U)
-#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
-#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
-#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
-#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
-#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
-#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
-#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
-#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
-#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
-#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
-#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
-#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define USART_ID_APERTURE_MASK                   (0xFFU)
-#define USART_ID_APERTURE_SHIFT                  (0U)
-#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
-#define USART_ID_MINOR_REV_MASK                  (0xF00U)
-#define USART_ID_MINOR_REV_SHIFT                 (8U)
-#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
-#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
-#define USART_ID_MAJOR_REV_SHIFT                 (12U)
-#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
-#define USART_ID_ID_MASK                         (0xFFFF0000U)
-#define USART_ID_ID_SHIFT                        (16U)
-#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group USART_Register_Masks */
-
-
-/* USART - Peripheral instance base addresses */
-/** Peripheral USART0 base address */
-#define USART0_BASE                              (0x40086000u)
-/** Peripheral USART0 base pointer */
-#define USART0                                   ((USART_Type *)USART0_BASE)
-/** Peripheral USART1 base address */
-#define USART1_BASE                              (0x40087000u)
-/** Peripheral USART1 base pointer */
-#define USART1                                   ((USART_Type *)USART1_BASE)
-/** Peripheral USART2 base address */
-#define USART2_BASE                              (0x40088000u)
-/** Peripheral USART2 base pointer */
-#define USART2                                   ((USART_Type *)USART2_BASE)
-/** Peripheral USART3 base address */
-#define USART3_BASE                              (0x40089000u)
-/** Peripheral USART3 base pointer */
-#define USART3                                   ((USART_Type *)USART3_BASE)
-/** Peripheral USART4 base address */
-#define USART4_BASE                              (0x4008A000u)
-/** Peripheral USART4 base pointer */
-#define USART4                                   ((USART_Type *)USART4_BASE)
-/** Peripheral USART5 base address */
-#define USART5_BASE                              (0x40096000u)
-/** Peripheral USART5 base pointer */
-#define USART5                                   ((USART_Type *)USART5_BASE)
-/** Peripheral USART6 base address */
-#define USART6_BASE                              (0x40097000u)
-/** Peripheral USART6 base pointer */
-#define USART6                                   ((USART_Type *)USART6_BASE)
-/** Peripheral USART7 base address */
-#define USART7_BASE                              (0x40098000u)
-/** Peripheral USART7 base pointer */
-#define USART7                                   ((USART_Type *)USART7_BASE)
-/** Peripheral USART8 base address */
-#define USART8_BASE                              (0x40099000u)
-/** Peripheral USART8 base pointer */
-#define USART8                                   ((USART_Type *)USART8_BASE)
-/** Peripheral USART9 base address */
-#define USART9_BASE                              (0x4009A000u)
-/** Peripheral USART9 base pointer */
-#define USART9                                   ((USART_Type *)USART9_BASE)
-/** Array initializer of USART peripheral base addresses */
-#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
-/** Array initializer of USART peripheral base pointers */
-#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
-/** Interrupt vectors for the USART peripheral type */
-#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group USART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USB Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
-  __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
-  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
-  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
-  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
-  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
-  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
-  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
-  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
-  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
-  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
-       uint8_t RESERVED_0[8];
-  __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USB Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/*! @name DEVCMDSTAT - USB Device Command/Status register */
-#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
-#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
-#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
-#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
-#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
-#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
-#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
-#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
-#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
-#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
-#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
-#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
-#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
-#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
-#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
-#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
-#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
-#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
-#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
-#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
-#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
-#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
-#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
-#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
-#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
-#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
-#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
-#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
-#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
-#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
-#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
-#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
-#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
-#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
-#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
-#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
-#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
-#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
-
-/*! @name INFO - USB Info register */
-#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
-#define USB_INFO_FRAME_NR_SHIFT                  (0U)
-#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
-#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
-#define USB_INFO_ERR_CODE_SHIFT                  (11U)
-#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
-#define USB_INFO_MINREV_MASK                     (0xFF0000U)
-#define USB_INFO_MINREV_SHIFT                    (16U)
-#define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
-#define USB_INFO_MAJREV_MASK                     (0xFF000000U)
-#define USB_INFO_MAJREV_SHIFT                    (24U)
-#define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
-
-/*! @name EPLISTSTART - USB EP Command/Status List start address */
-#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
-#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
-#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
-
-/*! @name DATABUFSTART - USB Data buffer start address */
-#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
-#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
-#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
-
-/*! @name LPM - USB Link Power Management register */
-#define USB_LPM_HIRD_HW_MASK                     (0xFU)
-#define USB_LPM_HIRD_HW_SHIFT                    (0U)
-#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
-#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
-#define USB_LPM_HIRD_SW_SHIFT                    (4U)
-#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
-#define USB_LPM_DATA_PENDING_MASK                (0x100U)
-#define USB_LPM_DATA_PENDING_SHIFT               (8U)
-#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
-
-/*! @name EPSKIP - USB Endpoint skip */
-#define USB_EPSKIP_SKIP_MASK                     (0x3FFU)
-#define USB_EPSKIP_SKIP_SHIFT                    (0U)
-#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
-
-/*! @name EPINUSE - USB Endpoint Buffer in use */
-#define USB_EPINUSE_BUF_MASK                     (0x3FCU)
-#define USB_EPINUSE_BUF_SHIFT                    (2U)
-#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
-
-/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
-#define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
-#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
-#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
-
-/*! @name INTSTAT - USB interrupt status register */
-#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
-#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
-#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
-#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
-#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
-#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
-#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
-#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
-#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
-#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
-#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
-#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
-#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
-#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
-#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
-#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
-#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
-#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
-#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
-#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
-#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
-#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
-#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
-#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
-#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
-#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
-#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
-#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
-#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
-#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
-#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
-#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
-#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
-#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
-#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
-#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
-
-/*! @name INTEN - USB interrupt enable register */
-#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
-#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
-#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
-#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
-#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
-#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
-#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
-#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
-#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
-
-/*! @name INTSETSTAT - USB set interrupt status register */
-#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
-#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
-#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
-#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
-#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
-#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
-#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
-#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
-
-/*! @name EPTOGGLE - USB Endpoint toggle register */
-#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
-#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
-#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE                                (0x40084000u)
-/** Peripheral USB0 base pointer */
-#define USB0                                     ((USB_Type *)USB0_BASE)
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS                           { USB0_BASE }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS                            { USB0 }
-/** Interrupt vectors for the USB peripheral type */
-#define USB_IRQS                                 { USB0_IRQn }
-#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USBFSH Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
- * @{
- */
-
-/** USBFSH - Register Layout Typedef */
-typedef struct {
-  __I  uint32_t HCREVISION;                        /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
-  __IO uint32_t HCCONTROL;                         /**< Defines the operating modes of the HC, offset: 0x4 */
-  __IO uint32_t HCCOMMANDSTATUS;                   /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
-  __IO uint32_t HCINTERRUPTSTATUS;                 /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
-  __IO uint32_t HCINTERRUPTENABLE;                 /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
-  __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
-  __IO uint32_t HCHCCA;                            /**< Contains the physical address of the host controller communication area, offset: 0x18 */
-  __IO uint32_t HCPERIODCURRENTED;                 /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
-  __IO uint32_t HCCONTROLHEADED;                   /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
-  __IO uint32_t HCCONTROLCURRENTED;                /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
-  __IO uint32_t HCBULKHEADED;                      /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
-  __IO uint32_t HCBULKCURRENTED;                   /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
-  __IO uint32_t HCDONEHEAD;                        /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
-  __IO uint32_t HCFMINTERVAL;                      /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
-  __IO uint32_t HCFMREMAINING;                     /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
-  __IO uint32_t HCFMNUMBER;                        /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
-  __IO uint32_t HCPERIODICSTART;                   /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
-  __IO uint32_t HCLSTHRESHOLD;                     /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
-  __IO uint32_t HCRHDESCRIPTORA;                   /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
-  __IO uint32_t HCRHDESCRIPTORB;                   /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
-  __IO uint32_t HCRHSTATUS;                        /**< This register is divided into two parts, offset: 0x50 */
-  __IO uint32_t HCRHPORTSTATUS;                    /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
-} USBFSH_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USBFSH Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
- * @{
- */
-
-/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
-#define USBFSH_HCREVISION_REV_MASK               (0xFFU)
-#define USBFSH_HCREVISION_REV_SHIFT              (0U)
-#define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
-
-/*! @name HCCONTROL - Defines the operating modes of the HC */
-#define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
-#define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
-#define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
-#define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
-#define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
-#define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
-#define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
-#define USBFSH_HCCONTROL_IE_SHIFT                (3U)
-#define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
-#define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
-#define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
-#define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
-#define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
-#define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
-#define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
-#define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
-#define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
-#define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
-#define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
-#define USBFSH_HCCONTROL_IR_SHIFT                (8U)
-#define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
-#define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
-#define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
-#define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
-#define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
-#define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
-#define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
-
-/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
-#define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
-#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
-#define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
-#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
-#define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
-#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
-#define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
-#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
-#define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
-#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
-#define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
-
-/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
-#define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
-#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
-#define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
-#define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
-#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
-#define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
-#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
-#define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
-#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
-#define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
-#define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
-#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
-#define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
-
-/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
-#define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
-#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
-#define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
-#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
-#define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
-#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
-#define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
-#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
-#define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
-#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
-#define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
-#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
-#define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
-#define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
-#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
-#define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
-#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
-#define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
-
-/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
-#define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
-#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
-#define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
-#define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
-#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
-#define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
-#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
-#define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
-#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
-#define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
-#define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
-#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
-#define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
-#define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
-
-/*! @name HCHCCA - Contains the physical address of the host controller communication area */
-#define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
-#define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
-#define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
-
-/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
-#define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
-#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
-#define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
-
-/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
-#define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
-#define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
-
-/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
-#define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
-#define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
-
-/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
-#define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
-#define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
-#define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
-
-/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
-#define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
-#define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
-#define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
-
-/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
-#define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
-#define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
-#define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
-
-/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
-#define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
-#define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
-#define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
-#define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
-#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
-#define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
-#define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
-#define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
-#define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
-
-/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
-#define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
-#define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
-#define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
-#define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
-#define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
-#define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
-
-/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
-#define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
-#define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
-#define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
-
-/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
-#define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
-#define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
-#define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
-
-/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
-#define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
-#define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
-#define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
-
-/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
-#define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
-#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
-#define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
-#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
-#define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
-#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
-#define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
-#define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
-#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
-#define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
-#define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
-#define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
-
-/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
-#define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
-#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
-#define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
-#define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
-
-/*! @name HCRHSTATUS - This register is divided into two parts */
-#define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
-#define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
-#define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
-#define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
-#define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
-#define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
-#define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
-#define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
-#define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
-#define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
-#define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
-#define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
-#define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
-#define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
-#define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
-#define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
-#define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
-#define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
-
-/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
-#define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
-#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
-#define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
-#define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
-#define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
-#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
-#define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
-#define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
-#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
-#define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
-#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
-#define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
-#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
-#define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
-#define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
-#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
-#define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
-#define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
-#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
-#define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
-#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
-#define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
-#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
-#define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
-#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
-#define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
-#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
-#define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
-
-/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
-#define USBFSH_PORTMODE_ID_MASK                  (0x1U)
-#define USBFSH_PORTMODE_ID_SHIFT                 (0U)
-#define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
-#define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
-#define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
-#define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
-#define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
-#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
-#define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBFSH_Register_Masks */
-
-
-/* USBFSH - Peripheral instance base addresses */
-/** Peripheral USBFSH base address */
-#define USBFSH_BASE                              (0x400A2000u)
-/** Peripheral USBFSH base pointer */
-#define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
-/** Array initializer of USBFSH peripheral base addresses */
-#define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
-/** Array initializer of USBFSH peripheral base pointers */
-#define USBFSH_BASE_PTRS                         { USBFSH }
-/** Interrupt vectors for the USBFSH peripheral type */
-#define USBFSH_IRQS                              { USB0_IRQn }
-#define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBFSH_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USBHSD Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
- * @{
- */
-
-/** USBHSD - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
-  __I  uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
-  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
-  __I  uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
-  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
-  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
-  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
-  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
-  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
-  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
-  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
-       uint8_t RESERVED_0[8];
-  __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t ULPIDEBUG;                         /**< UTMI/ULPI debug register, offset: 0x3C */
-} USBHSD_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USBHSD Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
- * @{
- */
-
-/*! @name DEVCMDSTAT - USB Device Command/Status register */
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK          (0x7FU)
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT         (0U)
-#define USBHSD_DEVCMDSTAT_DEV_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USBHSD_DEVCMDSTAT_DEV_EN_MASK            (0x80U)
-#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT           (7U)
-#define USBHSD_DEVCMDSTAT_DEV_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
-#define USBHSD_DEVCMDSTAT_SETUP_MASK             (0x100U)
-#define USBHSD_DEVCMDSTAT_SETUP_SHIFT            (8U)
-#define USBHSD_DEVCMDSTAT_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK     (0x200U)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT    (9U)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK        (0x400U)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT       (10U)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK           (0x800U)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT          (11U)
-#define USBHSD_DEVCMDSTAT_LPM_SUP(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK       (0x1000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT      (12U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK       (0x2000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT      (13U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK       (0x4000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT      (14U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK       (0x8000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT      (15U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_MASK              (0x10000U)
-#define USBHSD_DEVCMDSTAT_DCON_SHIFT             (16U)
-#define USBHSD_DEVCMDSTAT_DCON(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_MASK              (0x20000U)
-#define USBHSD_DEVCMDSTAT_DSUS_SHIFT             (17U)
-#define USBHSD_DEVCMDSTAT_DSUS(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK           (0x80000U)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT          (19U)
-#define USBHSD_DEVCMDSTAT_LPM_SUS(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK          (0x100000U)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT         (20U)
-#define USBHSD_DEVCMDSTAT_LPM_REWP(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
-#define USBHSD_DEVCMDSTAT_Speed_MASK             (0xC00000U)
-#define USBHSD_DEVCMDSTAT_Speed_SHIFT            (22U)
-#define USBHSD_DEVCMDSTAT_Speed(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_C_MASK            (0x1000000U)
-#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT           (24U)
-#define USBHSD_DEVCMDSTAT_DCON_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_C_MASK            (0x2000000U)
-#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT           (25U)
-#define USBHSD_DEVCMDSTAT_DSUS_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
-#define USBHSD_DEVCMDSTAT_DRES_C_MASK            (0x4000000U)
-#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT           (26U)
-#define USBHSD_DEVCMDSTAT_DRES_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK    (0x10000000U)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT   (28U)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
-
-/*! @name INFO - USB Info register */
-#define USBHSD_INFO_FRAME_NR_MASK                (0x7FFU)
-#define USBHSD_INFO_FRAME_NR_SHIFT               (0U)
-#define USBHSD_INFO_FRAME_NR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
-#define USBHSD_INFO_ERR_CODE_MASK                (0x7800U)
-#define USBHSD_INFO_ERR_CODE_SHIFT               (11U)
-#define USBHSD_INFO_ERR_CODE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
-#define USBHSD_INFO_Minrev_MASK                  (0xFF0000U)
-#define USBHSD_INFO_Minrev_SHIFT                 (16U)
-#define USBHSD_INFO_Minrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
-#define USBHSD_INFO_Majrev_MASK                  (0xFF000000U)
-#define USBHSD_INFO_Majrev_SHIFT                 (24U)
-#define USBHSD_INFO_Majrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
-
-/*! @name EPLISTSTART - USB EP Command/Status List start address */
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK      (0xFFF00U)
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT     (8U)
-#define USBHSD_EPLISTSTART_EP_LIST_PRG(x)        (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK    (0xFFF00000U)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT   (20U)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
-
-/*! @name DATABUFSTART - USB Data buffer start address */
-#define USBHSD_DATABUFSTART_DA_BUF_MASK          (0xFFFFFFFFU)
-#define USBHSD_DATABUFSTART_DA_BUF_SHIFT         (0U)
-#define USBHSD_DATABUFSTART_DA_BUF(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
-
-/*! @name LPM - USB Link Power Management register */
-#define USBHSD_LPM_HIRD_HW_MASK                  (0xFU)
-#define USBHSD_LPM_HIRD_HW_SHIFT                 (0U)
-#define USBHSD_LPM_HIRD_HW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
-#define USBHSD_LPM_HIRD_SW_MASK                  (0xF0U)
-#define USBHSD_LPM_HIRD_SW_SHIFT                 (4U)
-#define USBHSD_LPM_HIRD_SW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
-#define USBHSD_LPM_DATA_PENDING_MASK             (0x100U)
-#define USBHSD_LPM_DATA_PENDING_SHIFT            (8U)
-#define USBHSD_LPM_DATA_PENDING(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
-
-/*! @name EPSKIP - USB Endpoint skip */
-#define USBHSD_EPSKIP_SKIP_MASK                  (0xFFFU)
-#define USBHSD_EPSKIP_SKIP_SHIFT                 (0U)
-#define USBHSD_EPSKIP_SKIP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
-
-/*! @name EPINUSE - USB Endpoint Buffer in use */
-#define USBHSD_EPINUSE_BUF_MASK                  (0xFFCU)
-#define USBHSD_EPINUSE_BUF_SHIFT                 (2U)
-#define USBHSD_EPINUSE_BUF(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
-
-/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
-#define USBHSD_EPBUFCFG_BUF_SB_MASK              (0xFFCU)
-#define USBHSD_EPBUFCFG_BUF_SB_SHIFT             (2U)
-#define USBHSD_EPBUFCFG_BUF_SB(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
-
-/*! @name INTSTAT - USB interrupt status register */
-#define USBHSD_INTSTAT_EP0OUT_MASK               (0x1U)
-#define USBHSD_INTSTAT_EP0OUT_SHIFT              (0U)
-#define USBHSD_INTSTAT_EP0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
-#define USBHSD_INTSTAT_EP0IN_MASK                (0x2U)
-#define USBHSD_INTSTAT_EP0IN_SHIFT               (1U)
-#define USBHSD_INTSTAT_EP0IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
-#define USBHSD_INTSTAT_EP1OUT_MASK               (0x4U)
-#define USBHSD_INTSTAT_EP1OUT_SHIFT              (2U)
-#define USBHSD_INTSTAT_EP1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
-#define USBHSD_INTSTAT_EP1IN_MASK                (0x8U)
-#define USBHSD_INTSTAT_EP1IN_SHIFT               (3U)
-#define USBHSD_INTSTAT_EP1IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
-#define USBHSD_INTSTAT_EP2OUT_MASK               (0x10U)
-#define USBHSD_INTSTAT_EP2OUT_SHIFT              (4U)
-#define USBHSD_INTSTAT_EP2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
-#define USBHSD_INTSTAT_EP2IN_MASK                (0x20U)
-#define USBHSD_INTSTAT_EP2IN_SHIFT               (5U)
-#define USBHSD_INTSTAT_EP2IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
-#define USBHSD_INTSTAT_EP3OUT_MASK               (0x40U)
-#define USBHSD_INTSTAT_EP3OUT_SHIFT              (6U)
-#define USBHSD_INTSTAT_EP3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
-#define USBHSD_INTSTAT_EP3IN_MASK                (0x80U)
-#define USBHSD_INTSTAT_EP3IN_SHIFT               (7U)
-#define USBHSD_INTSTAT_EP3IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
-#define USBHSD_INTSTAT_EP4OUT_MASK               (0x100U)
-#define USBHSD_INTSTAT_EP4OUT_SHIFT              (8U)
-#define USBHSD_INTSTAT_EP4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
-#define USBHSD_INTSTAT_EP4IN_MASK                (0x200U)
-#define USBHSD_INTSTAT_EP4IN_SHIFT               (9U)
-#define USBHSD_INTSTAT_EP4IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
-#define USBHSD_INTSTAT_EP5OUT_MASK               (0x400U)
-#define USBHSD_INTSTAT_EP5OUT_SHIFT              (10U)
-#define USBHSD_INTSTAT_EP5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
-#define USBHSD_INTSTAT_EP5IN_MASK                (0x800U)
-#define USBHSD_INTSTAT_EP5IN_SHIFT               (11U)
-#define USBHSD_INTSTAT_EP5IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
-#define USBHSD_INTSTAT_FRAME_INT_MASK            (0x40000000U)
-#define USBHSD_INTSTAT_FRAME_INT_SHIFT           (30U)
-#define USBHSD_INTSTAT_FRAME_INT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
-#define USBHSD_INTSTAT_DEV_INT_MASK              (0x80000000U)
-#define USBHSD_INTSTAT_DEV_INT_SHIFT             (31U)
-#define USBHSD_INTSTAT_DEV_INT(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
-
-/*! @name INTEN - USB interrupt enable register */
-#define USBHSD_INTEN_EP_INT_EN_MASK              (0xFFFU)
-#define USBHSD_INTEN_EP_INT_EN_SHIFT             (0U)
-#define USBHSD_INTEN_EP_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
-#define USBHSD_INTEN_FRAME_INT_EN_MASK           (0x40000000U)
-#define USBHSD_INTEN_FRAME_INT_EN_SHIFT          (30U)
-#define USBHSD_INTEN_FRAME_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
-#define USBHSD_INTEN_DEV_INT_EN_MASK             (0x80000000U)
-#define USBHSD_INTEN_DEV_INT_EN_SHIFT            (31U)
-#define USBHSD_INTEN_DEV_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
-
-/*! @name INTSETSTAT - USB set interrupt status register */
-#define USBHSD_INTSETSTAT_EP_SET_INT_MASK        (0xFFFU)
-#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT       (0U)
-#define USBHSD_INTSETSTAT_EP_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK     (0x40000000U)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT    (30U)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK       (0x80000000U)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT      (31U)
-#define USBHSD_INTSETSTAT_DEV_SET_INT(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
-
-/*! @name EPTOGGLE - USB Endpoint toggle register */
-#define USBHSD_EPTOGGLE_TOGGLE_MASK              (0x3FFFFFFFU)
-#define USBHSD_EPTOGGLE_TOGGLE_SHIFT             (0U)
-#define USBHSD_EPTOGGLE_TOGGLE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
-
-/*! @name ULPIDEBUG - UTMI/ULPI debug register */
-#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK           (0xFFU)
-#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT          (0U)
-#define USBHSD_ULPIDEBUG_PHY_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)
-#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK          (0xFF00U)
-#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT         (8U)
-#define USBHSD_ULPIDEBUG_PHY_WDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)
-#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK          (0xFF0000U)
-#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT         (16U)
-#define USBHSD_ULPIDEBUG_PHY_RDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)
-#define USBHSD_ULPIDEBUG_PHY_RW_MASK             (0x1000000U)
-#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT            (24U)
-#define USBHSD_ULPIDEBUG_PHY_RW(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK         (0x2000000U)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT        (25U)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)
-#define USBHSD_ULPIDEBUG_PHY_MODE_MASK           (0x80000000U)
-#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT          (31U)
-#define USBHSD_ULPIDEBUG_PHY_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBHSD_Register_Masks */
-
-
-/* USBHSD - Peripheral instance base addresses */
-/** Peripheral USBHSD base address */
-#define USBHSD_BASE                              (0x40094000u)
-/** Peripheral USBHSD base pointer */
-#define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
-/** Array initializer of USBHSD peripheral base addresses */
-#define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
-/** Array initializer of USBHSD peripheral base pointers */
-#define USBHSD_BASE_PTRS                         { USBHSD }
-/** Interrupt vectors for the USBHSD peripheral type */
-#define USBHSD_IRQS                              { USB1_IRQn }
-#define USBHSD_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBHSD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USBHSH Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
- * @{
- */
-
-/** USBHSH - Register Layout Typedef */
-typedef struct {
-  __I  uint32_t CAPLENGTH_CHIPID;                  /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
-  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x4 */
-  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x8 */
-  __IO uint32_t FLADJ_FRINDEX;                     /**< Frame Length Adjustment, offset: 0xC */
-  __IO uint32_t ATL_PTD_BASE_ADDR;                 /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
-  __IO uint32_t ISO_PTD_BASE_ADDR;                 /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
-  __IO uint32_t INT_PTD_BASE_ADDR;                 /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
-  __IO uint32_t DATA_PAYLOAD_BASE_ADDR;            /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
-  __IO uint32_t USBCMD;                            /**< USB Command register, offset: 0x20 */
-  __IO uint32_t USBSTS;                            /**< USB Interrupt Status register, offset: 0x24 */
-  __IO uint32_t USBINTR;                           /**< USB Interrupt Enable register, offset: 0x28 */
-  __IO uint32_t PORTSC1;                           /**< Port Status and Control register, offset: 0x2C */
-  __IO uint32_t ATL_PTD_DONE_MAP;                  /**< Done map for each ATL PTD, offset: 0x30 */
-  __IO uint32_t ATL_PTD_SKIP_MAP;                  /**< Skip map for each ATL PTD, offset: 0x34 */
-  __IO uint32_t ISO_PTD_DONE_MAP;                  /**< Done map for each ISO PTD, offset: 0x38 */
-  __IO uint32_t ISO_PTD_SKIP_MAP;                  /**< Skip map for each ISO PTD, offset: 0x3C */
-  __IO uint32_t INT_PTD_DONE_MAP;                  /**< Done map for each INT PTD, offset: 0x40 */
-  __IO uint32_t INT_PTD_SKIP_MAP;                  /**< Skip map for each INT PTD, offset: 0x44 */
-  __IO uint32_t LAST_PTD_INUSE;                    /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
-  __IO uint32_t UTMIPLUS_ULPI_DEBUG;               /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */
-  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
-} USBHSH_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USBHSH Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
- * @{
- */
-
-/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK   (0xFFU)
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT  (0U)
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK      (0xFFFF0000U)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT     (16U)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
-
-/*! @name HCSPARAMS - Host Controller Structural Parameters */
-#define USBHSH_HCSPARAMS_N_PORTS_MASK            (0xFU)
-#define USBHSH_HCSPARAMS_N_PORTS_SHIFT           (0U)
-#define USBHSH_HCSPARAMS_N_PORTS(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
-#define USBHSH_HCSPARAMS_PPC_MASK                (0x10U)
-#define USBHSH_HCSPARAMS_PPC_SHIFT               (4U)
-#define USBHSH_HCSPARAMS_PPC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
-#define USBHSH_HCSPARAMS_P_INDICATOR_MASK        (0x10000U)
-#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT       (16U)
-#define USBHSH_HCSPARAMS_P_INDICATOR(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
-
-/*! @name HCCPARAMS - Host Controller Capability Parameters */
-#define USBHSH_HCCPARAMS_LPMC_MASK               (0x20000U)
-#define USBHSH_HCCPARAMS_LPMC_SHIFT              (17U)
-#define USBHSH_HCCPARAMS_LPMC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
-
-/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
-#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK          (0x3FU)
-#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT         (0U)
-#define USBHSH_FLADJ_FRINDEX_FLADJ(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK        (0x3FFF0000U)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT       (16U)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
-
-/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK    (0x1F0U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT   (4U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK   (0xFFFFFE00U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT  (9U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
-
-/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK  (0x3E0U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK   (0xFFFFFC00U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT  (10U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
-
-/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK  (0x3E0U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK   (0xFFFFFC00U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT  (10U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
-
-/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
-
-/*! @name USBCMD - USB Command register */
-#define USBHSH_USBCMD_RS_MASK                    (0x1U)
-#define USBHSH_USBCMD_RS_SHIFT                   (0U)
-#define USBHSH_USBCMD_RS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
-#define USBHSH_USBCMD_HCRESET_MASK               (0x2U)
-#define USBHSH_USBCMD_HCRESET_SHIFT              (1U)
-#define USBHSH_USBCMD_HCRESET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
-#define USBHSH_USBCMD_FLS_MASK                   (0xCU)
-#define USBHSH_USBCMD_FLS_SHIFT                  (2U)
-#define USBHSH_USBCMD_FLS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
-#define USBHSH_USBCMD_LHCR_MASK                  (0x80U)
-#define USBHSH_USBCMD_LHCR_SHIFT                 (7U)
-#define USBHSH_USBCMD_LHCR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
-#define USBHSH_USBCMD_ATL_EN_MASK                (0x100U)
-#define USBHSH_USBCMD_ATL_EN_SHIFT               (8U)
-#define USBHSH_USBCMD_ATL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
-#define USBHSH_USBCMD_ISO_EN_MASK                (0x200U)
-#define USBHSH_USBCMD_ISO_EN_SHIFT               (9U)
-#define USBHSH_USBCMD_ISO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
-#define USBHSH_USBCMD_INT_EN_MASK                (0x400U)
-#define USBHSH_USBCMD_INT_EN_SHIFT               (10U)
-#define USBHSH_USBCMD_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
-#define USBHSH_USBCMD_HIRD_MASK                  (0xF000000U)
-#define USBHSH_USBCMD_HIRD_SHIFT                 (24U)
-#define USBHSH_USBCMD_HIRD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
-#define USBHSH_USBCMD_LPM_RWU_MASK               (0x10000000U)
-#define USBHSH_USBCMD_LPM_RWU_SHIFT              (28U)
-#define USBHSH_USBCMD_LPM_RWU(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
-
-/*! @name USBSTS - USB Interrupt Status register */
-#define USBHSH_USBSTS_PCD_MASK                   (0x4U)
-#define USBHSH_USBSTS_PCD_SHIFT                  (2U)
-#define USBHSH_USBSTS_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
-#define USBHSH_USBSTS_FLR_MASK                   (0x8U)
-#define USBHSH_USBSTS_FLR_SHIFT                  (3U)
-#define USBHSH_USBSTS_FLR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
-#define USBHSH_USBSTS_ATL_IRQ_MASK               (0x10000U)
-#define USBHSH_USBSTS_ATL_IRQ_SHIFT              (16U)
-#define USBHSH_USBSTS_ATL_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
-#define USBHSH_USBSTS_ISO_IRQ_MASK               (0x20000U)
-#define USBHSH_USBSTS_ISO_IRQ_SHIFT              (17U)
-#define USBHSH_USBSTS_ISO_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
-#define USBHSH_USBSTS_INT_IRQ_MASK               (0x40000U)
-#define USBHSH_USBSTS_INT_IRQ_SHIFT              (18U)
-#define USBHSH_USBSTS_INT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
-#define USBHSH_USBSTS_SOF_IRQ_MASK               (0x80000U)
-#define USBHSH_USBSTS_SOF_IRQ_SHIFT              (19U)
-#define USBHSH_USBSTS_SOF_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
-
-/*! @name USBINTR - USB Interrupt Enable register */
-#define USBHSH_USBINTR_PCDE_MASK                 (0x4U)
-#define USBHSH_USBINTR_PCDE_SHIFT                (2U)
-#define USBHSH_USBINTR_PCDE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
-#define USBHSH_USBINTR_FLRE_MASK                 (0x8U)
-#define USBHSH_USBINTR_FLRE_SHIFT                (3U)
-#define USBHSH_USBINTR_FLRE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
-#define USBHSH_USBINTR_ATL_IRQ_E_MASK            (0x10000U)
-#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT           (16U)
-#define USBHSH_USBINTR_ATL_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
-#define USBHSH_USBINTR_ISO_IRQ_E_MASK            (0x20000U)
-#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT           (17U)
-#define USBHSH_USBINTR_ISO_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
-#define USBHSH_USBINTR_INT_IRQ_E_MASK            (0x40000U)
-#define USBHSH_USBINTR_INT_IRQ_E_SHIFT           (18U)
-#define USBHSH_USBINTR_INT_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
-#define USBHSH_USBINTR_SOF_E_MASK                (0x80000U)
-#define USBHSH_USBINTR_SOF_E_SHIFT               (19U)
-#define USBHSH_USBINTR_SOF_E(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
-
-/*! @name PORTSC1 - Port Status and Control register */
-#define USBHSH_PORTSC1_CCS_MASK                  (0x1U)
-#define USBHSH_PORTSC1_CCS_SHIFT                 (0U)
-#define USBHSH_PORTSC1_CCS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
-#define USBHSH_PORTSC1_CSC_MASK                  (0x2U)
-#define USBHSH_PORTSC1_CSC_SHIFT                 (1U)
-#define USBHSH_PORTSC1_CSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
-#define USBHSH_PORTSC1_PED_MASK                  (0x4U)
-#define USBHSH_PORTSC1_PED_SHIFT                 (2U)
-#define USBHSH_PORTSC1_PED(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
-#define USBHSH_PORTSC1_PEDC_MASK                 (0x8U)
-#define USBHSH_PORTSC1_PEDC_SHIFT                (3U)
-#define USBHSH_PORTSC1_PEDC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
-#define USBHSH_PORTSC1_OCA_MASK                  (0x10U)
-#define USBHSH_PORTSC1_OCA_SHIFT                 (4U)
-#define USBHSH_PORTSC1_OCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
-#define USBHSH_PORTSC1_OCC_MASK                  (0x20U)
-#define USBHSH_PORTSC1_OCC_SHIFT                 (5U)
-#define USBHSH_PORTSC1_OCC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
-#define USBHSH_PORTSC1_FPR_MASK                  (0x40U)
-#define USBHSH_PORTSC1_FPR_SHIFT                 (6U)
-#define USBHSH_PORTSC1_FPR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
-#define USBHSH_PORTSC1_SUSP_MASK                 (0x80U)
-#define USBHSH_PORTSC1_SUSP_SHIFT                (7U)
-#define USBHSH_PORTSC1_SUSP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
-#define USBHSH_PORTSC1_PR_MASK                   (0x100U)
-#define USBHSH_PORTSC1_PR_SHIFT                  (8U)
-#define USBHSH_PORTSC1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
-#define USBHSH_PORTSC1_SUS_L1_MASK               (0x200U)
-#define USBHSH_PORTSC1_SUS_L1_SHIFT              (9U)
-#define USBHSH_PORTSC1_SUS_L1(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
-#define USBHSH_PORTSC1_LS_MASK                   (0xC00U)
-#define USBHSH_PORTSC1_LS_SHIFT                  (10U)
-#define USBHSH_PORTSC1_LS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
-#define USBHSH_PORTSC1_PP_MASK                   (0x1000U)
-#define USBHSH_PORTSC1_PP_SHIFT                  (12U)
-#define USBHSH_PORTSC1_PP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
-#define USBHSH_PORTSC1_PIC_MASK                  (0xC000U)
-#define USBHSH_PORTSC1_PIC_SHIFT                 (14U)
-#define USBHSH_PORTSC1_PIC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
-#define USBHSH_PORTSC1_PTC_MASK                  (0xF0000U)
-#define USBHSH_PORTSC1_PTC_SHIFT                 (16U)
-#define USBHSH_PORTSC1_PTC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
-#define USBHSH_PORTSC1_PSPD_MASK                 (0x300000U)
-#define USBHSH_PORTSC1_PSPD_SHIFT                (20U)
-#define USBHSH_PORTSC1_PSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
-#define USBHSH_PORTSC1_WOO_MASK                  (0x400000U)
-#define USBHSH_PORTSC1_WOO_SHIFT                 (22U)
-#define USBHSH_PORTSC1_WOO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
-#define USBHSH_PORTSC1_SUS_STAT_MASK             (0x1800000U)
-#define USBHSH_PORTSC1_SUS_STAT_SHIFT            (23U)
-#define USBHSH_PORTSC1_SUS_STAT(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
-#define USBHSH_PORTSC1_DEV_ADD_MASK              (0xFE000000U)
-#define USBHSH_PORTSC1_DEV_ADD_SHIFT             (25U)
-#define USBHSH_PORTSC1_DEV_ADD(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
-
-/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK    (0xFFFFFFFFU)
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT   (0U)
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
-
-/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK    (0xFFFFFFFFU)
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT   (0U)
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
-
-/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK    (0xFFFFFFFFU)
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT   (0U)
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
-
-/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK    (0xFFFFFFFFU)
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT   (0U)
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
-
-/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK    (0xFFFFFFFFU)
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT   (0U)
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
-
-/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK    (0xFFFFFFFFU)
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT   (0U)
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
-
-/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK      (0x1FU)
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT     (0U)
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK      (0x1F00U)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT     (8U)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK      (0x1F0000U)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT     (16U)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
-
-/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK   (0x1000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT  (24U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)
-
-/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
-#define USBHSH_PORTMODE_ID0_MASK                 (0x1U)
-#define USBHSH_PORTMODE_ID0_SHIFT                (0U)
-#define USBHSH_PORTMODE_ID0(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
-#define USBHSH_PORTMODE_ID0_EN_MASK              (0x100U)
-#define USBHSH_PORTMODE_ID0_EN_SHIFT             (8U)
-#define USBHSH_PORTMODE_ID0_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
-#define USBHSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
-#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
-#define USBHSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK       (0x40000U)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT      (18U)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
-#define USBHSH_PORTMODE_SW_PDCOM_MASK            (0x80000U)
-#define USBHSH_PORTMODE_SW_PDCOM_SHIFT           (19U)
-#define USBHSH_PORTMODE_SW_PDCOM(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBHSH_Register_Masks */
-
-
-/* USBHSH - Peripheral instance base addresses */
-/** Peripheral USBHSH base address */
-#define USBHSH_BASE                              (0x400A3000u)
-/** Peripheral USBHSH base pointer */
-#define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
-/** Array initializer of USBHSH peripheral base addresses */
-#define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
-/** Array initializer of USBHSH peripheral base pointers */
-#define USBHSH_BASE_PTRS                         { USBHSH }
-/** Interrupt vectors for the USBHSH peripheral type */
-#define USBHSH_IRQS                              { USB1_IRQn }
-#define USBHSH_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBHSH_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- UTICK Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
- * @{
- */
-
-/** UTICK - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
-  __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
-  __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
-  __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
-  __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
-} UTICK_Type;
-
-/* ----------------------------------------------------------------------------
-   -- UTICK Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UTICK_Register_Masks UTICK Register Masks
- * @{
- */
-
-/*! @name CTRL - Control register. */
-#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
-#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
-#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
-#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
-#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
-#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
-
-/*! @name STAT - Status register. */
-#define UTICK_STAT_INTR_MASK                     (0x1U)
-#define UTICK_STAT_INTR_SHIFT                    (0U)
-#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
-#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
-#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
-#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
-
-/*! @name CFG - Capture configuration register. */
-#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
-#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
-#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
-#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
-#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
-#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
-#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
-#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
-#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
-#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
-#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
-#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
-#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
-#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
-#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
-#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
-#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
-#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
-#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
-#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
-#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
-#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
-#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
-#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
-
-/*! @name CAPCLR - Capture clear register. */
-#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
-#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
-#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
-#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
-#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
-#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
-#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
-#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
-#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
-#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
-#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
-#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
-
-/*! @name CAP - Capture register . */
-#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
-#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
-#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
-#define UTICK_CAP_VALID_MASK                     (0x80000000U)
-#define UTICK_CAP_VALID_SHIFT                    (31U)
-#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
-
-/* The count of UTICK_CAP */
-#define UTICK_CAP_COUNT                          (4U)
-
-
-/*!
- * @}
- */ /* end of group UTICK_Register_Masks */
-
-
-/* UTICK - Peripheral instance base addresses */
-/** Peripheral UTICK0 base address */
-#define UTICK0_BASE                              (0x4000E000u)
-/** Peripheral UTICK0 base pointer */
-#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
-/** Array initializer of UTICK peripheral base addresses */
-#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
-/** Array initializer of UTICK peripheral base pointers */
-#define UTICK_BASE_PTRS                          { UTICK0 }
-/** Interrupt vectors for the UTICK peripheral type */
-#define UTICK_IRQS                               { UTICK0_IRQn }
-
-/*!
- * @}
- */ /* end of group UTICK_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- WWDT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
- * @{
- */
-
-/** WWDT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
-  __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
-  __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
-  __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
-  __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
-} WWDT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- WWDT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WWDT_Register_Masks WWDT Register Masks
- * @{
- */
-
-/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-#define WWDT_MOD_WDEN_MASK                       (0x1U)
-#define WWDT_MOD_WDEN_SHIFT                      (0U)
-#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
-#define WWDT_MOD_WDRESET_MASK                    (0x2U)
-#define WWDT_MOD_WDRESET_SHIFT                   (1U)
-#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
-#define WWDT_MOD_WDTOF_MASK                      (0x4U)
-#define WWDT_MOD_WDTOF_SHIFT                     (2U)
-#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
-#define WWDT_MOD_WDINT_MASK                      (0x8U)
-#define WWDT_MOD_WDINT_SHIFT                     (3U)
-#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
-#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
-#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
-#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
-#define WWDT_MOD_LOCK_MASK                       (0x20U)
-#define WWDT_MOD_LOCK_SHIFT                      (5U)
-#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
-
-/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
-#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
-#define WWDT_TC_COUNT_SHIFT                      (0U)
-#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
-
-/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
-#define WWDT_FEED_FEED_MASK                      (0xFFU)
-#define WWDT_FEED_FEED_SHIFT                     (0U)
-#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
-
-/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
-#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
-#define WWDT_TV_COUNT_SHIFT                      (0U)
-#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
-
-/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
-#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
-#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
-#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
-
-/*! @name WINDOW - Watchdog Window compare value. */
-#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
-#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
-#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
-
-
-/*!
- * @}
- */ /* end of group WWDT_Register_Masks */
-
-
-/* WWDT - Peripheral instance base addresses */
-/** Peripheral WWDT base address */
-#define WWDT_BASE                                (0x4000C000u)
-/** Peripheral WWDT base pointer */
-#define WWDT                                     ((WWDT_Type *)WWDT_BASE)
-/** Array initializer of WWDT peripheral base addresses */
-#define WWDT_BASE_ADDRS                          { WWDT_BASE }
-/** Array initializer of WWDT peripheral base pointers */
-#define WWDT_BASE_PTRS                           { WWDT }
-/** Interrupt vectors for the WWDT peripheral type */
-#define WWDT_IRQS                                { WDT_BOD_IRQn }
-
-/*!
- * @}
- */ /* end of group WWDT_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
-  #pragma pop
-#elif defined(__GNUC__)
-  /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma language=default
-#else
-  #error Not supported compiler type
-#endif
-
-/*!
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
- * @{
- */
-
-#if defined(__ARMCC_VERSION)
-  #if (__ARMCC_VERSION >= 6010050)
-    #pragma clang system_header
-  #endif
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma system_include
-#endif
-
-/**
- * @brief Mask and left-shift a bit field value for use in a register bit range.
- * @param field Name of the register bit field.
- * @param value Value of the bit field.
- * @return Masked and shifted value.
- */
-#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
-/**
- * @brief Mask and right-shift a register value to extract a bit field value.
- * @param field Name of the register bit field.
- * @param value Value of the register.
- * @return Masked and shifted bit field value.
- */
-#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
-
-/*!
- * @}
- */ /* end of group Bit_Field_Generic_Macros */
-
-
-/* ----------------------------------------------------------------------------
-   -- SDK Compatibility
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
- * @{
- */
-
-/** EMC CS base address */
-#define EMC_CS0_BASE                                (0x80000000u)
-#define EMC_CS1_BASE                                (0x90000000u)
-#define EMC_CS2_BASE                                (0x98000000u)
-#define EMC_CS3_BASE                                (0x9C000000u)
-#define EMC_DYCS0_BASE                              (0xA0000000u)
-#define EMC_DYCS1_BASE                              (0xB0000000u)
-#define EMC_DYCS2_BASE                              (0xC0000000u)
-#define EMC_DYCS3_BASE                              (0xD0000000u)
-#define EMC_CS_ADDRESS                              {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
-#define EMC_DYCS_ADDRESS                            {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
-
-/** OTP API */
-typedef struct {
-  uint32_t (*otpInit)(void);                                    /** Initializes OTP controller */
-  uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask);        /** Unlock one or more OTP banks for write access */
-  uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask);       /** Lock one or more OTP banks for write access */
-  uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
-                                          uint32_t lockWrite);  /** Locks or unlocks write access to a register of an OTP bank and the write lock */
-  uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
-                                         uint32_t lockWrite);   /** Locks or unlocks read access to a register of an OTP bank and the write lock */
-  uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value);  /** Program a single register in an OTP bank */
-  uint32_t RESERVED_0[5];
-  uint32_t (*rngRead)(void);                                    /** Returns 32-bit number from hardware random number generator */
-  uint32_t (*otpGetDriverVersion)(void);                        /** Returns the version of the OTP driver in ROM */
-} OTP_API_Type;
-
-/** ROM API */
-typedef struct {
-  __I uint32_t usbdApiBase;                      /** USB API Base */
-      uint32_t RESERVED_0[13];
-  __I OTP_API_Type *otpApiBase;                  /** OTP API Base */
-  __I uint32_t aesApiBase;                       /** AES API Base */
-  __I uint32_t secureApiBase;                    /** Secure API Base */
-} ROM_API_Type;
-
-/** ROM API base address */
-#define ROM_API_BASE                             (0x03000200u)
-/** ROM API base pointer */
-#define ROM_API                                  (*(ROM_API_Type**) ROM_API_BASE)
-/** OTP API base pointer */
-#define OTP_API                                  (ROM_API->otpApiBase)
-
-/*!
- * @}
- */ /* end of group SDK_Compatibility_Symbols */
-
-
-#endif  /* _LPC54608_H_ */
-

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,231 +0,0 @@
-/*
-** ###################################################################
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b170112
-**
-**     Abstract:
-**         Chip specific module features.
-**
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016 - 2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2016-08-12)
-**         Initial version.
-**     - rev. 1.1 (2016-11-25)
-**         Update CANFD and Classic CAN register.
-**         Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-#ifndef _LPC54608_FEATURES_H_
-#define _LPC54608_FEATURES_H_
-
-/* SOC module features */
-
-/* @brief ADC availability on the SoC. */
-#define FSL_FEATURE_SOC_ADC_COUNT (1)
-/* @brief ASYNC_SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
-/* @brief CRC availability on the SoC. */
-#define FSL_FEATURE_SOC_CRC_COUNT (1)
-/* @brief DMA availability on the SoC. */
-#define FSL_FEATURE_SOC_DMA_COUNT (1)
-/* @brief DMIC availability on the SoC. */
-#define FSL_FEATURE_SOC_DMIC_COUNT (1)
-/* @brief FLEXCOMM availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10)
-/* @brief GINT availability on the SoC. */
-#define FSL_FEATURE_SOC_GINT_COUNT (2)
-/* @brief GPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_GPIO_COUNT (1)
-/* @brief I2C availability on the SoC. */
-#define FSL_FEATURE_SOC_I2C_COUNT (10)
-/* @brief I2S availability on the SoC. */
-#define FSL_FEATURE_SOC_I2S_COUNT (2)
-/* @brief INPUTMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
-/* @brief IOCON availability on the SoC. */
-#define FSL_FEATURE_SOC_IOCON_COUNT (1)
-/* @brief MRT availability on the SoC. */
-#define FSL_FEATURE_SOC_MRT_COUNT (1)
-/* @brief PINT availability on the SoC. */
-#define FSL_FEATURE_SOC_PINT_COUNT (1)
-/* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_RTC_COUNT (1)
-/* @brief SCT availability on the SoC. */
-#define FSL_FEATURE_SOC_SCT_COUNT (1)
-/* @brief SPI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPI_COUNT (10)
-/* @brief SPIFI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
-/* @brief SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
-/* @brief CTIMER availability on the SoC. */
-#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_USART_COUNT (10)
-/* @brief USB availability on the SoC. */
-#define FSL_FEATURE_SOC_USB_COUNT (1)
-/* @brief UTICK availability on the SoC. */
-#define FSL_FEATURE_SOC_UTICK_COUNT (1)
-/* @brief WWDT availability on the SoC. */
-#define FSL_FEATURE_SOC_WWDT_COUNT (1)
-/* @brief USBFSH availability on the SoC. */
-#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
-/* @brief USBHSD availability on the SoC. */
-#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
-/* @brief USBHSH availability on the SoC. */
-#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
-/* @brief EEPROM availability on the SoC. */
-#define FSL_FEATURE_SOC_EEPROM_COUNT (1)
-/* @brief EMC availability on the SoC. */
-#define FSL_FEATURE_SOC_EMC_COUNT (1)
-/* @brief ENET availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
-/* @brief SDIF availability on the SoC. */
-#define FSL_FEATURE_SOC_SDIF_COUNT (1)
-/* @brief SMARTCARD availability on the SoC. */
-#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
-/* @brief LCD availability on the SoC. */
-#define FSL_FEATURE_SOC_LCD_COUNT (1)
-/* @brief CAN availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
-/* @brief SHA availability on the SoC. */
-#define FSL_FEATURE_SOC_SHA_COUNT (0)
-/* @brief AES availability on the SoC. */
-#define FSL_FEATURE_SOC_AES_COUNT (0)
-/* @brief RIT availability on the SoC. */
-#define FSL_FEATURE_SOC_RIT_COUNT (1)
-/* @brief FMC availability on the SoC. */
-#define FSL_FEATURE_SOC_FMC_COUNT (1)
-/* @brief RNG availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
-
-/* CAN module features */
-
-/* @brief Support CANFD or not */
-#define FSL_FEATURE_CAN_SUPPORT_CANFD (0)
-
-/* DMA module features */
-
-/* @brief Number of channels */
-#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
-
-/* EEPROM module features */
-
-/* @brief Size of the EEPROM */
-#define FSL_FEATURE_EEPROM_SIZE (0x00004000)
-/* @brief Base address of the EEPROM */
-#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000)
-/* @brief Page count of the EEPROM */
-#define FSL_FEATURE_EEPROM_PAGE_COUNT (128)
-/* @brief Command number for eeprom program */
-#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6)
-/* @brief EEPROM internal clock freqency */
-#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000)
-
-/* IOCON module features */
-
-/* @brief Func bit field width */
-#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
-
-/* PINT module features */
-
-/* @brief Number of connected outputs */
-#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
-
-/* SCT module features */
-
-/* @brief Number of events */
-#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
-/* @brief Number of states */
-#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
-/* @brief Number of match capture */
-#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
-
-/* SDIF module features */
-
-/* @brief FIFO depth, every location is a WORD */
-#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
-/* @brief Max DMA buffer size */
-#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
-/* @brief Max source clock in HZ */
-#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
-
-/* SPIFI module features */
-
-/* @brief SPIFI start address */
-#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
-/* @brief SPIFI end address */
-#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
-
-/* SYSCON module features */
-
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
-/* @brief Flash page size in bytes */
-#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
-/* @brief Flash sector size in bytes */
-#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
-/* @brief Flash size in bytes */
-#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
-
-/* USB module features */
-
-/* @brief Size of the USB dedicated RAM */
-#define FSL_FEATURE_USB_USB_RAM (0x00002000)
-/* @brief Base address of the USB dedicated RAM */
-#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
-
-/* USBFSH module features */
-
-/* @brief Size of the USB dedicated RAM */
-#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
-/* @brief Base address of the USB dedicated RAM */
-#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
-
-/* USBHSD module features */
-
-/* @brief Size of the USB dedicated RAM */
-#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
-/* @brief Base address of the USB dedicated RAM */
-#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
-
-/* USBHSH module features */
-
-/* @brief Size of the USB dedicated RAM */
-#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
-/* @brief Base address of the USB dedicated RAM */
-#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
-
-#endif /* _LPC54608_FEATURES_H_ */
-

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-#! armcc -E
-/*
-** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
-**
-**     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b161227
-**
-**     Abstract:
-**         Linker file for the Keil ARM C/C++ Compiler
-**
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016 - 2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-** ###################################################################
-*/
-#define __ram_vector_table__            1
-
-#if (defined(__ram_vector_table__))
-  #define __ram_vector_table_size__    0x00000400
-#else
-  #define __ram_vector_table_size__    0x00000000
-#endif
-
-#define m_interrupts_start             0x00000000
-#define m_interrupts_size              0x00000400
-
-#define m_text_start                   0x00000400
-#define m_text_size                    0x0007FC00
-
-#define m_interrupts_ram_start         0x20000000
-#define m_interrupts_ram_size          __ram_vector_table_size__
-
-#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
-#define m_data_size                    (0x00028000 - m_interrupts_ram_size)
-
-#define m_usb_sram_start               0x40100000
-#define m_usb_sram_size                0x00002000
-
-/* USB BDT size */
-#define usb_bdt_size                   0x0
-/* Sizes */
-#if (defined(__stack_size__))
-  #define Stack_Size                   __stack_size__
-#else
-  #define Stack_Size                   0x0400
-#endif
-
-#if (defined(__heap_size__))
-  #define Heap_Size                    __heap_size__
-#else
-  #define Heap_Size                    0x0400
-#endif
-
-LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
-  }
-  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
-    * (InRoot$$Sections)
-    .ANY (+RO)
-  }
-
-#if (defined(__ram_vector_table__))
-  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
-  }
-#else
-  VECTOR_RAM m_interrupts_start EMPTY 0 {
-  }
-#endif
-  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    .ANY (+RW +ZI)
-  }
-  RW_IRAM1 +0 EMPTY Heap_Size {    ; Heap region growing up
-  }
-  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
-  }
-}
-
-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
-  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
-  }
-}
-
-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
-  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
-  }
-}
-

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar has changed

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,713 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC54608.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; *           LPC54608
-; * @version: 1.1
-; * @date:    2016-11-25
-; *
-; * Copyright 1997 - 2016 Freescale Semiconductor, Inc.
-; * Copyright 2016 - 2017 NXP
-; *
-; * Redistribution and use in source and binary forms, with or without modification,
-; * are permitted provided that the following conditions are met:
-; *
-; * o Redistributions of source code must retain the above copyright notice, this list
-; *   of conditions and the following disclaimer.
-; *
-; * o Redistributions in binary form must reproduce the above copyright notice, this
-; *   list of conditions and the following disclaimer in the documentation and/or
-; *   other materials provided with the distribution.
-; *
-; * o Neither the name of the copyright holder nor the names of its
-; *   contributors may be used to endorse or promote products derived from this
-; *   software without specific prior written permission.
-; *
-; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; *
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     NMI_Handler
-                DCD     HardFault_Handler
-                DCD     MemManage_Handler
-                DCD     BusFault_Handler
-                DCD     UsageFault_Handler
-__vector_table_0x1c
-                DCD     0                         ; Checksum of the first 7 words
-                DCD     0xFFFFFFFF                ; ECRP
-                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
-                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
-                DCD     SVC_Handler
-                DCD     DebugMon_Handler
-                DCD     0
-                DCD     PendSV_Handler
-                DCD     SysTick_Handler
-
-                ; External Interrupts
-                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
-                DCD     DMA0_IRQHandler  ; DMA controller
-                DCD     GINT0_IRQHandler  ; GPIO group 0
-                DCD     GINT1_IRQHandler  ; GPIO group 1
-                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
-                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
-                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
-                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
-                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
-                DCD     MRT0_IRQHandler  ; Multi-rate timer
-                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
-                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
-                DCD     SCT0_IRQHandler  ; SCTimer/PWM
-                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
-                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
-                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
-                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
-                DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
-                DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
-                DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
-                DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
-                DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
-                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
-                DCD     USB0_IRQHandler  ; USB device
-                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
-                DCD     Reserved46_IRQHandler  ; Reserved interrupt
-                DCD     Reserved47_IRQHandler  ; Reserved interrupt
-                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
-                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
-                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
-                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
-                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
-                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
-                DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
-                DCD     SPIFI0_IRQHandler  ; SPI flash interface
-                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
-                DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
-                DCD     SDIO_IRQHandler  ; SD/MMC
-                DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
-                DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
-                DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
-                DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
-                DCD     USB1_IRQHandler  ; USB1 interrupt
-                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
-                DCD     ETHERNET_IRQHandler  ; Ethernet
-                DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
-                DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
-                DCD     EEPROM_IRQHandler  ; EEPROM interrupt
-                DCD     LCD_IRQHandler  ; LCD interrupt
-                DCD     SHA_IRQHandler  ; SHA interrupt
-                DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
-                DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler               [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-
-                LDR     r0, =SystemInit
-                BLX     r0
-                LDR     r0, =__main
-                BX      r0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-
-HardFault_Handler \
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-
-MemManage_Handler     PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-
-BusFault_Handler PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-
-UsageFault_Handler PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-DebugMon_Handler PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-WDT_BOD_IRQHandler\
-                PROC
-                EXPORT     WDT_BOD_IRQHandler        [WEAK]
-                LDR        R0, =WDT_BOD_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMA0_IRQHandler\
-                PROC
-                EXPORT     DMA0_IRQHandler        [WEAK]
-                LDR        R0, =DMA0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT0_IRQHandler\
-                PROC
-                EXPORT     GINT0_IRQHandler        [WEAK]
-                LDR        R0, =GINT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-GINT1_IRQHandler\
-                PROC
-                EXPORT     GINT1_IRQHandler        [WEAK]
-                LDR        R0, =GINT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT0_IRQHandler\
-                PROC
-                EXPORT     PIN_INT0_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT1_IRQHandler\
-                PROC
-                EXPORT     PIN_INT1_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT2_IRQHandler\
-                PROC
-                EXPORT     PIN_INT2_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT3_IRQHandler\
-                PROC
-                EXPORT     PIN_INT3_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-UTICK0_IRQHandler\
-                PROC
-                EXPORT     UTICK0_IRQHandler        [WEAK]
-                LDR        R0, =UTICK0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-MRT0_IRQHandler\
-                PROC
-                EXPORT     MRT0_IRQHandler        [WEAK]
-                LDR        R0, =MRT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER0_IRQHandler\
-                PROC
-                EXPORT     CTIMER0_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER1_IRQHandler\
-                PROC
-                EXPORT     CTIMER1_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SCT0_IRQHandler\
-                PROC
-                EXPORT     SCT0_IRQHandler        [WEAK]
-                LDR        R0, =SCT0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER3_IRQHandler\
-                PROC
-                EXPORT     CTIMER3_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM0_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM1_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM2_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM3_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM3_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM4_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM5_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM6_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM7_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_SEQA_IRQHandler\
-                PROC
-                EXPORT     ADC0_SEQA_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_SEQA_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_SEQB_IRQHandler\
-                PROC
-                EXPORT     ADC0_SEQB_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_SEQB_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ADC0_THCMP_IRQHandler\
-                PROC
-                EXPORT     ADC0_THCMP_IRQHandler        [WEAK]
-                LDR        R0, =ADC0_THCMP_DriverIRQHandler
-                BX         R0
-                ENDP
-
-DMIC0_IRQHandler\
-                PROC
-                EXPORT     DMIC0_IRQHandler        [WEAK]
-                LDR        R0, =DMIC0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-HWVAD0_IRQHandler\
-                PROC
-                EXPORT     HWVAD0_IRQHandler        [WEAK]
-                LDR        R0, =HWVAD0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB0_IRQHandler\
-                PROC
-                EXPORT     USB0_IRQHandler        [WEAK]
-                LDR        R0, =USB0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-RTC_IRQHandler\
-                PROC
-                EXPORT     RTC_IRQHandler        [WEAK]
-                LDR        R0, =RTC_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved46_IRQHandler\
-                PROC
-                EXPORT     Reserved46_IRQHandler        [WEAK]
-                LDR        R0, =Reserved46_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Reserved47_IRQHandler\
-                PROC
-                EXPORT     Reserved47_IRQHandler        [WEAK]
-                LDR        R0, =Reserved47_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT4_IRQHandler\
-                PROC
-                EXPORT     PIN_INT4_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT5_IRQHandler\
-                PROC
-                EXPORT     PIN_INT5_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT5_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT6_IRQHandler\
-                PROC
-                EXPORT     PIN_INT6_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT6_DriverIRQHandler
-                BX         R0
-                ENDP
-
-PIN_INT7_IRQHandler\
-                PROC
-                EXPORT     PIN_INT7_IRQHandler        [WEAK]
-                LDR        R0, =PIN_INT7_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER2_IRQHandler\
-                PROC
-                EXPORT     CTIMER2_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER2_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CTIMER4_IRQHandler\
-                PROC
-                EXPORT     CTIMER4_IRQHandler        [WEAK]
-                LDR        R0, =CTIMER4_DriverIRQHandler
-                BX         R0
-                ENDP
-
-RIT_IRQHandler\
-                PROC
-                EXPORT     RIT_IRQHandler        [WEAK]
-                LDR        R0, =RIT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SPIFI0_IRQHandler\
-                PROC
-                EXPORT     SPIFI0_IRQHandler        [WEAK]
-                LDR        R0, =SPIFI0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM8_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM8_DriverIRQHandler
-                BX         R0
-                ENDP
-
-FLEXCOMM9_IRQHandler\
-                PROC
-                EXPORT     FLEXCOMM9_IRQHandler        [WEAK]
-                LDR        R0, =FLEXCOMM9_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SDIO_IRQHandler\
-                PROC
-                EXPORT     SDIO_IRQHandler        [WEAK]
-                LDR        R0, =SDIO_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CAN0_IRQ0_IRQHandler\
-                PROC
-                EXPORT     CAN0_IRQ0_IRQHandler        [WEAK]
-                LDR        R0, =CAN0_IRQ0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CAN0_IRQ1_IRQHandler\
-                PROC
-                EXPORT     CAN0_IRQ1_IRQHandler        [WEAK]
-                LDR        R0, =CAN0_IRQ1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CAN1_IRQ0_IRQHandler\
-                PROC
-                EXPORT     CAN1_IRQ0_IRQHandler        [WEAK]
-                LDR        R0, =CAN1_IRQ0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-CAN1_IRQ1_IRQHandler\
-                PROC
-                EXPORT     CAN1_IRQ1_IRQHandler        [WEAK]
-                LDR        R0, =CAN1_IRQ1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_IRQHandler\
-                PROC
-                EXPORT     USB1_IRQHandler        [WEAK]
-                LDR        R0, =USB1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-USB1_NEEDCLK_IRQHandler\
-                PROC
-                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
-                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ETHERNET_IRQHandler\
-                PROC
-                EXPORT     ETHERNET_IRQHandler        [WEAK]
-                LDR        R0, =ETHERNET_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ETHERNET_PMT_IRQHandler\
-                PROC
-                EXPORT     ETHERNET_PMT_IRQHandler        [WEAK]
-                LDR        R0, =ETHERNET_PMT_DriverIRQHandler
-                BX         R0
-                ENDP
-
-ETHERNET_MACLP_IRQHandler\
-                PROC
-                EXPORT     ETHERNET_MACLP_IRQHandler        [WEAK]
-                LDR        R0, =ETHERNET_MACLP_DriverIRQHandler
-                BX         R0
-                ENDP
-
-EEPROM_IRQHandler\
-                PROC
-                EXPORT     EEPROM_IRQHandler        [WEAK]
-                LDR        R0, =EEPROM_DriverIRQHandler
-                BX         R0
-                ENDP
-
-LCD_IRQHandler\
-                PROC
-                EXPORT     LCD_IRQHandler        [WEAK]
-                LDR        R0, =LCD_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SHA_IRQHandler\
-                PROC
-                EXPORT     SHA_IRQHandler        [WEAK]
-                LDR        R0, =SHA_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SMARTCARD0_IRQHandler\
-                PROC
-                EXPORT     SMARTCARD0_IRQHandler        [WEAK]
-                LDR        R0, =SMARTCARD0_DriverIRQHandler
-                BX         R0
-                ENDP
-
-SMARTCARD1_IRQHandler\
-                PROC
-                EXPORT     SMARTCARD1_IRQHandler        [WEAK]
-                LDR        R0, =SMARTCARD1_DriverIRQHandler
-                BX         R0
-                ENDP
-
-Default_Handler PROC
-                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
-                EXPORT     DMA0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT0_DriverIRQHandler        [WEAK]
-                EXPORT     GINT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
-                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
-                EXPORT     MRT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
-                EXPORT     SCT0_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_SEQA_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_SEQB_DriverIRQHandler        [WEAK]
-                EXPORT     ADC0_THCMP_DriverIRQHandler        [WEAK]
-                EXPORT     DMIC0_DriverIRQHandler        [WEAK]
-                EXPORT     HWVAD0_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     USB0_DriverIRQHandler        [WEAK]
-                EXPORT     RTC_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
-                EXPORT     Reserved47_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
-                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
-                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
-                EXPORT     RIT_DriverIRQHandler        [WEAK]
-                EXPORT     SPIFI0_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
-                EXPORT     FLEXCOMM9_DriverIRQHandler        [WEAK]
-                EXPORT     SDIO_DriverIRQHandler        [WEAK]
-                EXPORT     CAN0_IRQ0_DriverIRQHandler        [WEAK]
-                EXPORT     CAN0_IRQ1_DriverIRQHandler        [WEAK]
-                EXPORT     CAN1_IRQ0_DriverIRQHandler        [WEAK]
-                EXPORT     CAN1_IRQ1_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_DriverIRQHandler        [WEAK]
-                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
-                EXPORT     ETHERNET_DriverIRQHandler        [WEAK]
-                EXPORT     ETHERNET_PMT_DriverIRQHandler        [WEAK]
-                EXPORT     ETHERNET_MACLP_DriverIRQHandler        [WEAK]
-                EXPORT     EEPROM_DriverIRQHandler        [WEAK]
-                EXPORT     LCD_DriverIRQHandler        [WEAK]
-                EXPORT     SHA_DriverIRQHandler        [WEAK]
-                EXPORT     SMARTCARD0_DriverIRQHandler        [WEAK]
-                EXPORT     SMARTCARD1_DriverIRQHandler        [WEAK]
-
-WDT_BOD_DriverIRQHandler
-DMA0_DriverIRQHandler
-GINT0_DriverIRQHandler
-GINT1_DriverIRQHandler
-PIN_INT0_DriverIRQHandler
-PIN_INT1_DriverIRQHandler
-PIN_INT2_DriverIRQHandler
-PIN_INT3_DriverIRQHandler
-UTICK0_DriverIRQHandler
-MRT0_DriverIRQHandler
-CTIMER0_DriverIRQHandler
-CTIMER1_DriverIRQHandler
-SCT0_DriverIRQHandler
-CTIMER3_DriverIRQHandler
-FLEXCOMM0_DriverIRQHandler
-FLEXCOMM1_DriverIRQHandler
-FLEXCOMM2_DriverIRQHandler
-FLEXCOMM3_DriverIRQHandler
-FLEXCOMM4_DriverIRQHandler
-FLEXCOMM5_DriverIRQHandler
-FLEXCOMM6_DriverIRQHandler
-FLEXCOMM7_DriverIRQHandler
-ADC0_SEQA_DriverIRQHandler
-ADC0_SEQB_DriverIRQHandler
-ADC0_THCMP_DriverIRQHandler
-DMIC0_DriverIRQHandler
-HWVAD0_DriverIRQHandler
-USB0_NEEDCLK_DriverIRQHandler
-USB0_DriverIRQHandler
-RTC_DriverIRQHandler
-Reserved46_DriverIRQHandler
-Reserved47_DriverIRQHandler
-PIN_INT4_DriverIRQHandler
-PIN_INT5_DriverIRQHandler
-PIN_INT6_DriverIRQHandler
-PIN_INT7_DriverIRQHandler
-CTIMER2_DriverIRQHandler
-CTIMER4_DriverIRQHandler
-RIT_DriverIRQHandler
-SPIFI0_DriverIRQHandler
-FLEXCOMM8_DriverIRQHandler
-FLEXCOMM9_DriverIRQHandler
-SDIO_DriverIRQHandler
-CAN0_IRQ0_DriverIRQHandler
-CAN0_IRQ1_DriverIRQHandler
-CAN1_IRQ0_DriverIRQHandler
-CAN1_IRQ1_DriverIRQHandler
-USB1_DriverIRQHandler
-USB1_NEEDCLK_DriverIRQHandler
-ETHERNET_DriverIRQHandler
-ETHERNET_PMT_DriverIRQHandler
-ETHERNET_MACLP_DriverIRQHandler
-EEPROM_DriverIRQHandler
-LCD_DriverIRQHandler
-SHA_DriverIRQHandler
-SMARTCARD0_DriverIRQHandler
-SMARTCARD1_DriverIRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-                END
-

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,288 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC54608J512
-**
-**     Compiler:            GNU C Compiler
-**     Reference manual:    LPC54608 Series Reference Manual, Rev. 0 , 06/2017
-**     Version:             rev. 1.0, 2017-6-06
-**     Build:               b161214
-**
-**     Abstract:
-**         Linker file for the GNU C Compiler
-**
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright (c) 2016 - 2017 , NXP
-**     All rights reserved.
-**
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Copyright (c) 2016 NXP Semiconductors, Inc.
-**     All rights reserved.
-**
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of NXP Semiconductors, Inc. nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-** ###################################################################
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-__ram_vector_table__ = 1;
-
-__stack_size__ = 0x8000;
-__heap_size__ = 0xC000;
-
-HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
-STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
-M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0;
-
-
-/* Specify the memory areas */
-MEMORY
-{
-  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0007FC00
-  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00028000
-  m_sramx               (RW)  : ORIGIN = 0x04000000, LENGTH = 0x00008000
-  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00002000
-
-
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into internal flash */
-  .interrupts :
-  {
-    __VECTOR_TABLE = .;
-    . = ALIGN(4);
-    KEEP(*(.isr_vector))     /* Startup code */
-    . = ALIGN(4);
-  } > m_interrupts
-
-  /* The program code and other data goes into internal flash */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)                 /* .text sections (code) */
-    *(.text*)                /* .text* sections (code) */
-    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
-    *(.glue_7)               /* glue arm to thumb code */
-    *(.glue_7t)              /* glue thumb to arm code */
-    *(.eh_frame)
-    KEEP (*(.init))
-    KEEP (*(.fini))
-    . = ALIGN(4);
-  } > m_text
-
-  .ARM.extab :
-  {
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-  } > m_text
-
-  .ARM :
-  {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } > m_text
-
- .ctors :
-  {
-    __CTOR_LIST__ = .;
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-       from the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    __CTOR_END__ = .;
-  } > m_text
-
-  .dtors :
-  {
-    __DTOR_LIST__ = .;
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    __DTOR_END__ = .;
-  } > m_text
-
-  .preinit_array :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } > m_text
-
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } > m_text
-
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } > m_text
-
-  __etext = .;    /* define a global symbol at end of code */
-  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
-
-  .interrupts_ram :
-  {
-    . = ALIGN(4);
-    __VECTOR_RAM__ = .;
-    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
-    *(.m_interrupts_ram)     /* This is a user defined section */
-    . += M_VECTOR_RAM_SIZE;
-    . = ALIGN(4);
-    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
-  } > m_data
-
-  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
-  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
-
-  .data : AT(__DATA_ROM)
-  {
-    . = ALIGN(4);
-    __DATA_RAM = .;
-    __data_start__ = .;      /* create a global symbol at data start */
-    *(.ramfunc*)             /* for functions in ram */
-    *(.data)                 /* .data sections */
-    *(.data*)                /* .data* sections */
-    KEEP(*(.jcr*))
-    . = ALIGN(4);
-    __data_end__ = .;        /* define a global symbol at data end */
-  } > m_data
-
-  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
-  text_end = ORIGIN(m_text) + LENGTH(m_text);
-  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
-
-  /* Uninitialized data section */
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    . = ALIGN(4);
-    __START_BSS = .;
-    __bss_start__ = .;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-    . = ALIGN(4);
-    __bss_end__ = .;
-    __END_BSS = .;
-  } > m_data
-
-  .heap :
-  {
-    . = ALIGN(8);
-    __end__ = .;
-    PROVIDE(end = .);
-    __HeapBase = .;
-    . += HEAP_SIZE;
-    __HeapLimit = .;
-    __heap_limit = .; /* Add for _sbrk */
-  } > m_data
-
-  .stack :
-  {
-    . = ALIGN(8);
-    . += STACK_SIZE;
-  } > m_data
-
-  m_usb_bdt (NOLOAD) :
-  {
-    . = ALIGN(512);
-    *(m_usb_bdt)
-  } > m_usb_sram
-
-  m_usb_global (NOLOAD) :
-  {
-    *(m_usb_global)
-  } > m_usb_sram
-
-  /* Initializes stack on the end of block */
-  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
-  __StackLimit = __StackTop - STACK_SIZE;
-  PROVIDE(__stack = __StackTop);
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-
-  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
-}
-

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a has changed

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,892 +0,0 @@
-/* ---------------------------------------------------------------------------------------*/
-/*  @file:    startup_LPC54608.S                                                          */
-/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
-/*            LPC54608                                                                    */
-/*  @version: 1.0                                                                         */
-/*  @date:    2017-6-6                                                                    */
-/*  @build:   b161214                                                                     */
-/* ---------------------------------------------------------------------------------------*/
-/*                                                                                        */
-/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.                              */
-/* Copyright (c) 2016 - 2017 , NXP                                                        */
-/*                                                                                        */
-/* Redistribution and use in source and binary forms, with or without modification,       */
-/* are permitted provided that the following conditions are met:                          */
-/*                                                                                        */
-/* o Redistributions of source code must retain the above copyright notice, this list     */
-/*   of conditions and the following disclaimer.                                          */
-/*                                                                                        */
-/* o Redistributions in binary form must reproduce the above copyright notice, this       */
-/*   list of conditions and the following disclaimer in the documentation and/or          */
-/*   other materials provided with the distribution.                                      */
-/*                                                                                        */
-/* o Neither the name of copyright holder nor the names of its                            */
-/*   contributors may be used to endorse or promote products derived from this            */
-/*   software without specific prior written permission.                                  */
-/*                                                                                        */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
-/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
-/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
-/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
-/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
-/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
-/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
-/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
-/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
-/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
-/*                                                                                        */
-/* Copyright (c) 2016 , NXP Semiconductors, Inc.                                          */
-/* All rights reserved.                                                                   */
-/*                                                                                        */
-/* Redistribution and use in source and binary forms, with or without modification,       */
-/* are permitted provided that the following conditions are met:                          */
-/*                                                                                        */
-/* o Redistributions of source code must retain the above copyright notice, this list     */
-/*   of conditions and the following disclaimer.                                          */
-/*                                                                                        */
-/* o Redistributions in binary form must reproduce the above copyright notice, this       */
-/*   list of conditions and the following disclaimer in the documentation and/or          */
-/*   other materials provided with the distribution.                                      */
-/*                                                                                        */
-/* o Neither the name of NXP Semiconductors, Inc. nor the names of its                    */
-/*   contributors may be used to endorse or promote products derived from this            */
-/*   software without specific prior written permission.                                  */
-/*                                                                                        */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
-/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
-/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
-/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
-/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
-/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
-/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
-/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
-/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
-/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
-/*****************************************************************************/
-/* Version: GCC for ARM Embedded Processors                                  */
-/*****************************************************************************/
-    .syntax unified
-    .arch armv7-m
-
-    .section .isr_vector, "a"
-    .align 2
-    .globl __Vectors
-__Vectors:
-    .long   __StackTop                                      /* Top of Stack */
-    .long   Reset_Handler                                   /* Reset Handler */
-    .long   NMI_Handler                                     /* NMI Handler */
-    .long   HardFault_Handler                               /* Hard Fault Handler */
-    .long   MemManage_Handler                               /* MPU Fault Handler */
-    .long   BusFault_Handler                                /* Bus Fault Handler */
-    .long   UsageFault_Handler                              /* Usage Fault Handler */
-    .long   0                                               /* Reserved */
-    .long   0xFFFFFFFF                                      /* ECRP */
-    .long   0                                               /* Reserved */
-    .long   0                                               /* Reserved */
-    .long   SVC_Handler                                     /* SVCall Handler */
-    .long   DebugMon_Handler                                /* Debug Monitor Handler */
-    .long   0
-    .long   PendSV_Handler                                  /* PendSV Handler */
-    .long   SysTick_Handler                                 /* SysTick Handler */
-
-     /* External Interrupts */
-    .long   WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect */
-    .long   DMA0_IRQHandler                                 /* DMA controller */
-    .long   GINT0_IRQHandler                                /* GPIO group 0 */
-    .long   GINT1_IRQHandler                                /* GPIO group 1 */
-    .long   PIN_INT0_IRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
-    .long   PIN_INT1_IRQHandler                             /* Pin interrupt 1 or pattern match engine slice 1 */
-    .long   PIN_INT2_IRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
-    .long   PIN_INT3_IRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
-    .long   UTICK0_IRQHandler                               /* Micro-tick Timer */
-    .long   MRT0_IRQHandler                                 /* Multi-rate timer */
-    .long   CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
-    .long   CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
-    .long   SCT0_IRQHandler                                 /* SCTimer/PWM */
-    .long   CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
-    .long   FLEXCOMM0_IRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM1_IRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM2_IRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM3_IRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM4_IRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM5_IRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
-    .long   FLEXCOMM6_IRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-    .long   FLEXCOMM7_IRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-    .long   ADC0_SEQA_IRQHandler                            /* ADC0 sequence A completion. */
-    .long   ADC0_SEQB_IRQHandler                            /* ADC0 sequence B completion. */
-    .long   ADC0_THCMP_IRQHandler                           /* ADC0 threshold compare and error. */
-    .long   DMIC0_IRQHandler                                /* Digital microphone and DMIC subsystem */
-    .long   HWVAD0_IRQHandler                               /* Hardware Voice Activity Detector */
-    .long   USB0_NEEDCLK_IRQHandler                         /* USB Activity Wake-up Interrupt */
-    .long   USB0_IRQHandler                                 /* USB device */
-    .long   RTC_IRQHandler                                  /* RTC alarm and wake-up interrupts */
-    .long   0                                               /* Reserved interrupt */
-    .long   0                                               /* Reserved interrupt */
-    .long   PIN_INT4_IRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
-    .long   PIN_INT5_IRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
-    .long   PIN_INT6_IRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
-    .long   PIN_INT7_IRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
-    .long   CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
-    .long   CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
-    .long   RIT_IRQHandler                                  /* Repetitive Interrupt Timer */
-    .long   SPIFI0_IRQHandler                               /* SPI flash interface */
-    .long   FLEXCOMM8_IRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
-    .long   FLEXCOMM9_IRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
-    .long   SDIO_IRQHandler                                 /* SD/MMC */
-    .long   CAN0_IRQ0_IRQHandler                            /* CAN0 interrupt0 */
-    .long   CAN0_IRQ1_IRQHandler                            /* CAN0 interrupt1 */
-    .long   CAN1_IRQ0_IRQHandler                            /* CAN1 interrupt0 */
-    .long   CAN1_IRQ1_IRQHandler                            /* CAN1 interrupt1 */
-    .long   USB1_IRQHandler                                 /* USB1 interrupt */
-    .long   USB1_NEEDCLK_IRQHandler                         /* USB1 activity */
-    .long   ETHERNET_IRQHandler                             /* Ethernet */
-    .long   ETHERNET_PMT_IRQHandler                         /* Ethernet power management interrupt */
-    .long   ETHERNET_MACLP_IRQHandler                       /* Ethernet MAC interrupt */
-    .long   EEPROM_IRQHandler                               /* EEPROM interrupt */
-    .long   LCD_IRQHandler                                  /* LCD interrupt */
-    .long   SHA_IRQHandler                                  /* SHA interrupt */
-    .long   SMARTCARD0_IRQHandler                           /* Smart card 0 interrupt */
-    .long   SMARTCARD1_IRQHandler                           /* Smart card 1 interrupt */
-    .size   __Vectors, . - __Vectors
-
-
-    
-    .text
-    .thumb
-
-/* Reset Handler */
-
-    .thumb_func
-    .align 2
-    .globl   Reset_Handler
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-#ifndef __NO_SYSTEM_INIT
-    ldr   r0,=SystemInit
-    blx   r0
-#endif
-
-    /*      Loop to copy data from read only memory to RAM. The ranges
-     *      of copy from/to are specified by following symbols evaluated in
-     *      linker script.
-     *      __etext: End of code section, i.e., begin of data sections to copy from.
-     *      __data_start__/__data_end__: RAM address range that data should be
-     *      copied to. Both must be aligned to 4 bytes boundary.  */
-
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-#if 1
-/* Here are two copies of loop implemenations. First one favors code size
- * and the second one favors performance. Default uses the first one.
- * Change to "#if 0" to use the second one */
-.LC0:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt    .LC0
-#else
-    subs    r3, r2
-    ble    .LC1
-.LC0:
-    subs    r3, #4
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    bgt    .LC0
-.LC1:
-#endif
-
-#ifdef __STARTUP_CLEAR_BSS
-/*     This part of work usually is done in C library startup code. Otherwise,
- *     define this macro to enable it in this startup.
- *
- *     Loop to zero out BSS section, which uses following symbols
- *     in linker script:
- *      __bss_start__: start of BSS section. Must align to 4
- *      __bss_end__: end of BSS section. Must align to 4
- */
-    ldr r1, =__bss_start__
-    ldr r2, =__bss_end__
-
-    movs    r0, 0
-.LC2:
-    cmp     r1, r2
-    itt    lt
-    strlt   r0, [r1], #4
-    blt    .LC2
-#endif /* __STARTUP_CLEAR_BSS */
-
-#ifndef __START
-#define __START _start
-#endif
-#ifndef __ATOLLIC__
-    ldr   r0,=__START
-    blx   r0
-#else
-    ldr   r0,=__libc_init_array
-    blx   r0
-    ldr   r0,=main
-    bx    r0
-#endif
-
-    .pool
-    .size Reset_Handler, . - Reset_Handler
-
-    .align  1
-    .thumb_func
-    .weak DefaultISR
-    .type DefaultISR, %function
-DefaultISR:
-    b DefaultISR
-    .size DefaultISR, . - DefaultISR
-
-    .align 1
-    .thumb_func
-    .weak NMI_Handler
-    .type NMI_Handler, %function
-NMI_Handler:
-    ldr   r0,=NMI_Handler
-    bx    r0
-    .size NMI_Handler, . - NMI_Handler
-
-    .align 1
-    .thumb_func
-    .weak HardFault_Handler
-    .type HardFault_Handler, %function
-HardFault_Handler:
-    ldr   r0,=HardFault_Handler
-    bx    r0
-    .size HardFault_Handler, . - HardFault_Handler
-
-    .align 1
-    .thumb_func
-    .weak MemManage_Handler
-    .type MemManage_Handler, %function
-MemManage_Handler:
-    ldr   r0,=MemManage_Handler
-    bx    r0
-    .size MemManage_Handler, . - MemManage_Handler
-
-    .align 1
-    .thumb_func
-    .weak BusFault_Handler
-    .type BusFault_Handler, %function
-BusFault_Handler:
-    ldr   r0,=BusFault_Handler
-    bx    r0
-    .size BusFault_Handler, . - BusFault_Handler
-
-    .align 1
-    .thumb_func
-    .weak UsageFault_Handler
-    .type UsageFault_Handler, %function
-UsageFault_Handler:
-    ldr   r0,=UsageFault_Handler
-    bx    r0
-    .size UsageFault_Handler, . - UsageFault_Handler
-    
-    .align 1
-    .thumb_func
-    .weak SVC_Handler
-    .type SVC_Handler, %function
-SVC_Handler:
-    ldr   r0,=SVC_Handler
-    bx    r0
-    .size SVC_Handler, . - SVC_Handler
-
-    .align 1
-    .thumb_func
-    .weak DebugMon_Handler
-    .type DebugMon_Handler, %function
-DebugMon_Handler:
-    ldr   r0,=DebugMon_Handler
-    bx    r0
-    .size DebugMon_Handler, . - DebugMon_Handler
-    
-    .align 1
-    .thumb_func
-    .weak PendSV_Handler
-    .type PendSV_Handler, %function
-PendSV_Handler:
-    ldr   r0,=PendSV_Handler
-    bx    r0
-    .size PendSV_Handler, . - PendSV_Handler
-
-    .align 1
-    .thumb_func
-    .weak SysTick_Handler
-    .type SysTick_Handler, %function
-SysTick_Handler:
-    ldr   r0,=SysTick_Handler
-    bx    r0
-    .size SysTick_Handler, . - SysTick_Handler
-
-    .align 1
-    .thumb_func
-    .weak WDT_BOD_IRQHandler
-    .type WDT_BOD_IRQHandler, %function
-WDT_BOD_IRQHandler:
-    ldr   r0,=WDT_BOD_DriverIRQHandler
-    bx    r0
-    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak DMA0_IRQHandler
-    .type DMA0_IRQHandler, %function
-DMA0_IRQHandler:
-    ldr   r0,=DMA0_DriverIRQHandler
-    bx    r0
-    .size DMA0_IRQHandler, . - DMA0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak GINT0_IRQHandler
-    .type GINT0_IRQHandler, %function
-GINT0_IRQHandler:
-    ldr   r0,=GINT0_DriverIRQHandler
-    bx    r0
-    .size GINT0_IRQHandler, . - GINT0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak GINT1_IRQHandler
-    .type GINT1_IRQHandler, %function
-GINT1_IRQHandler:
-    ldr   r0,=GINT1_DriverIRQHandler
-    bx    r0
-    .size GINT1_IRQHandler, . - GINT1_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT0_IRQHandler
-    .type PIN_INT0_IRQHandler, %function
-PIN_INT0_IRQHandler:
-    ldr   r0,=PIN_INT0_DriverIRQHandler
-    bx    r0
-    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT1_IRQHandler
-    .type PIN_INT1_IRQHandler, %function
-PIN_INT1_IRQHandler:
-    ldr   r0,=PIN_INT1_DriverIRQHandler
-    bx    r0
-    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT2_IRQHandler
-    .type PIN_INT2_IRQHandler, %function
-PIN_INT2_IRQHandler:
-    ldr   r0,=PIN_INT2_DriverIRQHandler
-    bx    r0
-    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT3_IRQHandler
-    .type PIN_INT3_IRQHandler, %function
-PIN_INT3_IRQHandler:
-    ldr   r0,=PIN_INT3_DriverIRQHandler
-    bx    r0
-    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak UTICK0_IRQHandler
-    .type UTICK0_IRQHandler, %function
-UTICK0_IRQHandler:
-    ldr   r0,=UTICK0_DriverIRQHandler
-    bx    r0
-    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak MRT0_IRQHandler
-    .type MRT0_IRQHandler, %function
-MRT0_IRQHandler:
-    ldr   r0,=MRT0_DriverIRQHandler
-    bx    r0
-    .size MRT0_IRQHandler, . - MRT0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak CTIMER0_IRQHandler
-    .type CTIMER0_IRQHandler, %function
-CTIMER0_IRQHandler:
-    ldr   r0,=CTIMER0_DriverIRQHandler
-    bx    r0
-    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak CTIMER1_IRQHandler
-    .type CTIMER1_IRQHandler, %function
-CTIMER1_IRQHandler:
-    ldr   r0,=CTIMER1_DriverIRQHandler
-    bx    r0
-    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak SCT0_IRQHandler
-    .type SCT0_IRQHandler, %function
-SCT0_IRQHandler:
-    ldr   r0,=SCT0_DriverIRQHandler
-    bx    r0
-    .size SCT0_IRQHandler, . - SCT0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak CTIMER3_IRQHandler
-    .type CTIMER3_IRQHandler, %function
-CTIMER3_IRQHandler:
-    ldr   r0,=CTIMER3_DriverIRQHandler
-    bx    r0
-    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM0_IRQHandler
-    .type FLEXCOMM0_IRQHandler, %function
-FLEXCOMM0_IRQHandler:
-    ldr   r0,=FLEXCOMM0_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM1_IRQHandler
-    .type FLEXCOMM1_IRQHandler, %function
-FLEXCOMM1_IRQHandler:
-    ldr   r0,=FLEXCOMM1_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM2_IRQHandler
-    .type FLEXCOMM2_IRQHandler, %function
-FLEXCOMM2_IRQHandler:
-    ldr   r0,=FLEXCOMM2_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM3_IRQHandler
-    .type FLEXCOMM3_IRQHandler, %function
-FLEXCOMM3_IRQHandler:
-    ldr   r0,=FLEXCOMM3_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM4_IRQHandler
-    .type FLEXCOMM4_IRQHandler, %function
-FLEXCOMM4_IRQHandler:
-    ldr   r0,=FLEXCOMM4_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM5_IRQHandler
-    .type FLEXCOMM5_IRQHandler, %function
-FLEXCOMM5_IRQHandler:
-    ldr   r0,=FLEXCOMM5_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM6_IRQHandler
-    .type FLEXCOMM6_IRQHandler, %function
-FLEXCOMM6_IRQHandler:
-    ldr   r0,=FLEXCOMM6_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM7_IRQHandler
-    .type FLEXCOMM7_IRQHandler, %function
-FLEXCOMM7_IRQHandler:
-    ldr   r0,=FLEXCOMM7_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak ADC0_SEQA_IRQHandler
-    .type ADC0_SEQA_IRQHandler, %function
-ADC0_SEQA_IRQHandler:
-    ldr   r0,=ADC0_SEQA_DriverIRQHandler
-    bx    r0
-    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak ADC0_SEQB_IRQHandler
-    .type ADC0_SEQB_IRQHandler, %function
-ADC0_SEQB_IRQHandler:
-    ldr   r0,=ADC0_SEQB_DriverIRQHandler
-    bx    r0
-    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak ADC0_THCMP_IRQHandler
-    .type ADC0_THCMP_IRQHandler, %function
-ADC0_THCMP_IRQHandler:
-    ldr   r0,=ADC0_THCMP_DriverIRQHandler
-    bx    r0
-    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak DMIC0_IRQHandler
-    .type DMIC0_IRQHandler, %function
-DMIC0_IRQHandler:
-    ldr   r0,=DMIC0_DriverIRQHandler
-    bx    r0
-    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak HWVAD0_IRQHandler
-    .type HWVAD0_IRQHandler, %function
-HWVAD0_IRQHandler:
-    ldr   r0,=HWVAD0_DriverIRQHandler
-    bx    r0
-    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak USB0_NEEDCLK_IRQHandler
-    .type USB0_NEEDCLK_IRQHandler, %function
-USB0_NEEDCLK_IRQHandler:
-    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
-    bx    r0
-    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak USB0_IRQHandler
-    .type USB0_IRQHandler, %function
-USB0_IRQHandler:
-    ldr   r0,=USB0_DriverIRQHandler
-    bx    r0
-    .size USB0_IRQHandler, . - USB0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak RTC_IRQHandler
-    .type RTC_IRQHandler, %function
-RTC_IRQHandler:
-    ldr   r0,=RTC_DriverIRQHandler
-    bx    r0
-    .size RTC_IRQHandler, . - RTC_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT4_IRQHandler
-    .type PIN_INT4_IRQHandler, %function
-PIN_INT4_IRQHandler:
-    ldr   r0,=PIN_INT4_DriverIRQHandler
-    bx    r0
-    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak PIN_INT5_IRQHandler
-    .type PIN_INT5_IRQHandler, %function
-PIN_INT5_IRQHandler:
-    ldr   r0,=PIN_INT5_DriverIRQHandler
-    bx    r0
-    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT6_IRQHandler
-    .type PIN_INT6_IRQHandler, %function
-PIN_INT6_IRQHandler:
-    ldr   r0,=PIN_INT6_DriverIRQHandler
-    bx    r0
-    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak PIN_INT7_IRQHandler
-    .type PIN_INT7_IRQHandler, %function
-PIN_INT7_IRQHandler:
-    ldr   r0,=PIN_INT7_DriverIRQHandler
-    bx    r0
-    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak CTIMER2_IRQHandler
-    .type CTIMER2_IRQHandler, %function
-CTIMER2_IRQHandler:
-    ldr   r0,=CTIMER2_DriverIRQHandler
-    bx    r0
-    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak CTIMER4_IRQHandler
-    .type CTIMER4_IRQHandler, %function
-CTIMER4_IRQHandler:
-    ldr   r0,=CTIMER4_DriverIRQHandler
-    bx    r0
-    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak RIT_IRQHandler
-    .type RIT_IRQHandler, %function
-RIT_IRQHandler:
-    ldr   r0,=RIT_DriverIRQHandler
-    bx    r0
-    .size RIT_IRQHandler, . - RIT_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak SPIFI0_IRQHandler
-    .type SPIFI0_IRQHandler, %function
-SPIFI0_IRQHandler:
-    ldr   r0,=SPIFI0_DriverIRQHandler
-    bx    r0
-    .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler
- 
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM8_IRQHandler
-    .type FLEXCOMM8_IRQHandler, %function
-FLEXCOMM8_IRQHandler:
-    ldr   r0,=FLEXCOMM8_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak FLEXCOMM9_IRQHandler
-    .type FLEXCOMM9_IRQHandler, %function
-FLEXCOMM9_IRQHandler:
-    ldr   r0,=FLEXCOMM9_DriverIRQHandler
-    bx    r0
-    .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak SDIO_IRQHandler
-    .type SDIO_IRQHandler, %function
-SDIO_IRQHandler:
-    ldr   r0,=SDIO_DriverIRQHandler
-    bx    r0
-    .size SDIO_IRQHandler, . - SDIO_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak CAN0_IRQ0_IRQHandler
-    .type CAN0_IRQ0_IRQHandler, %function
-CAN0_IRQ0_IRQHandler:
-    ldr   r0,=CAN0_IRQ0_DriverIRQHandler
-    bx    r0
-    .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak CAN0_IRQ1_IRQHandler
-    .type CAN0_IRQ1_IRQHandler, %function
-CAN0_IRQ1_IRQHandler:
-    ldr   r0,=CAN0_IRQ1_DriverIRQHandler
-    bx    r0
-    .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak CAN1_IRQ0_IRQHandler
-    .type CAN1_IRQ0_IRQHandler, %function
-CAN1_IRQ0_IRQHandler:
-    ldr   r0,=CAN1_IRQ0_DriverIRQHandler
-    bx    r0
-    .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak CAN1_IRQ1_IRQHandler
-    .type CAN1_IRQ1_IRQHandler, %function
-CAN1_IRQ1_IRQHandler:
-    ldr   r0,=CAN1_IRQ1_DriverIRQHandler
-    bx    r0
-    .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak USB1_IRQHandler
-    .type USB1_IRQHandler, %function
-USB1_IRQHandler:
-    ldr   r0,=USB1_DriverIRQHandler
-    bx    r0
-    .size USB1_IRQHandler, . - USB1_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak USB1_NEEDCLK_IRQHandler
-    .type USB1_NEEDCLK_IRQHandler, %function
-USB1_NEEDCLK_IRQHandler:
-    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
-    bx    r0
-    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak ETHERNET_IRQHandler
-    .type ETHERNET_IRQHandler, %function
-ETHERNET_IRQHandler:
-    ldr   r0,=ETHERNET_DriverIRQHandler
-    bx    r0
-    .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak ETHERNET_PMT_IRQHandler
-    .type ETHERNET_PMT_IRQHandler, %function
-ETHERNET_PMT_IRQHandler:
-    ldr   r0,=ETHERNET_PMT_DriverIRQHandler
-    bx    r0
-    .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak ETHERNET_MACLP_IRQHandler
-    .type ETHERNET_MACLP_IRQHandler, %function
-ETHERNET_MACLP_IRQHandler:
-    ldr   r0,=ETHERNET_MACLP_DriverIRQHandler
-    bx    r0
-    .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak EEPROM_IRQHandler
-    .type EEPROM_IRQHandler, %function
-EEPROM_IRQHandler:
-    ldr   r0,=EEPROM_DriverIRQHandler
-    bx    r0
-    .size EEPROM_IRQHandler, . - EEPROM_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak LCD_IRQHandler
-    .type LCD_IRQHandler, %function
-LCD_IRQHandler:
-    ldr   r0,=LCD_DriverIRQHandler
-    bx    r0
-    .size LCD_IRQHandler, . - LCD_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak SHA_IRQHandler
-    .type SHA_IRQHandler, %function
-SHA_IRQHandler:
-    ldr   r0,=SHA_DriverIRQHandler
-    bx    r0
-    .size SHA_IRQHandler, . - SHA_IRQHandler
-    
-    .align 1
-    .thumb_func
-    .weak SMARTCARD0_IRQHandler
-    .type SMARTCARD0_IRQHandler, %function
-SMARTCARD0_IRQHandler:
-    ldr   r0,=SMARTCARD0_DriverIRQHandler
-    bx    r0
-    .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler
-
-    .align 1
-    .thumb_func
-    .weak SMARTCARD1_IRQHandler
-    .type SMARTCARD1_IRQHandler, %function
-SMARTCARD1_IRQHandler:
-    ldr   r0,=SMARTCARD1_DriverIRQHandler
-    bx    r0
-    .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler
-    
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-
-    .macro def_irq_handler  handler_name
-    .weak \handler_name
-    .set  \handler_name, DefaultISR
-    .endm
-
-/* Exception Handlers */
-    def_irq_handler   WDT_BOD_DriverIRQHandler                              /* Windowed watchdog timer, Brownout detect */
-    def_irq_handler   DMA0_DriverIRQHandler                                 /* DMA controller */
-    def_irq_handler   GINT0_DriverIRQHandler                                /* GPIO group 0 */
-    def_irq_handler   GINT1_DriverIRQHandler                                /* GPIO group 1 */
-    def_irq_handler   PIN_INT0_DriverIRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
-    def_irq_handler   PIN_INT1_DriverIRQHandler                             /* Pin interrupt 1or pattern match engine slice 1 */
-    def_irq_handler   PIN_INT2_DriverIRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
-    def_irq_handler   PIN_INT3_DriverIRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
-    def_irq_handler   UTICK0_DriverIRQHandler                               /* Micro-tick Timer */
-    def_irq_handler   MRT0_DriverIRQHandler                                 /* Multi-rate timer */
-    def_irq_handler   CTIMER0_DriverIRQHandler                              /* Standard counter/timer CTIMER0 */
-    def_irq_handler   CTIMER1_DriverIRQHandler                              /* Standard counter/timer CTIMER1 */
-    def_irq_handler   SCT0_DriverIRQHandler                                 /* SCTimer/PWM */
-    def_irq_handler   CTIMER3_DriverIRQHandler                              /* Standard counter/timer CTIMER3 */
-    def_irq_handler   FLEXCOMM0_DriverIRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM1_DriverIRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM2_DriverIRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM3_DriverIRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM4_DriverIRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM5_DriverIRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM6_DriverIRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM7_DriverIRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
-    def_irq_handler   ADC0_SEQA_DriverIRQHandler                            /* ADC0 sequence A completion. */
-    def_irq_handler   ADC0_SEQB_DriverIRQHandler                            /* ADC0 sequence B completion. */
-    def_irq_handler   ADC0_THCMP_DriverIRQHandler                           /* ADC0 threshold compare and error. */
-    def_irq_handler   DMIC0_DriverIRQHandler                                /* Digital microphone and DMIC subsystem */
-    def_irq_handler   HWVAD0_DriverIRQHandler                               /* Hardware Voice Activity Detector */
-    def_irq_handler   USB0_NEEDCLK_DriverIRQHandler                         /* USB Activity Wake-up Interrupt */
-    def_irq_handler   USB0_DriverIRQHandler                                 /* USB device */
-    def_irq_handler   RTC_DriverIRQHandler                                  /* RTC alarm and wake-up interrupts */
-    def_irq_handler   Reserved46_DriverIRQHandler                           /* Reserved interrupt */
-    def_irq_handler   Reserved47_DriverIRQHandler                           /* Reserved interrupt */
-    def_irq_handler   PIN_INT4_DriverIRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
-    def_irq_handler   PIN_INT5_DriverIRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
-    def_irq_handler   PIN_INT6_DriverIRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
-    def_irq_handler   PIN_INT7_DriverIRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
-    def_irq_handler   CTIMER2_DriverIRQHandler                              /* Standard counter/timer CTIMER2 */
-    def_irq_handler   CTIMER4_DriverIRQHandler                              /* Standard counter/timer CTIMER4 */
-    def_irq_handler   RIT_DriverIRQHandler                                  /* Repetitive Interrupt Timer */
-    def_irq_handler   SPIFI0_DriverIRQHandler                               /* SPI flash interface */
-    def_irq_handler   FLEXCOMM8_DriverIRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   FLEXCOMM9_DriverIRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
-    def_irq_handler   SDIO_DriverIRQHandler                                 /* SD/MMC */
-    def_irq_handler   CAN0_IRQ0_DriverIRQHandler                            /* CAN0 interrupt0 */
-    def_irq_handler   CAN0_IRQ1_DriverIRQHandler                            /* CAN0 interrupt1 */
-    def_irq_handler   CAN1_IRQ0_DriverIRQHandler                            /* CAN1 interrupt0 */
-    def_irq_handler   CAN1_IRQ1_DriverIRQHandler                            /* CAN1 interrupt1 */
-    def_irq_handler   USB1_DriverIRQHandler                                 /* USB1 interrupt */
-    def_irq_handler   USB1_NEEDCLK_DriverIRQHandler                         /* USB1 activity */
-    def_irq_handler   ETHERNET_DriverIRQHandler                             /* Ethernet */
-    def_irq_handler   ETHERNET_PMT_DriverIRQHandler                         /* Ethernet power management interrupt */
-    def_irq_handler   ETHERNET_MACLP_DriverIRQHandler                       /* Ethernet MAC interrupt */
-    def_irq_handler   EEPROM_DriverIRQHandler                               /* EEPROM interrupt */
-    def_irq_handler   LCD_DriverIRQHandler                                  /* LCD interrupt */
-    def_irq_handler   SHA_DriverIRQHandler                                  /* SHA interrupt */
-    def_irq_handler   SMARTCARD0_DriverIRQHandler                           /* Smart card 0 interrupt */
-    def_irq_handler   SMARTCARD1_DriverIRQHandler                           /* Smart card 1 interrupt */
-
-    .end

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
-**
-**     Compiler:            IAR ANSI C/C++ Compiler for ARM
-**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b161227
-**
-**     Abstract:
-**         Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016 - 2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-** ###################################################################
-*/
-define symbol __ram_vector_table__ = 1;
-
-define symbol __stack_size__=0x8000;
-define symbol __heap_size__=0xC000;
-
-define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
-define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
-
-define symbol m_interrupts_start       = 0x00000000;
-define symbol m_interrupts_end         = 0x000003FF;
-
-define symbol m_text_start             = 0x00000400;
-define symbol m_text_end               = 0x0007FFFF;
-
-define symbol m_interrupts_ram_start   = 0x20000000;
-define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;
-
-define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
-define symbol m_data_end               = 0x20027FFF;
-
-define symbol m_usb_sram_start         = 0x40100000;
-define symbol m_usb_sram_end           = 0x40101FFF;
-
-/* USB BDT size */
-define symbol usb_bdt_size             = 0x0;
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
-  define symbol __size_cstack__        = __stack_size__;
-} else {
-  define symbol __size_cstack__        = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
-  define symbol __size_heap__          = __heap_size__;
-} else {
-  define symbol __size_heap__          = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE  = m_interrupts_start;
-define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
-                          | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
-
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block RW        { readwrite };
-define block ZI        { zi };
-
-/* regions for USB */
-define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
-define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
-place in USB_BDT_region                     { section m_usb_bdt };
-place in USB_SRAM_region                    { section m_usb_global };
-
-initialize by copy { readwrite, section .textrw };
-
-if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
-{
-  /* Required in a multi-threaded application */
-  initialize by copy with packing = none { section __DLIB_PERTHREAD };
-}
-
-do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
-
-place at address mem: m_interrupts_start    { readonly section .intvec };
-place in TEXT_region                        { readonly };
-place in DATA_region                        { block RW };
-place in DATA_region                        { block ZI };
-place in DATA_region                        { last block HEAP };
-place in CSTACK_region                      { block CSTACK };
-place in m_interrupts_ram_region            { section m_interrupts_ram };
-

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a has changed

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,615 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC54608.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
-; *           LPC54608
-; * @version: 1.1
-; * @date:    2016-11-25
-; *----------------------------------------------------------------------------
-; *
-; * Copyright 1997 - 2016 Freescale Semiconductor.
-; * Copyright 2016 - 2017 NXP
-; *
-; Redistribution and use in source and binary forms, with or without modification,
-; are permitted provided that the following conditions are met:
-;
-; o Redistributions of source code must retain the above copyright notice, this list
-;   of conditions and the following disclaimer.
-;
-; o Redistributions in binary form must reproduce the above copyright notice, this
-;   list of conditions and the following disclaimer in the documentation and/or
-;   other materials provided with the distribution.
-;
-; o Neither the name of the copyright holder nor the names of its
-;   contributors may be used to endorse or promote products derived from this
-;   software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0xFFFFFFFF ;ECRP
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
-        DCD     DMA0_IRQHandler  ; DMA controller
-        DCD     GINT0_IRQHandler  ; GPIO group 0
-        DCD     GINT1_IRQHandler  ; GPIO group 1
-        DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
-        DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
-        DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
-        DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
-        DCD     UTICK0_IRQHandler  ; Micro-tick Timer
-        DCD     MRT0_IRQHandler  ; Multi-rate timer
-        DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
-        DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
-        DCD     SCT0_IRQHandler  ; SCTimer/PWM
-        DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
-        DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
-        DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
-        DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
-        DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
-        DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
-        DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
-        DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
-        DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
-        DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
-        DCD     USB0_IRQHandler  ; USB device
-        DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
-        DCD     Reserved46_IRQHandler  ; Reserved interrupt
-        DCD     Reserved47_IRQHandler  ; Reserved interrupt
-        DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
-        DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
-        DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
-        DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
-        DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
-        DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
-        DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
-        DCD     SPIFI0_IRQHandler  ; SPI flash interface
-        DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
-        DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
-        DCD     SDIO_IRQHandler  ; SD/MMC
-        DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
-        DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
-        DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
-        DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
-        DCD     USB1_IRQHandler  ; USB1 interrupt
-        DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
-        DCD     ETHERNET_IRQHandler  ; Ethernet
-        DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
-        DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
-        DCD     EEPROM_IRQHandler  ; EEPROM interrupt
-        DCD     LCD_IRQHandler  ; LCD interrupt
-        DCD     SHA_IRQHandler  ; SHA interrupt
-        DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
-        DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-                LDR     r0, =SystemInit
-                BLX     r0
-                LDR     r0, =__iar_program_start
-                BX      r0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B .
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B .
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B .
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B .
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B .
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B .
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B .
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B .
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B .
-
-        PUBWEAK WDT_BOD_IRQHandler
-        PUBWEAK WDT_BOD_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-WDT_BOD_IRQHandler
-        LDR     R0, =WDT_BOD_DriverIRQHandler
-        BX      R0
-        PUBWEAK DMA0_IRQHandler
-        PUBWEAK DMA0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-DMA0_IRQHandler
-        LDR     R0, =DMA0_DriverIRQHandler
-        BX      R0
-        PUBWEAK GINT0_IRQHandler
-        PUBWEAK GINT0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-GINT0_IRQHandler
-        LDR     R0, =GINT0_DriverIRQHandler
-        BX      R0
-        PUBWEAK GINT1_IRQHandler
-        PUBWEAK GINT1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-GINT1_IRQHandler
-        LDR     R0, =GINT1_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT0_IRQHandler
-        PUBWEAK PIN_INT0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT0_IRQHandler
-        LDR     R0, =PIN_INT0_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT1_IRQHandler
-        PUBWEAK PIN_INT1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT1_IRQHandler
-        LDR     R0, =PIN_INT1_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT2_IRQHandler
-        PUBWEAK PIN_INT2_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT2_IRQHandler
-        LDR     R0, =PIN_INT2_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT3_IRQHandler
-        PUBWEAK PIN_INT3_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT3_IRQHandler
-        LDR     R0, =PIN_INT3_DriverIRQHandler
-        BX      R0
-        PUBWEAK UTICK0_IRQHandler
-        PUBWEAK UTICK0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-UTICK0_IRQHandler
-        LDR     R0, =UTICK0_DriverIRQHandler
-        BX      R0
-        PUBWEAK MRT0_IRQHandler
-        PUBWEAK MRT0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-MRT0_IRQHandler
-        LDR     R0, =MRT0_DriverIRQHandler
-        BX      R0
-        PUBWEAK CTIMER0_IRQHandler
-        PUBWEAK CTIMER0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CTIMER0_IRQHandler
-        LDR     R0, =CTIMER0_DriverIRQHandler
-        BX      R0
-        PUBWEAK CTIMER1_IRQHandler
-        PUBWEAK CTIMER1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CTIMER1_IRQHandler
-        LDR     R0, =CTIMER1_DriverIRQHandler
-        BX      R0
-        PUBWEAK SCT0_IRQHandler
-        PUBWEAK SCT0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SCT0_IRQHandler
-        LDR     R0, =SCT0_DriverIRQHandler
-        BX      R0
-        PUBWEAK CTIMER3_IRQHandler
-        PUBWEAK CTIMER3_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CTIMER3_IRQHandler
-        LDR     R0, =CTIMER3_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM0_IRQHandler
-        PUBWEAK FLEXCOMM0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM0_IRQHandler
-        LDR     R0, =FLEXCOMM0_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM1_IRQHandler
-        PUBWEAK FLEXCOMM1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM1_IRQHandler
-        LDR     R0, =FLEXCOMM1_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM2_IRQHandler
-        PUBWEAK FLEXCOMM2_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM2_IRQHandler
-        LDR     R0, =FLEXCOMM2_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM3_IRQHandler
-        PUBWEAK FLEXCOMM3_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM3_IRQHandler
-        LDR     R0, =FLEXCOMM3_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM4_IRQHandler
-        PUBWEAK FLEXCOMM4_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM4_IRQHandler
-        LDR     R0, =FLEXCOMM4_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM5_IRQHandler
-        PUBWEAK FLEXCOMM5_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM5_IRQHandler
-        LDR     R0, =FLEXCOMM5_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM6_IRQHandler
-        PUBWEAK FLEXCOMM6_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM6_IRQHandler
-        LDR     R0, =FLEXCOMM6_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM7_IRQHandler
-        PUBWEAK FLEXCOMM7_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM7_IRQHandler
-        LDR     R0, =FLEXCOMM7_DriverIRQHandler
-        BX      R0
-        PUBWEAK ADC0_SEQA_IRQHandler
-        PUBWEAK ADC0_SEQA_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ADC0_SEQA_IRQHandler
-        LDR     R0, =ADC0_SEQA_DriverIRQHandler
-        BX      R0
-        PUBWEAK ADC0_SEQB_IRQHandler
-        PUBWEAK ADC0_SEQB_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ADC0_SEQB_IRQHandler
-        LDR     R0, =ADC0_SEQB_DriverIRQHandler
-        BX      R0
-        PUBWEAK ADC0_THCMP_IRQHandler
-        PUBWEAK ADC0_THCMP_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ADC0_THCMP_IRQHandler
-        LDR     R0, =ADC0_THCMP_DriverIRQHandler
-        BX      R0
-        PUBWEAK DMIC0_IRQHandler
-        PUBWEAK DMIC0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-DMIC0_IRQHandler
-        LDR     R0, =DMIC0_DriverIRQHandler
-        BX      R0
-        PUBWEAK HWVAD0_IRQHandler
-        PUBWEAK HWVAD0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-HWVAD0_IRQHandler
-        LDR     R0, =HWVAD0_DriverIRQHandler
-        BX      R0
-        PUBWEAK USB0_NEEDCLK_IRQHandler
-        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-USB0_NEEDCLK_IRQHandler
-        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
-        BX      R0
-        PUBWEAK USB0_IRQHandler
-        PUBWEAK USB0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-USB0_IRQHandler
-        LDR     R0, =USB0_DriverIRQHandler
-        BX      R0
-        PUBWEAK RTC_IRQHandler
-        PUBWEAK RTC_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-RTC_IRQHandler
-        LDR     R0, =RTC_DriverIRQHandler
-        BX      R0
-        PUBWEAK Reserved46_IRQHandler
-        PUBWEAK Reserved46_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reserved46_IRQHandler
-        LDR     R0, =Reserved46_DriverIRQHandler
-        BX      R0
-        PUBWEAK Reserved47_IRQHandler
-        PUBWEAK Reserved47_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reserved47_IRQHandler
-        LDR     R0, =Reserved47_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT4_IRQHandler
-        PUBWEAK PIN_INT4_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT4_IRQHandler
-        LDR     R0, =PIN_INT4_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT5_IRQHandler
-        PUBWEAK PIN_INT5_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT5_IRQHandler
-        LDR     R0, =PIN_INT5_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT6_IRQHandler
-        PUBWEAK PIN_INT6_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT6_IRQHandler
-        LDR     R0, =PIN_INT6_DriverIRQHandler
-        BX      R0
-        PUBWEAK PIN_INT7_IRQHandler
-        PUBWEAK PIN_INT7_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-PIN_INT7_IRQHandler
-        LDR     R0, =PIN_INT7_DriverIRQHandler
-        BX      R0
-        PUBWEAK CTIMER2_IRQHandler
-        PUBWEAK CTIMER2_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CTIMER2_IRQHandler
-        LDR     R0, =CTIMER2_DriverIRQHandler
-        BX      R0
-        PUBWEAK CTIMER4_IRQHandler
-        PUBWEAK CTIMER4_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CTIMER4_IRQHandler
-        LDR     R0, =CTIMER4_DriverIRQHandler
-        BX      R0
-        PUBWEAK RIT_IRQHandler
-        PUBWEAK RIT_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-RIT_IRQHandler
-        LDR     R0, =RIT_DriverIRQHandler
-        BX      R0
-        PUBWEAK SPIFI0_IRQHandler
-        PUBWEAK SPIFI0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SPIFI0_IRQHandler
-        LDR     R0, =SPIFI0_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM8_IRQHandler
-        PUBWEAK FLEXCOMM8_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM8_IRQHandler
-        LDR     R0, =FLEXCOMM8_DriverIRQHandler
-        BX      R0
-        PUBWEAK FLEXCOMM9_IRQHandler
-        PUBWEAK FLEXCOMM9_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-FLEXCOMM9_IRQHandler
-        LDR     R0, =FLEXCOMM9_DriverIRQHandler
-        BX      R0
-        PUBWEAK SDIO_IRQHandler
-        PUBWEAK SDIO_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SDIO_IRQHandler
-        LDR     R0, =SDIO_DriverIRQHandler
-        BX      R0
-        PUBWEAK CAN0_IRQ0_IRQHandler
-        PUBWEAK CAN0_IRQ0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CAN0_IRQ0_IRQHandler
-        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
-        BX      R0
-        PUBWEAK CAN0_IRQ1_IRQHandler
-        PUBWEAK CAN0_IRQ1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CAN0_IRQ1_IRQHandler
-        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
-        BX      R0
-        PUBWEAK CAN1_IRQ0_IRQHandler
-        PUBWEAK CAN1_IRQ0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CAN1_IRQ0_IRQHandler
-        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
-        BX      R0
-        PUBWEAK CAN1_IRQ1_IRQHandler
-        PUBWEAK CAN1_IRQ1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-CAN1_IRQ1_IRQHandler
-        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
-        BX      R0
-        PUBWEAK USB1_IRQHandler
-        PUBWEAK USB1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-USB1_IRQHandler
-        LDR     R0, =USB1_DriverIRQHandler
-        BX      R0
-        PUBWEAK USB1_NEEDCLK_IRQHandler
-        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-USB1_NEEDCLK_IRQHandler
-        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
-        BX      R0
-        PUBWEAK ETHERNET_IRQHandler
-        PUBWEAK ETHERNET_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ETHERNET_IRQHandler
-        LDR     R0, =ETHERNET_DriverIRQHandler
-        BX      R0
-        PUBWEAK ETHERNET_PMT_IRQHandler
-        PUBWEAK ETHERNET_PMT_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ETHERNET_PMT_IRQHandler
-        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
-        BX      R0
-        PUBWEAK ETHERNET_MACLP_IRQHandler
-        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-ETHERNET_MACLP_IRQHandler
-        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
-        BX      R0
-        PUBWEAK EEPROM_IRQHandler
-        PUBWEAK EEPROM_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-EEPROM_IRQHandler
-        LDR     R0, =EEPROM_DriverIRQHandler
-        BX      R0
-        PUBWEAK LCD_IRQHandler
-        PUBWEAK LCD_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-LCD_IRQHandler
-        LDR     R0, =LCD_DriverIRQHandler
-        BX      R0
-        PUBWEAK SHA_IRQHandler
-        PUBWEAK SHA_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SHA_IRQHandler
-        LDR     R0, =SHA_DriverIRQHandler
-        BX      R0
-        PUBWEAK SMARTCARD0_IRQHandler
-        PUBWEAK SMARTCARD0_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SMARTCARD0_IRQHandler
-        LDR     R0, =SMARTCARD0_DriverIRQHandler
-        BX      R0
-        PUBWEAK SMARTCARD1_IRQHandler
-        PUBWEAK SMARTCARD1_DriverIRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-SMARTCARD1_IRQHandler
-        LDR     R0, =SMARTCARD1_DriverIRQHandler
-        BX      R0
-WDT_BOD_DriverIRQHandler
-DMA0_DriverIRQHandler
-GINT0_DriverIRQHandler
-GINT1_DriverIRQHandler
-PIN_INT0_DriverIRQHandler
-PIN_INT1_DriverIRQHandler
-PIN_INT2_DriverIRQHandler
-PIN_INT3_DriverIRQHandler
-UTICK0_DriverIRQHandler
-MRT0_DriverIRQHandler
-CTIMER0_DriverIRQHandler
-CTIMER1_DriverIRQHandler
-SCT0_DriverIRQHandler
-CTIMER3_DriverIRQHandler
-FLEXCOMM0_DriverIRQHandler
-FLEXCOMM1_DriverIRQHandler
-FLEXCOMM2_DriverIRQHandler
-FLEXCOMM3_DriverIRQHandler
-FLEXCOMM4_DriverIRQHandler
-FLEXCOMM5_DriverIRQHandler
-FLEXCOMM6_DriverIRQHandler
-FLEXCOMM7_DriverIRQHandler
-ADC0_SEQA_DriverIRQHandler
-ADC0_SEQB_DriverIRQHandler
-ADC0_THCMP_DriverIRQHandler
-DMIC0_DriverIRQHandler
-HWVAD0_DriverIRQHandler
-USB0_NEEDCLK_DriverIRQHandler
-USB0_DriverIRQHandler
-RTC_DriverIRQHandler
-Reserved46_DriverIRQHandler
-Reserved47_DriverIRQHandler
-PIN_INT4_DriverIRQHandler
-PIN_INT5_DriverIRQHandler
-PIN_INT6_DriverIRQHandler
-PIN_INT7_DriverIRQHandler
-CTIMER2_DriverIRQHandler
-CTIMER4_DriverIRQHandler
-RIT_DriverIRQHandler
-SPIFI0_DriverIRQHandler
-FLEXCOMM8_DriverIRQHandler
-FLEXCOMM9_DriverIRQHandler
-SDIO_DriverIRQHandler
-CAN0_IRQ0_DriverIRQHandler
-CAN0_IRQ1_DriverIRQHandler
-CAN1_IRQ0_DriverIRQHandler
-CAN1_IRQ1_DriverIRQHandler
-USB1_DriverIRQHandler
-USB1_NEEDCLK_DriverIRQHandler
-ETHERNET_DriverIRQHandler
-ETHERNET_PMT_DriverIRQHandler
-ETHERNET_MACLP_DriverIRQHandler
-EEPROM_DriverIRQHandler
-LCD_DriverIRQHandler
-SHA_DriverIRQHandler
-SMARTCARD0_DriverIRQHandler
-SMARTCARD1_DriverIRQHandler
-DefaultISR
-        B .
-
-        END

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2017 ARM Limited. All rights reserved.
- *
- * A generic CMSIS include header, pulling in LPC54608 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "fsl_device_registers.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 - 2017 NXP
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef __FSL_DEVICE_REGISTERS_H__
-#define __FSL_DEVICE_REGISTERS_H__
-
-/*
- * Include the cpu specific register header files.
- *
- * The CPU macro should be declared in the project or makefile.
- */
-#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180))
-
-#define LPC54608_SERIES
-
-/* CMSIS-style register definitions */
-#include "LPC54608.h"
-/* CPU specific feature definitions */
-#include "LPC54608_features.h"
-
-#else
-    #error "No valid CPU defined!"
-#endif
-
-#endif /* __FSL_DEVICE_REGISTERS_H__ */
-
-/*******************************************************************************
- * EOF
- ******************************************************************************/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,361 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
-**
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**                          MCUXpresso Compiler
-**
-**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b170214
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2016-08-12)
-**         Initial version.
-**     - rev. 1.1 (2016-11-25)
-**         Update CANFD and Classic CAN register.
-**         Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54608
- * @version 1.1
- * @date 2016-11-25
- * @brief Device specific configuration file for LPC54608 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "fsl_device_registers.h"
-
-#define NVALMAX (0x100)
-#define PVALMAX (0x20)
-#define MVALMAX (0x8000)
-#define PLL_MDEC_VAL_P (0)                                       /* MDEC is in bits  16:0 */
-#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
-#define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
-#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
-#define PLL_PDEC_VAL_P (0)                                       /* PDEC is in bits  6:0 */
-#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
-
-extern void *__Vectors;
-
-static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
-                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
-/* Get WATCH DOG Clk */
-static uint32_t getWdtOscFreq(void)
-{
-    uint8_t freq_sel, div_sel;
-    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
-    {
-        return 0U;
-    }
-    else
-    {
-        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
-        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
-        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
-    }
-}
-/* Find decoded N value for raw NDEC value */
-static uint32_t pllDecodeN(uint32_t NDEC)
-{
-    uint32_t n, x, i;
-
-    /* Find NDec */
-    switch (NDEC)
-    {
-        case 0x3FF:
-            n = 0;
-            break;
-        case 0x302:
-            n = 1;
-            break;
-        case 0x202:
-            n = 2;
-            break;
-        default:
-            x = 0x080;
-            n = 0xFFFFFFFFU;
-            for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
-                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
-                {
-                    /* Decoded value of NDEC */
-                    n = i;
-                }
-            }
-            break;
-    }
-    return n;
-}
-
-/* Find decoded P value for raw PDEC value */
-static uint32_t pllDecodeP(uint32_t PDEC)
-{
-    uint32_t p, x, i;
-    /* Find PDec */
-    switch (PDEC)
-    {
-        case 0x7F:
-            p = 0;
-            break;
-        case 0x62:
-            p = 1;
-            break;
-        case 0x42:
-            p = 2;
-            break;
-        default:
-            x = 0x10;
-            p = 0xFFFFFFFFU;
-            for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU);
-                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
-                {
-                    /* Decoded value of PDEC */
-                    p = i;
-                }
-            }
-            break;
-    }
-    return p;
-}
-
-/* Find decoded M value for raw MDEC value */
-static uint32_t pllDecodeM(uint32_t MDEC)
-{
-    uint32_t m, i, x;
-
-    /* Find MDec */
-    switch (MDEC)
-    {
-        case 0x1FFFF:
-            m = 0;
-            break;
-        case 0x18003:
-            m = 1;
-            break;
-        case 0x10003:
-            m = 2;
-            break;
-        default:
-            x = 0x04000;
-            m = 0xFFFFFFFFU;
-            for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU);
-                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
-                {
-                    /* Decoded value of MDEC */
-                    m = i;
-                }
-            }
-            break;
-    }
-    return m;
-}
-
-/* Get predivider (N) from PLL NDEC setting */
-static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
-{
-    uint32_t preDiv = 1;
-
-    /* Direct input is not used? */
-    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
-    {
-        /* Decode NDEC value to get (N) pre divider */
-        preDiv = pllDecodeN(nDecReg & 0x3FF);
-        if (preDiv == 0)
-        {
-            preDiv = 1;
-        }
-    }
-    /* Adjusted by 1, directi is used to bypass */
-    return preDiv;
-}
-
-/* Get postdivider (P) from PLL PDEC setting */
-static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
-{
-    uint32_t postDiv = 1;
-
-    /* Direct input is not used? */
-    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
-    {
-        /* Decode PDEC value to get (P) post divider */
-        postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
-        if (postDiv == 0)
-        {
-            postDiv = 2;
-        }
-    }
-    /* Adjusted by 1, directo is used to bypass */
-    return postDiv;
-}
-
-/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
-static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
-{
-    uint32_t mMult = 1;
-
-    /* Decode MDEC value to get (M) multiplier */
-    mMult = pllDecodeM(mDecReg & 0x1FFFF);
-    if (mMult == 0)
-    {
-        mMult = 1;
-    }
-    return mMult;
-}
-
-
-
-/* ----------------------------------------------------------------------------
-   -- Core clock
-   ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
-   -- SystemInit()
-   ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
-  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-
-#if defined(__MCUXPRESSO)
-    extern void(*const g_pfnVectors[]) (void);
-    SCB->VTOR = (uint32_t) &g_pfnVectors;
-#else
-    extern void *__Vectors;
-    SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-    SYSCON->ARMTRACECLKDIV = 0;
-/* Optionally enable RAM banks that may be off by default at reset */
-#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
-  SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
-#endif
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemCoreClockUpdate()
-   ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-uint32_t clkRate = 0;
-    uint32_t prediv, postdiv;
-    uint64_t workRate;
-
-    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
-    {
-        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
-            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
-            {
-                case 0x00: /* FRO 12 MHz (fro_12m) */
-                    clkRate = CLK_FRO_12MHZ;
-                    break;
-                case 0x01: /* CLKIN (clk_in) */
-                    clkRate = CLK_CLK_IN;
-                    break;
-                case 0x02: /* Watchdog oscillator (wdt_clk) */
-                    clkRate = getWdtOscFreq();
-                    break;
-                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
-                    if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
-                    {
-                        clkRate = CLK_FRO_96MHZ;
-                    }
-                    else
-                    {
-                        clkRate = CLK_FRO_48MHZ;
-                    }
-                    break;
-            }
-            break;
-        case 0x02: /* System PLL clock (pll_clk)*/
-            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
-            {
-                case 0x00: /* FRO 12 MHz (fro_12m) */
-                    clkRate = CLK_FRO_12MHZ;
-                    break;
-                case 0x01: /* CLKIN (clk_in) */
-                    clkRate = CLK_CLK_IN;
-                    break;
-                case 0x02: /* Watchdog oscillator (wdt_clk) */
-                    clkRate = getWdtOscFreq();
-                    break;
-                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
-                    clkRate = CLK_RTC_32K_CLK;
-                    break;
-                default:
-                    break;
-            }
-            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
-            {
-                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
-                prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
-                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
-                /* Adjust input clock */
-                clkRate = clkRate / prediv;
-
-                /* MDEC used for rate */
-                workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
-                clkRate = workRate / ((uint64_t)postdiv);
-                clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
-            }
-            break;
-        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
-            clkRate = CLK_RTC_32K_CLK;
-            break;
-        default:
-            break;
-    }
-    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/*
-** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
-**
-**     Compilers:           Keil ARM C/C++ Compiler
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**                          MCUXpresso Compiler
-**
-**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
-**     Version:             rev. 1.1, 2016-11-25
-**     Build:               b161227
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016 - 2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.nxp.com
-**     mail:                 support@nxp.com
-**
-**     Revisions:
-**     - rev. 1.0 (2016-08-12)
-**         Initial version.
-**     - rev. 1.1 (2016-11-25)
-**         Update CANFD and Classic CAN register.
-**         Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54608
- * @version 1.1
- * @date 2016-11-25
- * @brief Device specific configuration file for LPC54608 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef _SYSTEM_LPC54608_H_
-#define _SYSTEM_LPC54608_H_                      /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
-#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
-#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
-#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
-#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
-#define CLK_CLK_IN                            0u           /* Default CLK_IN pin clock */
-
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SYSTEM_LPC54608_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,316 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_adc.h"
-#include "fsl_clock.h"
-
-static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-static uint32_t ADC_GetInstance(ADC_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
-    {
-        if (s_adcBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_adcBases));
-
-    return instance;
-}
-
-void ADC_Init(ADC_Type *base, const adc_config_t *config)
-{
-    assert(config != NULL);
-
-    uint32_t tmp32 = 0U;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable clock. */
-    CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Disable the interrupts. */
-    base->INTEN = 0U; /* Quickly disable all the interrupts. */
-
-    /* Configure the ADC block. */
-    tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
-
-    /* Async or Sync clock mode. */
-    switch (config->clockMode)
-    {
-        case kADC_ClockAsynchronousMode:
-            tmp32 |= ADC_CTRL_ASYNMODE_MASK;
-            break;
-        default: /* kADC_ClockSynchronousMode */
-            break;
-    }
-
-    /* Resolution. */
-    tmp32 |= ADC_CTRL_RESOL(config->resolution);
-
-    /* Bypass calibration. */
-    if (config->enableBypassCalibration)
-    {
-        tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
-    }
-
-    /* Sample time clock count. */
-    tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
-
-    base->CTRL = tmp32;
-}
-
-void ADC_GetDefaultConfig(adc_config_t *config)
-{
-    config->clockMode = kADC_ClockSynchronousMode;
-    config->clockDividerNumber = 0U;
-    config->resolution = kADC_Resolution12bit;
-    config->enableBypassCalibration = false;
-    config->sampleTimeNumber = 0U;
-}
-
-void ADC_Deinit(ADC_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the clock. */
-    CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-bool ADC_DoSelfCalibration(ADC_Type *base)
-{
-    uint32_t i;
-
-    /* Enable the converter. */
-    /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
-       This bit should be set after at least 10 ms after the ADC is powered on. */
-    base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
-    for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
-    {
-        __ASM("NOP");
-    }
-    if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
-    {
-        return false; /* ADC is not powered up. */
-    }
-
-    /* If not in by-pass mode, do the calibration. */
-    if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
-        (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
-    {
-        /* Calibration is needed, do it now. */
-        base->CALIB = ADC_CALIB_CALIB_MASK;
-        i = 0xF0000;
-        while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
-        {
-        }
-        if (i == 0U)
-        {
-            return false; /* Calibration timeout. */
-        }
-    }
-
-    /* A dummy conversion cycle will be performed. */
-    base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
-    i = 0x7FFFF;
-    while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
-    {
-    }
-    if (i == 0U)
-    {
-        return false;
-    }
-
-    return true;
-}
-
-void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
-{
-    assert(config != NULL);
-
-    uint32_t tmp32;
-
-    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
-            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
-
-    /* Polarity for tirgger signal. */
-    switch (config->triggerPolarity)
-    {
-        case kADC_TriggerPolarityPositiveEdge:
-            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
-            break;
-        default: /* kADC_TriggerPolarityNegativeEdge */
-            break;
-    }
-
-    /* Bypass the clock Sync. */
-    if (config->enableSyncBypass)
-    {
-        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
-    }
-
-    /* Interrupt point. */
-    switch (config->interruptMode)
-    {
-        case kADC_InterruptForEachSequence:
-            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
-            break;
-        default: /* kADC_InterruptForEachConversion */
-            break;
-    }
-
-    /* One trigger for a conversion, or for a sequence. */
-    if (config->enableSingleStep)
-    {
-        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
-    }
-
-    base->SEQ_CTRL[0] = tmp32;
-}
-
-void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
-{
-    assert(config != NULL);
-
-    uint32_t tmp32;
-
-    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
-            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
-
-    /* Polarity for tirgger signal. */
-    switch (config->triggerPolarity)
-    {
-        case kADC_TriggerPolarityPositiveEdge:
-            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
-            break;
-        default: /* kADC_TriggerPolarityPositiveEdge */
-            break;
-    }
-
-    /* Bypass the clock Sync. */
-    if (config->enableSyncBypass)
-    {
-        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
-    }
-
-    /* Interrupt point. */
-    switch (config->interruptMode)
-    {
-        case kADC_InterruptForEachSequence:
-            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
-            break;
-        default: /* kADC_InterruptForEachConversion */
-            break;
-    }
-
-    /* One trigger for a conversion, or for a sequence. */
-    if (config->enableSingleStep)
-    {
-        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
-    }
-
-    base->SEQ_CTRL[1] = tmp32;
-}
-
-bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
-{
-    assert(info != NULL);
-
-    uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
-
-    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
-    {
-        return false;
-    }
-
-    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
-    info->thresholdCompareStatus =
-        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
-    info->thresholdCorssingStatus =
-        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
-    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
-    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
-
-    return true;
-}
-
-bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
-{
-    assert(info != NULL);
-
-    uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
-
-    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
-    {
-        return false;
-    }
-
-    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
-    info->thresholdCompareStatus =
-        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
-    info->thresholdCorssingStatus =
-        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
-    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
-    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
-
-    return true;
-}
-
-bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
-{
-    assert(info != NULL);
-    assert(channel < ADC_DAT_COUNT);
-
-    uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
-
-    if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
-    {
-        return false;
-    }
-
-    info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
-    info->thresholdCompareStatus =
-        (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
-    info->thresholdCorssingStatus =
-        (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
-    info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
-    info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
-
-    return true;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,664 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __FSL_ADC_H__
-#define __FSL_ADC_H__
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpc_adc
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief ADC driver version 2.0.0. */
-#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*!
- * @brief Flags
- */
-enum _adc_status_flags
-{
-    kADC_ThresholdCompareFlagOnChn0 = 1U << 0U,   /*!< Threshold comparison event on Channel 0. */
-    kADC_ThresholdCompareFlagOnChn1 = 1U << 1U,   /*!< Threshold comparison event on Channel 1. */
-    kADC_ThresholdCompareFlagOnChn2 = 1U << 2U,   /*!< Threshold comparison event on Channel 2. */
-    kADC_ThresholdCompareFlagOnChn3 = 1U << 3U,   /*!< Threshold comparison event on Channel 3. */
-    kADC_ThresholdCompareFlagOnChn4 = 1U << 4U,   /*!< Threshold comparison event on Channel 4. */
-    kADC_ThresholdCompareFlagOnChn5 = 1U << 5U,   /*!< Threshold comparison event on Channel 5. */
-    kADC_ThresholdCompareFlagOnChn6 = 1U << 6U,   /*!< Threshold comparison event on Channel 6. */
-    kADC_ThresholdCompareFlagOnChn7 = 1U << 7U,   /*!< Threshold comparison event on Channel 7. */
-    kADC_ThresholdCompareFlagOnChn8 = 1U << 8U,   /*!< Threshold comparison event on Channel 8. */
-    kADC_ThresholdCompareFlagOnChn9 = 1U << 9U,   /*!< Threshold comparison event on Channel 9. */
-    kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
-    kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
-    kADC_OverrunFlagForChn0 =
-        1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
-    kADC_OverrunFlagForChn1 =
-        1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
-    kADC_OverrunFlagForChn2 =
-        1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
-    kADC_OverrunFlagForChn3 =
-        1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
-    kADC_OverrunFlagForChn4 =
-        1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
-    kADC_OverrunFlagForChn5 =
-        1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
-    kADC_OverrunFlagForChn6 =
-        1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
-    kADC_OverrunFlagForChn7 =
-        1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
-    kADC_OverrunFlagForChn8 =
-        1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
-    kADC_OverrunFlagForChn9 =
-        1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
-    kADC_OverrunFlagForChn10 =
-        1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
-    kADC_OverrunFlagForChn11 =
-        1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
-    kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
-    kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
-    kADC_ConvSeqAInterruptFlag = 1U << 28U,    /*!< Sequence A interrupt/DMA trigger. */
-    kADC_ConvSeqBInterruptFlag = 1U << 29U,    /*!< Sequence B interrupt/DMA trigger. */
-    kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
-    kADC_OverrunInterruptFlag = 1U << 31U,          /*!< Overrun interrupt flag. */
-};
-
-/*!
- * @brief Interrupts
- * @note Not all the interrupt options are listed here
- */
-enum _adc_interrupt_enable
-{
-    kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
-                                                                   conversion in sequence A, or entire sequence. */
-    kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
-                                                                   conversion in sequence B, or entire sequence. */
-    kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
-                                                                 the channel data registers will cause an overrun
-                                                                 interrupt/DMA trigger. */
-};
-
-/*!
- * @brief Define selection of clock mode.
- */
-typedef enum _adc_clock_mode
-{
-    kADC_ClockSynchronousMode =
-        0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
-    kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
-} adc_clock_mode_t;
-
-/*!
- * @brief Define selection of resolution.
- */
-typedef enum _adc_resolution
-{
-    kADC_Resolution6bit = 0U,  /*!< 6-bit resolution. */
-    kADC_Resolution8bit = 1U,  /*!< 8-bit resolution. */
-    kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
-    kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
-} adc_resolution_t;
-
-/*!
- * @brief Define selection of polarity of selected input trigger for conversion sequence.
- */
-typedef enum _adc_trigger_polarity
-{
-    kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
-    kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
-} adc_trigger_polarity_t;
-
-/*!
- * @brief Define selection of conversion sequence's priority.
- */
-typedef enum _adc_priority
-{
-    kADC_PriorityLow = 0U,  /*!< This sequence would be preempted when another sequence is started. */
-    kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */
-} adc_priority_t;
-
-/*!
- * @brief Define selection of conversion sequence's interrupt.
- */
-typedef enum _adc_seq_interrupt_mode
-{
-    kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
-                                               individual ADC conversion inside this conversion sequence. */
-    kADC_InterruptForEachSequence = 1U,   /*!< The sequence interrupt/DMA trigger will be set when the entire set of
-                                               this sequence conversions completes. */
-} adc_seq_interrupt_mode_t;
-
-/*!
- * @brief Define status of threshold compare result.
- */
-typedef enum _adc_threshold_compare_status
-{
-    kADC_ThresholdCompareInRange = 0U,    /*!< LOW threshold <= conversion value <= HIGH threshold. */
-    kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
-    kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
-} adc_threshold_compare_status_t;
-
-/*!
- * @brief Define status of threshold crossing detection result.
- */
-typedef enum _adc_threshold_crossing_status
-{
-    /* The conversion on this channel had the same relationship (above or below) to the threshold value established by
-     * the designated LOW threshold value as did the previous conversion on this channel. */
-    kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
-
-    /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
-     * channel was above the threshold value established by the designated LOW threshold value and the current sample is
-     * below that threshold. */
-    kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
-
-    /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
-     * channel was below the threshold value established by the designated LOW threshold value and the current sample is
-     * above that threshold. */
-    kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
-} adc_threshold_crossing_status_t;
-
-/*!
- * @brief Define interrupt mode for threshold compare event.
- */
-typedef enum _adc_threshold_interrupt_mode
-{
-    kADC_ThresholdInterruptDisabled = 0U,   /*!< Threshold comparison interrupt is disabled. */
-    kADC_ThresholdInterruptOnOutside = 1U,  /*!< Threshold comparison interrupt is enabled on outside threshold. */
-    kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
-} adc_threshold_interrupt_mode_t;
-
-/*!
- * @brief Define structure for configuring the block.
- */
-typedef struct _adc_config
-{
-    adc_clock_mode_t clockMode;   /*!< Select the clock mode for ADC converter. */
-    uint32_t clockDividerNumber;  /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
-                                       field. The divider would be plused by 1 based on the value in this field. The
-                                       available range is in 8 bits. */
-    adc_resolution_t resolution;  /*!< Select the conversion bits. */
-    bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
-                                       powered-up. Re-calibration may be warranted periodically - especially if
-                                       operating conditions have changed. To enable this option would avoid the need to
-                                       calibrate if offset error is not a concern in the application. */
-    uint32_t sampleTimeNumber;    /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
-                                       to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
-} adc_config_t;
-
-/*!
- * @brief Define structure for configuring conversion sequence.
- */
-typedef struct _adc_conv_seq_config
-{
-    uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
-                               sequence is launched. The masked channels would be involved in current conversion
-                               sequence, beginning with the lowest-order. The available range is in 12-bit. */
-    uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
-                               conversion sequence to be initiated. The available range is 6-bit.*/
-    adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
-    bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
-                                flip-flop stages and therefore shorten the time between the trigger input signal and the
-                                start of a conversion. */
-    bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
-                                channel in the sequence instead of the default response of launching an entire sequence
-                                of conversions. */
-    adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
-} adc_conv_seq_config_t;
-
-/*!
- * @brief Define structure of keeping conversion result information.
- */
-typedef struct _adc_result_info
-{
-    uint32_t result;                                         /*!< Keey the conversion data value. */
-    adc_threshold_compare_status_t thresholdCompareStatus;   /*!< Keep the threshold compare status. */
-    adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
-    uint32_t channelNumber;                                  /*!< Keep the channel number for this conversion. */
-    bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
-    /* The data available flag would be returned by the reading result API. */
-} adc_result_info_t;
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-/*!
- * @name Initialization and Deinitialization
- * @{
- */
-
-/*!
- * @brief Initialize the ADC module.
- *
- * @param base ADC peripheral base address.
- * @param config Pointer to configuration structure, see to #adc_config_t.
- */
-void ADC_Init(ADC_Type *base, const adc_config_t *config);
-
-/*!
- * @brief Deinitialize the ADC module.
- *
- * @param base ADC peripheral base address.
- */
-void ADC_Deinit(ADC_Type *base);
-
-/*!
- * @brief Gets an available pre-defined settings for initial configuration.
- *
- * This function initializes the initial configuration structure with an available settings. The default values are:
- * @code
- *   config->clockMode = kADC_ClockSynchronousMode;
- *   config->clockDividerNumber = 0U;
- *   config->resolution = kADC_Resolution12bit;
- *   config->enableBypassCalibration = false;
- *   config->sampleTimeNumber = 0U;
- * @endcode
- * @param config Pointer to configuration structure.
- */
-void ADC_GetDefaultConfig(adc_config_t *config);
-
-/*!
- * @brief Do the self hardware calibration.
- *
- * @param base ADC peripheral base address.
- * @retval true  Calibration succeed.
- * @retval false Calibration failed.
- */
-bool ADC_DoSelfCalibration(ADC_Type *base);
-
-/*!
- * @brief Enable the internal temperature sensor measurement.
- *
- * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
- * instead of external pin.
- *
- * @param base ADC peripheral base address.
- * @param enable Switcher to enable the feature or not.
- */
-static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
-    }
-    else
-    {
-        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
-    }
-}
-
-/* @} */
-
-/*!
- * @name Control conversion sequence A.
- * @{
- */
-
-/*!
- * @brief Enable the conversion sequence A.
- *
- * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
- * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
- * sequence during changing the sequence's setting.
- *
- * @param base ADC peripheral base address.
- * @param enable Switcher to enable the feature or not.
- */
-static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
-    }
-    else
-    {
-        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
-    }
-}
-
-/*!
- * @brief Configure the conversion sequence A.
- *
- * @param base ADC peripheral base address.
- * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
- */
-void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
-
-/*!
- * @brief Do trigger the sequence's conversion by software.
- *
- * @param base ADC peripheral base address.
- */
-static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
-{
-    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
-}
-
-/*!
- * @brief Enable the burst conversion of sequence A.
- *
- * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
- * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
- * currently in process will be completed before cnversions are terminated.
- * Note that a new sequence could begin just before the burst mode is disabled.
- *
- * @param base ADC peripheral base address.
- * @param enable Switcher to enable this feature.
- */
-static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
-    }
-    else
-    {
-        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
-    }
-}
-
-/*!
- * @brief Set the high priority for conversion sequence A.
- *
- * @param base ADC peripheral bass address.
- */
-static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
-{
-    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
-}
-
-/* @} */
-
-/*!
- * @name Control conversion sequence B.
- * @{
- */
-
-/*!
- * @brief Enable the conversion sequence B.
- *
- * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
- * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
- * sequence during changing the sequence's setting.
- *
- * @param base ADC peripheral base address.
- * @param enable Switcher to enable the feature or not.
- */
-static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
-    }
-    else
-    {
-        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
-    }
-}
-
-/*!
- * @brief Configure the conversion sequence B.
- *
- * @param base ADC peripheral base address.
- * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
- */
-void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
-
-/*!
- * @brief Do trigger the sequence's conversion by software.
- *
- * @param base ADC peripheral base address.
- */
-static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
-{
-    base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
-}
-
-/*!
- * @brief Enable the burst conversion of sequence B.
- *
- * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
- * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
- * currently in process will be completed before cnversions are terminated.
- * Note that a new sequence could begin just before the burst mode is disabled.
- *
- * @param base ADC peripheral base address.
- * @param enable Switcher to enable this feature.
- */
-static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
-    }
-    else
-    {
-        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
-    }
-}
-
-/*!
- * @brief Set the high priority for conversion sequence B.
- *
- * @param base ADC peripheral bass address.
- */
-static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
-{
-    base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
-}
-
-/* @} */
-
-/*!
- * @name Data result.
- * @{
- */
-
-/*!
- * @brief Get the global ADC conversion infomation of sequence A.
- *
- * @param base ADC peripheral base address.
- * @param info Pointer to information structure, see to #adc_result_info_t;
- * @retval true  The conversion result is ready.
- * @retval false The conversion result is not ready yet.
- */
-bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
-
-/*!
- * @brief Get the global ADC conversion infomation of sequence B.
- *
- * @param base ADC peripheral base address.
- * @param info Pointer to information structure, see to #adc_result_info_t;
- * @retval true  The conversion result is ready.
- * @retval false The conversion result is not ready yet.
- */
-bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
-
-/*!
- * @brief Get the channel's ADC conversion completed under each conversion sequence.
- *
- * @param base ADC peripheral base address.
- * @param channel The indicated channel number.
- * @param info Pointer to information structure, see to #adc_result_info_t;
- * @retval true  The conversion result is ready.
- * @retval false The conversion result is not ready yet.
- */
-bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
-
-/* @} */
-
-/*!
- * @name Threshold function.
- * @{
- */
-
-/*!
- * @brief Set the threshhold pair 0 with low and high value.
- *
- * @param base ADC peripheral base address.
- * @param lowValue LOW threshold value.
- * @param highValue HIGH threshold value.
- */
-static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
-{
-    base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
-    base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
-}
-
-/*!
- * @brief Set the threshhold pair 1 with low and high value.
- *
- * @param base ADC peripheral base address.
- * @param lowValue LOW threshold value. The available value is with 12-bit.
- * @param highValue HIGH threshold value. The available value is with 12-bit.
- */
-static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
-{
-    base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
-    base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
-}
-
-/*!
- * @brief Set given channels to apply the threshold pare 0.
- *
- * @param base ADC peripheral base address.
- * @param channelMask Indicated channels' mask.
- */
-static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
-{
-    base->CHAN_THRSEL &= ~(channelMask);
-}
-
-/*!
- * @brief Set given channels to apply the threshold pare 1.
- *
- * @param base ADC peripheral base address.
- * @param channelMask Indicated channels' mask.
- */
-static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
-{
-    base->CHAN_THRSEL |= channelMask;
-}
-
-/* @} */
-
-/*!
- * @name Interrupts.
- * @{
- */
-
-/*!
- * @brief Enable interrupts for conversion sequences.
- *
- * @param base ADC peripheral base address.
- * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
- */
-static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
-{
-    base->INTEN |= (0x7 & mask);
-}
-
-/*!
- * @brief Disable interrupts for conversion sequence.
- *
- * @param base ADC peripheral base address.
- * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
- */
-static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
-{
-    base->INTEN &= ~(0x7 & mask);
-}
-
-/*!
- * @brief Enable the interrupt of shreshold compare event for each channel.
- *
- * @param base ADC peripheral base address.
- * @param channel Channel number.
- * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
- */
-static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
-                                                       uint32_t channel,
-                                                       adc_threshold_interrupt_mode_t mode)
-{
-    base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
-}
-
-/* @} */
-
-/*!
- * @name Status.
- * @{
- */
-
-/*!
- * @brief Get status flags of ADC module.
- *
- * @param base ADC peripheral base address.
- * @return Mask of status flags of module, see to #_adc_status_flags.
- */
-static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
-{
-    return base->FLAGS;
-}
-
-/*!
- * @brief Clear status flags of ADC module.
- *
- * @param base ADC peripheral base address.
- * @param mask Mask of status flags of module, see to #_adc_status_flags.
- */
-static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
-{
-    base->FLAGS = mask; /* Write 1 to clear. */
-}
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/* @} */
-
-#endif /* __FSL_ADC_H__ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2106 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016 - 2017 , NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_common.h"
-#include "fsl_clock.h"
-#include "fsl_power.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define NVALMAX (0x100U)
-#define PVALMAX (0x20U)
-#define MVALMAX (0x8000U)
-
-#define USB_NVALMAX (0x4U)
-#define USB_PVALMAX (0x8U)
-#define USB_MVALMAX (0x100U)
-
-#define PLL_MAX_N_DIV 0x100U
-#define USB_PLL_MAX_N_DIV 0x100U
-
-#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U)
-#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU)
-/*--------------------------------------------------------------------------
-!!! If required these #defines can be moved to chip library file
-----------------------------------------------------------------------------*/
-
-#define PLL_MDEC_VAL_P (0U)                                      /*!<  MDEC is in bits  16 downto 0 */
-#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)             /*!<  NDEC is in bits  9 downto 0 */
-#define PLL_NDEC_VAL_P (0U)                                      /*!<  NDEC is in bits  9:0 */
-#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
-#define PLL_PDEC_VAL_P (0U)                                      /*!<  PDEC is in bits 6:0 */
-#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
-
-#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
-#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
-#define PLL_LOWER_IN_LIMIT (4000U)                               /*!<  Minimum PLL input rate */
-#define PLL_MIN_IN_SSMODE (2000000U)
-#define PLL_MAX_IN_SSMODE (4000000U)
-
-/*!<  Middle of the range values for spread-spectrum */
-#define PLL_SSCG_MF_FREQ_VALUE 4U
-#define PLL_SSCG_MC_COMP_VALUE 2U
-#define PLL_SSCG_MR_DEPTH_VALUE 4U
-#define PLL_SSCG_DITHER_VALUE 0U
-
-/*!<  USB PLL CCO MAX AND MIN FREQ */
-#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)
-#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)
-#define USB_PLL_LOWER_IN_LIMIT (1000000U)                             /*!<  Minimum PLL input rate */
-
-#define USB_PLL_MSEL_VAL_P (0U)                                       /*!<  MSEL is in bits  7 downto 0 */
-#define USB_PLL_MSEL_VAL_M (0xFFU)
-#define USB_PLL_PSEL_VAL_P (8U)                                       /*!<  PDEC is in bits 9:8 */
-#define USB_PLL_PSEL_VAL_M (0x3U)
-#define USB_PLL_NSEL_VAL_P (10U)                                      /*!<  NDEC is in bits  11:10 */
-#define USB_PLL_NSEL_VAL_M (0x3U)
-
-/*!<  SWITCH USB POSTDIVIDER FOR REGITSER WRITING */
-#define SWITCH_USB_PSEL(x)    ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U)
-
-/*!<  SYS PLL NDEC reg */
-#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
-/*!<  SYS PLL PDEC reg */
-#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
-/*!<  SYS PLL MDEC reg */
-#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)
-
-/*!<  SYS PLL NSEL reg */
-#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)
-/*!<  SYS PLL PSEL reg */
-#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)
-/*!<  SYS PLL MSEL reg */
-#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)
-
-/*!<  FRAC control */
-#define AUDIO_PLL_FRACT_MD_P (0U)
-#define AUDIO_PLL_FRACT_MD_INT_P (15U)
-#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)
-#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)
-
-#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)
-#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)
-
-/* Saved value of PLL output rate, computed whenever needed to save run-time
-   computation on each call to retrive the PLL rate. */
-static uint32_t s_Pll_Freq;
-static uint32_t s_Usb_Pll_Freq;
-static uint32_t s_Audio_Pll_Freq;
-
-
-/** External clock rate on the CLKIN pin in Hz. If not used,
-    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
-    being driven at. */
-const uint32_t g_I2S_Mclk_Freq = 0U;
-const uint32_t g_Ext_Clk_Freq = 12000000U;
-const uint32_t g_Lcd_Clk_In_Freq = 0U;
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/* Find encoded NDEC value for raw N value, max N = NVALMAX */
-static uint32_t pllEncodeN(uint32_t N);
-/* Find decoded N value for raw NDEC value */
-static uint32_t pllDecodeN(uint32_t NDEC);
-/* Find encoded PDEC value for raw P value, max P = PVALMAX */
-static uint32_t pllEncodeP(uint32_t P);
-/* Find decoded P value for raw PDEC value */
-static uint32_t pllDecodeP(uint32_t PDEC);
-/* Find encoded MDEC value for raw M value, max M = MVALMAX */
-static uint32_t pllEncodeM(uint32_t M);
-/* Find decoded M value for raw MDEC value */
-static uint32_t pllDecodeM(uint32_t MDEC);
-/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
-static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
-/* Get predivider (N) from PLL NDEC setting */
-static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
-/* Get postdivider (P) from PLL PDEC setting */
-static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
-/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
-static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
-/* Get the greatest common divisor */
-static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
-/* Set PLL output based on desired output rate */
-static pll_error_t CLOCK_GetPllConfig(
-    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);
-
-/* Update local PLL rate variable */
-static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
-static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);
-
-static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
-                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* Clock Selection for IP */
-void CLOCK_AttachClk(clock_attach_id_t connection)
-{
-    bool final_descriptor = false;
-    uint8_t mux;
-    uint8_t pos;
-    uint32_t i;
-    volatile uint32_t *pClkSel;
-
-    pClkSel = &(SYSCON->MAINCLKSELA);
-
-    for (i = 0U; (i <= 2U) && (!final_descriptor); i++)
-    {
-        connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!<  pick up next descriptor */
-        mux = (uint8_t)connection;
-        if (connection)
-        {
-            pos = ((connection & 0xf00U) >> 8U) - 1U;
-            if (mux == CM_ASYNCAPB)
-            {
-                SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
-                ASYNC_SYSCON->ASYNCAPBCLKSELA = pos;
-            }
-            else
-            {
-                pClkSel[mux] = pos;
-            }
-        }
-        else
-        {
-            final_descriptor = true;
-        }
-    }
-}
-
-/* Set IP Clock Divider */
-void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
-{
-    volatile uint32_t *pClkDiv;
-
-    pClkDiv = &(SYSCON->SYSTICKCLKDIV);
-    if (reset)
-    {
-        pClkDiv[div_name] = 1U << 29U;
-    }
-    if (divided_by_value == 0U) /*!<  halt */
-    {
-        pClkDiv[div_name] = 1U << 30U;
-    }
-    else
-    {
-        pClkDiv[div_name] = (divided_by_value - 1U);
-    }
-}
-
-/* Set FRO Clocking */
-status_t CLOCK_SetupFROClocking(uint32_t iFreq)
-{
-    uint32_t usb_adj;
-    if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))
-    {
-        return kStatus_Fail;
-    }
-    /* Power up the FRO and set this as the base clock */
-    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
-    /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */
-    usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT;
-    if (iFreq > 12000000U)
-    {
-        if (iFreq == 96000000U)
-        {
-            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) |
-                                SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
-                                SYSCON_FROCTRL_HSPDCLK(1);
-        }
-        else
-        {
-            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) |
-                                SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
-                                SYSCON_FROCTRL_HSPDCLK(1);
-        }
-    }
-    else
-    {
-        SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1);
-    }
-
-    return 0U;
-}
-
-/* Get CLOCK OUT Clk */
-uint32_t CLOCK_GetClockOutClkFreq(void)
-{
-    return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq():
-           (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq():
-           (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U;
-}
-
-/* Get SPIFI Clk */
-uint32_t CLOCK_GetSpifiClkFreq(void)
-{
-    return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get ADC Clk */
-uint32_t CLOCK_GetAdcClkFreq(void)
-{
-    return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->ADCCLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get USB0 Clk */
-uint32_t CLOCK_GetUsb0ClkFreq(void)
-{
-    return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->USB0CLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get USB1 Clk */
-uint32_t CLOCK_GetUsb1ClkFreq(void)
-{
-
-    return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->USB1CLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get MCLK Clk */
-uint32_t CLOCK_GetMclkClkFreq(void)
-{
-    return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U):
-           (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get SCTIMER Clk */
-uint32_t CLOCK_GetSctClkFreq(void)
-{
-    return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->SCTCLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get SDIO Clk */
-uint32_t CLOCK_GetSdioClkFreq(void)
-{
-    return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
-           (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
-           (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
-           (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U;
-}
-
-/* Get LCD Clk */
-uint32_t CLOCK_GetLcdClkFreq(void)
-{
-    return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
-           (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn():
-           (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
-           (SYSCON->LCDCLKSEL == 3U) ? 0U:0U;
-}
-
-/* Get LCD CLK IN Clk */
-uint32_t CLOCK_GetLcdClkIn(void)
-{
-  return g_Lcd_Clk_In_Freq;
-}
-
-/* Get FRO 12M Clk */
-uint32_t CLOCK_GetFro12MFreq(void)
-{
-    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U;
-}
-
-/* Get EXT OSC Clk */
-uint32_t CLOCK_GetExtClkFreq(void)
-{
-    return g_Ext_Clk_Freq;
-}
-
-/* Get WATCH DOG Clk */
-uint32_t CLOCK_GetWdtOscFreq(void)
-{
-    uint8_t freq_sel, div_sel;
-    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
-    {
-        return 0U;
-    }
-    else
-    {
-        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
-        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
-        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
-    }
-}
-
-/* Get HF FRO Clk */
-uint32_t CLOCK_GetFroHfFreq(void)
-{
-    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : 
-          !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 :
-           (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U;
-}
-
-/* Get SYSTEM PLL Clk */
-uint32_t CLOCK_GetPllOutFreq(void)
-{
-    return s_Pll_Freq;
-}
-
-/* Get AUDIO PLL Clk */
-uint32_t CLOCK_GetAudioPllOutFreq(void)
-{
-    return s_Audio_Pll_Freq;
-}
-
-/* Get USB PLL Clk */
-uint32_t CLOCK_GetUsbPllOutFreq(void)
-{
-    return s_Usb_Pll_Freq;
-}
-
-/* Get RTC OSC Clk */
-uint32_t CLOCK_GetOsc32KFreq(void)
-{
-    return CLK_RTC_32K_CLK;               /* Needs to be corrected to check that RTC Clock is enabled */
-}
-
-/* Get MAIN Clk */
-uint32_t CLOCK_GetCoreSysClkFreq(void)
-{
-    return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() :
-           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() :
-           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() :
-           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() :
-           (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() :
-           (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U;
-}
-
-/* Get I2S MCLK Clk */
-uint32_t CLOCK_GetI2SMClkFreq(void)
-{
-    return g_I2S_Mclk_Freq;
-}
-
-/* Get ASYNC APB Clk */
-uint32_t CLOCK_GetAsyncApbClkFreq(void)
-{
-    async_clock_src_t clkSrc;
-    uint32_t clkRate;
-
-    clkSrc = CLOCK_GetAsyncApbClkSrc();
-
-    switch (clkSrc)
-    {
-        case kCLOCK_AsyncMainClk:
-            clkRate = CLOCK_GetCoreSysClkFreq();
-            break;
-        case kCLOCK_AsyncFro12Mhz:
-            clkRate = CLK_FRO_12MHZ;
-            break;
-        default:
-            clkRate = 0U;
-            break;
-    }
-
-    return clkRate;
-}
-
-/* Get FLEXCOMM Clk */
-uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
-{
-    return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : 
-           (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() :
-           (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() :
-           (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() :
-           (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U;
-}
-
-/* Get FRG Clk */
-uint32_t CLOCK_GetFRGInputClock(void)
-{
-    return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
-           (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
-           (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : 
-           (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
-}
-
-/* Set FRG Clk */
-uint32_t CLOCK_SetFRGClock(uint32_t freq)
-{
-    uint32_t input = CLOCK_GetFRGInputClock();
-    uint32_t mul;
-
-    if ((freq > 48000000) || (freq > input) || (input / freq >= 2))
-    {
-        /* FRG output frequency should be less than equal to 48MHz */
-        return 0;
-    }
-    else
-    {
-        mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
-        SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
-        return 1;
-    }
-}
-
-/* Set IP Clk */
-uint32_t CLOCK_GetFreq(clock_name_t clockName)
-{
-    uint32_t freq;
-    switch (clockName)
-    {
-        case kCLOCK_CoreSysClk:
-            freq = CLOCK_GetCoreSysClkFreq();
-            break;
-        case kCLOCK_BusClk:
-            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_ClockOut:
-            freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_SpiFi:
-            freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U );
-            break;
-        case kCLOCK_Adc:
-            freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U );
-            break;
-        case kCLOCK_Usb0:
-            freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U );
-            break;
-        case kCLOCK_Usb1:
-            freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U );
-            break;
-        case kCLOCK_Mclk:
-            freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U );
-            break;
-        case kCLOCK_FroHf:
-            freq = CLOCK_GetFroHfFreq();
-            break;
-        case kCLOCK_Fro12M:
-            freq = CLOCK_GetFro12MFreq();
-            break;
-        case kCLOCK_ExtClk:
-            freq = CLOCK_GetExtClkFreq();
-            break;
-        case kCLOCK_PllOut:
-            freq = CLOCK_GetPllOutFreq();
-            break;
-        case kClock_WdtOsc:
-            freq = CLOCK_GetWdtOscFreq();
-            break;
-        case kCLOCK_Frg:
-            freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
-                   (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
-                   (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() :
-                   (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
-            break;
-        case kCLOCK_Dmic:
-            freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : 
-                   (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() :
-                   (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() :
-                   (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() :
-                   (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() :
-                   (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U;
-            freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
-            break;
-
-        case kCLOCK_AsyncApbClk:
-            freq = CLOCK_GetAsyncApbClkFreq();
-            break;
-        case kCLOCK_Sct:
-            freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_SDio:
-            freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_EMC:
-            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_LCD:
-            freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_MCAN0:
-            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_MCAN1:
-            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);
-            break;
-        case kCLOCK_FlexI2S:
-            freq = CLOCK_GetI2SMClkFreq();
-            break;
-        case kCLOCK_Flexcomm0:
-            freq = CLOCK_GetFlexCommClkFreq(0U);
-            break;
-        case kCLOCK_Flexcomm1:
-            freq = CLOCK_GetFlexCommClkFreq(1U);
-            break;
-        case kCLOCK_Flexcomm2:
-            freq = CLOCK_GetFlexCommClkFreq(2U);
-            break;
-        case kCLOCK_Flexcomm3:
-            freq = CLOCK_GetFlexCommClkFreq(3U);
-            break;
-        case kCLOCK_Flexcomm4:
-            freq = CLOCK_GetFlexCommClkFreq(4U);
-            break;
-        case kCLOCK_Flexcomm5:
-            freq = CLOCK_GetFlexCommClkFreq(5U);
-            break;
-        case kCLOCK_Flexcomm6:
-            freq = CLOCK_GetFlexCommClkFreq(6U);
-            break;
-        case kCLOCK_Flexcomm7:
-            freq = CLOCK_GetFlexCommClkFreq(7U);
-            break;
-        case kCLOCK_Flexcomm8:
-            freq = CLOCK_GetFlexCommClkFreq(8U);
-            break;
-        case kCLOCK_Flexcomm9:
-            freq = CLOCK_GetFlexCommClkFreq(9U);
-            break;
-        default:
-            freq = 0U;
-            break;
-    }
-
-    return freq;
-}
-
-/* Set the FLASH wait states for the passed frequency */
-void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
-{
-    if (iFreq <= 12000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle);
-    }
-    else if (iFreq <= 24000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle);
-    }
-    else if (iFreq <= 36000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle);
-    }
-    else if (iFreq <= 60000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle);
-    }
-    else if (iFreq <= 96000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle);
-    }
-    else if (iFreq <= 120000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle);
-    }
-    else if (iFreq <= 144000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash7Cycle);
-    }
-    else if (iFreq <= 168000000U)
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash8Cycle);
-    }
-    else
-    {
-        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash9Cycle);
-    }
-}
-
-/* Find encoded NDEC value for raw N value, max N = NVALMAX */
-static uint32_t pllEncodeN(uint32_t N)
-{
-    uint32_t x, i;
-
-    /* Find NDec */
-    switch (N)
-    {
-        case 0U:
-            x = 0x3FFU;
-            break;
-
-        case 1U:
-            x = 0x302U;
-            break;
-
-        case 2U:
-            x = 0x202U;
-            break;
-
-        default:
-            x = 0x080U;
-            for (i = N; i <= NVALMAX; i++)
-            {
-                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
-            }
-            break;
-    }
-
-    return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
-}
-
-/* Find decoded N value for raw NDEC value */
-static uint32_t pllDecodeN(uint32_t NDEC)
-{
-    uint32_t n, x, i;
-
-    /* Find NDec */
-    switch (NDEC)
-    {
-        case 0x3FFU:
-            n = 0U;
-            break;
-
-        case 0x302U:
-            n = 1U;
-            break;
-
-        case 0x202U:
-            n = 2U;
-            break;
-
-        default:
-            x = 0x080U;
-            n = 0xFFFFFFFFU;
-            for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
-                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
-                {
-                    /* Decoded value of NDEC */
-                    n = i;
-                }
-            }
-            break;
-    }
-
-    return n;
-}
-
-/* Find encoded PDEC value for raw P value, max P = PVALMAX */
-static uint32_t pllEncodeP(uint32_t P)
-{
-    uint32_t x, i;
-
-    /* Find PDec */
-    switch (P)
-    {
-        case 0U:
-            x = 0x7FU;
-            break;
-
-        case 1U:
-            x = 0x62U;
-            break;
-
-        case 2U:
-            x = 0x42U;
-            break;
-
-        default:
-            x = 0x10U;
-            for (i = P; i <= PVALMAX; i++)
-            {
-                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
-            }
-            break;
-    }
-
-    return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
-}
-
-/* Find decoded P value for raw PDEC value */
-static uint32_t pllDecodeP(uint32_t PDEC)
-{
-    uint32_t p, x, i;
-
-    /* Find PDec */
-    switch (PDEC)
-    {
-        case 0x7FU:
-            p = 0U;
-            break;
-
-        case 0x62U:
-            p = 1U;
-            break;
-
-        case 0x42U:
-            p = 2U;
-            break;
-
-        default:
-            x = 0x10U;
-            p = 0xFFFFFFFFU;
-            for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
-                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
-                {
-                    /* Decoded value of PDEC */
-                    p = i;
-                }
-            }
-            break;
-    }
-
-    return p;
-}
-
-/* Find encoded MDEC value for raw M value, max M = MVALMAX */
-static uint32_t pllEncodeM(uint32_t M)
-{
-    uint32_t i, x;
-
-    /* Find MDec */
-    switch (M)
-    {
-        case 0U:
-            x = 0x1FFFFU;
-            break;
-
-        case 1U:
-            x = 0x18003U;
-            break;
-
-        case 2U:
-            x = 0x10003U;
-            break;
-
-        default:
-            x = 0x04000U;
-            for (i = M; i <= MVALMAX; i++)
-            {
-                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
-            }
-            break;
-    }
-
-    return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);
-}
-
-/* Find decoded M value for raw MDEC value */
-static uint32_t pllDecodeM(uint32_t MDEC)
-{
-    uint32_t m, i, x;
-
-    /* Find MDec */
-    switch (MDEC)
-    {
-        case 0x1FFFFU:
-            m = 0U;
-            break;
-
-        case 0x18003U:
-            m = 1U;
-            break;
-
-        case 0x10003U:
-            m = 2U;
-            break;
-
-        default:
-            x = 0x04000U;
-            m = 0xFFFFFFFFU;
-            for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--)
-            {
-                x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU);
-                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
-                {
-                    /* Decoded value of MDEC */
-                    m = i;
-                }
-            }
-            break;
-    }
-
-    return m;
-}
-
-/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
-static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
-{
-    /* bandwidth: compute selP from Multiplier */
-    if (M < 60U)
-    {
-        *pSelP = (M >> 1U) + 1U;
-    }
-    else
-    {
-        *pSelP = PVALMAX - 1U;
-    }
-
-    /* bandwidth: compute selI from Multiplier */
-    if (M > 16384U)
-    {
-        *pSelI = 1U;
-    }
-    else if (M > 8192U)
-    {
-        *pSelI = 2U;
-    }
-    else if (M > 2048U)
-    {
-        *pSelI = 4U;
-    }
-    else if (M >= 501U)
-    {
-        *pSelI = 8U;
-    }
-    else if (M >= 60U)
-    {
-        *pSelI = 4U * (1024U / (M + 9U));
-    }
-    else
-    {
-        *pSelI = (M & 0x3CU) + 4U;
-    }
-
-    if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
-    {
-        *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
-    }
-
-    *pSelR = 0U;
-}
-
-/* Get predivider (N) from PLL NDEC setting */
-static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
-{
-    uint32_t preDiv = 1;
-
-    /* Direct input is not used? */
-    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
-    {
-        /* Decode NDEC value to get (N) pre divider */
-        preDiv = pllDecodeN(nDecReg & 0x3FFU);
-        if (preDiv == 0U)
-        {
-            preDiv = 1U;
-        }
-    }
-
-    /* Adjusted by 1, directi is used to bypass */
-    return preDiv;
-}
-
-/* Get postdivider (P) from PLL PDEC setting */
-static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
-{
-    uint32_t postDiv = 1U;
-
-    /* Direct input is not used? */
-    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
-    {
-        /* Decode PDEC value to get (P) post divider */
-        postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
-        if (postDiv == 0U)
-        {
-            postDiv = 2U;
-        }
-    }
-
-    /* Adjusted by 1, directo is used to bypass */
-    return postDiv;
-}
-
-/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
-static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
-{
-    uint32_t mMult = 1U;
-
-    /* Decode MDEC value to get (M) multiplier */
-    mMult = pllDecodeM(mDecReg & 0x1FFFFU);
-
-    if (mMult == 0U)
-    {
-        mMult = 1U;
-    }
-
-    return mMult;
-}
-
-/* Find greatest common divisor between m and n */
-static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
-{
-    uint32_t tmp;
-
-    while (n != 0U)
-    {
-        tmp = n;
-        n = m % n;
-        m = tmp;
-    }
-
-    return m;
-}
-
-/* Set PLL output based on desired output rate */
-static pll_error_t CLOCK_GetPllConfig(
-    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
-{
-    uint32_t nDivOutHz, fccoHz, multFccoDiv;
-    uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
-    uint32_t pllDirectInput, pllDirectOutput;
-    uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
-
-    /* Baseline parameters (no input or output dividers) */
-    pllPreDivider = 1U;  /* 1 implies pre-divider will be disabled */
-    pllPostDivider = 0U; /* 0 implies post-divider will be disabled */
-    pllDirectOutput = 1U;
-    multFccoDiv = 2U;
-
-    /* Verify output rate parameter */
-    if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
-    {
-        /* Maximum PLL output with post divider=1 cannot go above this frequency */
-        return kStatus_PLL_OutputTooHigh;
-    }
-    if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
-    {
-        /* Minmum PLL output with maximum post divider cannot go below this frequency */
-        return kStatus_PLL_OutputTooLow;
-    }
-
-    /* Verify input rate parameter */
-    if (finHz < PLL_LOWER_IN_LIMIT)
-    {
-        /* Input clock into the PLL cannot be lower than this */
-        return kStatus_PLL_InputTooLow;
-    }
-
-    /* Find the optimal CCO frequency for the output and input that
-       will keep it inside the PLL CCO range. This may require
-       tweaking the post-divider for the PLL. */
-    fccoHz = foutHz;
-    while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
-    {
-        /* CCO output is less than minimum CCO range, so the CCO output
-           needs to be bumped up and the post-divider is used to bring
-           the PLL output back down. */
-        pllPostDivider++;
-        if (pllPostDivider > PVALMAX)
-        {
-            return kStatus_PLL_OutsideIntLimit;
-        }
-
-        /* Target CCO goes up, PLL output goes down */
-        fccoHz = foutHz * (pllPostDivider * 2U);
-        pllDirectOutput = 0U;
-    }
-
-    /* Determine if a pre-divider is needed to get the best frequency */
-    if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))
-    {
-        uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
-
-        if (a > 20000U)
-        {
-            a = (multFccoDiv * finHz) / a;
-            if ((a != 0U) && (a < PLL_MAX_N_DIV))
-            {
-                pllPreDivider = a;
-            }
-        }
-    }
-
-    /* Bypass pre-divider hardware if pre-divider is 1 */
-    if (pllPreDivider > 1U)
-    {
-        pllDirectInput = 0U;
-    }
-    else
-    {
-        pllDirectInput = 1U;
-    }
-
-    /* Determine PLL multipler */
-    nDivOutHz = (finHz / pllPreDivider);
-    pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
-
-    /* Find optimal values for filter */
-    /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
-    if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
-    {
-        pllMultiplier++;
-    }
-
-    /* Setup filtering */
-    pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
-    uplimoff = 0U;
-
-    /* Get encoded value for M (mult) and use manual filter, disable SS mode */
-    pSetup->pllmdec =
-        PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ;
-
-    /* Get encoded values for N (prediv) and P (postdiv) */
-    pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
-    pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
-
-    /* PLL control */
-    pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) |                  /* Filter coefficient */
-                         (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) |                  /* Filter coefficient */
-                         (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) |                  /* Filter coefficient */
-                         (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) |                      /* PLL bypass mode disabled */
-                         (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) |             /* SS/fractional mode disabled */
-                         (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
-                         (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
-
-    return kStatus_PLL_Success;
-}
-
-
-/* Update SYSTEM PLL rate variable */
-static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
-{
-    s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
-}
-
-/* Update AUDIO PLL rate variable */
-static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)
-{
-    s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
-}
-
-/* Update USB PLL rate variable */
-static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
-{
-    s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);
-}
-
-/* Return System PLL input clock rate */
-uint32_t CLOCK_GetSystemPLLInClockRate(void)
-{
-    uint32_t clkRate = 0U;
-
-    switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
-    {
-        case 0x00U:
-            clkRate = CLK_FRO_12MHZ;
-            break;
-
-        case 0x01U:
-            clkRate = CLOCK_GetExtClkFreq();
-            break;
-
-        case 0x02U:
-            clkRate = CLOCK_GetWdtOscFreq();
-            break;
-
-        case 0x03U:
-            clkRate = CLOCK_GetOsc32KFreq();
-            break;
-
-        default:
-            clkRate = 0U;
-            break;
-    }
-
-    return clkRate;
-}
-
-/* Return Audio PLL input clock rate */
-uint32_t CLOCK_GetAudioPLLInClockRate(void)
-{
-    uint32_t clkRate = 0U;
-
-    switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))
-    {
-        case 0x00U:
-            clkRate = CLK_FRO_12MHZ;
-            break;
-
-        case 0x01U:
-            clkRate = CLOCK_GetExtClkFreq();
-            break;
-            
-        default:
-            clkRate = 0U;
-            break;
-    }
-
-    return clkRate;
-}
-
-/* Return System PLL output clock rate from setup structure */
-uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
-{
-    uint32_t prediv, postdiv, mMult, inPllRate;
-    uint64_t workRate;
-
-    inPllRate = CLOCK_GetSystemPLLInClockRate();
-    /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/
-    if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)
-    {
-        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
-        /*
-         * 1. Pre-divider
-         * Pre-divider is only available when the DIRECTI is disabled.
-         */
-        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))
-        {
-            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
-        }
-        else
-        {
-            prediv = 1U; /* The pre-divider is bypassed. */
-        }
-        /*
-         * 2. Post-divider
-         * Post-divider is only available when the DIRECTO is disabled.
-         */
-        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))
-        {
-            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
-        }
-        else
-        {
-            postdiv = 1U;           /* The post-divider is bypassed. */
-        }
-        /* Adjust input clock */
-        inPllRate = inPllRate / prediv;
-
-        /* MDEC used for rate */
-        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
-        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
-
-        workRate = workRate / ((uint64_t)postdiv);
-        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
-
-    }
-    else
-    {
-        /* In bypass mode */
-        workRate = (uint64_t)inPllRate;
-    }
-
-    return (uint32_t)workRate;
-}
-
-/* Return Usb PLL output clock rate from setup structure */
-uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)
-{
-    uint32_t nsel, psel, msel, inPllRate;
-    uint64_t workRate;
-    inPllRate = CLOCK_GetExtClkFreq();
-    msel = pSetup->msel;
-    psel = pSetup->psel;
-    nsel = pSetup->nsel;
-
-    if (pSetup->fbsel == 1U)
-       {   
-           /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
-           workRate = (inPllRate) * (msel + 1U) / (nsel + 1U);
-       }
-       else
-       {
-           /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
-           workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));
-       }
-   
-    return (uint32_t)workRate;
-}
-
-/* Return Audio PLL output clock rate from setup structure */
-uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)
-{
-    uint32_t prediv, postdiv, mMult, inPllRate;
-    uint64_t workRate;
-
-    inPllRate = CLOCK_GetAudioPLLInClockRate();
-    if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
-    {
-        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
-        /*
-         * 1. Pre-divider
-         * Pre-divider is only available when the DIRECTI is disabled.
-         */
-        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
-        {
-            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
-        }
-        else
-        {
-            prediv = 1U; /* The pre-divider is bypassed. */
-        }
-        /*
-         * 2. Post-divider
-         * Post-divider is only available when the DIRECTO is disabled.
-         */
-        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
-        {
-            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
-        }
-        else
-        {
-            postdiv = 1U;           /* The post-divider is bypassed. */
-        }
-        /* Adjust input clock */
-        inPllRate = inPllRate / prediv;
-
-        /* MDEC used for rate */
-        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
-        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
-
-        workRate = workRate / ((uint64_t)postdiv);
-        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
-    }
-    else
-    {
-        /* In bypass mode */
-        workRate = (uint64_t)inPllRate;
-    }
-
-    return (uint32_t)workRate;
-}
-
-/* Set the current PLL Rate */
-void CLOCK_SetStoredPLLClockRate(uint32_t rate)
-{
-    s_Pll_Freq = rate;
-}
-
-/* Set the current Audio PLL Rate */
-void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)
-{
-    s_Audio_Pll_Freq = rate;
-}
-
-/* Set the current Usb PLL Rate */
-void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)
-{
-    s_Usb_Pll_Freq = rate;
-}
-
-/* Return System PLL output clock rate */
-uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
-{
-    pll_setup_t Setup;
-    uint32_t rate;
-
-    if ((recompute) || (s_Pll_Freq == 0U))
-    {
-        Setup.pllctrl = SYSCON->SYSPLLCTRL;
-        Setup.pllndec = SYSCON->SYSPLLNDEC;
-        Setup.pllpdec = SYSCON->SYSPLLPDEC;
-        Setup.pllmdec = SYSCON->SYSPLLMDEC;
-
-        CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
-    }
-
-    rate = s_Pll_Freq;
-
-    return rate;
-}
-
-/* Return AUDIO PLL output clock rate */
-uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)
-{
-    pll_setup_t Setup;
-    uint32_t rate;
-
-    if ((recompute) || (s_Audio_Pll_Freq == 0U))
-    {
-        Setup.pllctrl = SYSCON->AUDPLLCTRL;
-        Setup.pllndec = SYSCON->AUDPLLNDEC;
-        Setup.pllpdec = SYSCON->AUDPLLPDEC;
-        Setup.pllmdec = SYSCON->AUDPLLMDEC;
-
-        CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);
-    }
-
-    rate = s_Audio_Pll_Freq;
-    return rate;
-}
-
-/* Return USB PLL output clock rate */
-uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)
-{
-    usb_pll_setup_t Setup;
-    uint32_t rate;
-
-    if ((recompute) || (s_Usb_Pll_Freq == 0U))
-    {
-        Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK;
-        Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK;
-        Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK;
-        Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK;
-        Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK;
-        Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; 
-        CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);
-    }
-
-    rate = s_Usb_Pll_Freq;
-    return rate;
-}
-
-/* Set PLL output based on the passed PLL setup data */
-pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
-{
-    uint32_t inRate;
-    pll_error_t pllError;
-
-    /* Determine input rate for the PLL */
-    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
-    {
-        inRate = pControl->inputRate;
-    }
-    else
-    {
-        inRate = CLOCK_GetSystemPLLInClockRate();
-    }
-
-    /* PLL flag options */
-    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
-    pSetup->pllRate = pControl->desiredRate;
-    return pllError;
-}
-
-/* Set PLL output from PLL setup structure */
-pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
-{
-    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
-    {
-       /* Turn on the ext clock if system pll input select clk_in */
-       CLOCK_Enable_SysOsc(true);
-    }
-    /* Enable power for PLLs */
-    POWER_SetPLL();
-    /* Power off PLL during setup changes */
-    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
-    /*!< Set FLASH waitstates for core */
-    CLOCK_SetFLASHAccessCyclesForFreq(pSetup->pllRate);
-    pSetup->flags = flagcfg;
-
-    /* Write PLL setup data */
-    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
-    SYSCON->SYSPLLNDEC = pSetup->pllndec;
-    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
-    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
-    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
-    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
-    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
-
-    /* Flags for lock or power on */
-    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
-    {
-        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
-        volatile uint32_t delayX;
-        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
-        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
-
-        /* Initialize  and power up PLL */
-        SYSCON->SYSPLLMDEC = maxCCO;
-        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
-
-        /* Set mreq to activate */
-        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
-
-        /* Delay for 72 uSec @ 12Mhz */
-        for (delayX = 0U; delayX < 172U; ++delayX)
-        {
-        }
-
-        /* clear mreq to prepare for restoring mreq */
-        SYSCON->SYSPLLMDEC = curSSCTRL;
-
-        /* set original value back and activate */
-        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
-
-        /* Enable peripheral states by setting low */
-        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
-    }
-    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
-    {
-        while (CLOCK_IsSystemPLLLocked() == false)
-        {
-        }
-    }
-
-    /* Update current programmed PLL rate var */
-    CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
-
-    /* System voltage adjustment, occurs prior to setting main system clock */
-    if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
-    {
-        POWER_SetVoltageForFreq(s_Pll_Freq);
-    }
-
-    return kStatus_PLL_Success;
-}
-
-
-/* Set AUDIO PLL output from AUDIO PLL setup structure */
-pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
-{
-    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
-    {
-       /* Turn on the ext clock if system pll input select clk_in */
-       CLOCK_Enable_SysOsc(true);
-    }
-    /* Enable power VD3 for PLLs */
-    POWER_SetPLL();
-    /* Power off PLL during setup changes */
-    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
-
-    pSetup->flags = flagcfg;
-
-    /* Write PLL setup data */
-    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
-    SYSCON->AUDPLLNDEC = pSetup->pllndec;
-    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
-    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
-    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
-    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
-    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
-    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */
-
-    /* Flags for lock or power on */
-    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
-    {
-        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
-        volatile uint32_t delayX;
-        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
-        uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U);
-
-        /* Initialize  and power up PLL */
-        SYSCON->AUDPLLMDEC = maxCCO;
-        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
-
-        /* Set mreq to activate */
-        SYSCON->AUDPLLMDEC = maxCCO | (1U << 17U);
-
-        /* Delay for 72 uSec @ 12Mhz */
-        for (delayX = 0U; delayX < 172U; ++delayX)
-        {
-        }
-
-        /* clear mreq to prepare for restoring mreq */
-        SYSCON->AUDPLLMDEC = curSSCTRL;
-
-        /* set original value back and activate */
-        SYSCON->AUDPLLMDEC = curSSCTRL | (1U << 17U);
-
-        /* Enable peripheral states by setting low */
-        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
-    }
-    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
-    {
-        while (CLOCK_IsAudioPLLLocked() == false)
-        {
-        }
-    }
-
-    /* Update current programmed PLL rate var */
-    CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);
-
-    return kStatus_PLL_Success;
-}
-
-/* Set Audio PLL output based on the passed Audio PLL setup data */
-pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
-{
-    uint32_t inRate;
-    pll_error_t pllError;
-
-    /* Determine input rate for the PLL */
-    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
-    {
-        inRate = pControl->inputRate;
-    }
-    else
-    {
-        inRate = CLOCK_GetAudioPLLInClockRate();
-    }
-
-    /* PLL flag options */
-    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
-    pSetup->pllRate = pControl->desiredRate;
-    return pllError;
-}
-
-
-
-/* Setup PLL Frequency from pre-calculated value */
-pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
-{
-    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
-    {
-       /* Turn on the ext clock if system pll input select clk_in */
-       CLOCK_Enable_SysOsc(true);
-    }
-    /* Enable power VD3 for PLLs */
-    POWER_SetPLL();
-    /* Power off PLL during setup changes */
-    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
-
-    /* Write PLL setup data */
-    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
-    SYSCON->SYSPLLNDEC = pSetup->pllndec;
-    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
-    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
-    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
-    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
-    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
-
-    /* Flags for lock or power on */
-    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
-    {
-        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
-        volatile uint32_t delayX;
-        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
-        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
-
-        /* Initialize  and power up PLL */
-        SYSCON->SYSPLLMDEC = maxCCO;
-        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
-
-        /* Set mreq to activate */
-        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
-
-        /* Delay for 72 uSec @ 12Mhz */
-        for (delayX = 0U; delayX < 172U; ++delayX)
-        {
-        }
-
-        /* clear mreq to prepare for restoring mreq */
-        SYSCON->SYSPLLMDEC = curSSCTRL;
-
-        /* set original value back and activate */
-        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
-
-        /* Enable peripheral states by setting low */
-        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
-    }
-    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
-    {
-        while (CLOCK_IsSystemPLLLocked() == false)
-        {
-        }
-    }
-
-    /* Update current programmed PLL rate var */
-    s_Pll_Freq = pSetup->pllRate;
-
-    return kStatus_PLL_Success;
-}
-
-/* Setup Audio PLL Frequency from pre-calculated value */
-pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
-{
-    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
-    {
-       /* Turn on the ext clock if system pll input select clk_in */
-       CLOCK_Enable_SysOsc(true);
-    }
-    /* Enable power VD3 for PLLs */
-    POWER_SetPLL();
-    /* Power off Audio PLL during setup changes */
-    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
-
-    /* Write Audio PLL setup data */
-    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
-    SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
-    SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT);  /* latch */
-    SYSCON->AUDPLLNDEC = pSetup->pllndec;
-    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT);    /* latch */
-    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
-    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT);    /* latch */
-    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
-    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT);    /* latch */
-    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1);                              /* disable fractional function */
-
-    /* Flags for lock or power on */
-    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
-    {
-        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
-        volatile uint32_t delayX;
-        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
-        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
-
-        /* Initialize  and power up PLL */
-        SYSCON->SYSPLLMDEC = maxCCO;
-        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
-
-        /* Set mreq to activate */
-        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
-
-        /* Delay for 72 uSec @ 12Mhz */
-        for (delayX = 0U; delayX < 172U; ++delayX)
-        {
-        }
-
-        /* clear mreq to prepare for restoring mreq */
-        SYSCON->SYSPLLMDEC = curSSCTRL;
-
-        /* set original value back and activate */
-        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
-
-        /* Enable peripheral states by setting low */
-        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
-    }
-    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
-    {
-        while (CLOCK_IsAudioPLLLocked() == false)
-        {
-        }
-    }
-
-    /* Update current programmed PLL rate var */
-    s_Audio_Pll_Freq = pSetup->pllRate;
-
-    return kStatus_PLL_Success;
-}
-
-/* Setup USB PLL Frequency from pre-calculated value */
-pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)
-{       
-    uint32_t usbpllctrl, fccoHz;
-    uint8_t msel, psel, nsel;
-    bool pllDirectInput, pllDirectOutput, pllfbsel;
-    volatile uint32_t delayX;
-
-    msel = pSetup->msel;
-    psel = pSetup->psel;
-    nsel = pSetup->nsel;
-    pllDirectInput = pSetup->direct;
-    pllDirectOutput = pSetup->bypass;
-    pllfbsel = pSetup->fbsel;
-    
-    /* Input clock into the PLL cannot be lower than this */
-    if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT )
-    {
-        return kStatus_PLL_InputTooLow;
-    }
-    
-    if (pllfbsel == 1U)
-    {   
-        /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
-        fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ;
-        
-        /* USB PLL CCO out rate cannot be lower than this */        
-        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
-        {       
-            return kStatus_PLL_CCOTooLow;
-        }
-        /* USB PLL CCO out rate cannot be Higher than this */
-        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
-        { 
-            return kStatus_PLL_CCOTooHigh;
-        }
-    }
-    else
-    {
-        /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
-        fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U);
-        
-        /* USB PLL CCO out rate cannot be lower than this */        
-        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
-        {       
-            return kStatus_PLL_CCOTooLow;
-        }
-        /* USB PLL CCO out rate cannot be Higher than this */
-        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
-        { 
-            return kStatus_PLL_CCOTooHigh;
-        }       
-    }
-    
-    /* If configure the USB HOST clock, VD5 power for USB PHY should be enable 
-       before the the PLL is working */
-    /* Turn on the ext clock for usb pll input */
-    CLOCK_Enable_SysOsc(true);
-    
-    /* Enable power VD3 for PLLs */
-    POWER_SetPLL();
-    
-    /* Power on the VD5 for USB PHY */    
-    POWER_SetUsbPhy();
-
-    /* Power off USB PLL during setup changes */
-    POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);
-      
-    /* Write USB PLL setup data */
-    usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel)  |                  /* NSEL VALUE */
-                 USB_PLL_PSEL_VAL_SET(psel)  |                  /* PSEL VALUE */
-                 USB_PLL_MSEL_VAL_SET(msel)  |                  /* MSEL VALUE */
-                 (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT  |            /* BYPASS DISABLE */
-                 (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT |            /* DIRECTO DISABLE */
-                 (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT;                     /* FBSEL SELECT */   
-    
-    SYSCON->USBPLLCTRL = usbpllctrl;
-    
-    POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
-  
-    /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */
-    for (delayX = 0U; delayX < 172U; ++delayX)
-    {
-    }
-    
-    while (CLOCK_IsUsbPLLLocked() == false)
-    {
-    }
-    CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);
-    return kStatus_PLL_Success;
-}
-
-/* Set System PLL clock based on the input frequency and multiplier */
-void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
-{
-    uint32_t cco_freq = input_freq * multiply_by;
-    uint32_t pdec = 1U;
-    uint32_t selr;
-    uint32_t seli;
-    uint32_t selp;
-    uint32_t mdec, ndec;
-
-    uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);
-
-    while (cco_freq < 275000000U)
-    {
-        multiply_by <<= 1U; /* double value in each iteration */
-        pdec <<= 1U;        /* correspondingly double pdec to cancel effect of double msel */
-        cco_freq = input_freq * multiply_by;
-    }
-    selr = 0U;
-    if (multiply_by < 60U)
-    {
-        seli = (multiply_by & 0x3cU) + 4U;
-        selp = (multiply_by >> 1U) + 1U;
-    }
-    else
-    {
-        selp = 31U;
-        if (multiply_by > 16384U)
-        {
-            seli = 1U;
-        }
-        else if (multiply_by > 8192U)
-        {
-            seli = 2U;
-        }
-        else if (multiply_by > 2048U)
-        {
-            seli = 4U;
-        }
-        else if (multiply_by >= 501U)
-        {
-            seli = 8U;
-        }
-        else
-        {
-            seli = 4U * (1024U / (multiply_by + 9U));
-        }
-    }
-
-    if (pdec > 1U)
-    {
-        directo = 0U;     /* use post divider */
-        pdec = pdec / 2U; /* Account for minus 1 encoding */
-                          /* Translate P value */
-        switch (pdec)
-        {
-            case 1U:
-                pdec = 0x62U; /* 1  * 2 */
-                break;
-            case 2U:
-                pdec = 0x42U; /* 2  * 2 */
-                break;
-            case 4U:
-                pdec = 0x02U; /* 4  * 2 */
-                break;
-            case 8U:
-                pdec = 0x0bU; /* 8  * 2 */
-                break;
-            case 16U:
-                pdec = 0x11U; /* 16 * 2 */
-                break;
-            case 32U:
-                pdec = 0x08U; /* 32 * 2 */
-                break;
-            default:
-                pdec = 0x08U;
-                break;
-        }
-    }
-
-    mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));
-    ndec = 0x302U; /* pre divide by 1 (hardcoded) */
-
-    SYSCON->SYSPLLCTRL = directo |
-                         (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
-                         (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
-    SYSCON->SYSPLLPDEC = pdec | (1U << 7U);  /* set Pdec value and assert preq */
-    SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */
-    SYSCON->SYSPLLMDEC = (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
-}
-
-/* Enable USB DEVICE FULL SPEED clock */
-bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
-{
-    bool ret = true;
-
-    CLOCK_DisableClock(kCLOCK_Usbd0);
-
-    if (kCLOCK_UsbSrcFro == src)
-    {
-        switch (freq)
-        {
-            case 96000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
-                break;
-            
-            case 48000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
-                break;
-            
-            default:
-                ret = false;
-                break;
-        }
-        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
-        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
-                          SYSCON_FROCTRL_USBCLKADJ_MASK;
-        /* Select FRO 96 or 48 MHz */
-        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-    }
-    else
-    {
-        /*Set the USB PLL as the Usb0 CLK*/
-        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
-    
-        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
-
-        CLOCK_SetUsbPLLFreq(&pll_setup);
-        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
-        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
-        uint32_t delay = 100000;
-        while (delay --)
-        {
-            __asm("nop");
-        }
-    }
-    CLOCK_EnableClock(kCLOCK_Usbd0);
-    CLOCK_EnableClock(kCLOCK_UsbRam1);
-    
-    return ret;
-}
-
-/* Enable USB HOST FULL SPEED clock */
-bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)
-{
-    bool ret = true;
-
-    CLOCK_DisableClock(kCLOCK_Usbhmr0);
-    CLOCK_DisableClock(kCLOCK_Usbhsl0);
-
-    if (kCLOCK_UsbSrcFro == src)
-    {
-        switch (freq)
-        {
-            case 96000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
-                break;
-            
-            case 48000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
-                break;
-            
-            default:
-                ret = false;
-                break;
-        }
-        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
-        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
-                          SYSCON_FROCTRL_USBCLKADJ_MASK;
-        /* Select FRO 96 or 48 MHz */
-        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-    }
-    else
-    {
-        /*Set the USB PLL as the Usb0 CLK*/
-        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
-    
-        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
-
-        CLOCK_SetUsbPLLFreq(&pll_setup);
-        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
-        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
-        uint32_t delay = 100000;
-        while (delay --)
-        {
-            __asm("nop");
-        }
-    }
-    CLOCK_EnableClock(kCLOCK_Usbhmr0);
-    CLOCK_EnableClock(kCLOCK_Usbhsl0);
-    CLOCK_EnableClock(kCLOCK_UsbRam1); 
-
-    return ret;
-}
-
-/* Enable USB DEVICE HIGH SPEED clock */
-bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)
-{
-    bool ret = true;
-    uint32_t delay;
-    CLOCK_DisableClock(kCLOCK_Usbd1);
-    /* Power on the VD5 for USB PHY */    
-    POWER_SetUsbPhy();
-    if (kCLOCK_UsbSrcFro == src)
-    {
-        switch (freq)
-        {
-            case 96000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
-                break;
-            
-            case 48000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
-                break;
-            
-            default:
-                ret = false;
-                break;
-        }
-        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
-        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
-                          SYSCON_FROCTRL_USBCLKADJ_MASK;
-        /* Select FRO 96 or 48 MHz */
-        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
-    }
-    else
-    {    
-        delay = 100000;
-        while (delay --)
-        {
-            __asm("nop");
-        }    
-        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
-      
-        CLOCK_SetUsbPLLFreq(&pll_setup);
-        
-        /* Select USB PLL output as USB clock src */
-        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
-        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);  
-    }
-
-    delay = 100000;
-    while (delay --)
-    {
-        __asm("nop");
-    }
-    /* Enable USB1D and USB1RAM */
-    CLOCK_EnableClock(kCLOCK_Usbd1);
-    CLOCK_EnableClock(kCLOCK_UsbRam1); 
-    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
-    return ret;
-}
-
-
-/* Enable USB HOST HIGH SPEED clock */
-bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)
-{
-    bool ret = true;
-    uint32_t delay;
-    CLOCK_DisableClock(kCLOCK_Usbh1);
-    /* Power on the VD5 for USB PHY */    
-    POWER_SetUsbPhy();
-    if (kCLOCK_UsbSrcFro == src)
-    {
-        switch (freq)
-        {
-            case 96000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
-                break;
-            
-            case 48000000U:
-                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
-                break;
-            
-            default:
-                ret = false;
-                break;
-        }
-        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
-        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
-                          SYSCON_FROCTRL_USBCLKADJ_MASK;
-        /* Select FRO 96 or 48 MHz */
-        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
-    }
-    else
-    {
-        delay = 100000;
-        while (delay --)
-        {
-            __asm("nop");
-        }    
-        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
-
-        CLOCK_SetUsbPLLFreq(&pll_setup);
-        
-        /* Select USB PLL output as USB clock src */
-        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
-        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
-    }
-
-    delay = 100000;
-    while (delay --)
-    {
-        __asm("nop");
-    }
-    /* Enable USBh1 and USB1RAM */
-    CLOCK_EnableClock(kCLOCK_Usbh1);
-    CLOCK_EnableClock(kCLOCK_UsbRam1); 
-    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
-    return ret;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1265 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016 - 2017 , NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name ofcopyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_CLOCK_H_
-#define _FSL_CLOCK_H_
-
-#include "fsl_device_registers.h"
-#include <stdint.h>
-#include <stdbool.h>
-#include <assert.h>
-
-/*! @addtogroup clock */
-/*! @{ */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- *****************************************************************************/
-
-/*! @brief Configure whether driver controls clock
- *
- * When set to 0, peripheral drivers will enable clock in initialize function
- * and disable clock in de-initialize function. When set to 1, peripheral
- * driver will not control the clock, application could contol the clock out of
- * the driver.
- *
- * @note All drivers share this feature switcher. If it is set to 1, application
- * should handle clock enable and disable for all drivers.
- */
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
-#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
-#endif
-/*! @brief Clock ip name array for ROM. */
-#define ADC_CLOCKS \
-    {              \
-        kCLOCK_Adc0 \
-    }
-/*! @brief Clock ip name array for ROM. */
-#define ROM_CLOCKS \
-    {              \
-        kCLOCK_Rom \
-    }
-/*! @brief Clock ip name array for SRAM. */
-#define SRAM_CLOCKS \
-    {               \
-        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
-    }
-/*! @brief Clock ip name array for FLASH. */
-#define FLASH_CLOCKS \
-    {                \
-        kCLOCK_Flash \
-    }
-/*! @brief Clock ip name array for FMC. */
-#define FMC_CLOCKS \
-    {              \
-        kCLOCK_Fmc \
-    }
-/*! @brief Clock ip name array for EEPROM. */
-#define EEPROM_CLOCKS  \
-    {                  \
-        kCLOCK_Eeprom  \
-    }
-/*! @brief Clock ip name array for SPIFI. */
-#define SPIFI_CLOCKS  \
-    {                 \
-        kCLOCK_Spifi  \
-    }
-/*! @brief Clock ip name array for INPUTMUX. */
-#define INPUTMUX_CLOCKS      \
-    {                        \
-        kCLOCK_InputMux      \
-    }
-/*! @brief Clock ip name array for IOCON. */
-#define IOCON_CLOCKS         \
-    {                        \
-        kCLOCK_Iocon         \
-    }
-/*! @brief Clock ip name array for GPIO. */
-#define GPIO_CLOCKS          \
-    {                        \
-        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5     \
-    }
-/*! @brief Clock ip name array for PINT. */
-#define PINT_CLOCKS          \
-    {                        \
-        kCLOCK_Pint          \
-    }
-/*! @brief Clock ip name array for GINT. */
-#define GINT_CLOCKS          \
-    {                        \
-        kCLOCK_Gint, kCLOCK_Gint          \
-    }
-/*! @brief Clock ip name array for DMA. */
-#define DMA_CLOCKS          \
-    {                       \
-        kCLOCK_Dma          \
-    }
-/*! @brief Clock ip name array for CRC. */
-#define CRC_CLOCKS          \
-    {                       \
-        kCLOCK_Crc          \
-    }
-/*! @brief Clock ip name array for WWDT. */
-#define WWDT_CLOCKS          \
-    {                        \
-        kCLOCK_Wwdt          \
-    }
-/*! @brief Clock ip name array for RTC. */
-#define RTC_CLOCKS          \
-    {                       \
-        kCLOCK_Rtc          \
-    }
-/*! @brief Clock ip name array for ADC0. */
-#define ADC0_CLOCKS          \
-    {                        \
-        kCLOCK_Adc0          \
-    }
-/*! @brief Clock ip name array for MRT. */
-#define MRT_CLOCKS           \
-    {                        \
-        kCLOCK_Mrt           \
-    }
-/*! @brief Clock ip name array for RIT. */
-#define RIT_CLOCKS           \
-    {                        \
-        kCLOCK_Rit           \
-    }
-/*! @brief Clock ip name array for SCT0. */
-#define SCT_CLOCKS          \
-    {                        \
-        kCLOCK_Sct0          \
-    }
-/*! @brief Clock ip name array for MCAN. */
-#define MCAN_CLOCKS          \
-    {                        \
-        kCLOCK_Mcan0, kCLOCK_Mcan1          \
-    }
-/*! @brief Clock ip name array for UTICK. */
-#define UTICK_CLOCKS         \
-    {                        \
-        kCLOCK_Utick         \
-    }
-/*! @brief Clock ip name array for FLEXCOMM. */
-#define FLEXCOMM_CLOCKS                                                        \
-    {                                                                          \
-        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
-					kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \
-                                        kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
-    }
-/*! @brief Clock ip name array for LPUART. */
-#define LPUART_CLOCKS                                                                                         \
-    {                                                                                                         \
-        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
-            kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9     \
-    }
-
-/*! @brief Clock ip name array for BI2C. */
-#define BI2C_CLOCKS                                                                                                     \
-    {                                                                                                                   \
-        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \
-        kCLOCK_BI2c8, kCLOCK_BI2c9  \
-    }
-/*! @brief Clock ip name array for LSPI. */
-#define LPSI_CLOCKS                                                                                                     \
-    {                                                                                                                   \
-        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \
-        kCLOCK_LSpi8, kCLOCK_LSpi9  \
-    }
-/*! @brief Clock ip name array for FLEXI2S. */
-#define FLEXI2S_CLOCKS                                                                                        \
-    {                                                                                                         \
-        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
-            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9                                                                  \
-    }
-/*! @brief Clock ip name array for DMIC. */
-#define DMIC_CLOCKS \
-    {               \
-        kCLOCK_DMic \
-    }
-/*! @brief Clock ip name array for CT32B. */
-#define CTIMER_CLOCKS                                                               \
-    {                                                                               \
-        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4   \
-    }
-/*! @brief Clock ip name array for LCD. */
-#define LCD_CLOCKS  \
-    {               \
-        kCLOCK_Lcd  \
-    }
-/*! @brief Clock ip name array for SDIO. */
-#define SDIO_CLOCKS  \
-    {                \
-        kCLOCK_Sdio  \
-    }
-/*! @brief Clock ip name array for USBRAM. */
-#define USBRAM_CLOCKS    \
-    {                    \
-        kCLOCK_UsbRam1   \
-    }
-/*! @brief Clock ip name array for EMC. */
-#define EMC_CLOCKS       \
-    {                    \
-        kCLOCK_Emc       \
-    }
-/*! @brief Clock ip name array for ETH. */
-#define ETH_CLOCKS       \
-    {                    \
-        kCLOCK_Eth       \
-    }
-/*! @brief Clock ip name array for AES. */
-#define AES_CLOCKS       \
-    {                    \
-        kCLOCK_Aes       \
-    }
-/*! @brief Clock ip name array for OTP. */
-#define OTP_CLOCKS       \
-    {                    \
-        kCLOCK_Otp       \
-    }
-/*! @brief Clock ip name array for RNG. */
-#define RNG_CLOCKS       \
-    {                    \
-        kCLOCK_Rng       \
-    }
-/*! @brief Clock ip name array for USBHMR0. */
-#define USBHMR0_CLOCKS       \
-    {                        \
-        kCLOCK_Usbhmr0       \
-    }
-/*! @brief Clock ip name array for USBHSL0. */
-#define USBHSL0_CLOCKS       \
-    {                        \
-        kCLOCK_Usbhsl0       \
-    }
-/*! @brief Clock ip name array for SHA0. */
-#define SHA0_CLOCKS       \
-    {                     \
-        kCLOCK_Sha0       \
-    }
-/*! @brief Clock ip name array for SMARTCARD. */
-#define SMARTCARD_CLOCKS  \
-    {                     \
-        kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
-    }
-/*! @brief Clock ip name array for USBD. */
-#define USBD_CLOCKS  \
-    {                \
-        kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
-    }
-/*! @brief Clock ip name array for USBH. */
-#define USBH_CLOCKS  \
-    {                \
-        kCLOCK_Usbh1 \
-    }
-/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
-/*------------------------------------------------------------------------------
- clock_ip_name_t definition:
-------------------------------------------------------------------------------*/
-
-#define CLK_GATE_REG_OFFSET_SHIFT 8U
-#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
-#define CLK_GATE_BIT_SHIFT_SHIFT 0U
-#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
-
-#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
-    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
-     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
-
-#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
-#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
-
-#define AHB_CLK_CTRL0 0
-#define AHB_CLK_CTRL1 1
-#define AHB_CLK_CTRL2 2
-#define ASYNC_CLK_CTRL0 3
-
-/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
-typedef enum _clock_ip_name
-{
-    kCLOCK_IpInvalid = 0U,
-    kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
-    kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
-    kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
-    kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
-    kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
-    kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
-    kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9),
-    kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
-    kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
-    kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
-    kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
-    kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
-    kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
-    kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
-    kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
-    kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
-    kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
-    kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
-    kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
-    kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
-    kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
-    kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
-    kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
-    kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
-    kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
-    kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
-    kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
-    kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
-    kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
-    kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
-    kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
-    kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
-    kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
-    kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
-    kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
-    kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
-    kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
-    kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
-    kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
-    kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
-    kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
-    kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
-    kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
-    kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
-    kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
-    kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
-    kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
-    kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
-    kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
-    kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
-    kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
-    kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
-    kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
-    kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
-    kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
-    kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
-    kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
-    kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
-    kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
-    kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
-    kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
-    kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
-    kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
-    kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
-    kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
-    kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
-    kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
-    kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
-    kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
-    kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
-    kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
-    kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
-    kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
-    kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
-    kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
-    kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
-    kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
-    kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
-    kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
-    kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
-    kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8),
-    kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
-    kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
-    kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
-    kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
-    kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
-    kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
-    kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
-    kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
-    kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
-    kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
-    kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
-    kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
-    kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
-    kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
-    kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
-    kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
-    kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
-    kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
-    kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
-    kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
-
-    kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
-    kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
-} clock_ip_name_t;
-
-/*! @brief Clock name used to get clock frequency. */
-typedef enum _clock_name
-{
-    kCLOCK_CoreSysClk,  /*!< Core/system clock  (aka MAIN_CLK)                       */
-    kCLOCK_BusClk,      /*!< Bus clock (AHB clock)                                   */
-    kCLOCK_ClockOut,    /*!< CLOCKOUT                                                */
-    kCLOCK_FroHf,       /*!< FRO48/96                                                */
-    kCLOCK_SpiFi,       /*!< SPIFI                                                   */
-    kCLOCK_Adc,         /*!< ADC                                                     */
-    kCLOCK_Usb0,        /*!< USB0                                                    */
-    kCLOCK_Usb1,        /*!< USB1                                                    */
-    kCLOCK_UsbPll,      /*!< USB1 PLL                                                */
-    kCLOCK_Mclk,        /*!< MCLK                                                    */
-    kCLOCK_Sct,         /*!< SCT                                                     */
-    kCLOCK_SDio,        /*!< SDIO                                                    */
-    kCLOCK_EMC,         /*!< EMC                                                     */
-    kCLOCK_LCD,         /*!< LCD                                                     */
-    kCLOCK_MCAN0,       /*!< MCAN0                                                   */
-    kCLOCK_MCAN1,       /*!< MCAN1                                                   */
-    kCLOCK_Fro12M,      /*!< FRO12M                                                  */
-    kCLOCK_ExtClk,      /*!< External Clock                                          */
-    kCLOCK_PllOut,      /*!< PLL Output                                              */
-    kCLOCK_UsbClk,      /*!< USB input                                               */
-    kClock_WdtOsc,      /*!< Watchdog Oscillator                                     */
-    kCLOCK_Frg,         /*!< Frg Clock                                               */
-    kCLOCK_Dmic,        /*!< Digital Mic clock                                       */
-    kCLOCK_AsyncApbClk, /*!< Async APB clock										 */
-    kCLOCK_FlexI2S,     /*!< FlexI2S clock                                           */
-    kCLOCK_Flexcomm0,   /*!< Flexcomm0Clock                                          */
-    kCLOCK_Flexcomm1,   /*!< Flexcomm1Clock                                          */
-    kCLOCK_Flexcomm2,   /*!< Flexcomm2Clock                                          */
-    kCLOCK_Flexcomm3,   /*!< Flexcomm3Clock                                          */
-    kCLOCK_Flexcomm4,   /*!< Flexcomm4Clock                                          */
-    kCLOCK_Flexcomm5,   /*!< Flexcomm5Clock                                          */
-    kCLOCK_Flexcomm6,   /*!< Flexcomm6Clock                                          */
-    kCLOCK_Flexcomm7,   /*!< Flexcomm7Clock                                          */
-    kCLOCK_Flexcomm8,   /*!< Flexcomm8Clock                                          */
-    kCLOCK_Flexcomm9,   /*!< Flexcomm9Clock                                          */
-
-} clock_name_t;
-
-/**
- * Clock source selections for the asynchronous APB clock
- */
-typedef enum _async_clock_src
-{
-    kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
-    kCLOCK_AsyncFro12Mhz,    /*!< 12MHz FRO */
-    kCLOCK_AsyncAudioPllClk,
-    kCLOCK_AsyncI2cClkFc6,
-
-} async_clock_src_t;
-
-/*! @brief Clock Mux Switches
-*  The encoding is as follows each connection identified is 64bits wide
-*  starting from LSB upwards
-*
-*  [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
-*
-*/
-
-#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
-#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
-#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
-#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
-#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
-
-#define CM_MAINCLKSELA 0
-#define CM_MAINCLKSELB 1
-#define CM_CLKOUTCLKSELA 2
-#define CM_SYSPLLCLKSEL 4
-#define CM_AUDPLLCLKSEL 6
-#define CM_SPIFICLKSEL 8
-#define CM_ADCASYNCCLKSEL 9
-#define CM_USB0CLKSEL 10
-#define CM_USB1CLKSEL 11
-#define CM_FXCOMCLKSEL0 12
-#define CM_FXCOMCLKSEL1 13
-#define CM_FXCOMCLKSEL2 14
-#define CM_FXCOMCLKSEL3 15
-#define CM_FXCOMCLKSEL4 16
-#define CM_FXCOMCLKSEL5 17
-#define CM_FXCOMCLKSEL6 18
-#define CM_FXCOMCLKSEL7 19
-#define CM_FXCOMCLKSEL8 20
-#define CM_FXCOMCLKSEL9 21
-#define CM_MCLKCLKSEL 24
-#define CM_FRGCLKSEL 26
-#define CM_DMICCLKSEL 27
-#define CM_SCTCLKSEL  28
-#define CM_LCDCLKSEL  29
-#define CM_SDIOCLKSEL 30
-
-#define CM_ASYNCAPB 31
-
-typedef enum _clock_attach_id
-{
-
-    kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
-    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
-    kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
-    kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
-    kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
-    kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
-
-    kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
-    kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
-    kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
-    kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
-    kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
-    kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
-    kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
-    kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
-
-    kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
-    kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
-    kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
-    kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
-    kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
-
-    kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
-    kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
-    kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
-
-    kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
-    kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
-    kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
-    kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
-    kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
-    kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
-
-    kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
-    kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
-    kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
-    kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
-    kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
-
-    kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
-    kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
-    kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
-    kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
-
-    kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
-    kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
-    kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
-    kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
-
-    kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
-    kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
-    kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
-    kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
-    kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
-    kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
-
-    kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
-    kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
-    kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
-    kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
-    kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
-    kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
-
-    kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
-    kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
-    kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
-    kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
-    kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
-    kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
-
-    kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
-    kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
-    kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
-    kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
-    kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
-    kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
-
-    kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
-    kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
-    kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
-    kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
-    kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
-    kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
-
-    kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
-    kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
-    kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
-    kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
-    kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
-    kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
-
-    kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
-    kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
-    kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
-    kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
-    kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
-    kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
-
-    kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
-    kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
-    kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
-    kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
-    kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
-    kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
-
-    kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
-    kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
-    kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
-    kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
-    kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
-    kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
-
-    kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
-    kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
-    kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
-    kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
-    kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
-    kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
-
-    kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
-    kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
-    kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
-
-    kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
-    kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
-    kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
-    kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
-    kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
-
-    kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
-    kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
-    kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
-    kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
-    kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
-
-    kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
-    kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
-    kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
-    kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
-    kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
-
-    kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
-    kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
-    kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
-    kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
-    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
-    kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
-
-    kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
-    kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
-    kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
-    kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
-
-    kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
-    kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
-    kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
-    kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
-    kNONE_to_NONE = 0x80000000U,
-} clock_attach_id_t;
-
-/*  Clock dividers */
-typedef enum _clock_div_name
-{
-    kCLOCK_DivSystickClk = 0,
-    kCLOCK_DivArmTrClkDiv = 1,
-    kCLOCK_DivCan0Clk = 2,
-    kCLOCK_DivCan1Clk = 3,
-    kCLOCK_DivSmartCard0Clk = 4,
-    kCLOCK_DivSmartCard1Clk = 5,
-    kCLOCK_DivAhbClk = 32,
-    kCLOCK_DivClkOut = 33,
-    kCLOCK_DivFrohfClk = 34,
-    kCLOCK_DivSpifiClk = 36,
-    kCLOCK_DivAdcAsyncClk = 37,
-    kCLOCK_DivUsb0Clk = 38,
-    kCLOCK_DivUsb1Clk = 39,
-    kCLOCK_DivFrg = 40,
-    kCLOCK_DivDmicClk = 42,
-    kCLOCK_DivMClk = 43,
-    kCLOCK_DivLcdClk = 44,
-    kCLOCK_DivSctClk = 45,
-    kCLOCK_DivEmcClk = 46,
-    kCLOCK_DivSdioClk = 47
-} clock_div_name_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-static inline void CLOCK_EnableClock(clock_ip_name_t clk)
-{
-    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
-    if (index < 3)
-    {
-        SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
-    }
-    else
-    {
-        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
-        ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
-    }
-}
-
-static inline void CLOCK_DisableClock(clock_ip_name_t clk)
-{
-    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
-    if (index < 3)
-    {
-        SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
-    }
-    else
-    {
-        ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
-        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
-
-    }
-}
-/**
- * @brief FLASH Access time definitions
- */
-typedef enum _clock_flashtim
-{
-    kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
-    kCLOCK_Flash2Cycle,     /*!< Flash accesses use 2 CPU clocks */
-    kCLOCK_Flash3Cycle,     /*!< Flash accesses use 3 CPU clocks */
-    kCLOCK_Flash4Cycle,     /*!< Flash accesses use 4 CPU clocks */
-    kCLOCK_Flash5Cycle,     /*!< Flash accesses use 5 CPU clocks */
-    kCLOCK_Flash6Cycle,     /*!< Flash accesses use 6 CPU clocks */
-    kCLOCK_Flash7Cycle,     /*!< Flash accesses use 7 CPU clocks */
-    kCLOCK_Flash8Cycle,     /*!< Flash accesses use 8 CPU clocks */
-    kCLOCK_Flash9Cycle      /*!< Flash accesses use 9 CPU clocks */
-} clock_flashtim_t;
-
-/**
- * @brief	Set FLASH memory access time in clocks
- * @param	clks	: Clock cycles for FLASH access
- * @return	Nothing
- */
-static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
-{
-    uint32_t tmp;
-
-    tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
-
-    /* Don't alter lower bits */
-    SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
-}
-
-/**
- * @brief	Initialize the Core clock to given frequency (12, 48 or 96 MHz).
- * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
- * enabled.
- * @param	iFreq	: Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
- * @return	returns success or fail status.
- */
-status_t CLOCK_SetupFROClocking(uint32_t iFreq);
-/**
- * @brief	Configure the clock selection muxes.
- * @param	connection	: Clock to be configured.
- * @return	Nothing
- */
-void CLOCK_AttachClk(clock_attach_id_t connection);
-/**
- * @brief	Setup peripheral clock dividers.
- * @param	div_name	: Clock divider name
- * @param divided_by_value: Value to be divided
- * @param reset :  Whether to reset the divider counter.
- * @return	Nothing
- */
-void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
-/**
- * @brief	Set the flash wait states for the input freuqency.
- * @param	iFreq	: Input frequency
- * @return	Nothing
- */
-void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
-/*! @brief	Return Frequency of selected clock
- *  @return	Frequency of selected clock
- */
-uint32_t CLOCK_GetFreq(clock_name_t clockName);
-/*! @brief	Return Frequency of FRO 12MHz
- *  @return	Frequency of FRO 12MHz
- */
-uint32_t CLOCK_GetFro12MFreq(void);
-/*! @brief	Return Frequency of ClockOut
- *  @return	Frequency of ClockOut
- */
-uint32_t CLOCK_GetClockOutClkFreq(void);
-/*! @brief	Return Frequency of Spifi Clock
- *  @return	Frequency of Spifi.
- */
-uint32_t CLOCK_GetSpifiClkFreq(void);
-/*! @brief	Return Frequency of Adc Clock
- *  @return	Frequency of Adc Clock.
- */
-uint32_t CLOCK_GetAdcClkFreq(void);
-/*! @brief	Return Frequency of Usb0 Clock
- *  @return	Frequency of Usb0 Clock.
- */
-uint32_t CLOCK_GetUsb0ClkFreq(void);
-/*! @brief	Return Frequency of Usb1 Clock
- *  @return	Frequency of Usb1 Clock.
- */
-uint32_t CLOCK_GetUsb1ClkFreq(void);
-/*! @brief	Return Frequency of MClk Clock
- *  @return	Frequency of MClk Clock.
- */
-uint32_t CLOCK_GetMclkClkFreq(void);
-/*! @brief	Return Frequency of SCTimer Clock
- *  @return	Frequency of SCTimer Clock.
- */
-uint32_t CLOCK_GetSctClkFreq(void);
-/*! @brief	Return Frequency of SDIO Clock
- *  @return	Frequency of SDIO Clock.
- */
-uint32_t CLOCK_GetSdioClkFreq(void);
-/*! @brief	Return Frequency of LCD Clock
- *  @return	Frequency of LCD Clock.
- */
-uint32_t CLOCK_GetLcdClkFreq(void);
-/*! @brief	Return Frequency of LCD CLKIN Clock
- *  @return	Frequency of LCD CLKIN Clock.
- */
-uint32_t CLOCK_GetLcdClkIn(void);
-/*! @brief	Return Frequency of External Clock
- *  @return	Frequency of External Clock. If no external clock is used returns 0.
- */
-uint32_t CLOCK_GetExtClkFreq(void);
-/*! @brief	Return Frequency of Watchdog Oscillator
- *  @return	Frequency of Watchdog Oscillator
- */
-uint32_t CLOCK_GetWdtOscFreq(void);
-/*! @brief	Return Frequency of High-Freq output of FRO
- *  @return	Frequency of High-Freq output of FRO
- */
-uint32_t CLOCK_GetFroHfFreq(void);
-/*! @brief	Return Frequency of PLL
- *  @return	Frequency of PLL
- */
-uint32_t CLOCK_GetPllOutFreq(void);
-/*! @brief	Return Frequency of USB PLL
- *  @return	Frequency of PLL
- */
-uint32_t CLOCK_GetUsbPllOutFreq(void);
-/*! @brief	Return Frequency of AUDIO PLL
- *  @return	Frequency of PLL
- */
-uint32_t CLOCK_GetAudioPllOutFreq(void);
-/*! @brief	Return Frequency of 32kHz osc
- *  @return	Frequency of 32kHz osc
- */
-uint32_t CLOCK_GetOsc32KFreq(void);
-/*! @brief	Return Frequency of Core System
- *  @return	Frequency of Core System
- */
-uint32_t CLOCK_GetCoreSysClkFreq(void);
-/*! @brief	Return Frequency of I2S MCLK Clock
- *  @return	Frequency of I2S MCLK Clock
- */
-uint32_t CLOCK_GetI2SMClkFreq(void);
-/*! @brief	Return Frequency of Flexcomm functional Clock
- *  @return	Frequency of Flexcomm functional Clock
- */
-uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
-/*! @brief	Return Asynchronous APB Clock source
- *  @return	Asynchronous APB CLock source
- */
-__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
-{
-    return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
-}
-/*! @brief	Return Frequency of Asynchronous APB Clock
- *  @return	Frequency of Asynchronous APB Clock Clock
- */
-uint32_t CLOCK_GetAsyncApbClkFreq(void);
-/*! @brief	Return Audio PLL input clock rate
- *  @return	Audio PLL input clock rate
- */
-uint32_t CLOCK_GetAudioPLLInClockRate(void);
-/*! @brief	Return System PLL input clock rate
- *  @return	System PLL input clock rate
- */
-uint32_t CLOCK_GetSystemPLLInClockRate(void);
-
-/*! @brief	Return System PLL output clock rate
- *  @param	recompute	: Forces a PLL rate recomputation if true
- *  @return	System PLL output clock rate
- *  @note	The PLL rate is cached in the driver in a variable as
- *  the rate computation function can take some time to perform. It
- *  is recommended to use 'false' with the 'recompute' parameter.
- */
-uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
-
-/*! @brief	Return System AUDIO PLL output clock rate
- *  @param	recompute	: Forces a AUDIO PLL rate recomputation if true
- *  @return	System AUDIO PLL output clock rate
- *  @note	The AUDIO PLL rate is cached in the driver in a variable as
- *  the rate computation function can take some time to perform. It
- *  is recommended to use 'false' with the 'recompute' parameter.
- */
-uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
-
-/*! @brief	Return System USB PLL output clock rate
- *  @param	recompute	: Forces a USB PLL rate recomputation if true
- *  @return	System USB PLL output clock rate
- *  @note	The USB PLL rate is cached in the driver in a variable as
- *  the rate computation function can take some time to perform. It
- *  is recommended to use 'false' with the 'recompute' parameter.
- */
-uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute);
-
-/*! @brief	Enables and disables PLL bypass mode
- *  @brief	bypass	: true to bypass PLL (PLL output = PLL input, false to disable bypass
- *  @return	System PLL output clock rate
- */
-__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
-{
-    if (bypass)
-    {
-        SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
-    }
-    else
-    {
-        SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
-    }
-}
-
-/*! @brief	Check if PLL is locked or not
- *  @return	true if the PLL is locked, false if not locked
- */
-__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
-{
-    return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
-}
-
-/*! @brief	Check if USB PLL is locked or not
- *  @return	true if the USB PLL is locked, false if not locked
- */
-__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
-{
-    return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0);
-}
-
-/*! @brief	Check if AUDIO PLL is locked or not
- *  @return	true if the AUDIO PLL is locked, false if not locked
- */
-__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
-{
-    return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0);
-}
-
-/*! @brief	Enables and disables SYS OSC
- *  @brief	enable	: true to enable SYS OSC, false to disable SYS OSC
-*/
-__STATIC_INLINE  void CLOCK_Enable_SysOsc(bool enable)
-{
-    if(enable)
-    {
-        SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
-        SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
-    }
-
-    else
-    {
-        SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
-        SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
-
-    }
-}
-
-/*! @brief Store the current PLL rate
- *  @param	rate: Current rate of the PLL
- *  @return	Nothing
- **/
-void CLOCK_SetStoredPLLClockRate(uint32_t rate);
-
-/*! @brief Store the current AUDIO PLL rate
- *  @param	rate: Current rate of the PLL
- *  @return	Nothing
- **/
-void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
-
-/*! @brief PLL configuration structure flags for 'flags' field
- * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
- *
- * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
- * configuration structure must be assigned with the expected PLL frequency. If the
- * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
- * function and the driver will determine the PLL rate from the currently selected
- * PLL source. This flag might be used to configure the PLL input clock more accurately
- * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
- *
- * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
- * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
- * are not used.<br>
- */
-#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
-#define PLL_CONFIGFLAG_FORCENOFRACT                                                                                    \
-    (1                                                                                                                 \
-     << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
-                \ \ \                                                                                                                     \
-                  \ \ \ \ \                                                                                                                     \
-                    \ \ \ \ \ \ \                                                                                                                     \
-                      hardware */
-
-/*! @brief PLL configuration structure
- *
- * This structure can be used to configure the settings for a PLL
- * setup structure. Fill in the desired configuration for the PLL
- * and call the PLL setup function to fill in a PLL setup structure.
- */
-typedef struct _pll_config
-{
-    uint32_t desiredRate; /*!< Desired PLL rate in Hz */
-    uint32_t inputRate;   /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
-    uint32_t flags;       /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
-} pll_config_t;
-
-/*! @brief PLL setup structure flags for 'flags' field
-* These flags control how the PLL setup function sets up the PLL
-*/
-#define PLL_SETUPFLAG_POWERUP (1 << 0)  /*!< Setup will power on the PLL after setup */
-#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
-#define PLL_SETUPFLAG_ADGVOLT (1 << 2)  /*!< Optimize system voltage for the new PLL rate */
-
-/*! @brief PLL setup structure
-* This structure can be used to pre-build a PLL setup configuration
-* at run-time and quickly set the PLL to the configuration. It can be
-* populated with the PLL setup function. If powering up or waiting
-* for PLL lock, the PLL input clock source should be configured prior
-* to PLL setup.
-*/
-typedef struct _pll_setup
-{
-    uint32_t pllctrl;         /*!< PLL control register SYSPLLCTRL */
-    uint32_t pllndec;         /*!< PLL NDEC register SYSPLLNDEC */
-    uint32_t pllpdec;         /*!< PLL PDEC register SYSPLLPDEC */
-    uint32_t pllmdec;         /*!< PLL MDEC registers SYSPLLPDEC */
-    uint32_t pllRate;         /*!< Acutal PLL rate */
-    uint32_t audpllfrac;      /*!< only aduio PLL has this function*/
-    uint32_t flags;           /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
-} pll_setup_t;
-
-/*! @brief PLL status definitions
- */
-typedef enum _pll_error
-{
-    kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),         /*!< PLL operation was successful */
-    kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),    /*!< PLL output rate request was too low */
-    kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),   /*!< PLL output rate request was too high */
-    kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),     /*!< PLL input rate is too low */
-    kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),    /*!< PLL input rate is too high */
-    kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
-    kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6),       /*!< Requested CCO rate isn't possible */
-    kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7)       /*!< Requested CCO rate isn't possible */
-} pll_error_t;
-
-/*! @brief USB clock source definition. */
-typedef enum _clock_usb_src
-{
-    kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,            /*!< Use FRO 96 or 48 MHz. */
-    kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,     /*!< Use System PLL output. */
-    kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock.    */
-    kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll,        /*!< Use USB PLL clock.    */
-
-    kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7)          /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
-} clock_usb_src_t;
-
-/*! @brief USB PDEL Divider. */
-typedef enum _usb_pll_psel
-{
-    pSel_Divide_1 = 0U,
-    pSel_Divide_2,
-    pSel_Divide_4,
-    pSel_Divide_8
-}usb_pll_psel;
-
-/*! @brief PLL setup structure
-* This structure can be used to pre-build a USB PLL setup configuration
-* at run-time and quickly set the usb PLL to the configuration. It can be
-* populated with the USB PLL setup function. If powering up or waiting
-* for USB PLL lock, the PLL input clock source should be configured prior
-* to USB PLL setup.
-*/
-typedef struct _usb_pll_setup
-{
-  uint8_t msel;           /*!< USB PLL control register msel:1U-256U */
-  uint8_t psel;           /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
-  uint8_t nsel;           /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
-  bool direct;            /*!< USB PLL CCO output control */
-  bool bypass;            /*!< USB PLL inout clock bypass control  */
-  bool fbsel;             /*!< USB PLL ineter mode and non-integer mode control*/
-  uint32_t inputRate;     /*!< USB PLL input rate */
-} usb_pll_setup_t;
-
-/*! @brief	Return System PLL output clock rate from setup structure
- *  @param	pSetup	: Pointer to a PLL setup structure
- *  @return	System PLL output clock rate the setup structure will generate
- */
-uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
-
-/*! @brief	Return System AUDIO PLL output clock rate from setup structure
- *  @param	pSetup	: Pointer to a PLL setup structure
- *  @return	System PLL output clock rate the setup structure will generate
- */
-uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
-
-/*! @brief	Return System USB PLL output clock rate from setup structure
- *  @param	pSetup	: Pointer to a PLL setup structure
- *  @return	System PLL output clock rate the setup structure will generate
- */
-uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
-
-/*! @brief	Set PLL output based on the passed PLL setup data
- *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
- *  @param	pSetup		: Pointer to PLL setup structure to be filled
- *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
- *  @note	Actual frequency for setup may vary from the desired frequency based on the
- *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
- */
-pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
-
-/*! @brief	Set AUDIO PLL output based on the passed AUDIO PLL setup data
- *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
- *  @param	pSetup		: Pointer to PLL setup structure to be filled
- *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
- *  @note	Actual frequency for setup may vary from the desired frequency based on the
- *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
- */
-pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
-
-/*! @brief	Set PLL output from PLL setup structure (precise frequency)
- * @param	pSetup	: Pointer to populated PLL setup structure
-* @param flagcfg : Flag configuration for PLL config structure
- * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
- * @note	This function will power off the PLL, setup the PLL with the
- * new setup data, and then optionally powerup the PLL, wait for PLL lock,
- * and adjust system voltages to the new PLL rate. The function will not
- * alter any source clocks (ie, main systen clock) that may use the PLL,
- * so these should be setup prior to and after exiting the function.
- */
-pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
-
-/*! @brief	Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
- * @param	pSetup	: Pointer to populated PLL setup structure
-* @param flagcfg : Flag configuration for PLL config structure
- * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
- * @note	This function will power off the PLL, setup the PLL with the
- * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
- * and adjust system voltages to the new AUDIOPLL rate. The function will not
- * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
- * so these should be setup prior to and after exiting the function.
- */
-pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
-
-/**
- * @brief	Set PLL output from PLL setup structure (precise frequency)
- * @param	pSetup	: Pointer to populated PLL setup structure
- * @return	kStatus_PLL_Success on success, or PLL setup error code
- * @note	This function will power off the PLL, setup the PLL with the
- * new setup data, and then optionally powerup the PLL, wait for PLL lock,
- * and adjust system voltages to the new PLL rate. The function will not
- * alter any source clocks (ie, main systen clock) that may use the PLL,
- * so these should be setup prior to and after exiting the function.
- */
-pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
-
-/**
- * @brief	Set Audio PLL output from Audio PLL setup structure (precise frequency)
- * @param	pSetup	: Pointer to populated PLL setup structure
- * @return	kStatus_PLL_Success on success, or Audio PLL setup error code
- * @note	This function will power off the PLL, setup the Audio PLL with the
- * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
- * and adjust system voltages to the new PLL rate. The function will not
- * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
- * so these should be setup prior to and after exiting the function.
- */
-pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
-
-/**
- * @brief	Set USB PLL output from USB PLL setup structure (precise frequency)
- * @param	pSetup	: Pointer to populated USB PLL setup structure
- * @return	kStatus_PLL_Success on success, or USB PLL setup error code
- * @note	This function will power off the USB PLL, setup the PLL with the
- * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
- * and adjust system voltages to the new USB PLL rate. The function will not
- * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
- * so these should be setup prior to and after exiting the function.
- */
-pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
-
-/*! @brief	Set PLL output based on the multiplier and input frequency
- * @param	multiply_by	: multiplier
- * @param	input_freq	: Clock input frequency of the PLL
- * @return	Nothing
- * @note	Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
- * function does not disable or enable PLL power, wait for PLL lock,
- * or adjust system voltages. These must be done in the application.
- * The function will not alter any source clocks (ie, main systen clock)
- * that may use the PLL, so these should be setup prior to and after
- * exiting the function.
- */
-void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
-
-/*! @brief Disable USB clock.
- *
- * Disable USB clock.
- */
-static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
-{
-    CLOCK_DisableClock(clk);
-}
-
-/*! @brief Enable USB Device FS clock.
- * @param	src	: clock source
- * @param	freq: clock frequency
- * Enable USB Device Full Speed clock.
- */
-bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
-
-/*! @brief Enable USB HOST FS clock.
- * @param	src	: clock source
- * @param	freq: clock frequency
- * Enable USB HOST Full Speed clock.
- */
-bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
-
-/*! @brief Enable USB Device HS clock.
- * @param	src	: clock source
- * @param	freq: clock frequency
- * Enable USB Device High Speed clock.
- */
-bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
-
-/*! @brief Enable USB HOST HS clock.
- * @param	src	: clock source
- * @param	freq: clock frequency
- * Enable USB HOST High Speed clock.
- */
-bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-/*! @} */
-
-#endif /* _FSL_CLOCK_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
-    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
-    for (;;)
-    {
-        __BKPT(0);
-    }
-}
-#elif(defined(__REDLIB__))
-
-#if SDK_DEBUGCONSOLE
-void __assertion_failed(char *_Expr)
-{
-    PRINTF("%s\n", _Expr);
-    for (;;)
-    {
-        __asm("bkpt #0");
-    }
-}
-#endif
-
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
-    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
-    for (;;)
-    {
-        __BKPT(0);
-    }
-}
-#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
-#ifndef __GIC_PRIO_BITS
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-    extern uint32_t Image$$VECTOR_ROM$$Base[];
-    extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
-    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
-    uint32_t n;
-    uint32_t ret;
-    uint32_t irqMaskValue;
-
-    irqMaskValue = DisableGlobalIRQ();
-    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
-    {
-        /* Copy the vector table from ROM to RAM */
-        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
-        {
-            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
-        }
-        /* Point the VTOR to the position of vector table */
-        SCB->VTOR = (uint32_t)__VECTOR_RAM;
-    }
-
-    ret = __VECTOR_RAM[irq + 16];
-    /* make sure the __VECTOR_RAM is noncachable */
-    __VECTOR_RAM[irq + 16] = irqHandler;
-
-    EnableGlobalIRQ(irqMaskValue);
-
-    return ret;
-}
-#endif
-
-#ifndef CPU_QN908X
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t index = 0;
-    uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    SYSCON->STARTERSET[index] = 1u << intNumber;
-    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t index = 0;
-    uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-    SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#else
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t index = 0;
-    uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    /*   SYSCON->STARTERSET[index] = 1u << intNumber; */
-    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t index = 0;
-    uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-                           /*   SYSCON->STARTERCLR[index] = 1u << intNumber; */
-}
-#endif /*CPU_QN908X */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,348 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_COMMON_H_
-#define _FSL_COMMON_H_
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-#if defined(__ICCARM__)
-#include <stddef.h>
-#endif
-
-#include "fsl_device_registers.h"
-
-/*!
- * @addtogroup ksdk_common
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Construct a status code value from a group and code number. */
-#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
-
-/*! @brief Construct the version number for drivers. */
-#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
-
-/* Debug console type definition. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
-
-/*! @brief Status group numbers. */
-enum _status_groups
-{
-    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
-    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
-    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
-    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
-    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
-    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
-    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
-    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
-    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
-    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
-    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
-    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
-    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
-    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
-    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
-    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
-    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
-    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
-    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
-    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
-    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
-    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
-    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
-    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
-    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
-    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
-    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
-    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
-    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
-    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
-    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
-    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
-    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
-    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
-    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
-    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
-    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
-    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
-    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
-    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
-    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
-    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
-    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
-    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
-    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
-    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
-    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
-    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
-    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
-    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
-    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
-    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
-    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
-    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
-    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
-    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
-};
-
-/*! @brief Generic status return codes. */
-enum _generic_status
-{
-    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
-    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
-    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
-    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
-    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
-    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
-    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
-};
-
-/*! @brief Type used for all status and error return values. */
-typedef int32_t status_t;
-
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
-/*
- * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
- */
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
-     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-#include "fsl_reset.h"
-#endif
-
-/*! @name Min/max macros */
-/* @{ */
-#if !defined(MIN)
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-#endif
-
-#if !defined(MAX)
-#define MAX(a, b) ((a) > (b) ? (a) : (b))
-#endif
-/* @} */
-
-/*! @brief Computes the number of elements in an array. */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-/*! @name UINT16_MAX/UINT32_MAX value */
-/* @{ */
-#if !defined(UINT16_MAX)
-#define UINT16_MAX ((uint16_t)-1)
-#endif
-
-#if !defined(UINT32_MAX)
-#define UINT32_MAX ((uint32_t)-1)
-#endif
-/* @} */
-
-/*! @name Timer utilities */
-/* @{ */
-/*! Macro to convert a microsecond period to raw count value */
-#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
-/*! Macro to convert a raw count value to microsecond */
-#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
-
-/*! Macro to convert a millisecond period to raw count value */
-#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
-/*! Macro to convert a raw count value to millisecond */
-#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
-/* @} */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Enable specific interrupt.
- *
- * Enable the interrupt not routed from intmux.
- *
- * @param interrupt The IRQ number.
- */
-static inline void EnableIRQ(IRQn_Type interrupt)
-{
-    if (NotAvail_IRQn == interrupt)
-    {
-        return;
-    }
-
-#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
-    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
-#endif
-    {
-#if defined(__GIC_PRIO_BITS)
-        GIC_EnableIRQ(interrupt);
-#else
-        NVIC_EnableIRQ(interrupt);
-#endif
-    }
-}
-
-/*!
- * @brief Disable specific interrupt.
- *
- * Disable the interrupt not routed from intmux.
- *
- * @param interrupt The IRQ number.
- */
-static inline void DisableIRQ(IRQn_Type interrupt)
-{
-    if (NotAvail_IRQn == interrupt)
-    {
-        return;
-    }
-
-#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
-    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
-#endif
-    {
-#if defined(__GIC_PRIO_BITS)
-        GIC_DisableIRQ(interrupt);
-#else
-        NVIC_DisableIRQ(interrupt);
-#endif
-    }
-}
-
-/*!
- * @brief Disable the global IRQ
- *
- * Disable the global interrupt and return the current primask register. User is required to provided the primask
- * register for the EnableGlobalIRQ().
- *
- * @return Current primask value.
- */
-static inline uint32_t DisableGlobalIRQ(void)
-{
-#if defined(CPSR_I_Msk)
-    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
-
-    __disable_irq();
-
-    return cpsr;
-#else
-    uint32_t regPrimask = __get_PRIMASK();
-
-    __disable_irq();
-
-    return regPrimask;
-#endif
-}
-
-/*!
- * @brief Enaable the global IRQ
- *
- * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
- * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
- * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
- *
- * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
- * DisableGlobalIRQ().
- */
-static inline void EnableGlobalIRQ(uint32_t primask)
-{
-#if defined(CPSR_I_Msk)
-    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
-#else
-    __set_PRIMASK(primask);
-#endif
-}
-
-/*!
- * @brief install IRQ handler
- *
- * @param irq IRQ number
- * @param irqHandler IRQ handler address
- * @return The old IRQ handler address
- */
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-/*!
- * @brief Enable specific interrupt for wake-up from deep-sleep mode.
- *
- * Enable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
- *
- * @param interrupt The IRQ number.
- */
-void EnableDeepSleepIRQ(IRQn_Type interrupt);
-
-/*!
- * @brief Disable specific interrupt for wake-up from deep-sleep mode.
- *
- * Disable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
- *
- * @param interrupt The IRQ number.
- */
-void DisableDeepSleepIRQ(IRQn_Type interrupt);
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @} */
-
-#endif /* _FSL_COMMON_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "fsl_crc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
-/* @brief Default user configuration structure for CRC-CCITT */
-#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
-/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
-#define CRC_DRIVER_DEFAULT_REVERSE_IN false
-/*< Default is no bit reverse */
-#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
-/*< Default is without complement of written data */
-#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
-/*< Default is no bit reverse */
-#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
-/*< Default is without complement of CRC data register read data */
-#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
-/*< Default initial checksum */
-#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void CRC_Init(CRC_Type *base, const crc_config_t *config)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* enable clock to CRC */
-    CLOCK_EnableClock(kCLOCK_Crc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* configure CRC module and write the seed */
-    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
-                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
-                 CRC_MODE_CMPL_SUM(config->complementOut);
-    base->SEED = config->seed;
-}
-
-void CRC_GetDefaultConfig(crc_config_t *config)
-{
-    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
-                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
-                                                CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
-
-    *config = default_config;
-}
-
-void CRC_Reset(CRC_Type *base)
-{
-    crc_config_t config;
-    CRC_GetDefaultConfig(&config);
-    CRC_Init(base, &config);
-}
-
-void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
-{
-    /* extract CRC mode settings */
-    uint32_t mode = base->MODE;
-    config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
-    config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
-    config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
-    config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
-    config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
-
-    /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
-    base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
-
-    /* now we can obtain intermediate raw CRC sum value */
-    config->seed = base->SUM;
-
-    /* restore original CRC sum bit reverse and 1's complement setting */
-    base->MODE = mode;
-}
-
-void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
-{
-    const uint32_t *data32;
-
-    /* 8-bit reads and writes till source address is aligned 4 bytes */
-    while ((dataSize) && ((uint32_t)data & 3U))
-    {
-        *((__O uint8_t *)&(base->WR_DATA)) = *data;
-        data++;
-        dataSize--;
-    }
-
-    /* use 32-bit reads and writes as long as possible */
-    data32 = (const uint32_t *)data;
-    while (dataSize >= sizeof(uint32_t))
-    {
-        *((__O uint32_t *)&(base->WR_DATA)) = *data32;
-        data32++;
-        dataSize -= sizeof(uint32_t);
-    }
-
-    data = (const uint8_t *)data32;
-
-    /* 8-bit reads and writes till end of data buffer */
-    while (dataSize)
-    {
-        *((__O uint8_t *)&(base->WR_DATA)) = *data;
-        data++;
-        dataSize--;
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,203 +0,0 @@
-/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_CRC_H_
-#define _FSL_CRC_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup crc
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief CRC driver version. Version 2.0.1.
- *
- * Current version: 2.0.1
- *
- * Change log:
- * - Version 2.0.0
- *   - initial version
- * - Version 2.0.1
- *   - add explicit type cast when writing to WR_DATA
- */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
-/*@}*/
-
-#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
-/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
-#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
-#endif
-
-/*! @brief CRC polynomials to use. */
-typedef enum _crc_polynomial
-{
-    kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
-    kCRC_Polynomial_CRC_16 = 1U,    /*!< x^16+x^15+x^2+1 */
-    kCRC_Polynomial_CRC_32 = 2U     /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
-} crc_polynomial_t;
-
-/*!
-* @brief CRC protocol configuration.
-*
-* This structure holds the configuration for the CRC protocol.
-*
-*/
-typedef struct _crc_config
-{
-    crc_polynomial_t polynomial; /*!< CRC polynomial. */
-    bool reverseIn;              /*!< Reverse bits on input. */
-    bool complementIn;           /*!< Perform 1's complement on input. */
-    bool reverseOut;             /*!< Reverse bits on output. */
-    bool complementOut;          /*!< Perform 1's complement on output. */
-    uint32_t seed;               /*!< Starting checksum value. */
-} crc_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Enables and configures the CRC peripheral module.
- *
- * This functions enables the CRC peripheral clock in the LPC SYSCON block.
- * It also configures the CRC engine and starts checksum computation by writing the seed.
- *
- * @param base   CRC peripheral address.
- * @param config CRC module configuration structure.
- */
-void CRC_Init(CRC_Type *base, const crc_config_t *config);
-
-/*!
- * @brief Disables the CRC peripheral module.
- *
- * This functions disables the CRC peripheral clock in the LPC SYSCON block.
- *
- * @param base CRC peripheral address.
- */
-static inline void CRC_Deinit(CRC_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* disable clock to CRC */
-    CLOCK_DisableClock(kCLOCK_Crc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-/*!
- * @brief resets CRC peripheral module.
- *
- * @param base   CRC peripheral address.
- */
-void CRC_Reset(CRC_Type *base);
-
-/*!
- * @brief Loads default values to CRC protocol configuration structure.
- *
- * Loads default values to CRC protocol configuration structure. The default values are:
- * @code
- *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
- *   config->reverseIn = false;
- *   config->complementIn = false;
- *   config->reverseOut = false;
- *   config->complementOut = false;
- *   config->seed = 0xFFFFU;
- * @endcode
- *
- * @param config CRC protocol configuration structure
- */
-void CRC_GetDefaultConfig(crc_config_t *config);
-
-/*!
- * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
- *
- * The values, including seed, can be used to resume CRC calculation later.
-
- * @param base   CRC peripheral address.
- * @param config CRC protocol configuration structure
- */
-void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
-
-/*!
- * @brief Writes data to the CRC module.
- *
- * Writes input data buffer bytes to CRC data register.
- *
- * @param base     CRC peripheral address.
- * @param data     Input data stream, MSByte in data[0].
- * @param dataSize Size of the input data buffer in bytes.
- */
-void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
-
-/*!
- * @brief Reads 32-bit checksum from the CRC module.
- *
- * Reads CRC data register.
- *
- * @param base CRC peripheral address.
- * @return final 32-bit checksum, after configured bit reverse and complement operations.
- */
-static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
-{
-    return base->SUM;
-}
-
-/*!
- * @brief Reads 16-bit checksum from the CRC module.
- *
- * Reads CRC data register.
- *
- * @param base CRC peripheral address.
- * @return final 16-bit checksum, after configured bit reverse and complement operations.
- */
-static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
-{
-    return (uint16_t)base->SUM;
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- *@}
- */
-
-#endif /* _FSL_CRC_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,352 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_ctimer.h"
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Gets the instance from the base address
- *
- * @param base Ctimer peripheral base address
- *
- * @return The Timer instance
- */
-static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to Timer bases for each instance. */
-static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to Timer clocks for each instance. */
-static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to Timer resets for each instance. */
-static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
-
-/*! @brief Pointers real ISRs installed by drivers for each instance. */
-static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
-
-/*! @brief Callback type installed by drivers for each instance. */
-static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
-
-/*! @brief Array to map timer instance to IRQ number. */
-static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
-{
-    uint32_t instance;
-    uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ctimerArrayCount; instance++)
-    {
-        if (s_ctimerBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ctimerArrayCount);
-
-    return instance;
-}
-
-void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
-{
-    assert(config);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the timer clock*/
-    CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the module */
-    RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
-
-    /* Setup the cimer mode and count select */
-    base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
-
-    /* Setup the timer prescale value */
-    base->PR = CTIMER_PR_PRVAL(config->prescale);
-}
-
-void CTIMER_Deinit(CTIMER_Type *base)
-{
-    uint32_t index = CTIMER_GetInstance(base);
-    /* Stop the timer */
-    base->TCR &= ~CTIMER_TCR_CEN_MASK;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the timer clock*/
-    CLOCK_DisableClock(s_ctimerClocks[index]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Disable IRQ at NVIC Level */
-    DisableIRQ(s_ctimerIRQ[index]);
-}
-
-void CTIMER_GetDefaultConfig(ctimer_config_t *config)
-{
-    assert(config);
-
-    /* Run as a timer */
-    config->mode = kCTIMER_TimerMode;
-    /* This field is ignored when mode is timer */
-    config->input = kCTIMER_Capture_0;
-    /* Timer counter is incremented on every APB bus clock */
-    config->prescale = 0;
-}
-
-status_t CTIMER_SetupPwm(CTIMER_Type *base,
-                         ctimer_match_t matchChannel,
-                         uint8_t dutyCyclePercent,
-                         uint32_t pwmFreq_Hz,
-                         uint32_t srcClock_Hz,
-                         bool enableInt)
-{
-    assert(pwmFreq_Hz > 0);
-
-    uint32_t reg;
-    uint32_t period, pulsePeriod = 0;
-    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
-    uint32_t index = CTIMER_GetInstance(base);
-
-    if (matchChannel == kCTIMER_Match_3)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Enable PWM mode on the channel */
-    base->PWMC |= (1U << matchChannel);
-
-    /* Clear the stop, reset and interrupt bits for this channel */
-    reg = base->MCR;
-    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
-
-    /* If call back function is valid then enable match interrupt for the channel */
-    if (enableInt)
-    {
-        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
-    }
-
-    /* Reset the counter when match on channel 3 */
-    reg |= CTIMER_MCR_MR3R_MASK;
-
-    base->MCR = reg;
-
-    /* Calculate PWM period match value */
-    period = (timerClock / pwmFreq_Hz) - 1;
-
-    /* Calculate pulse width match value */
-    if (dutyCyclePercent == 0)
-    {
-        pulsePeriod = period + 1;
-    }
-    else
-    {
-        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
-    }
-
-    /* Match on channel 3 will define the PWM period */
-    base->MR[kCTIMER_Match_3] = period;
-
-    /* This will define the PWM pulse period */
-    base->MR[matchChannel] = pulsePeriod;
-    /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
-    /* If call back function is valid then enable interrupt and update the call back function */
-    if (enableInt)
-    {
-        EnableIRQ(s_ctimerIRQ[index]);
-    }
-
-    return kStatus_Success;
-}
-
-void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
-{
-    uint32_t pulsePeriod = 0, period;
-
-    /* Match channel 3 defines the PWM period */
-    period = base->MR[kCTIMER_Match_3];
-
-    /* Calculate pulse width match value */
-    pulsePeriod = (period * dutyCyclePercent) / 100;
-
-    /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
-    if (dutyCyclePercent == 0)
-    {
-        pulsePeriod = period + 1;
-    }
-    else
-    {
-        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
-    }
-
-    /* Update dutycycle */
-    base->MR[matchChannel] = pulsePeriod;
-}
-
-void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
-{
-    uint32_t reg;
-    uint32_t index = CTIMER_GetInstance(base);
-
-    /* Set the counter operation when a match on this channel occurs */
-    reg = base->MCR;
-    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
-    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
-    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
-    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
-    base->MCR = reg;
-
-    reg = base->EMR;
-    /* Set the match output operation when a match on this channel occurs */
-    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
-    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
-
-    /* Set the initial state of the EM bit/output */
-    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
-    reg |= (uint32_t)config->outPinInitState << matchChannel;
-    base->EMR = reg;
-
-    /* Set the match value */
-    base->MR[matchChannel] = config->matchValue;
-    /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
-    /* If interrupt is enabled then enable interrupt and update the call back function */
-    if (config->enableInterrupt)
-    {
-        EnableIRQ(s_ctimerIRQ[index]);
-    }
-}
-
-void CTIMER_SetupCapture(CTIMER_Type *base,
-                         ctimer_capture_channel_t capture,
-                         ctimer_capture_edge_t edge,
-                         bool enableInt)
-{
-    uint32_t reg = base->CCR;
-    uint32_t index = CTIMER_GetInstance(base);
-
-    /* Set the capture edge */
-    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
-    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
-    /* Clear status flags */
-    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
-    /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
-    if (enableInt)
-    {
-        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
-        EnableIRQ(s_ctimerIRQ[index]);
-    }
-    base->CCR = reg;
-}
-
-void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
-{
-    uint32_t index = CTIMER_GetInstance(base);
-    s_ctimerCallback[index] = cb_func;
-    ctimerCallbackType[index] = cb_type;
-}
-
-void CTIMER_GenericIRQHandler(uint32_t index)
-{
-    uint32_t int_stat, i, mask;
-    /* Get Interrupt status flags */
-    int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
-    /* Clear the status flags that were set */
-    CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
-    if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
-    {
-        if (s_ctimerCallback[index][0])
-        {
-            s_ctimerCallback[index][0](int_stat);
-        }
-    }
-    else
-    {
-        for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
-        {
-            mask = 0x01 << i;
-            /* For each status flag bit that was set call the callback function if it is valid */
-            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
-            {
-                s_ctimerCallback[index][i](int_stat);
-            }
-        }
-    }
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(CTIMER0)
-void CTIMER0_DriverIRQHandler(void)
-{
-    CTIMER_GenericIRQHandler(0);
-}
-#endif
-
-#if defined(CTIMER1)
-void CTIMER1_DriverIRQHandler(void)
-{
-    CTIMER_GenericIRQHandler(1);
-}
-#endif
-
-#if defined(CTIMER2)
-void CTIMER2_DriverIRQHandler(void)
-{
-    CTIMER_GenericIRQHandler(2);
-}
-#endif
-
-#if defined(CTIMER3)
-void CTIMER3_DriverIRQHandler(void)
-{
-    CTIMER_GenericIRQHandler(3);
-}
-#endif
-
-#if defined(CTIMER4)
-void CTIMER4_DriverIRQHandler(void)
-{
-    CTIMER_GenericIRQHandler(4);
-}
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,434 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_CTIMER_H_
-#define _FSL_CTIMER_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup ctimer
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/*! @brief List of Timer capture channels */
-typedef enum _ctimer_capture_channel
-{
-    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
-    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
-    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
-    kCTIMER_Capture_3       /*!< Timer capture channel 3 */
-} ctimer_capture_channel_t;
-
-/*! @brief List of capture edge options */
-typedef enum _ctimer_capture_edge
-{
-    kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
-    kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
-    kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
-} ctimer_capture_edge_t;
-
-/*! @brief List of Timer match registers */
-typedef enum _ctimer_match
-{
-    kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
-    kCTIMER_Match_1,      /*!< Timer match register 1 */
-    kCTIMER_Match_2,      /*!< Timer match register 2 */
-    kCTIMER_Match_3       /*!< Timer match register 3 */
-} ctimer_match_t;
-
-/*! @brief List of output control options */
-typedef enum _ctimer_match_output_control
-{
-    kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
-    kCTIMER_Output_Clear,         /*!< Clear the EM bit/output to 0 */
-    kCTIMER_Output_Set,           /*!< Set the EM bit/output to 1 */
-    kCTIMER_Output_Toggle         /*!< Toggle the EM bit/output */
-} ctimer_match_output_control_t;
-
-/*! @brief List of Timer modes */
-typedef enum _ctimer_timer_mode
-{
-    kCTIMER_TimerMode = 0U,     /* TC is incremented every rising APB bus clock edge */
-    kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
-    kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
-    kCTIMER_IncreaseOnBothEdge  /* TC is incremented on both edges of input signal */
-} ctimer_timer_mode_t;
-
-/*! @brief List of Timer interrupts */
-typedef enum _ctimer_interrupt_enable
-{
-    kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK,    /*!< Match 0 interrupt */
-    kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK,    /*!< Match 1 interrupt */
-    kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK,    /*!< Match 2 interrupt */
-    kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK,    /*!< Match 3 interrupt */
-    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
-    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
-    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
-    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
-} ctimer_interrupt_enable_t;
-
-/*! @brief List of Timer flags */
-typedef enum _ctimer_status_flags
-{
-    kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK,   /*!< Match 0 interrupt flag */
-    kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK,   /*!< Match 1 interrupt flag */
-    kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK,   /*!< Match 2 interrupt flag */
-    kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK,   /*!< Match 3 interrupt flag */
-    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
-    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
-    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
-    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
-} ctimer_status_flags_t;
-
-typedef void (*ctimer_callback_t)(uint32_t flags);
-
-/*! @brief Callback type when registering for a callback. When registering a callback
- *         an array of function pointers is passed the size could be 1 or 8, the callback
- *         type will tell that.
- */
-typedef enum
-{
-    kCTIMER_SingleCallback,  /*!< Single Callback type where there is only one callback for the timer. 
-                                 based on the status flags different channels needs to be handled differently */
-    kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. 
-                                 for both match/capture */
-} ctimer_callback_type_t;
-
-/*!
- * @brief Match configuration
- *
- * This structure holds the configuration settings for each match register.
- */
-typedef struct _ctimer_match_config
-{
-    uint32_t matchValue;                      /*!< This is stored in the match register */
-    bool enableCounterReset;                  /*!< true: Match will reset the counter
-                                                   false: Match will not reser the counter */
-    bool enableCounterStop;                   /*!< true: Match will stop the counter
-                                                   false: Match will not stop the counter */
-    ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
-    bool outPinInitState;                     /*!< Initial value of the EM bit/output */
-    bool enableInterrupt;                     /*!< true: Generate interrupt upon match
-                                                   false: Do not generate interrupt on match */
-
-} ctimer_match_config_t;
-
-/*!
- * @brief Timer configuration structure
- *
- * This structure holds the configuration settings for the Timer peripheral. To initialize this
- * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
- * pointer to the configuration structure instance.
- *
- * The configuration structure can be made constant so as to reside in flash.
- */
-typedef struct _ctimer_config
-{
-    ctimer_timer_mode_t mode;       /*!< Timer mode */
-    ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
-                                        modes that rely on this input signal to increment TC */
-    uint32_t prescale;              /*!< Prescale value */
-} ctimer_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Ungates the clock and configures the peripheral for basic operation.
- *
- * @note This API should be called at the beginning of the application before using the driver.
- *
- * @param base   Ctimer peripheral base address
- * @param config Pointer to the user configuration structure.
- */
-void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
-
-/*!
- * @brief Gates the timer clock.
- *
- * @param base Ctimer peripheral base address
- */
-void CTIMER_Deinit(CTIMER_Type *base);
-
-/*!
- * @brief  Fills in the timers configuration structure with the default settings.
- *
- * The default values are:
- * @code
- *   config->mode = kCTIMER_TimerMode;
- *   config->input = kCTIMER_Capture_0;
- *   config->prescale = 0;
- * @endcode
- * @param config Pointer to the user configuration structure.
- */
-void CTIMER_GetDefaultConfig(ctimer_config_t *config);
-
-/*! @}*/
-
-/*!
- * @name PWM setup operations
- * @{
- */
-
-/*!
- * @brief Configures the PWM signal parameters.
- *
- * Enables PWM mode on the match channel passed in and will then setup the match value
- * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
- *
- * @note When setting PWM output from multiple output pins, all should use the same PWM
- * frequency
- *
- * @param base             Ctimer peripheral base address
- * @param matchChannel     Match pin to be used to output the PWM signal
- * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
- * @param pwmFreq_Hz       PWM signal frequency in Hz
- * @param srcClock_Hz      Timer counter clock in Hz
- * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
- */
-status_t CTIMER_SetupPwm(CTIMER_Type *base,
-                         ctimer_match_t matchChannel,
-                         uint8_t dutyCyclePercent,
-                         uint32_t pwmFreq_Hz,
-                         uint32_t srcClock_Hz,
-                         bool enableInt);
-
-/*!
- * @brief Updates the duty cycle of an active PWM signal.
- *
- * @param base             Ctimer peripheral base address
- * @param matchChannel     Match pin to be used to output the PWM signal
- * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
- */
-void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
-
-/*! @}*/
-
-/*!
- * @brief Setup the match register.
- *
- * User configuration is used to setup the match value and action to be taken when a match occurs.
- *
- * @param base         Ctimer peripheral base address
- * @param matchChannel Match register to configure
- * @param config       Pointer to the match configuration structure
- */
-void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
-
-/*!
- * @brief Setup the capture.
- *
- * @param base      Ctimer peripheral base address
- * @param capture   Capture channel to configure
- * @param edge      Edge on the channel that will trigger a capture
- * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
- *                  is called upon capture
- */
-void CTIMER_SetupCapture(CTIMER_Type *base,
-                         ctimer_capture_channel_t capture,
-                         ctimer_capture_edge_t edge,
-                         bool enableInt);
-
-/*!
- * @brief Register callback.
- *
- * @param base      Ctimer peripheral base address
- * @param cb_func   callback function
- * @param cb_type   callback function type, singular or multiple
- */
-void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
-
-/*!
- * @name Interrupt Interface
- * @{
- */
-
-/*!
- * @brief Enables the selected Timer interrupts.
- *
- * @param base Ctimer peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::ctimer_interrupt_enable_t
- */
-static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
-{
-    /* Enable match interrupts */
-    base->MCR |= mask;
-
-    /* Enable capture interrupts */
-    base->CCR |= mask;
-}
-
-/*!
- * @brief Disables the selected Timer interrupts.
- *
- * @param base Ctimer peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::ctimer_interrupt_enable_t
- */
-static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
-{
-    /* Disable match interrupts */
-    base->MCR &= ~mask;
-
-    /* Disable capture interrupts */
-    base->CCR &= ~mask;
-}
-
-/*!
- * @brief Gets the enabled Timer interrupts.
- *
- * @param base Ctimer peripheral base address
- *
- * @return The enabled interrupts. This is the logical OR of members of the
- *         enumeration ::ctimer_interrupt_enable_t
- */
-static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
-{
-    uint32_t enabledIntrs = 0;
-
-    /* Get all the match interrupts enabled */
-    enabledIntrs =
-        base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT);
-
-    /* Get all the capture interrupts enabled */
-    enabledIntrs |=
-        base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT);
-
-    return enabledIntrs;
-}
-
-/*! @}*/
-
-/*!
- * @name Status Interface
- * @{
- */
-
-/*!
- * @brief Gets the Timer status flags.
- *
- * @param base Ctimer peripheral base address
- *
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::ctimer_status_flags_t
- */
-static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
-{
-    return base->IR;
-}
-
-/*!
- * @brief Clears the Timer status flags.
- *
- * @param base Ctimer peripheral base address
- * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::ctimer_status_flags_t
- */
-static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
-{
-    base->IR = mask;
-}
-
-/*! @}*/
-
-/*!
- * @name Counter Start and Stop
- * @{
- */
-
-/*!
- * @brief Starts the Timer counter.
- *
- * @param base Ctimer peripheral base address
- */
-static inline void CTIMER_StartTimer(CTIMER_Type *base)
-{
-    base->TCR |= CTIMER_TCR_CEN_MASK;
-}
-
-/*!
- * @brief Stops the Timer counter.
- *
- * @param base Ctimer peripheral base address
- */
-static inline void CTIMER_StopTimer(CTIMER_Type *base)
-{
-    base->TCR &= ~CTIMER_TCR_CEN_MASK;
-}
-
-/*! @}*/
-
-/*!
- * @brief Reset the counter.
- *
- * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
- *
- * @param base Ctimer peripheral base address
- */
-static inline void CTIMER_Reset(CTIMER_Type *base)
-{
-    base->TCR |= CTIMER_TCR_CRST_MASK;
-    base->TCR &= ~CTIMER_TCR_CRST_MASK;
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_CTIMER_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,421 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_dma.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get instance number for DMA.
- *
- * @param base DMA peripheral base address.
- */
-static int32_t DMA_GetInstance(DMA_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Array to map DMA instance number to base pointer. */
-static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
-
-/*! @brief Array to map DMA instance number to IRQ number. */
-static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
-
-/*! @brief Pointers to transfer handle for each DMA channel. */
-static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS];
-
-/*! @brief Static table of descriptors */
-#if defined(__ICCARM__)
-#pragma data_alignment = 512
-dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
-#elif defined(__CC_ARM)
-__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
-#elif defined(__GNUC__)
-__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static int32_t DMA_GetInstance(DMA_Type *base)
-{
-    int32_t instance;
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
-    {
-        if (s_dmaBases[instance] == base)
-        {
-            break;
-        }
-    }
-    assert(instance < ARRAY_SIZE(s_dmaBases));
-    return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1;
-}
-
-void DMA_Init(DMA_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* enable dma clock gate */
-    CLOCK_EnableClock(kCLOCK_Dma);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    /* set descriptor table */
-    base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
-    /* enable dma peripheral */
-    base->CTRL |= DMA_CTRL_ENABLE_MASK;
-}
-
-void DMA_Deinit(DMA_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable DMA peripheral */
-    base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
-{
-    assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
-
-    uint32_t tmp = (
-        DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
-        DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
-        DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK
-    );
-    tmp = base->CHANNEL[channel].CFG & (~tmp);
-    tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
-    base->CHANNEL[channel].CFG = tmp;
-}
-
-/*!
- * @brief Gets the remaining bytes of the current DMA descriptor transfer.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return The number of bytes which have not been transferred yet.
- */
-uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-
-    /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes 
-     * impossible to distinguish between:
-     * - transfer finishes (represented by value '0x3FF')
-     * - and remaining 1024 bytes to transfer (value 0x3FF)
-     * for all descriptor in chain, except the last one.
-     * If you decide to use this function, please use 1023 transfers as maximal value */
-
-    /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
-    if (
-        (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && 
-        (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))
-    )
-    {
-        return 0;
-    }
-
-    return base->CHANNEL[channel].XFERCFG + 1;
-}
-
-static void DMA_SetupDescriptor(
-    dma_descriptor_t    *desc,
-    uint32_t            xfercfg,
-    void                *srcEndAddr,
-    void                *dstEndAddr,
-    void                *nextDesc
-)
-{
-    desc->xfercfg = xfercfg;
-    desc->srcEndAddr = srcEndAddr;
-    desc->dstEndAddr = dstEndAddr;
-    desc->linkToNextDesc = nextDesc;
-}
-
-/* Verify and convert dma_xfercfg_t to XFERCFG register */
-static void DMA_SetupXferCFG(
-    dma_xfercfg_t *xfercfg,
-    uint32_t *xfercfg_addr
-)
-{
-    assert(xfercfg != NULL);
-    /* check source increment */
-    assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
-    /* check destination increment */
-    assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
-    /* check data width */
-    assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
-    /* check transfer count */
-    assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
-
-    uint32_t xfer = 0, tmp;
-    /* set valid flag - descriptor is ready now */
-    xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
-    /* set reload - allow link to next descriptor */
-    xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
-    /* set swtrig flag - start transfer */
-    xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0);
-    /* set transfer count */
-    xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0);
-    /* set INTA */
-    xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
-    /* set INTB */
-    xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
-    /* set data width */
-    tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
-    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
-    /* set source increment value */
-    tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
-    xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
-    /* set destination increment value */
-    tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
-    xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
-    /* set transfer count */
-    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
-
-    /* store xferCFG */
-    *xfercfg_addr = xfer;
-}
-
-void DMA_CreateDescriptor(
-    dma_descriptor_t    *desc,
-    dma_xfercfg_t       *xfercfg,
-    void                *srcAddr,
-    void                *dstAddr,
-    void                *nextDesc
-)
-{
-    uint32_t xfercfg_reg = 0;
-
-    assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
-    assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
-    assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
-    assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
-
-    /* Setup channel configuration */
-    DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
-
-    /* Set descriptor structure */
-    DMA_SetupDescriptor(desc, xfercfg_reg,
-        (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
-        (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
-        nextDesc
-    );
-}
-
-void DMA_AbortTransfer(dma_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    DMA_DisableChannel(handle->base, handle->channel);
-    while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
-    { }
-    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
-    DMA_EnableChannel(handle->base, handle->channel);
-}
-
-void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
-{
-    int32_t dmaInstance;
-    assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS));
-
-    /* base address is invalid DMA instance */
-    dmaInstance = DMA_GetInstance(base);
-
-    memset(handle, 0, sizeof(*handle));
-    handle->base = base;
-    handle->channel = channel;
-    s_DMAHandle[channel] = handle;
-    /* Enable NVIC interrupt */
-    EnableIRQ(s_dmaIRQNumber[dmaInstance]);
-}
-
-void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
-{
-    assert(handle != NULL);
-
-    handle->callback = callback;
-    handle->userData = userData;
-}
-
-void DMA_PrepareTransfer(dma_transfer_config_t *config,
-                          void *srcAddr,
-                          void *dstAddr,
-                          uint32_t byteWidth,
-                          uint32_t transferBytes,
-                          dma_transfer_type_t type,
-                          void *nextDesc)
-{
-    uint32_t xfer_count;
-    assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
-    assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
-
-    /* check max */
-    xfer_count = transferBytes / byteWidth;
-    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
-
-    memset(config, 0, sizeof(*config));
-    switch (type)
-    {
-    case kDMA_MemoryToMemory:
-        config->xfercfg.srcInc = 1;
-        config->xfercfg.dstInc = 1;
-        config->isPeriph = false;
-        break;
-    case kDMA_PeripheralToMemory:
-        /* Peripheral register - source doesn't increment */
-        config->xfercfg.srcInc = 0;
-        config->xfercfg.dstInc = 1;
-        config->isPeriph = true;
-        break;
-    case kDMA_MemoryToPeripheral:
-        /* Peripheral register - destination doesn't increment */
-        config->xfercfg.srcInc = 1;
-        config->xfercfg.dstInc = 0;
-        config->isPeriph = true;
-        break;
-    case kDMA_StaticToStatic:
-        config->xfercfg.srcInc = 0;
-        config->xfercfg.dstInc = 0;
-        config->isPeriph = true;
-        break;
-    default:
-        return;
-    }
-
-    config->dstAddr = (uint8_t*)dstAddr;
-    config->srcAddr = (uint8_t*)srcAddr;
-    config->nextDesc = (uint8_t*)nextDesc;
-    config->xfercfg.transferCount = xfer_count;
-    config->xfercfg.byteWidth = byteWidth;
-    config->xfercfg.intA = true;
-    config->xfercfg.reload = nextDesc != NULL;
-    config->xfercfg.valid = true;
-}
-
-status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
-{
-    assert((NULL != handle) && (NULL != config));
-
-    /* Previous transfer has not finished */
-    if (DMA_ChannelIsActive(handle->base, handle->channel))
-    {
-         return kStatus_DMA_Busy;
-    }
-
-    /* enable/disable peripheral request */
-    if (config->isPeriph)
-    {
-        DMA_EnableChannelPeriphRq(handle->base, handle->channel);
-    }
-    else
-    {
-        DMA_DisableChannelPeriphRq(handle->base, handle->channel);
-    }
-
-    DMA_CreateDescriptor(
-        &s_dma_descriptor_table[ handle->channel ], &config->xfercfg,
-        config->srcAddr, config->dstAddr, config->nextDesc
-    );
-
-    return kStatus_Success;
-}
-
-void DMA_StartTransfer(dma_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    /* Enable channel interrupt */
-    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel);
-
-    /* If HW trigger is enabled - disable SW trigger */
-    if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
-    {
-        s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
-    }
-    /* Otherwise enable SW trigger */
-    else
-    {
-        s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
-    }
-
-    /* Set channel XFERCFG register according first channel descriptor. */
-    handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg;
-    /* At this moment, the channel ACTIVE bit is set and application cannot modify 
-     * or start another transfer using this channel. Channel ACTIVE bit is cleared by 
-    * 'AbortTransfer' function or when the transfer finishes */
-}
-
-void DMA0_DriverIRQHandler(void)
-{
-    dma_handle_t *handle;
-    int32_t channel_group;
-    int32_t channel_index;
-
-    /* Find channels that have completed transfer */
-    for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++)
-    {
-        handle = s_DMAHandle[i];
-        /* Handle is not present */
-        if (NULL == handle)
-        {
-            continue;
-        }
-        channel_group = DMA_CHANNEL_GROUP(handle->channel);
-        channel_index = DMA_CHANNEL_INDEX(handle->channel);
-        /* Channel uses INTA flag */
-        if (handle->base->COMMON[channel_group].INTA & (1U << channel_index))
-        {
-            /* Clear INTA flag */
-            handle->base->COMMON[channel_group].INTA = 1U << channel_index;
-            if (handle->callback)
-            {
-                (handle->callback)(handle, handle->userData, true, kDMA_IntA);
-            }
-        }
-        /* Channel uses INTB flag */
-        if (handle->base->COMMON[channel_group].INTB & (1U << channel_index))
-        {
-            /* Clear INTB flag */
-            handle->base->COMMON[channel_group].INTB = 1U << channel_index;
-            if (handle->callback)
-            {
-                (handle->callback)(handle, handle->userData, true, kDMA_IntB);
-            }
-        }
-    }
-}
-

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_DMA_H_
-#define _FSL_DMA_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup dma
- * @{
- */
-
-/*! @file */
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief DMA driver version */
-#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-/*@}*/
-
-#define DMA_MAX_TRANSFER_COUNT 0x400
-
-/* Channel group consists of 32 channels. channel_group = (channel / 32) */
-#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
-/* Channel index in channel group. channel_index = (channel % 32) */
-#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
-
-
-/*! @brief DMA descriptor structure */
-typedef struct _dma_descriptor {
-    uint32_t xfercfg;       /*!< Transfer configuration */
-    void *srcEndAddr;       /*!< Last source address of DMA transfer */
-    void *dstEndAddr;       /*!< Last destination address of DMA transfer */
-    void *linkToNextDesc;   /*!< Address of next DMA descriptor in chain */
-} dma_descriptor_t;
-
-/*! @brief DMA transfer configuration */
-typedef struct _dma_xfercfg {
-    bool valid;             /*!< Descriptor is ready to transfer */
-    bool reload;            /*!< Reload channel configuration register after
-                                 current descriptor is exhausted */
-    bool swtrig;            /*!< Perform software trigger. Transfer if fired
-                                 when 'valid' is set */
-    bool clrtrig;           /*!< Clear trigger */
-    bool intA;              /*!< Raises IRQ when transfer is done and set IRQA status register flag */
-    bool intB;              /*!< Raises IRQ when transfer is done and set IRQB status register flag */
-    uint8_t byteWidth;      /*!< Byte width of data to transfer */
-    uint8_t srcInc;         /*!< Increment source address by 'srcInc' x 'byteWidth' */
-    uint8_t dstInc;         /*!< Increment destination address by 'dstInc' x 'byteWidth' */
-    uint16_t transferCount; /*!< Number of transfers */
-} dma_xfercfg_t;
-
-/*! @brief DMA channel priority */
-typedef enum _dma_priority {
-    kDMA_ChannelPriority0 = 0,  /*!< Highest channel priority - priority 0 */
-    kDMA_ChannelPriority1,      /*!< Channel priority 1 */
-    kDMA_ChannelPriority2,      /*!< Channel priority 2 */
-    kDMA_ChannelPriority3,      /*!< Channel priority 3 */
-    kDMA_ChannelPriority4,      /*!< Channel priority 4 */
-    kDMA_ChannelPriority5,      /*!< Channel priority 5 */
-    kDMA_ChannelPriority6,      /*!< Channel priority 6 */
-    kDMA_ChannelPriority7,      /*!< Lowest channel priority - priority 7 */
-} dma_priority_t;
-
-/*! @brief DMA interrupt flags */
-typedef enum _dma_int {
-    kDMA_IntA,  /*!< DMA interrupt flag A */
-    kDMA_IntB,  /*!< DMA interrupt flag B */
-} dma_irq_t;
-
-/*! @brief DMA trigger type*/
-typedef enum _dma_trigger_type {
-    kDMA_NoTrigger = 0, /*!< Trigger is disabled */
-    kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
-    kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
-    kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
-    kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
-} dma_trigger_type_t;
-
-/*! @brief DMA trigger burst */
-typedef enum _dma_trigger_burst {
-    kDMA_SingleTransfer = 0,                                                    /*!< Single transfer */
-    kDMA_LevelBurstTransfer  = DMA_CHANNEL_CFG_TRIGBURST(1),                            /*!< Burst transfer driven by level trigger */
-    kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1),                             /*!< Perform 1 transfer by edge trigger */
-    kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1),     /*!< Perform 2 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2),     /*!< Perform 4 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3),     /*!< Perform 8 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4),    /*!< Perform 16 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5),    /*!< Perform 32 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6),    /*!< Perform 64 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7),   /*!< Perform 128 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8),   /*!< Perform 256 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9),   /*!< Perform 512 transfers by edge trigger */
-    kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
-} dma_trigger_burst_t;  
-
-/*! @brief DMA burst wrapping */
-typedef enum _dma_burst_wrap {
-    kDMA_NoWrap = 0,                                                            /*!< Wrapping is disabled */
-    kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1),                                     /*!< Wrapping is enabled for source */
-    kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1),                                     /*!< Wrapping is enabled for destination */
-    kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1),     /*!< Wrapping is enabled for source and destination */
-} dma_burst_wrap_t;
-
-/*! @brief DMA transfer type */
-typedef enum _dma_transfer_type
-{
-    kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
-    kDMA_PeripheralToMemory,    /*!< Transfer from peripheral to memory (increment only destination) */
-    kDMA_MemoryToPeripheral,    /*!< Transfer from memory to peripheral (increment only source)*/
-    kDMA_StaticToStatic,        /*!< Peripheral to static memory (do not increment source or destination) */
-} dma_transfer_type_t;
-
-/*! @brief DMA channel trigger */
-typedef struct _dma_channel_trigger {
-    dma_trigger_type_t type;
-    dma_trigger_burst_t burst;
-    dma_burst_wrap_t wrap;
-} dma_channel_trigger_t;
-
-/*! @brief DMA transfer status */
-enum _dma_transfer_status
-{
-    kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0),      /*!< Channel is busy and can't handle the
-                                                                     transfer request. */
-};
-
-/*! @brief DMA transfer configuration */
-typedef struct _dma_transfer_config
-{
-    uint8_t             *srcAddr;       /*!< Source data address */
-    uint8_t             *dstAddr;       /*!< Destination data address */
-    uint8_t             *nextDesc;      /*!< Chain custom descriptor */
-    dma_xfercfg_t       xfercfg;        /*!< Transfer options */
-    bool                isPeriph;       /*!< DMA transfer is driven by peripheral */
-} dma_transfer_config_t;
-
-/*! @brief Callback for DMA */
-struct _dma_handle;
-
-/*! @brief Define Callback function for DMA. */
-typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
-
-/*! @brief DMA transfer handle structure */
-typedef struct _dma_handle
-{
-    dma_callback callback;  /*!< Callback function. Invoked when transfer 
-                                of descriptor with interrupt flag finishes */
-    void *userData;         /*!< Callback function parameter */
-    DMA_Type *base;         /*!< DMA peripheral base address */
-    uint8_t channel;        /*!< DMA channel number */
-} dma_handle_t;
-
-/*******************************************************************************
- * APIs
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*!
- * @name DMA initialization and De-initialization
- * @{
- */
-
-/*!
- * @brief Initializes DMA peripheral.
- *
- * This function enable the DMA clock, set descriptor table and
- * enable DMA peripheral.
- *
- * @param base DMA peripheral base address.
- */
-void DMA_Init(DMA_Type *base);
-
-/*!
- * @brief Deinitializes DMA peripheral.
- *
- * This function gates the DMA clock.
- *
- * @param base DMA peripheral base address.
- */
-void DMA_Deinit(DMA_Type *base);
-
-/* @} */
-/*!
- * @name DMA Channel Operation
- * @{
- */
-
- /*!
- * @brief Return whether DMA channel is processing transfer
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return True for active state, false otherwise.
- */
-static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
-}
-
-/*!
- * @brief Enables the interrupt source for the DMA transfer.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
-}
-
-/*!
- * @brief Disables the interrupt source for the DMA transfer.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
-}
-
-/*!
- * @brief Enable DMA channel.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
-}
-
-/*!
- * @brief Disable DMA channel.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
-}
-
-/*!
- * @brief Set PERIPHREQEN of channel configuration register.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
-}
-
-/*!
- * @brief Get PERIPHREQEN value of channel configuration register.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return True for enabled PeriphRq, false for disabled.
- */
-static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
-}
-
-/*!
- * @brief Set trigger settings of DMA channel.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @param trigger trigger configuration.
- */
-void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
-
-/*!
- * @brief Gets the remaining bytes of the current DMA descriptor transfer.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return The number of bytes which have not been transferred yet.
- */
-uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
-
-/*!
- * @brief Set priority of channel configuration register.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @param priority Channel priority value.
- */
-static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
-}
-
-/*!
- * @brief Get priority of channel configuration register.
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return Channel priority value.
- */
-static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
-{
-    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
-    return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
-}
-
-/*!
- * @brief Create application specific DMA descriptor 
- *        to be used in a chain in transfer
- *
- * @param desc DMA descriptor address.
- * @param xfercfg Transfer configuration for DMA descriptor.
- * @param srcAddr Address of last item to transmit
- * @param dstAddr Address of last item to receive.
- * @param nextDesc Address of next descriptor in chain.
- */
-void DMA_CreateDescriptor(
-    dma_descriptor_t    *desc,
-    dma_xfercfg_t       *xfercfg,
-    void                *srcAddr,
-    void                *dstAddr,
-    void                *nextDesc
-);
-
-/* @} */
-
-/*!
- * @name DMA Transactional Operation
- * @{
- */
-
-/*!
- * @brief Abort running transfer by handle.
- *
- * This function aborts DMA transfer specified by handle.
- *
- * @param handle DMA handle pointer. 
- */
-void DMA_AbortTransfer(dma_handle_t *handle);
-
-/*!
- * @brief Creates the DMA handle.
- *
- * This function is called if using transaction API for DMA. This function
- * initializes the internal state of DMA handle.
- *
- * @param handle DMA handle pointer. The DMA handle stores callback function and
- *               parameters.
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- */
-void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
-
-/*!
- * @brief Installs a callback function for the DMA transfer.
- *
- * This callback is called in DMA IRQ handler. Use the callback to do something after
- * the current major loop transfer completes.
- *
- * @param handle DMA handle pointer.
- * @param callback DMA callback function pointer.
- * @param userData Parameter for callback function.
- */
-void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
-
-/*!
- * @brief Prepares the DMA transfer structure.
- *
- * This function prepares the transfer configuration structure according to the user input.
- *
- * @param config The user configuration structure of type dma_transfer_t.
- * @param srcAddr DMA transfer source address.
- * @param dstAddr DMA transfer destination address.
- * @param byteWidth DMA transfer destination address width(bytes).
- * @param transferBytes DMA transfer bytes to be transferred.
- * @param type DMA transfer type.
- * @param nextDesc Chain custom descriptor to transfer.
- * @note The data address and the data width must be consistent. For example, if the SRC
- *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
- *       source address error(SAE).
- */
-void DMA_PrepareTransfer(dma_transfer_config_t *config,
-                          void *srcAddr,
-                          void *dstAddr,
-                          uint32_t byteWidth,
-                          uint32_t transferBytes,
-                          dma_transfer_type_t type,
-                          void *nextDesc);
-
-/*!
- * @brief Submits the DMA transfer request.
- *
- * This function submits the DMA transfer request according to the transfer configuration structure.
- * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
- * a TCD and enables scatter/gather feature to process it in the next time.
- *
- * @param handle DMA handle pointer.
- * @param config Pointer to DMA transfer configuration structure.
- * @retval kStatus_DMA_Success It means submit transfer request succeed.
- * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
- * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
- */
-status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
-
-/*!
- * @brief DMA start transfer.
- *
- * This function enables the channel request. User can call this function after submitting the transfer request
- * or before submitting the transfer request.
- *
- * @param handle DMA handle pointer.
- */
-void DMA_StartTransfer(dma_handle_t *handle);
-
-/*!
- * @brief DMA IRQ handler for descriptor transfer complete.
- *
- * This function clears the channel major interrupt flag and call
- * the callback function if it is not NULL.
- */
-void DMA_HandleIRQ(void);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-/* @} */
-
-#endif /*_FSL_DMA_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,235 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_dmic.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/* Array of DMIC peripheral base address. */
-static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS;
-
-/* Array of DMIC clock name. */
-static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS;
-
-/* Array of DMIC IRQ number. */
-static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS;
-
-/*! @brief Callback function array for DMIC(s). */
-static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT];
-
-/* Array of HWVAD IRQ number. */
-static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS;
-
-/*! @brief Callback function array for HWVAD(s). */
-static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT];
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Get the DMIC instance from peripheral base address.
- *
- * @param base DMIC peripheral base address.
- * @return DMIC instance.
- */
-uint32_t DMIC_GetInstance(DMIC_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++)
-    {
-        if (s_dmicBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_dmicBases));
-
-    return instance;
-}
-
-void DMIC_Init(DMIC_Type *base)
-{
-    assert(base);
-
-    /* Enable the clock to the register interface */
-    CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
-
-    /* Reset the peripheral */
-    RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
-
-    /* Disable DMA request*/
-    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
-    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
-
-    /* Disable DMIC interrupt. */
-    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
-    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
-}
-
-void DMIC_DeInit(DMIC_Type *base)
-{
-    assert(base);
-    /* Disable the clock to the register interface */
-    CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]);
-}
-
-void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config)
-{
-    base->IOCFG = config;
-}
-
-void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode)
-{
-    if (mode == kDMIC_OperationModeInterrupt)
-    {
-        /* Enable DMIC interrupt. */
-        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
-        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
-    }
-    if (mode == kDMIC_OperationModeDma)
-    {
-        /* enable DMA request*/
-        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
-        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
-    }
-}
-
-void DMIC_ConfigChannel(DMIC_Type *base,
-                        dmic_channel_t channel,
-                        stereo_side_t side,
-                        dmic_channel_config_t *channel_config)
-{
-    base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk;
-    base->CHANNEL[channel].OSR = channel_config->osr;
-    base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft;
-    base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef;
-    base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef;
-    base->CHANNEL[channel].PHY_CTRL =
-        DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate);
-    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) |
-                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) |
-                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit);
-}
-
-void DMIC_CfgChannelDc(DMIC_Type *base,
-                       dmic_channel_t channel,
-                       dc_removal_t dc_cut_level,
-                       uint32_t post_dc_gain_reduce,
-                       bool saturate16bit)
-{
-    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) |
-                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) |
-                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit);
-}
-
-void DMIC_Use2fs(DMIC_Type *base, bool use2fs)
-{
-    base->USE2FS = (use2fs) ? 0x1 : 0x0;
-}
-
-void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask)
-{
-    base->CHANEN = channelmask;
-}
-
-void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn)
-{
-    base->CHANNEL[channel].FIFO_CTRL |=
-        (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) |
-        DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) |
-        DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn);
-}
-
-void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb)
-{
-    uint32_t instance;
-
-    instance = DMIC_GetInstance(base);
-    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
-    /* Save callback pointer */
-    s_dmicCallback[instance] = cb;
-    EnableIRQ(s_dmicIRQ[instance]);
-}
-
-void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb)
-{
-    uint32_t instance;
-
-    instance = DMIC_GetInstance(base);
-    DisableIRQ(s_dmicIRQ[instance]);
-    s_dmicCallback[instance] = NULL;
-    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
-}
-
-void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
-{
-    uint32_t instance;
-
-    instance = DMIC_GetInstance(base);
-    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
-    /* Save callback pointer */
-    s_dmicHwvadCallback[instance] = vadcb;
-    EnableIRQ(s_dmicHwvadIRQ[instance]);
-}
-
-void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
-{
-    uint32_t instance;
-
-    instance = DMIC_GetInstance(base);
-    DisableIRQ(s_dmicHwvadIRQ[instance]);
-    s_dmicHwvadCallback[instance] = NULL;
-    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(DMIC0)
-/*DMIC0 IRQ handler */
-void DMIC0_DriverIRQHandler(void)
-{
-    if (s_dmicCallback[0] != NULL)
-    {
-        s_dmicCallback[0]();
-    }
-}
-/*DMIC0 HWVAD IRQ handler */
-void HWVAD0_IRQHandler(void)
-{
-    if (s_dmicHwvadCallback[0] != NULL)
-    {
-        s_dmicHwvadCallback[0]();
-    }
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,439 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_DMIC_H_
-#define _FSL_DMIC_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup dmic_driver
- * @{
- */
-
-/*! @file*/
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*!
- * @name DMIC version
- * @{
- */
-
-/*! @brief DMIC driver version 2.0.0. */
-#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief DMIC different operation modes. */
-typedef enum _operation_mode
-{
-    kDMIC_OperationModePoll = 0U,      /*!< Polling mode */
-    kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
-    kDMIC_OperationModeDma = 2U,       /*!< DMA mode */
-} operation_mode_t;
-
-/*! @brief DMIC left/right values. */
-typedef enum _stereo_side
-{
-    kDMIC_Left = 0U,  /*!< Left Stereo channel */
-    kDMIC_Right = 1U, /*!< Right Stereo channel */
-} stereo_side_t;
-
-/*! @brief DMIC Clock pre-divider values. */
-typedef enum
-{
-    kDMIC_PdmDiv1 = 0U,    /*!< DMIC pre-divider set in divide by 1 */
-    kDMIC_PdmDiv2 = 1U,    /*!< DMIC pre-divider set in divide by 2 */
-    kDMIC_PdmDiv3 = 2U,    /*!< DMIC pre-divider set in divide by 3 */
-    kDMIC_PdmDiv4 = 3U,    /*!< DMIC pre-divider set in divide by 4 */
-    kDMIC_PdmDiv6 = 4U,    /*!< DMIC pre-divider set in divide by 6 */
-    kDMIC_PdmDiv8 = 5U,    /*!< DMIC pre-divider set in divide by 8 */
-    kDMIC_PdmDiv12 = 6U,   /*!< DMIC pre-divider set in divide by 12 */
-    kDMIC_PdmDiv16 = 7U,   /*!< DMIC pre-divider set in divide by 16*/
-    kDMIC_PdmDiv24 = 8U,   /*!< DMIC pre-divider set in divide by 24*/
-    kDMIC_PdmDiv32 = 9U,   /*!< DMIC pre-divider set in divide by 32 */
-    kDMIC_PdmDiv48 = 10U,  /*!< DMIC pre-divider set in divide by 48 */
-    kDMIC_PdmDiv64 = 11U,  /*!< DMIC pre-divider set in divide by 64*/
-    kDMIC_PdmDiv96 = 12U,  /*!< DMIC pre-divider set in divide by 96*/
-    kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
-} pdm_div_t;
-
-/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
-typedef enum _compensation
-{
-    kDMIC_CompValueZero = 0U,            /*!< Compensation 0 */
-    kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
-    kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
-    kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
-} compensation_t;
-
-/*! @brief DMIC DC filter control values. */
-typedef enum _dc_removal
-{
-    kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
-    kDMIC_DcCut155 = 1U,   /*!< Cut off Frequency is 155 Hz  */
-    kDMIC_DcCut78 = 2U,    /*!< Cut off Frequency is 78 Hz  */
-    kDMIC_DcCut39 = 3U,    /*!< Cut off Frequency is 39 Hz  */
-} dc_removal_t;
-
-/*! @brief DMIC IO configiration. */
-typedef enum _dmic_io
-{
-    kDMIC_PdmDual = 0U,       /*!< Two separate pairs of PDM wires */
-    kDMIC_PdmStereo = 4U,     /*!< Stereo Mic */
-    kDMIC_PdmBypass = 3U,     /*!< Clk Bypass clocks both channels */
-    kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */
-    kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */
-} dmic_io_t;
-
-/*! @brief DMIC Channel number. */
-typedef enum _dmic_channel
-{
-    kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
-    kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
-} dmic_channel_t;
-
-/*! @brief DMIC and decimator sample rates. */
-typedef enum _dmic_phy_sample_rate
-{
-    kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
-    kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
-} dmic_phy_sample_rate_t;
-
-/*! @brief DMIC transfer status.*/
-enum _dmic_status
-{
-    kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0),          /*!< DMIC is busy */
-    kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1),          /*!< DMIC is idle */
-    kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2),  /*!< DMIC  over run Error */
-    kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
-};
-
-/*! @brief DMIC Channel configuration structure. */
-typedef struct _dmic_channel_config
-{
-    pdm_div_t divhfclk;                 /*!< DMIC Clock pre-divider values */
-    uint32_t osr;                       /*!< oversampling rate(CIC decimation rate) for PCM */
-    int32_t gainshft;                   /*!< 4FS PCM data gain control */
-    compensation_t preac2coef;          /*!< Pre-emphasis Filter coefficient value for 2FS */
-    compensation_t preac4coef;          /*!< Pre-emphasis Filter coefficient value for 4FS */
-    dc_removal_t dc_cut_level;          /*!< DMIC DC filter control values. */
-    uint32_t post_dc_gain_reduce;       /*!< Fine gain adjustment in the form of a number of bits to downshift */
-    dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
-    bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
-                1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
-                0x8000 for negative overflow.*/
-} dmic_channel_config_t;
-
-/*! @brief DMIC Callback function. */
-typedef void (*dmic_callback_t)(void);
-
-/*! @brief HWVAD Callback function. */
-typedef void (*dmic_hwvad_callback_t)(void);
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*!
- * @brief Get the DMIC instance from peripheral base address.
- *
- * @param base DMIC peripheral base address.
- * @return DMIC instance.
- */
-uint32_t DMIC_GetInstance(DMIC_Type *base);
-
-/*!
- * @brief	Turns DMIC Clock on
- * @param	base	: DMIC base
- * @return	Nothing
- */
-void DMIC_Init(DMIC_Type *base);
-
-/*!
- * @brief	Turns DMIC Clock off
- * @param	base	: DMIC base
- * @return	Nothing
- */
-void DMIC_DeInit(DMIC_Type *base);
-
-/*!
- * @brief	Configure DMIC io
- * @param	base	: The base address of DMIC interface
- * @param	config		: DMIC io configuration
- * @return	Nothing
- */
-void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
-
-/*!
- * @brief	Set DMIC operating mode
- * @param	base	: The base address of DMIC interface
- * @param	mode	: DMIC mode
- * @return	Nothing
- */
-void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
-
-/*!
- * @brief	Configure DMIC channel
- * @param	base		: The base address of DMIC interface
- * @param	channel		: DMIC channel
- * @param side     : stereo_side_t, choice of left or right
- * @param	channel_config	: Channel configuration
- * @return	Nothing
- */
-void DMIC_ConfigChannel(DMIC_Type *base,
-                        dmic_channel_t channel,
-                        stereo_side_t side,
-                        dmic_channel_config_t *channel_config);
-
-/*!
- * @brief	Configure Clock scaling
- * @param	base		: The base address of DMIC interface
- * @param	use2fs		: clock scaling
- * @return	Nothing
- */
-void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
-
-/*!
- * @brief	Enable a particualr channel
- * @param	base		: The base address of DMIC interface
- * @param	channelmask	: Channel selection
- * @return	Nothing
- */
-void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
-
-/*!
- * @brief	Configure fifo settings for DMIC channel
- * @param	base		: The base address of DMIC interface
- * @param	channel		: DMIC channel
- * @param	trig_level	: FIFO trigger level
- * @param	enable		: FIFO level
- * @param	resetn		: FIFO reset
- * @return	Nothing
- */
-void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
-
-/*!
- * @brief	Get FIFO status
- * @param	base		: The base address of DMIC interface
- * @param	channel		: DMIC channel
- * @return	FIFO status
- */
-static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
-{
-    return base->CHANNEL[channel].FIFO_STATUS;
-}
-
-/*!
- * @brief	Clear FIFO status
- * @param	base		: The base address of DMIC interface
- * @param	channel		: DMIC channel
- * @param	mask		: Bits to be cleared
- * @return	FIFO status
- */
-static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
-{
-    base->CHANNEL[channel].FIFO_STATUS = mask;
-}
-
-/*!
- * @brief	Get FIFO data
- * @param	base		: The base address of DMIC interface
- * @param	channel		: DMIC channel
- * @return	FIFO data
- */
-static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
-{
-    return base->CHANNEL[channel].FIFO_DATA;
-}
-
-/*!
- * @brief	Enable callback.
-
- * This function enables the interrupt for the selected DMIC peripheral.
- * The callback function is not enabled until this function is called.
- *
- * @param base Base address of the DMIC peripheral.
- * @param cb callback Pointer to store callback function.
- * @retval None.
- */
-void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
-
-/*!
- * @brief	Disable callback.
-
- * This function disables the interrupt for the selected DMIC peripheral.
- *
- * @param base Base address of the DMIC peripheral.
- * @param cb callback Pointer to store callback function..
- * @retval None.
- */
-void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
-
-/**
- * @}
- */
-
-/*!
- * @name hwvad
- * @{
- */
-
-/*!
- * @brief Sets the gain value for the noise estimator.
- *
- * @param base DMIC base pointer
- * @param value gain value for the noise estimator.
- * @retval None.
- */
-static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
-{
-    assert(NULL != base);
-    base->HWVADTHGN = value & 0xFu;
-}
-
-/*!
- * @brief Sets the gain value for the signal estimator.
- *
- * @param base DMIC base pointer
- * @param value gain value for the signal estimator.
- * @retval None.
- */
-static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
-{
-    assert(NULL != base);
-    base->HWVADTHGS = value & 0xFu;
-}
-
-/*!
- * @brief Sets the hwvad filter cutoff frequency parameter.
- *
- * @param base DMIC base pointer
- * @param value cut off frequency value.
- * @retval None.
- */
-static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
-{
-    assert(NULL != base);
-    base->HWVADHPFS = value & 0x3u;
-}
-
-/*!
- * @brief Sets the input gain of hwvad.
- *
- * @param base DMIC base pointer
- * @param value input gain value for hwvad.
- * @retval None.
- */
-static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
-{
-    assert(NULL != base);
-    base->HWVADGAIN = value & 0xFu;
-}
-
-/*!
- * @brief Clears hwvad internal interrupt flag.
- *
- * @param base DMIC base pointer
- * @param st10 bit value.
- * @retval None.
- */
-static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
-{
-    assert(NULL != base);
-    base->HWVADST10 = (st10) ? 0x1 : 0x0;
-}
-
-/*!
- * @brief Resets hwvad filters.
- *
- * @param base DMIC base pointer
- * @param rstt Reset bit value.
- * @retval None.
- */
-static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
-{
-    assert(NULL != base);
-    base->HWVADRSTT = (rstt) ? 0x1 : 0x0;
-}
-
-/*!
- * @brief Gets the value from output of the filter z7.
- *
- * @param base DMIC base pointer
- * @retval output of filter z7.
- */
-static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
-{
-    assert(NULL != base);
-    return (base->HWVADLOWZ & 0xFFFFu);
-}
-
-/*!
- * @brief	Enable hwvad callback.
-
- * This function enables the hwvad interrupt for the selected DMIC  peripheral.
- * The callback function is not enabled until this function is called.
- *
- * @param base Base address of the DMIC peripheral.
- * @param vadcb callback Pointer to store callback function.
- * @retval None.
- */
-void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
-
-/*!
- * @brief	Disable callback.
-
- * This function disables the hwvad interrupt for the selected DMIC peripheral.
- *
- * @param base Base address of the DMIC peripheral.
- * @param vadcb callback Pointer to store callback function..
- * @retval None.
- */
-void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
-
-/*! @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*! @}*/
-
-#endif /* __FSL_DMIC_H */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_dmic_dma.h"
-#include "fsl_dmic.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define DMIC_HANDLE_ARRAY_SIZE 1
-
-/*<! Structure definition for dmic_dma_handle_t. The structure is private. */
-typedef struct _dmic_dma_private_handle
-{
-    DMIC_Type *base;
-    dmic_dma_handle_t *handle;
-} dmic_dma_private_handle_t;
-
-/*! @brief DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */
-enum _dmic_dma_states_t
-{
-    kDMIC_Idle = 0x0, /*!< DMIC is idle state */
-    kDMIC_Busy        /*!< DMIC is busy tranferring data. */
-};
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Get the DMIC instance from peripheral base address.
- *
- * @param base DMIC peripheral base address.
- * @return DMIC instance.
- */
-extern uint32_t DMIC_GetInstance(DMIC_Type *base);
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*<! Private handle only used for internally. */
-static dmic_dma_private_handle_t s_dmaPrivateHandle[DMIC_HANDLE_ARRAY_SIZE];
-
-/*******************************************************************************
- * Code
-********************************************************************************/
-
-static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
-{
-    assert(handle);
-    assert(param);
-
-    dmic_dma_private_handle_t *dmicPrivateHandle = (dmic_dma_private_handle_t *)param;
-    dmicPrivateHandle->handle->state = kDMIC_Idle;
-
-    if (dmicPrivateHandle->handle->callback)
-    {
-        dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle,
-                                            dmicPrivateHandle->handle->userData);
-    }
-}
-
-status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
-                                      dmic_dma_handle_t *handle,
-                                      dmic_dma_transfer_callback_t callback,
-                                      void *userData,
-                                      dma_handle_t *rxDmaHandle)
-{
-    int32_t instance = 0;
-
-    /* check 'base' */
-    assert(!(NULL == base));
-    if (NULL == base)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* check 'handle' */
-    assert(!(NULL == handle));
-    if (NULL == handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* check DMIC instance by 'base'*/
-    instance = DMIC_GetInstance(base);
-    assert(!(instance < 0));
-    if (instance < 0)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    memset(handle, 0, sizeof(*handle));
-    /* assign 'base' and 'handle' */
-    s_dmaPrivateHandle[instance].base = base;
-    s_dmaPrivateHandle[instance].handle = handle;
-
-    handle->callback = callback;
-    handle->userData = userData;
-
-    handle->rxDmaHandle = rxDmaHandle;
-
-    /* Set DMIC state to idle */
-    handle->state = kDMIC_Idle;
-    /* Configure RX. */
-    if (rxDmaHandle)
-    {
-        DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
-    }
-
-    return kStatus_Success;
-}
-
-status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
-                                 dmic_dma_handle_t *handle,
-                                 dmic_transfer_t *xfer,
-                                 uint32_t dmic_channel)
-{
-    assert(handle);
-    assert(handle->rxDmaHandle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
-
-    dma_transfer_config_t xferConfig;
-    status_t status;
-
-    /* Check if the device is busy. If previous RX not finished.*/
-    if (handle->state == kDMIC_Busy)
-    {
-        status = kStatus_DMIC_Busy;
-    }
-    else
-    {
-        handle->state = kDMIC_Busy;
-        handle->transferSize = xfer->dataSize;
-
-        /* Prepare transfer. */
-        DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t),
-                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
-
-        /* Submit transfer. */
-        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
-
-        DMA_StartTransfer(handle->rxDmaHandle);
-
-        status = kStatus_Success;
-    }
-    return status;
-}
-
-void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle)
-{
-    assert(NULL != handle);
-    assert(NULL != handle->rxDmaHandle);
-
-    /* Stop transfer. */
-    DMA_AbortTransfer(handle->rxDmaHandle);
-    handle->state = kDMIC_Idle;
-}
-
-status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count)
-{
-    assert(handle);
-    assert(handle->rxDmaHandle);
-    assert(count);
-
-    if (kDMIC_Idle == handle->state)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
-
-    return kStatus_Success;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,152 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_DMIC_DMA_H_
-#define _FSL_DMIC_DMA_H_
-
-#include "fsl_common.h"
-#include "fsl_dma.h"
-
-/*!
- * @addtogroup dmic_dma_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief DMIC transfer structure. */
-typedef struct _dmic_transfer
-{
-    uint16_t *data;  /*!< The buffer of data to be transfer.*/
-    size_t dataSize; /*!< The byte count to be transfer. */
-} dmic_transfer_t;
-
-/* Forward declaration of the handle typedef. */
-typedef struct _dmic_dma_handle dmic_dma_handle_t;
-
-/*! @brief DMIC transfer callback function. */
-typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base,
-                                             dmic_dma_handle_t *handle,
-                                             status_t status,
-                                             void *userData);
-
-/*!
-* @brief DMIC DMA handle
-*/
-struct _dmic_dma_handle
-{
-    DMIC_Type *base;                       /*!< DMIC peripheral base address. */
-    dma_handle_t *rxDmaHandle;             /*!< The DMA RX channel used. */
-    dmic_dma_transfer_callback_t callback; /*!< Callback function. */
-    void *userData;                        /*!< DMIC callback function parameter.*/
-    size_t transferSize;                   /*!< Size of the data to receive. */
-    volatile uint8_t state;                /*!< Internal state of DMIC DMA transfer */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name DMA transactional
- * @{
- */
-
-/*!
- * @brief Initializes the DMIC handle which is used in transactional functions.
- * @param base DMIC peripheral base address.
- * @param handle Pointer to dmic_dma_handle_t structure.
- * @param callback Callback function.
- * @param userData User data.
- * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
- */
-status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
-                                      dmic_dma_handle_t *handle,
-                                      dmic_dma_transfer_callback_t callback,
-                                      void *userData,
-                                      dma_handle_t *rxDmaHandle);
-
-/*!
- * @brief Receives data using DMA.
- *
- * This function receives data using DMA. This is a non-blocking function, which returns
- * right away. When all data is received, the receive callback function is called.
- *
- * @param base USART peripheral base address.
- * @param handle Pointer to usart_dma_handle_t structure.
- * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t.
- * @param dmic_channel DMIC channel 
- * @retval kStatus_Success
- */
-status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
-                                 dmic_dma_handle_t *handle,
-                                 dmic_transfer_t *xfer,
-                                 uint32_t dmic_channel);
-
-/*!
- * @brief Aborts the received data using DMA.
- *
- * This function aborts the received data using DMA.
- *
- * @param base DMIC peripheral base address
- * @param handle Pointer to dmic_dma_handle_t structure
- */
-void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle);
-
-/*!
- * @brief Get the number of bytes that have been received.
- *
- * This function gets the number of bytes that have been received.
- *
- * @param base DMIC peripheral base address.
- * @param handle DMIC handle pointer.
- * @param count Receive bytes count.
- * @retval kStatus_NoTransferInProgress No receive in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
- * @retval kStatus_Success Get successfully through the parameter count;
- */
-status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_DMIC_DMA_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_eeprom.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get the EEPROM instance from peripheral base address.
- *
- * @param base EEPROM peripheral base address.
- * @return EEPROM instance.
- */
-static uint32_t EEPROM_GetInstance(EEPROM_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/* Array of EEPROM peripheral base address. */
-static EEPROM_Type *const s_eepromBases[] = EEPROM_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/* Array of EEPROM clock name. */
-static const clock_ip_name_t s_eepromClock[] = EEPROM_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t EEPROM_GetInstance(EEPROM_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_eepromBases); instance++)
-    {
-        if (s_eepromBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_eepromBases));
-
-    return instance;
-}
-
-void EEPROM_GetDefaultConfig(eeprom_config_t *config)
-{
-    config->autoProgram = kEEPROM_AutoProgramWriteWord;
-    config->writeWaitPhase1 = 0x5U;
-    config->writeWaitPhase2 = 0x9U;
-    config->writeWaitPhase3 = 0x3U;
-    config->readWaitPhase1 = 0xFU;
-    config->readWaitPhase2 = 0x8U;
-    config->lockTimingParam = false;
-}
-
-void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz)
-{
-    assert(config);
-
-    uint32_t clockDiv = 0;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the SAI clock */
-    CLOCK_EnableClock(s_eepromClock[EEPROM_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Set the clock divider */
-    clockDiv = sourceClock_Hz / FSL_FEATURE_EEPROM_INTERNAL_FREQ;
-    if ((sourceClock_Hz % FSL_FEATURE_EEPROM_INTERNAL_FREQ) > (FSL_FEATURE_EEPROM_INTERNAL_FREQ / 2U))
-    {
-        clockDiv += 1U;
-    }
-    base->CLKDIV = clockDiv - 1U;
-
-    /* Set the auto program feature */
-    EEPROM_SetAutoProgram(base, config->autoProgram);
-
-    /* Set time delay parameter */
-    base->RWSTATE =
-        EEPROM_RWSTATE_RPHASE1(config->readWaitPhase1 - 1U) | EEPROM_RWSTATE_RPHASE2(config->readWaitPhase2 - 1U);
-    base->WSTATE = EEPROM_WSTATE_PHASE1(config->writeWaitPhase1 - 1U) |
-                   EEPROM_WSTATE_PHASE2(config->writeWaitPhase2 - 1U) |
-                   EEPROM_WSTATE_PHASE3(config->writeWaitPhase3 - 1U);
-    base->WSTATE |= EEPROM_WSTATE_LCK_PARWEP(config->lockTimingParam);
- 
-    /* Clear the remaining write operation  */
-    base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
-    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
-    {}
-}
-
-void EEPROM_Deinit(EEPROM_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the SAI clock */
-    CLOCK_DisableClock(s_eepromClock[EEPROM_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data)
-{
-    uint32_t *addr = 0;
-
-    if ((offset % 4U) || (offset > FSL_FEATURE_EEPROM_SIZE))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Set auto program settings */
-    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
-    {
-        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramWriteWord);
-    }
-
-    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
-
-    /* Compute the page */
-    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + offset);
-    *addr = data;
-
-    /* Check if need to do program erase manually */
-    if (base->AUTOPROG != kEEPROM_AutoProgramWriteWord)
-    {
-        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
-    }
-
-    /* Waiting for operation finished */
-    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
-    {}
-
-    return kStatus_Success;
-}
-
-status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data)
-{
-    uint32_t i = 0;
-    uint32_t *addr = NULL;
-
-    if ((pageNum > FSL_FEATURE_EEPROM_PAGE_COUNT) || (!data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Set auto program settings */
-    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
-    {
-        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramLastWord);
-    }
-
-    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
-
-    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + pageNum * (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT));
-    for (i = 0; i < (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT) / 4U; i++)
-    {
-        addr[i] = data[i];
-    }
-
-    if (base->AUTOPROG == kEEPROM_AutoProgramDisable)
-    {
-        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
-    }
-
-    /* Waiting for operation finished */
-    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
-    {}
-
-    return kStatus_Success;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,258 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_EEPROM_H_
-#define _FSL_EEPROM_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup eeprom
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief EEPROM driver version 2.0.0. */
-#define FSL_EEPROM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief EEPROM automatic program option */
-typedef enum _eeprom_auto_program
-{
-    kEEPROM_AutoProgramDisable = 0x0,   /*!< Disable auto program */
-    kEEPROM_AutoProgramWriteWord = 0x1, /*!< Auto program triggered after 1 word is written */
-    kEEPROM_AutoProgramLastWord = 0x2   /*!< Auto program triggered after last word of a page written */
-} eeprom_auto_program_t;
-
-/*! @brief EEPROM interrupt source */
-typedef enum _eeprom_interrupt_enable
-{
-    kEEPROM_ProgramFinishInterruptEnable = EEPROM_INTENSET_PROG_SET_EN_MASK, /*!< Interrupt while program finished */
-} eeprom_interrupt_enable_t;
-
-/*!
- * @brief EEPROM region configuration structure.
- */
-typedef struct _eeprom_config
-{
-    eeprom_auto_program_t autoProgram; /*!< Automatic program feature. */
-    uint8_t readWaitPhase1;            /*!< EEPROM read waiting phase 1 */
-    uint8_t readWaitPhase2;            /*!< EEPROM read waiting phase 2 */
-    uint8_t writeWaitPhase1;           /*!< EEPROM write waiting phase 1 */
-    uint8_t writeWaitPhase2;           /*!< EEPROM write waiting phase 2 */
-    uint8_t writeWaitPhase3;           /*!< EEPROM write waiting phase 3 */
-    bool lockTimingParam;              /*!< If lock the read and write wait phase settings */
-} eeprom_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes the EEPROM with the user configuration structure.
- *
- * This function configures the EEPROM module with the user-defined configuration. This function also sets the
- * internal clock frequency to about 155kHz according to the source clock frequency.
- *
- * @param base     EEPROM peripheral base address.
- * @param config   The pointer to the configuration structure.
- * @param sourceClock_Hz EEPROM source clock frequency in Hz.
- */
-void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz);
-
-/*!
- * @brief Get EEPROM default configure settings.
- *
- * @param config  EEPROM config structure pointer.
- */
-void EEPROM_GetDefaultConfig(eeprom_config_t *config);
-
-/*!
- * @brief Deinitializes the EEPROM regions.
- *
- * @param base     EEPROM peripheral base address.
- */
-void EEPROM_Deinit(EEPROM_Type *base);
-
-/* @}*/
-
-/*!
- * @name Basic Control Operations
- * @{
- */
-
-/*!
- * @brief Set EEPROM automatic program feature.
- *
- * EEPROM write always needs a program and erase cycle to write the data into EEPROM. This program and erase cycle can
- * be finished automaticlly or manually. If users want to use or disable auto program feature, users can call this API.
- *
- * @param base     EEPROM peripheral base address.
- * @param autoProgram EEPROM auto program feature need to set.
- */
-static inline void EEPROM_SetAutoProgram(EEPROM_Type *base, eeprom_auto_program_t autoProgram)
-{
-    base->AUTOPROG = autoProgram;
-}
-
-/*!
- * @brief Set EEPROM to in/out power down mode.
- *
- * This function make EEPROM eneter or out of power mode. Notice that, users shall not put EEPROM into power down mode
- * while there is still any pending EEPROM operation. While EEPROM is wakes up from power down mode, any EEPROM
- * operation has to be suspended for 100 us.
- *
- * @param base     EEPROM peripheral base address.
- * @param enable   True means enter to power down mode, false means wake up.
- */
-static inline void EEPROM_SetPowerDownMode(EEPROM_Type *base, bool enable)
-{
-    base->PWRDWN = enable;
-}
-
-/*!
- * @brief Enable EEPROM interrupt.
- *
- * @param base     EEPROM peripheral base address.
- * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
- *                 enumeration :: eeprom_interrupt_enable_t
- */
-static inline void EEPROM_EnableInterrupt(EEPROM_Type *base, uint32_t mask)
-{
-    base->INTENSET = mask;
-}
-
-/*!
- * @brief Disable EEPROM interrupt.
- *
- * @param base     EEPROM peripheral base address.
- * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
- *                 enumeration :: eeprom_interrupt_enable_t
- */
-static inline void EEPROM_DisableInterrupt(EEPROM_Type *base, uint32_t mask)
-{
-    base->INTENCLR = mask;
-}
-
-/*!
- * @brief Get the status of all interrupt flags for ERPROM.
- *
- * @param base     EEPROM peripheral base address.
- * @return EEPROM interrupt flag status
- */
-static inline uint32_t EEPROM_GetInterruptStatus(EEPROM_Type *base)
-{
-    return base->INTSTAT;
-}
-
-/*!
- * @brief Get the status of enabled interrupt flags for ERPROM.
- *
- * @param base     EEPROM peripheral base address.
- * @return EEPROM enabled interrupt flag status
- */
-static inline uint32_t EEPROM_GetEnabledInterruptStatus(EEPROM_Type *base)
-{
-    return base->INTEN;
-}
-
-/*!
- * @brief Set interrupt flags manually.
- *
- * This API trigger a interrupt manually, users can no need to wait for hardware trigger interrupt. Call this API will
- * set the corresponding bit in INSTAT register.
- *
- * @param base     EEPROM peripheral base address.
- * @param mask     EEPROM interrupt flag need to be set. It is a logic OR of members of
- *                 enumeration:: eeprom_interrupt_enable_t
- */
-static inline void EEPROM_SetInterruptFlag(EEPROM_Type *base, uint32_t mask)
-{
-    base->INTSTATSET = mask;
-}
-
-/*!
- * @brief Clear interrupt flags manually.
- *
- * This API clears interrupt flags manually. Call this API will clear the corresponding bit in INSTAT register.
- *
- * @param base     EEPROM peripheral base address.
- * @param mask     EEPROM interrupt flag need to be cleared. It is a logic OR of members of
- *                 enumeration:: eeprom_interrupt_enable_t
- */
-static inline void EEPROM_ClearInterruptFlag(EEPROM_Type *base, uint32_t mask)
-{
-    base->INTSTATCLR = mask;
-}
-
-/*!
- * @brief Write a word data in address of EEPROM.
- *
- * Users can write a page or at least a word data into EEPROM address.
- *
- * @param base     EEPROM peripheral base address.
- * @param offset   Offset from the begining address of EEPROM. This value shall be 4-byte aligned.
- * @param data     Data need be write.
- */
-status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data);
-
-/*!
- * @brief Write a page data into EEPROM.
- *
- * Users can write a page or at least a word data into EEPROM address.
- *
- * @param base     EEPROM peripheral base address.
- * @param pageNum  Page number to be written.
- * @param data     Data need be write. This array data size shall equals to the page size.
- */
-status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_EEPROM_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,380 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_emc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Define macros for EMC driver. */
-#define EMC_REFRESH_CLOCK_PARAM   (16U)
-#define EMC_SDRAM_WAIT_CYCLES  (2000U)
-#define EMC_DYNCTL_COLUMNBASE_OFFSET  (0U)
-#define EMC_DYNCTL_COLUMNBASE_MASK    (0x3U)
-#define EMC_DYNCTL_COLUMNPLUS_OFFSET  (3U)
-#define EMC_DYNCTL_COLUMNPLUS_MASK    (0x18U)
-#define EMC_DYNCTL_BUSWIDTH_MASK      (0x80U)
-#define EMC_DYNCTL_BUSADDRMAP_MASK    (0x20U)
-#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
-#define EMC_SDRAM_BANKCS_BA0_MASK   (uint32_t)(0x2000)
-#define EMC_SDRAM_BANKCS_BA1_MASK   (uint32_t)(0x4000)
-#define EMC_SDRAM_BANKCS_BA_MASK    (EMC_SDRAM_BANKCS_BA0_MASK|EMC_SDRAM_BANKCS_BA1_MASK)
-#define EMC_DIV_ROUND_UP(n, m)   ((n + m -1)/m)
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Get instance number for EMC module.
- *
- * @param base EMC peripheral base address
- */
-static uint32_t EMC_GetInstance(EMC_Type *base);
-
-/*!
- * @brief Get the clock cycles of EMC clock.
- * The function is used to calculate the multiple of the 
- * 16 EMCCLKs between the timer_Ns period.
- *
- * @param base EMC peripheral base address
- * @param timer_Ns The timer/period in unit of nanosecond
- * @param plus The plus added to the register settings to reach the calculated cycles.
- * @return The calculated cycles. 
- */
-static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);
-
-/*!
- * @brief Get the shift value to shift the mode register content by.
- *
- * @param addrMap EMC address map for the dynamic memory configuration. 
- *                It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.
- * @return The offset value to shift the mode register content by. 
- */
-static uint32_t EMC_ModeOffset(uint32_t addrMap);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Pointers to EMC clocks for each instance. */
-static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;
-
-/*! @brief Pointers to EMC bases for each instance. */
-static EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;
-
-/*! @brief Define the the start address for each chip controlled by EMC. */
-static uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static uint32_t EMC_GetInstance(EMC_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)
-    {
-        if (s_EMCBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_EMCBases));
-
-    return instance;
-}
-
-static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
-{
-    uint32_t cycles;
-
-    cycles = CLOCK_GetFreq(kCLOCK_EMC) / EMC_HZ_ONEMHZ * timer_Ns;
-    cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
-
-    /* Decrese according to the plus. */
-    if (cycles >= plus)
-    {
-        cycles = cycles - plus;
-    }
-    else
-    {
-        cycles = 0;
-    }
-    
-    return cycles;
-}
-
-static uint32_t EMC_ModeOffset(uint32_t addrMap)
-{
-    uint8_t offset = 0;
-    uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
-
-    /* First calculate the column length. */
-    if (columbase == 0x10)
-    {
-        offset = 8;
-    }
-    else
-    {
-        if (!columbase)
-        {
-            offset = 9;          
-        }
-        else
-        {
-            offset = 8;
-        }
-        /* Add column length increase check. */
-        if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1)
-        {
-            offset += 1;   
-        }
-        else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2)
-        {
-            offset += 2;
-        }
-        else
-        {
-            /* To avoid MISRA rule 14.10 error. */
-        }        
-    }
-
-    /* Add Buswidth/16. */
-    if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK)
-    {
-        offset += 2;
-    }
-    else
-    {
-        offset += 1;
-    }
-
-    /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
-    if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
-    {
-        if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
-        {
-          offset += 1; 
-        }
-        else
-        {
-          offset += 2;
-        }
-    }
-
-    return offset;
-}
-
-void EMC_Init(EMC_Type *base, emc_basic_config_t *config)
-{
-    /* Enable EMC clock. */
-    CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));
-
-    /* Reset the EMC. */
-    SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
-    SYSCON->PRESETCTRL[2] &= ~ SYSCON_PRESETCTRL_EMC_RESET_MASK;
-    
-    /* Set the EMC sytem configure. */
-    SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);
-
-    SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);
-
-    /* Set the endian mode. */
-    base->CONFIG = config->endian;
-    /* Enable the EMC module with normal memory map mode and normal work mode. */
-    base->CONTROL = EMC_CONTROL_E_MASK;
-}
-
-void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
-        emc_dynamic_chip_config_t *config, uint32_t totalChips)
-{
-    assert(config);
-    assert(timing);
-    assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);
-
-    uint32_t count;
-    uint8_t casLatency;
-    uint32_t addr;
-    uint32_t offset;
-    uint32_t data;
-    emc_dynamic_chip_config_t *dynamicConfig = config;
-
-    /* Setting for dynamic memory controller chip independent configuration. */
-    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
-    {
-        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG  = EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) |
-            EMC_ADDRMAP(dynamicConfig->devAddrMap);
-        /* Abstract CAS latency from the sdram mode reigster setting values. */
-        casLatency = (dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
-        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS  =  EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) |
-        EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
-        
-        dynamicConfig ++;
-    }
-
-    /* Configure the Dynamic Memory controller timing/latency for all chips. */
-    base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
-    base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
-    base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
-    base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
-    base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
-    base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
-    base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
-    base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
-    base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) &EMC_DYNAMICRFC_TRFC_MASK;
-    base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
-    base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
-    base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0)?timing->tMrd_Nclk - 1:0);
-
-    /* Initialize the SDRAM.*/ 
-    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
-    {
-    }
-    /* Step 2. issue nop command. */
-    base->DYNAMICCONTROL  = 0x00000183;
-    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
-    {
-    }
-    /* Step 3. issue precharge all command. */
-    base->DYNAMICCONTROL  = 0x00000103;
-
-    /* Step 4. issue two auto-refresh command. */
-    base->DYNAMICREFRESH = 2;
-    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES/2; count ++)
-    {
-    }
-
-    base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0)/EMC_REFRESH_CLOCK_PARAM;
-
-    /* Step 5. issue a mode command and set the mode value. */
-    base->DYNAMICCONTROL  = 0x00000083;
-
-    /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
-    dynamicConfig = config;
-    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
-    {
-        /* Get the shift value first. */
-        offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
-        addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | 
-            ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset));
-        /* Set the right mode setting value. */
-        data = *(volatile uint32_t *)addr;
-        data = data;
-        dynamicConfig ++;
-    }
-
-    if (config->dynamicDevice)
-    {
-        /* Add extended mode register if the low-power sdram is used. */
-        base->DYNAMICCONTROL  = 0x00000083;
-        /* Calculate the mode settings for extended mode register. */
-        dynamicConfig = config;
-        for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
-        {
-            /* Get the shift value first. */
-            offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
-            addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |
-                EMC_SDRAM_BANKCS_BA1_MASK) << offset));
-            /* Set the right mode setting value. */
-            data = *(volatile uint32_t *)addr;
-            data = data;
-            dynamicConfig ++;
-        }        
-    }
-
-    /* Step 6. issue normal operation command. */
-    base->DYNAMICCONTROL  = 0x00000000; /* Issue NORMAL command */
-
-    /* The buffer shall be disabled when do the sdram initialization and
-     * enabled after the initialization during normal opeation.
-     */
-    dynamicConfig = config;
-    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
-    {
-        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;        
-        dynamicConfig ++;
-    }
-}
-
-void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, 
-         emc_static_chip_config_t *config, uint32_t totalChips)
-{
-    assert(config);
-
-    uint32_t count;
-    emc_static_chip_config_t *staticConfig = config;
-
-    /* Initialize extended wait. */
-    if (extWait_Ns)
-    {   
-        for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
-        {
-            assert(staticConfig->specailConfig & kEMC_AsynchronosPageEnable);
-        }
-
-        base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);
-        staticConfig ++;
-    }
-
-    /* Initialize the static memory chip specific configure. */
-    staticConfig = config;
-    for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
-    {
-
-        base->STATIC[staticConfig->chipIndex].STATICCONFIG = 
-            (staticConfig->specailConfig | staticConfig->memWidth);
-        base->STATIC[staticConfig->chipIndex].STATICWAITWEN =
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);
-        base->STATIC[staticConfig->chipIndex].STATICWAITOEN = 
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);
-        base->STATIC[staticConfig->chipIndex].STATICWAITRD = 
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);
-        base->STATIC[staticConfig->chipIndex].STATICWAITPAGE = 
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);
-        base->STATIC[staticConfig->chipIndex].STATICWAITWR = 
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);
-        base->STATIC[staticConfig->chipIndex].STATICWAITTURN = 
-            EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);
-        
-        staticConfig ++;
-    }
-}   
-
-void EMC_Deinit(EMC_Type *base)
-{
-    /* Deinit the EMC. */
-    base->CONTROL &= ~EMC_CONTROL_E_MASK;
-
-    /* Disable EMC clock. */
-    CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,372 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_EMC_H_
-#define _FSL_EMC_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup emc
- * @{
- */
-
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief EMC driver version 2.0.0. */
-#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief Define the chip numbers for dynamic and static memory devices. */
-#define EMC_STATIC_MEMDEV_NUM        (4U)
-#define EMC_DYNAMIC_MEMDEV_NUM       (4U)
-#define EMC_ADDRMAP_SHIFT        EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
-#define EMC_ADDRMAP_MASK         (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK |EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
-#define EMC_ADDRMAP(x)    (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)     
-#define EMC_HZ_ONEMHZ   (1000000U)
-#define EMC_MILLISECS_ONESEC   (1000U)
-#define EMC_SDRAM_MODE_CL_SHIFT   (4U)
-#define EMC_SDRAM_MODE_CL_MASK   (0x70U)
-
-/*!
- * @brief Define EMC memory width for static memory device.
- */
-typedef enum _emc_static_memwidth
-{
-    kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */
-    kEMC_16BitWidth,       /*!< 16 bit memory width. */
-    kEMC_32BitWidth        /*!< 32 bit memory width. */
-} emc_static_memwidth_t;
-
-/*!
- * @brief Define EMC static configuration.
- */
-typedef enum _emc_static_special_config
-{ 
-    kEMC_AsynchronosPageEnable = 0x0008U,/*!< Enable the asynchronous page mode. page length four. */
-    kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */
-    kEMC_ByteLaneStateAllLow = 0x0080U,  /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */
-    kEMC_ExtWaitEnable = 0x0100U,        /*!< Extended wait enable. */
-    kEMC_BufferEnable = 0x80000U         /*!< Buffer enable. */
-} emc_static_special_config_t;
-
-/*! @brief EMC dynamic memory device. */
-typedef enum _emc_dynamic_device
-{
-    kEMC_Sdram = 0x0U,   /*!< Dynamic memory device: SDRAM. */
-    kEMC_Lpsdram,        /*!< Dynamic memory device: Low-power SDRAM. */
-} emc_dynamic_device_t;
-
-/*! @brief EMC dynamic read strategy. */
-typedef enum _emc_dynamic_read
-{
-    kEMC_NoDelay = 0x0U,        /*!< No delay. */ 
-    kEMC_Cmddelay,              /*!< Command delayed strategy, using EMCCLKDELAY. */
-    kEMC_CmdDelayPulseOneclk,   /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
-    kEMC_CmddelayPulsetwoclk,   /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
-} emc_dynamic_read_t;
-
-/*! @brief EMC endian mode. */
-typedef enum _emc_endian_mode
-{
-    kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */
-    kEMC_BigEndian,           /*!< Big endian mode. */
-} emc_endian_mode_t;
-
-/*! @brief EMC Feedback clock input source select. */
-typedef enum _emc_fbclk_src
-{
-    kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */
-    kEMC_EMCFbclkInput    /*!< Use the external EMC_FBCLK input. */
-} emc_fbclk_src_t;
-
-/*! @brief EMC dynamic timing/delay configure structure. */
-typedef struct _emc_dynamic_timing_config
-{
-    emc_dynamic_read_t readConfig;   /* Dynamic read strategy. */
-    uint32_t refreshPeriod_Nanosec;  /*!< The refresh period in unit of nanosecond. */
-    uint32_t tRp_Ns;      /*!< Precharge command period in unit of nanosecond. */
-    uint32_t tRas_Ns;     /*!< Active to precharge command period in unit of nanosecond. */
-    uint32_t tSrex_Ns;    /*!< Self-refresh exit time in unit of nanosecond. */
-    uint32_t tApr_Ns;     /*!< Last data out to active command time in unit of nanosecond. */
-    uint32_t tDal_Ns;     /*!< Data-in to active command in unit of nanosecond. */
-    uint32_t tWr_Ns;      /*!< Write recovery time in unit of nanosecond. */
-    uint32_t tRc_Ns;      /*!< Active to active command period in unit of nanosecond. */       
-    uint32_t tRfc_Ns;     /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
-    uint32_t tXsr_Ns;     /*!< Exit self-refresh to active command time in unit of nanosecond. */
-    uint32_t tRrd_Ns;     /*!< Active bank A to active bank B latency in unit of nanosecond. */
-    uint8_t tMrd_Nclk;     /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
-} emc_dynamic_timing_config_t;
-
-/*!
- * @brief EMC dynamic memory controller independent chip configuration structure.
- * Please take refer to the address mapping table in the RM in EMC chapter when you 
- * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
- * according to the bus width/banks/row/colum length for you device.
- * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7) 
- * and inset the bit 13 with 0.
- * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
- * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length. 
- * Set devAddrMap with 0x81.
- */
-typedef struct _emc_dynamic_chip_config
-{
-    uint8_t chipIndex;    /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
-    emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */
-    uint8_t rAS_Nclk;    /*!< Active to read/write delay tRCD. */
-    uint16_t sdramModeReg;   /*!< Sdram mode register setting. */
-    uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
-    uint8_t devAddrMap;  /*!< dynamic device address mapping, choose the address mapping for your specific device. */
-} emc_dynamic_chip_config_t;
-
-/*!
- * @brief EMC static memory controller independent chip configuration structure.
- */
-typedef struct _emc_static_chip_config
-{
-    uint8_t chipIndex;
-    emc_static_memwidth_t memWidth; /*!< Memory width. */
-    uint32_t specailConfig;     /*!< Static configuration,a logical OR of "emc_static_special_config_t". */
-    uint32_t tWaitWriteEn_Ns;/*!< The delay form chip select to write enable in unit of nanosecond. */
-    uint32_t tWaitOutEn_Ns;  /*!< The delay from chip selcet to output enable in unit of nanosecond. */
-    uint32_t tWaitReadNoPage_Ns;/*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */
-    uint32_t tWaitReadPage_Ns;  /*!< In page mode, the read after the first read wait states in unit of nanosecond. */ 
-    uint32_t tWaitWrite_Ns;     /*!< The delay from chip select to write access in unit of nanosecond. */
-    uint32_t tWaitTurn_Ns;      /*!< The Bus turn-around time in unit of nanosecond. */
-} emc_static_chip_config_t;
-
-/*!
- * @brief EMC module basic configuration structure.
- *
- * Defines the static memory controller configure structure and 
- * uses the EMC_Init() function to make necessary initializations.
- *
- */
-typedef struct _emc_basic_config
-{
-    emc_endian_mode_t endian;   /*!< Endian mode . */
-    emc_fbclk_src_t fbClkSrc;    /*!< The feedback clock source. */
-    uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
-} emc_basic_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name EMC Initialize and de-initialize opeartion
- * @{
- */
-/*!
- * @brief Initializes the basic for EMC.
- * This function ungates the EMC clock, initializes the emc system configure
- * and enable the EMC module. This function must be called in the first step to initialize
- * the external memory.
- *
- * @param base EMC peripheral base address.
- * @param config The EMC basic configuration.
- */
-void EMC_Init(EMC_Type *base, emc_basic_config_t *config);
-
-/*!
- * @brief Initializes the dynamic memory controller.
- * This function initializes the dynamic memory controller in external memory controller.
- * This function must be called after EMC_Init and before accessing the external dynamic memory.
- *
- * @param base EMC peripheral base address.
- * @param timing The timing and latency for dynamica memory controller setting. It shall
- *        be used for all dynamica memory chips, threfore the worst timing value for all
- *        used chips must be given.
- * @param configure The EMC dynamic memory controller chip independent configuration pointer.
- *       This configuration pointer is actually pointer to a configration array. the array number
- *       depends on the "totalChips".
- * @param totalChips The total dynamic memory chip numbers been used or the length of the 
- *        "emc_dynamic_chip_config_t" type memory.
- */
-void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
-        emc_dynamic_chip_config_t *config, uint32_t totalChips);
-
-/*!
- * @brief Initializes the static memory controller.
- * This function initializes the static memory controller in external memory controller.
- * This function must be called after EMC_Init and before accessing the external static memory.
- *
- * @param base EMC peripheral base address.
- * @param extWait_Ns The extended wait timeout or the read/write transfer time.
- *        This is common for all static memory chips and set with NULL if not required.
- * @param configure The EMC static memory controller chip independent configuration pointer.
- *       This configuration pointer is actually pointer to a configration array. the array number
- *       depends on the "totalChips".
- * @param totalChips The total static memory chip numbers been used or the length of the 
- *        "emc_static_chip_config_t" type memory.
- */
-void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);
-
-/*!
- * @brief Deinitializes the EMC module and gates the clock.
- * This function gates the EMC controller clock. As a result, the EMC
- * module doesn't work after calling this function.
- *
- * @param base EMC peripheral base address.
- */
-void EMC_Deinit(EMC_Type *base);
-
-/* @} */
-
-/*!
- * @name EMC Basic Operation
- * @{
- */
-
-/*!
- * @brief Enables/disables the EMC module.
- *
- * @param base EMC peripheral base address.
- * @param enable True enable EMC module, false disable.
- */
-static inline void EMC_Enable(EMC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CONTROL |= EMC_CONTROL_E_MASK;
-    }
-    else
-    {
-        base->CONTROL &= ~EMC_CONTROL_E_MASK;
-    }
-}
-
-/*!
- * @brief Enables/disables the EMC Dynaimc memory controller.
- *
- * @param base EMC peripheral base address.
- * @param enable True enable EMC dynamic memory controller, false disable.
- */
-static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
-    }
-    else
-    {
-        base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
-    }
-}
-
-/*!
- * @brief Enables/disables the EMC address mirror.
- * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0
- * and EMC_DYCS0 memory areas. Disable the address mirror enables
- * EMC_cS0 and EMC_DYCS0 memory to be accessed.
- *
- * @param base EMC peripheral base address.
- * @param enable True enable the address mirror, false disable the address mirror.
- */
-static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)
-{
-    if (enable) 
-    {
-        base->CONTROL |= EMC_CONTROL_M_MASK;
-    }
-    else 
-    {
-        base->CONTROL &= ~EMC_CONTROL_M_MASK;
-    }
-}
-
-/*!
- * @brief Enter the self-refresh mode for dynamic memory controller.
- * This function provided self-refresh mode enter or exit for application. 
- *
- * @param base EMC peripheral base address.
- * @param enable   True enter the self-refresh mode, false to exit self-refresh
- *                 and enter the normal mode.
- */
-static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;
-    }
-    else
-    {
-        base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;
-    }
-}
-
-/*!
- * @brief Get the operating mode of the EMC.
- * This function can be used to get the operating mode of the EMC. 
- *
- * @param base EMC peripheral base address.
- * @return The EMC in self-refresh mode if true, else in normal mode.
- */
-static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)
-{
-    return ((base->STATUS & EMC_STATUS_SA_MASK) ? true : false);
-}
-
-/*!
- * @brief Enter/exit the low-power mode.
- *
- * @param base EMC peripheral base address.
- * @param enable True Enter the low-power mode, false exit low-power mode
- *        and return to normal mode. 
- */
-static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CONTROL |= EMC_CONTROL_L_MASK;
-    }
-    else
-    {
-        base->CONTROL &= ~ EMC_CONTROL_L_MASK;
-    }
-}
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_EMC_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1810 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_enet.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief IPv4 PTP message IP version offset. */
-#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
-/*! @brief IPv4 PTP message UDP protocol offset. */
-#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U
-/*! @brief IPv4 PTP message UDP port offset. */
-#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U
-/*! @brief IPv4 PTP message UDP message type offset. */
-#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU
-/*! @brief IPv4 PTP message UDP version offset. */
-#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU
-/*! @brief IPv4 PTP message UDP clock id offset. */
-#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU
-/*! @brief IPv4 PTP message UDP sequence id offset. */
-#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U
-/*! @brief IPv4 PTP message UDP control offset. */
-#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU
-/*! @brief IPv6 PTP message UDP protocol offset. */
-#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U
-/*! @brief IPv6 PTP message UDP port offset. */
-#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U
-/*! @brief IPv6 PTP message UDP message type offset. */
-#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU
-/*! @brief IPv6 PTP message UDP version offset. */
-#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU
-/*! @brief IPv6 PTP message UDP clock id offset. */
-#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U
-/*! @brief IPv6 PTP message UDP sequence id offset. */
-#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU
-/*! @brief IPv6 PTP message UDP control offset. */
-#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU
-/*! @brief PTPv2 message Ethernet packet type offset. */
-#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU
-/*! @brief PTPv2 message Ethernet message type offset. */
-#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU
-/*! @brief PTPv2 message Ethernet version type offset. */
-#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU
-/*! @brief PTPv2 message Ethernet clock id offset. */
-#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22
-/*! @brief PTPv2 message Ethernet sequence id offset. */
-#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c
-/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */
-#define ENET_ETHERNETL2 0x88F7U
-/*! @brief Packet type IPv4. */
-#define ENET_IPV4 0x0800U
-/*! @brief Packet type IPv6. */
-#define ENET_IPV6 0x86ddU
-/*! @brief Packet type VLAN. */
-#define ENET_8021QVLAN 0x8100U
-/*! @brief UDP protocol type. */
-#define ENET_UDPVERSION 0x0011U
-/*! @brief Packet IP version IPv4. */
-#define ENET_IPV4VERSION 0x0004U
-/*! @brief Packet IP version IPv6. */
-#define ENET_IPV6VERSION 0x0006U
-
-/*! @brief Defines 10^9 nanosecond. */
-#define ENET_NANOSECS_ONESECOND (1000000000U)
-/*! @brief Defines 10^6 microsecond.*/
-#define ENET_MICRSECS_ONESECOND (1000000U)
-
-/*! @brief Rx buffer LSB ignore bits. */
-#define ENET_RXBUFF_IGNORELSB_BITS (2U)
-/*! @brief ENET FIFO size unit. */
-#define ENET_FIFOSIZE_UNIT (256U)
-/*! @brief ENET half-dulpex default IPG. */
-#define ENET_HALFDUPLEX_DEFAULTIPG (4U)
-/*! @breif ENET miminum ring length. */
-#define ENET_MIN_RINGLEN (4U)
-/*! @breif ENET wakeup filter numbers. */
-#define ENET_WAKEUPFILTER_NUM (8U)
-/*! @breif Requried systime timer frequency. */
-#define ENET_SYSTIME_REQUIRED_CLK_MHZ (50U)
-/*! @brief Ethernet VLAN tag length. */
-#define ENET_FRAME_VLAN_TAGLEN 4U
-
-/*! @brief AVB TYPE */
-#define ENET_AVBTYPE 0x22F0U
-#define ENET_HEAD_TYPE_OFFSET (12)
-#define ENET_HEAD_AVBTYPE_OFFSET (16)
-
-/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
-#define ENET_HTONS(n) __REV16(n)
-#define ENET_HTONL(n) __REV(n)
-#define ENET_NTOHS(n) __REV16(n)
-#define ENET_NTOHL(n) __REV(n)
-
-/* Typedef for interrupt handler. */
-typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get the ENET instance from peripheral base address.
- *
- * @param base ENET peripheral base address.
- * @return ENET instance.
- */
-uint32_t ENET_GetInstance(ENET_Type *base);
-
-/*!
- * @brief Increase the index in the ring.
- *
- * @param index The current index.
- * @param max The size.
- * @return the increased index.
- */
-static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max);
-
-/*!
- * @brief Set ENET system configuration.
- *  This function reset the ethernet module and set the phy selection.
- *  It should be called before any other ethernet operation.
- *
- * @param miiMode  The MII/RMII mode for interface between the phy and ethernet.
- */
-static void ENET_SetSYSControl(enet_mii_mode_t miiMode);
-
-/*!
- * @brief Set ENET DMA controller with the configuration.
- *
- * @param base ENET peripheral base address.
- * @param config ENET Mac configuration.
- */
-static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config);
-
-/*!
- * @brief Set ENET MAC controller with the configuration.
- *
- * @param base ENET peripheral base address.
- * @param config ENET Mac configuration.
- * @param macAddr ENET six-byte mac address.
- */
-static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr);
-/*!
- * @brief Set ENET MTL with the configuration.
- *
- * @param base ENET peripheral base address.
- * @param config ENET Mac configuration.
- */
-static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config);
-
-/*!
- * @brief Set ENET DMA transmit buffer descriptors for one channel.
- *
- * @param base ENET peripheral base address.
- * @param bufferConfig ENET buffer configuration.
- * @param intTxEnable tx interrupt enable.
- * @param channel The channel number, 0 , 1.
- */
-static status_t ENET_TxDescriptorsInit(ENET_Type *base,
-                                       const enet_buffer_config_t *bufferConfig,
-                                       bool intTxEnable,
-                                       uint8_t channel);
-
-/*!
- * @brief Set ENET DMA receive buffer descriptors for one channel.
- *
- * @param base ENET peripheral base address.
- * @param bufferConfig ENET buffer configuration.
- * @param intRxEnable tx interrupt enable.
- * @param channel The channel number, 0 , 1.
- * @param doubleBuffEnable Two buffers are enabled.
- */
-static status_t ENET_RxDescriptorsInit(ENET_Type *base,
-                                       const enet_buffer_config_t *bufferConfig,
-                                       bool intRxEnable,
-                                       uint8_t channel,
-                                       bool doubleBuffEnable);
-
-/*!
- * @brief Set ENET get transmit ring descriptors.
- *
- * @param data The ENET data to be transfered.
- * @param handle ENET handler.
- */
-static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle);
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-/*!
- * @brief Sets the ENET 1588 feature.
- *
- * Enable the enhacement 1588 buffer descriptor mode and start
- * the 1588 timer.
- *
- * @param base ENET peripheral base address.
- * @param config The ENET configuration.
- * @param refClk_Hz The reference clock for ptp 1588.
- */
-static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz);
-
-/*!
- * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame.
- *
- * @param data  The ENET read data for frame parse.
- * @param ptpTsData The ENET PTP message and time-stamp data pointer.
- * @param isFastEnabled The fast parse flag.
- *        - true , Fast processing, only check if this is a PTP message.
- *        - false, Store the PTP message data after check the PTP message.
- */
-static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled);
-
-/*!
- * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring.
- *
- * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
- * @param ptpTimeData   The new PTP 1588 time-stamp data pointer.
- */
-static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData);
-
-/*!
- * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring.
- *
- * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
- * @param ptpTimeData   The find out right PTP 1588 time-stamp data pointer with the specific PTP message.
- */
-static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata);
-
-/*!
- * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring.
- *
- * @param base   ENET peripheral base address.
- * @param handle ENET handler.
- * @param rxDesc The ENET receive descriptor pointer.
- * @param channel The rx channel.
- * @param ptpTimeData The PTP 1588 time-stamp data pointer.
- */
-static status_t ENET_StoreRxFrameTime(ENET_Type *base,
-                                      enet_handle_t *handle,
-                                      enet_rx_bd_struct_t *rxDesc,
-                                      uint8_t channel,
-                                      enet_ptp_time_data_t *ptpTimeData);
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Pointers to enet handles for each instance. */
-static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_LPC_ENET_COUNT] = {NULL};
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to enet clocks for each instance. */
-const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT] = ETH_CLOCKS;
-#endif /*  FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to enet bases for each instance. */
-static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
-
-/*! @brief Pointers to enet IRQ number for each instance. */
-static const IRQn_Type s_enetIrqId[] = ENET_IRQS;
-
-/* ENET ISR for transactional APIs. */
-static enet_isr_t s_enetIsr;
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max)
-{
-    /* Increase the index. */
-    index++;
-    if (index >= max)
-    {
-        index = 0;
-    }
-    return index;
-}
-
-static void ENET_SetSYSControl(enet_mii_mode_t miiMode)
-{
-    /* Reset first. */
-    SYSCON->PRESETCTRL[2] = SYSCON_PRESETCTRL_ETH_RST_MASK;
-    SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_ETH_RST_MASK;
-    /* Set MII/RMII before the peripheral ethernet dma reset. */
-    SYSCON->ETHPHYSEL = (SYSCON->ETHPHYSEL & ~SYSCON_ETHPHYSEL_PHY_SEL_MASK) | SYSCON_ETHPHYSEL_PHY_SEL(miiMode);
-}
-
-static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config)
-{
-    assert(config);
-
-    uint8_t index;
-    uint32_t reg;
-    uint32_t burstLen;
-
-    /* Reset first and wait for the complete
-     * The reset bit will automatically be cleared after complete. */
-    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
-    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
-    {
-    }
-
-    /* Set the burst length. */
-    for (index = 0; index < ENET_RING_NUM_MAX; index++)
-    {
-        burstLen = kENET_BurstLen1;
-        if (config->multiqueueCfg)
-        {
-            burstLen = config->multiqueueCfg->burstLen;
-        }
-        base->DMA_CH[index].DMA_CHX_CTRL = burstLen & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK;
-
-        reg = base->DMA_CH[index].DMA_CHX_TX_CTRL & ~ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK;
-        base->DMA_CH[index].DMA_CHX_TX_CTRL = reg | ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(burstLen & 0x3F);
-
-        reg = base->DMA_CH[index].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK;
-        base->DMA_CH[index].DMA_CHX_RX_CTRL = reg | ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(burstLen & 0x3F);
-    }
-}
-
-static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config)
-{
-    assert(config);
-
-    uint32_t txqOpreg = 0;
-    uint32_t rxqOpReg = 0;
-    enet_multiqueue_config_t *multiqCfg = config->multiqueueCfg;
-    uint8_t index;
-
-    /* Set transmit operation mode. */
-    if (config->specialControl & kENET_StoreAndForward)
-    {
-        txqOpreg = ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK;
-        rxqOpReg = ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK;
-    }
-    txqOpreg |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK |
-                ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(ENET_MTL_TXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
-    base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = txqOpreg | ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
-    base->MTL_QUEUE[1].MTL_TXQX_OP_MODE = txqOpreg;
-
-    /* Set receive operation mode. */
-    rxqOpReg |= ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK |
-                ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(ENET_MTL_RXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
-    base->MTL_QUEUE[0].MTL_RXQX_OP_MODE = rxqOpReg;
-
-    /* Set the schedule/arbitration(set for multiple queues). */
-    if (multiqCfg)
-    {
-        base->MTL_OP_MODE = ENET_MTL_OP_MODE_SCHALG(multiqCfg->mtltxSche) | ENET_MTL_OP_MODE_RAA(multiqCfg->mtlrxSche);
-        /* Set the rx queue mapping to dma channel. */
-        base->MTL_RXQ_DMA_MAP = multiqCfg->mtlrxQuemap;
-        /* Set the tx/rx queue operation mode for multi-queue. */
-        base->MTL_QUEUE[1].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
-        base->MTL_QUEUE[1].MTL_RXQX_OP_MODE = rxqOpReg;
-
-        /* Set the tx/rx queue weight. */
-        for (index = 0; index < ENET_RING_NUM_MAX; index++)
-        {
-            base->MTL_QUEUE[index].MTL_TXQX_QNTM_WGHT = multiqCfg->txqueweight[index];
-            base->MTL_QUEUE[index].MTL_RXQX_CTRL = ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(multiqCfg->rxqueweight[index]);
-        }
-    }
-}
-
-static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr)
-{
-    assert(config);
-
-    uint32_t reg = 0;
-
-    /* Set Macaddr */
-    /* The dma channel 0 is set as to which the rx packet
-     * whose DA matches the MAC address content is routed. */
-    if (macAddr)
-    {
-        ENET_SetMacAddr(base, macAddr);
-    }
-
-    /* Set the receive filter. */
-    reg = ENET_MAC_FRAME_FILTER_PR(!!(config->specialControl & kENET_PromiscuousEnable)) |
-          ENET_MAC_FRAME_FILTER_DBF(!!(config->specialControl & kENET_BroadCastRxDisable)) |
-          ENET_MAC_FRAME_FILTER_PM(!!(config->specialControl & kENET_MulticastAllEnable));
-    base->MAC_FRAME_FILTER = reg;
-    /* Flow control. */
-    if (config->specialControl & kENET_FlowControlEnable)
-    {
-        base->MAC_RX_FLOW_CTRL = ENET_MAC_RX_FLOW_CTRL_RFE_MASK | ENET_MAC_RX_FLOW_CTRL_UP_MASK;
-        base->MAC_TX_FLOW_CTRL_Q[0] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
-        base->MAC_TX_FLOW_CTRL_Q[1] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
-    }
-
-    /* Set the 1us ticket. */
-    reg = CLOCK_GetFreq(kCLOCK_CoreSysClk) / ENET_MICRSECS_ONESECOND - 1;
-    base->MAC_1US_TIC_COUNTR = ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(reg);
-
-    /* Set the speed and duplex. */
-    reg = ENET_MAC_CONFIG_ECRSFD_MASK | ENET_MAC_CONFIG_PS_MASK | ENET_MAC_CONFIG_DM(config->miiDuplex) |
-          ENET_MAC_CONFIG_FES(config->miiSpeed) |
-          ENET_MAC_CONFIG_S2KP(!!(config->specialControl & kENET_8023AS2KPacket));
-    if (config->miiDuplex == kENET_MiiHalfDuplex)
-    {
-        reg |= ENET_MAC_CONFIG_IPG(ENET_HALFDUPLEX_DEFAULTIPG);
-    }
-    base->MAC_CONFIG = reg;
-
-    /* Enable channel. */
-    base->MAC_RXQ_CTRL[0] = ENET_MAC_RXQ_CTRL_RXQ0EN(1) | ENET_MAC_RXQ_CTRL_RXQ1EN(1);
-}
-
-static status_t ENET_TxDescriptorsInit(ENET_Type *base,
-                                       const enet_buffer_config_t *bufferConfig,
-                                       bool intTxEnable,
-                                       uint8_t channel)
-{
-    uint16_t j;
-    enet_tx_bd_struct_t *txbdPtr;
-    uint32_t control = intTxEnable ? ENET_TXDESCRIP_RD_IOC_MASK : 0;
-    const enet_buffer_config_t *buffCfg = bufferConfig;
-
-    if (!buffCfg)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Check the ring length. */
-    if (buffCfg->txRingLen < ENET_MIN_RINGLEN)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* Set the tx descriptor start/tail pointer, shall be word aligned. */
-    base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR =
-        (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
-    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR =
-        (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
-    /* Set the tx ring length. */
-    base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH =
-        (uint16_t)(buffCfg->txRingLen - 1) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;
-
-    /* Init the txbdPtr to the transmit descriptor start address. */
-    txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign);
-    for (j = 0; j < buffCfg->txRingLen; j++)
-    {
-        txbdPtr->buff1Addr = 0;
-        txbdPtr->buff2Addr = 0;
-        txbdPtr->buffLen = control;
-        txbdPtr->controlStat = 0;
-        txbdPtr++;
-    }
-
-    return kStatus_Success;
-}
-
-static status_t ENET_RxDescriptorsInit(
-    ENET_Type *base, const enet_buffer_config_t *bufferConfig, bool intRxEnable, uint8_t channel, bool doubleBuffEnable)
-{
-    uint16_t j;
-    uint32_t reg;
-    enet_rx_bd_struct_t *rxbdPtr;
-    uint16_t index;
-    const enet_buffer_config_t *buffCfg = bufferConfig;
-    uint32_t control = ENET_RXDESCRIP_WR_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
-
-    if (!buffCfg)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    if (intRxEnable)
-    {
-        control |= ENET_RXDESCRIP_RD_IOC_MASK;
-    }
-
-    if (doubleBuffEnable)
-    {
-        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
-    }
-
-    /* Check the ring length. */
-    if (buffCfg->rxRingLen < ENET_MIN_RINGLEN)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Set the rx descriptor start/tail pointer, shall be word aligned. */
-    base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR =
-        (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
-    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR =
-        (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
-    base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH =
-        (uint16_t)(buffCfg->rxRingLen - 1) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK;
-    reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK;
-    reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS);
-    base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg;
-
-    /* Init the rxbdPtr to the receive descriptor start address. */
-    rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign);
-
-    for (j = 0; j < buffCfg->rxRingLen; j++)
-    {
-        if (doubleBuffEnable)
-        {
-            index = 2 * j;
-        }
-        else
-        {
-            index = j;
-        }
-        rxbdPtr->buff1Addr = *(buffCfg->rxBufferStartAddr + index);
-        /* The second buffer is set with 0 because it is not required for normal case. */
-        if (doubleBuffEnable)
-        {
-            rxbdPtr->buff2Addr = *(buffCfg->rxBufferStartAddr + index + 1);
-        }
-        else
-        {
-            rxbdPtr->buff2Addr = 0;
-        }
-
-        /* Set the valid and DMA own flag.*/
-        rxbdPtr->control = control;
-        rxbdPtr++;
-    }
-
-    return kStatus_Success;
-}
-
-static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle)
-{
-    /* Defuault use the queue/ring 0. */
-    uint8_t ringId = 0;
-
-    if (handle->multiQueEnable)
-    {
-        /* Parse the frame and choose the queue id for different avb frames
-         *  AVB Class frame in queue 1.
-         *  non-AVB frame in queue 0.
-         */
-        if ((*(uint16_t *)(data + ENET_HEAD_TYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) &&
-            ((*(uint16_t *)(data + ENET_HEAD_AVBTYPE_OFFSET)) == ENET_HTONS(ENET_AVBTYPE)))
-        {
-            /* AVBTP stream data frame. */
-            ringId = 1;
-        }
-    }
-
-    return ringId;
-}
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz)
-{
-    assert(config);
-    assert(config->ptpConfig);
-    assert(refClk_Hz);
-
-    uint32_t control;
-    enet_ptp_config_t *ptpConfig = config->ptpConfig;
-
-    /* Clear the timestamp interrupt first. */
-    base->MAC_INTR_EN &= ~ENET_MAC_INTR_EN_TSIE_MASK;
-
-    if (ptpConfig->fineUpdateEnable)
-    {
-        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK;
-        /* Set the initial added value for the fine update. */
-        control = 100000000U / (refClk_Hz / ENET_MICRSECS_ONESECOND / ENET_SYSTIME_REQUIRED_CLK_MHZ);
-        base->MAC_SYS_TIMESTMP_ADDEND = control;
-        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
-        while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
-        {
-        }
-    }
-
-    /* Enable the IEEE 1588 timestamping and snapshot for event message. */
-    control = ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK |
-              ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK |
-              ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK | ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK |
-              ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(ptpConfig->tsRollover);
-
-    if (ptpConfig->ptp1588V2Enable)
-    {
-        control |= ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK;
-    }
-
-    /* Initialize the sub-second increment register. */
-    if (ptpConfig->tsRollover)
-    {
-        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(ENET_NANOSECS_ONESECOND / refClk_Hz);
-        base->MAC_SYS_TIME_NSCND_UPD = 0;
-    }
-    else
-    {
-        /* round up. */
-        uint32_t data = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK / refClk_Hz;
-        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(data);
-        base->MAC_SYS_TIME_NSCND_UPD = 0;
-    }
-    /* Set the second.*/
-    base->MAC_SYS_TIME_SCND_UPD = 0;
-    base->MAC_SYS_TIME_HWORD_SCND = 0;
-
-    /* Initialize the system timer. */
-    base->MAC_TIMESTAMP_CTRL = control | ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK;
-}
-
-static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled)
-{
-    assert(data);
-    if (!isFastEnabled)
-    {
-        assert(ptpTsData);
-    }
-
-    bool isPtpMsg = false;
-    uint8_t *buffer = data;
-    uint16_t ptpType;
-
-    /* Check for VLAN frame. */
-    if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN))
-    {
-        buffer += ENET_FRAME_VLAN_TAGLEN;
-    }
-
-    ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET);
-    switch (ENET_HTONS(ptpType))
-    { /* Ethernet layer 2. */
-        case ENET_ETHERNETL2:
-            if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType)
-            {
-                isPtpMsg = true;
-                if (!isFastEnabled)
-                {
-                    /* It's a ptpv2 message and store the ptp header information. */
-                    ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F;
-                    ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F;
-                    ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET));
-                    memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET),
-                           kENET_PtpSrcPortIdLen);
-                }
-            }
-            break;
-        /* IPV4. */
-        case ENET_IPV4:
-            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION)
-            {
-                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
-                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
-                {
-                    /* Set the PTP message flag. */
-                    isPtpMsg = true;
-                    if (!isFastEnabled)
-                    {
-                        /* It's a IPV4 ptp message and store the ptp header information. */
-                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F;
-                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F;
-                        ptpTsData->sequenceId =
-                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET));
-                        memcpy((void *)&ptpTsData->sourcePortId[0],
-                               (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
-                    }
-                }
-            }
-            break;
-        /* IPV6. */
-        case ENET_IPV6:
-            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION)
-            {
-                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
-                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
-                {
-                    /* Set the PTP message flag. */
-                    isPtpMsg = true;
-                    if (!isFastEnabled)
-                    {
-                        /* It's a IPV6 ptp message and store the ptp header information. */
-                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F;
-                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F;
-                        ptpTsData->sequenceId =
-                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET));
-                        memcpy((void *)&ptpTsData->sourcePortId[0],
-                               (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
-                    }
-                }
-            }
-            break;
-        default:
-            break;
-    }
-    return isPtpMsg;
-}
-
-static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData)
-{
-    assert(ptpTsDataRing);
-    assert(ptpTsDataRing->ptpTsData);
-    assert(ptpTimeData);
-
-    uint16_t usedBuffer = 0;
-
-    /* Check if the buffers ring is full. */
-    if (ptpTsDataRing->end >= ptpTsDataRing->front)
-    {
-        usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
-    }
-    else
-    {
-        usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
-    }
-
-    if (usedBuffer == ptpTsDataRing->size)
-    {
-        return kStatus_ENET_PtpTsRingFull;
-    }
-
-    /* Copy the new data into the buffer. */
-    memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t));
-
-    /* Increase the buffer pointer to the next empty one. */
-    ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size;
-
-    return kStatus_Success;
-}
-
-static status_t ENET_StoreRxFrameTime(ENET_Type *base,
-                                      enet_handle_t *handle,
-                                      enet_rx_bd_struct_t *rxDesc,
-                                      uint8_t channel,
-                                      enet_ptp_time_data_t *ptpTimeData)
-{
-    assert(ptpTimeData);
-
-    uint32_t nanosecond;
-    uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
-
-    /* Get transmit time stamp second. */
-    nanosecond = rxDesc->reserved | rxDesc->buff1Addr;
-    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
-    {
-        /* Binary rollover. */
-        nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
-    }
-    ptpTimeData->timeStamp.second = nanosecond / nanoOverSize;
-    ptpTimeData->timeStamp.nanosecond = nanosecond % nanoOverSize;
-
-    /* Store the timestamp to the receive time stamp ring. */
-    /* Check if the buffers ring is full. */
-    return ENET_Ptp1588UpdateTimeRing(&handle->rxBdRing[channel].rxPtpTsDataRing, ptpTimeData);
-}
-
-static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata)
-{
-    assert(ptpTsDataRing);
-    assert(ptpTsDataRing->ptpTsData);
-    assert(ptpTimedata);
-
-    uint32_t index;
-    uint32_t size;
-    uint16_t usedBuffer = 0;
-
-    /* Check the PTP 1588 timestamp ring. */
-    if (ptpTsDataRing->front == ptpTsDataRing->end)
-    {
-        return kStatus_ENET_PtpTsRingEmpty;
-    }
-
-    /* Search the element in the ring buffer */
-    index = ptpTsDataRing->front;
-    size = ptpTsDataRing->size;
-    while (index != ptpTsDataRing->end)
-    {
-        if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) &&
-            (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]),
-                     (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) &&
-            ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) &&
-            ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType))
-        {
-            break;
-        }
-
-        /* Increase the ptp ring index. */
-        index = (index + 1) % size;
-    }
-
-    if (index == ptpTsDataRing->end)
-    {
-        /* Check if buffers is full. */
-        if (ptpTsDataRing->end >= ptpTsDataRing->front)
-        {
-            usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
-        }
-        else
-        {
-            usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
-        }
-
-        if (usedBuffer == ptpTsDataRing->size)
-        { /* Drop one in the front. */
-            ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
-        }
-        return kStatus_ENET_PtpTsRingFull;
-    }
-
-    /* Get the right timestamp of the required ptp messag. */
-    ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second;
-    ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond;
-
-    /* Increase the index. */
-    ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
-
-    return kStatus_Success;
-}
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-uint32_t ENET_GetInstance(ENET_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++)
-    {
-        if (s_enetBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < FSL_FEATURE_SOC_LPC_ENET_COUNT);
-
-    return instance;
-}
-
-void ENET_GetDefaultConfig(enet_config_t *config)
-{
-    /* Checks input parameter. */
-    assert(config);
-
-    /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */
-    config->miiMode = kENET_RmiiMode;
-    config->miiSpeed = kENET_MiiSpeed100M;
-    config->miiDuplex = kENET_MiiFullDuplex;
-
-    /* Sets default configuration for other options. */
-    config->specialControl = false;
-    config->multiqueueCfg = NULL;
-    config->pauseDuration = 0;
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    config->ptpConfig = NULL;
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-}
-
-void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz)
-{
-    assert(config);
-
-    uint32_t instance = ENET_GetInstance(base);
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate ENET clock. */
-    CLOCK_EnableClock(s_enetClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    /* System configure fistly. */
-    ENET_SetSYSControl(config->miiMode);
-
-    /* Initializes the ENET DMA with basic function. */
-    ENET_SetDMAControl(base, config);
-
-    /* Initializes the ENET MTL with basic function. */
-    ENET_SetMTL(base, config);
-
-    /* Initializes the ENET MAC with basic function. */
-    ENET_SetMacControl(base, config, macAddr);
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    ENET_SetPtp1588(base, config, refclkSrc_Hz);
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-}
-
-void ENET_Deinit(ENET_Type *base)
-{
-    /* Reset first and wait for the complete
-     * The reset bit will automatically be cleared after complete. */
-    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
-    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
-    {
-    }
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disables the clock source. */
-    CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig)
-{
-    assert(config);
-    assert(bufferConfig);
-
-    bool intTxEnable;
-    bool intRxEnable;
-    bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false;
-    uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2;
-    uint8_t channel;
-
-    for (channel = 0; channel < ringNum; channel++)
-    {
-        intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false;
-
-        if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success)
-        {
-            return kStatus_Fail;
-        }
-        intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false;
-
-        if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success)
-        {
-            return kStatus_Fail;
-        }
-
-        bufferConfig++;
-        if (!bufferConfig)
-        {
-            return kStatus_InvalidArgument;
-        }
-    }
-    return kStatus_Success;
-}
-
-void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum)
-{
-    assert(txRingNum);
-    assert(rxRingNum);
-
-    uint8_t index;
-
-    if (txRingNum > ENET_RING_NUM_MAX)
-    {
-        txRingNum = ENET_RING_NUM_MAX;
-    }
-    if (rxRingNum > ENET_RING_NUM_MAX)
-    {
-        rxRingNum = ENET_RING_NUM_MAX;
-    }
-    /* Start/Acive the DMA first. */
-    for (index = 0; index < rxRingNum; index++)
-    {
-        base->DMA_CH[index].DMA_CHX_RX_CTRL |= ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK;
-    }
-    for (index = 0; index < txRingNum; index++)
-    {
-        base->DMA_CH[index].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
-    }
-
-    /* Enable the RX/TX then. */
-    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
-    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
-}
-
-void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
-{
-    uint32_t interrupt = mask & 0xFFFFU;
-    uint8_t index;
-
-    /* For dma interrupt. */
-    if (interrupt)
-    {
-        for (index = 0; index < ENET_RING_NUM_MAX; index++)
-        {
-            /* Set for all abnormal interrupts. */
-            if (ENET_ABNORM_INT_MASK & interrupt)
-            {
-                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
-            }
-            /* Set for all normal interrupts. */
-            if (ENET_NORM_INT_MASK & interrupt)
-            {
-                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
-            }
-            base->DMA_CH[index].DMA_CHX_INT_EN = interrupt;
-        }
-    }
-    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
-    if (interrupt)
-    {
-        /* MAC interrupt */
-        base->MAC_INTR_EN |= interrupt;
-    }
-}
-
-void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask)
-{
-    volatile uint32_t dummy;
-
-    if (mask & kENET_MacTimestamp)
-    {
-       dummy = base->MAC_SYS_TIMESTMP_STAT;
-    }
-    else if (mask & kENET_MacPmt)
-    {
-       dummy = base->MAC_PMT_CRTL_STAT;
-    }
-    else
-    {
-        /* Add for avoid the misra 2004 rule 14.10 */
-    }
-    (void)dummy;
-}
-
-void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
-{
-    uint32_t interrupt = mask & 0xFFFFU;
-    uint8_t index;
-
-    /* For dma interrupt. */
-    if (interrupt)
-    {
-        for (index = 0; index < ENET_RING_NUM_MAX; index++)
-        {
-            /* Set for all abnormal interrupts. */
-            if (ENET_ABNORM_INT_MASK & interrupt)
-            {
-                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
-            }
-            /* Set for all normal interrupts. */
-            if (ENET_NORM_INT_MASK & interrupt)
-            {
-                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
-            }
-            base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt;
-        }
-    }
-    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
-    if (interrupt)
-    {
-        /* MAC interrupt */
-        base->MAC_INTR_EN &= ~interrupt;
-    }
-}
-
-void ENET_CreateHandler(ENET_Type *base,
-                        enet_handle_t *handle,
-                        enet_config_t *config,
-                        enet_buffer_config_t *bufferConfig,
-                        enet_callback_t callback,
-                        void *userData)
-{
-    assert(config);
-    assert(bufferConfig);
-    assert(callback);
-
-    uint8_t ringNum = 1;
-    uint8_t count = 0;
-    uint8_t rxIntEnable = 0;
-    enet_buffer_config_t *buffConfig = bufferConfig;
-
-    if (config->multiqueueCfg)
-    {
-        ringNum = 2;
-        handle->multiQueEnable = true;
-    }
-
-    /* Store transfer parameters in handle pointer. */
-    memset(handle, 0, sizeof(enet_handle_t));
-    if (config->specialControl & kENET_DescDoubleBuffer)
-    {
-        handle->doubleBuffEnable = true;
-    }
-    if (config->multiqueueCfg)
-    {
-        handle->multiQueEnable = true;
-    }
-    for (count = 0; count < ringNum; count++)
-    {
-        handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign;
-        handle->rxBdRing[count].rxGenIdx = 0;
-        handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen;
-        handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign;
-
-        handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign;
-        handle->txBdRing[count].txRingLen = buffConfig->txRingLen;
-        handle->txBdRing[count].txGenIdx = 0;
-        handle->txBdRing[count].txConsumIdx = 0;
-        handle->txBdRing[count].txDescUsed = 0;
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-        assert(bufferConfig->rxPtpTsData);
-        assert(bufferConfig->txPtpTsData);
-        assert(buffConfig->rxRingLen <= ENET_RXBUFFSTORE_NUM);
-
-        uint32_t index;
-
-        handle->rxBdRing[count].rxPtpTsDataRing.ptpTsData = buffConfig->rxPtpTsData;
-        handle->rxBdRing[count].rxPtpTsDataRing.front = 0;
-        handle->rxBdRing[count].rxPtpTsDataRing.end = 0;
-        handle->rxBdRing[count].rxPtpTsDataRing.size = buffConfig->ptpTsRxBuffNum;
-        handle->txBdRing[count].txPtpTsDataRing.ptpTsData = buffConfig->txPtpTsData;
-        handle->txBdRing[count].txPtpTsDataRing.front = 0;
-        handle->txBdRing[count].txPtpTsDataRing.end = 0;
-        handle->txBdRing[count].txPtpTsDataRing.size = buffConfig->ptpTsTxBuffNum;
-
-        for (index = 0; index < buffConfig->rxRingLen; index++)
-        {
-            handle->rxbuffers[index] = *(buffConfig->rxBufferStartAddr + index);
-        }
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-        /* Enable tx interrupt for use transactional API to do tx buffer free/requeue. */
-        base->DMA_CH[count].DMA_CHX_INT_EN |= ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
-        /* Check if the rx interrrupt is enabled. */
-        rxIntEnable |= (base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK);
-        buffConfig++;
-    }
-
-    handle->rxintEnable = rxIntEnable ? true : false;
-
-    /* Save the handle pointer in the global variables. */
-    s_ENETHandle[ENET_GetInstance(base)] = handle;
-
-    /* Set callback and userData. */
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* Enable the NVIC for tx. */
-    s_enetIsr = ENET_IRQHandler;
-    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
-}
-
-void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
-{
-    assert(macAddr);
-
-    uint32_t address = base->MAC_ADDR_LOW;
-
-    /* Get from physical address lower register. */
-    macAddr[2] = 0xFFU & (address >> 24U);
-    macAddr[3] = 0xFFU & (address >> 16U);
-    macAddr[4] = 0xFFU & (address >> 8U);
-    macAddr[5] = 0xFFU & address;
-
-    /* Get from physical address high register. */
-    address = base->MAC_ADDR_HIGH;
-    macAddr[0] = 0xFFU & (address >> 8U);
-    macAddr[1] = 0xFFU & address;
-}
-
-void ENET_SetSMI(ENET_Type *base)
-{
-    uint32_t crDiv;
-    uint32_t srcClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000000U;
-
-    if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35))
-    {
-        crDiv = 2;
-    }
-    else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60))
-    {
-        crDiv = 3;
-    }
-    else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150))
-    {
-        crDiv = 1;
-    }
-    else
-    {
-        crDiv = 0;
-    }
-
-    base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv);
-}
-
-void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
-{
-    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
-
-    /* Build MII write command. */
-    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiWriteFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
-                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
-    base->MAC_MDIO_DATA = data;
-    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
-}
-
-void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
-{
-    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
-
-    /* Build MII read command. */
-    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiReadFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
-                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
-    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
-}
-
-void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter)
-{
-    uint8_t index;
-    uint32_t *reg = wakeFilter;
-
-    /* Disable the tx dma. */
-    base->DMA_CH[0].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
-    base->DMA_CH[1].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
-
-    /* Disable the mac tx/rx. */
-    base->MAC_CONFIG &= ~(ENET_MAC_CONFIG_RE_MASK | ENET_MAC_CONFIG_TE_MASK);
-    /* Enable the remote wakeup packet and enable the power down mode. */
-    if (wakeFilter)
-    {
-        for (index = 0; index < ENET_WAKEUPFILTER_NUM; index++)
-        {
-            base->MAC_RWAKE_FRFLT = *reg;
-            reg++;
-        }
-    }
-    base->MAC_PMT_CRTL_STAT = ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK | ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK |
-                              ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
-
-    /* Enable the MAC rx. */
-    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
-}
-
-status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel)
-{
-    assert(handle);
-    assert(length);
-
-    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
-    enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
-    uint16_t index;
-
-    /* Reset the length to zero. */
-    *length = 0;
-
-    if (rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK)
-    {
-        return kStatus_ENET_RxFrameEmpty;
-    }
-    else
-    {
-        do
-        {
-            /* Application owns the buffer descriptor, get the length. */
-            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
-            {
-                if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK)
-                {
-                    return kStatus_ENET_RxFrameError;
-                }
-                *length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK;
-                return kStatus_Success;
-            }
-
-            index = ENET_IncreaseIndex(index, rxBdRing->rxRingLen);
-            rxDesc = rxBdRing->rxBdBase + index;
-        } while (index != rxBdRing->rxGenIdx);
-
-        return kStatus_ENET_RxFrameError;
-    }
-}
-
-status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel)
-{
-    assert(handle);
-
-    uint32_t len = 0;
-    uint32_t offset = 0;
-    uint32_t control;
-    bool isLastBuff = false;
-    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
-    enet_rx_bd_struct_t *rxDesc;
-    status_t result = kStatus_Fail;
-    uint16_t index = rxBdRing->rxGenIdx;
-    bool suspend = false;
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    uint32_t buffer;
-    uint32_t bufferAdd;
-#endif /* ENET_PTP1588FEATURE_REQUIRED  */
-
-    /* Suspend and command for rx. */
-    if (base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
-    {
-        suspend = true;
-    }
-
-    /* For data-NULL input, only update the buffer descriptor. */
-    if ((!data))
-    {
-        do
-        {
-            /* Get the control flag. */
-            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
-            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
-            control = rxDesc->control;
-            /* Updates the receive buffer descriptors. */
-            ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
-
-            /* Find the last buffer descriptor for the frame. */
-            if (control & ENET_RXDESCRIP_WR_LD_MASK)
-            {
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-                /* Reinit for the context descritor which has been updated by DMA. */
-                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
-                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
-                {
-                    if (!handle->doubleBuffEnable)
-                    {
-                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
-                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
-                                                handle->doubleBuffEnable);
-                    }
-                    else
-                    {
-                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
-                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
-                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
-                                                handle->doubleBuffEnable);
-                    }
-                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
-                }
-#endif /*  ENET_PTP1588FEATURE_REQUIRED */
-                break;
-            }
-        } while (rxBdRing->rxGenIdx != index);
-
-        result = kStatus_Success;
-    }
-    else
-    {
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-        enet_ptp_time_data_t ptpTsData;
-        bool ptp1588 = false;
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-        while ((!isLastBuff))
-        {
-            /* The last buffer descriptor of a frame. */
-            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
-            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-            if (rxDesc->control & ENET_RXDESCRIP_WR_FD_MASK)
-            {
-                ptp1588 = ENET_Ptp1588ParseFrame((uint8_t *)rxDesc->buff1Addr, &ptpTsData, false);
-            }
-#endif
-            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
-            {
-                /* This is a valid frame. */
-                isLastBuff = true;
-                if (length == (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK))
-                {
-                    /* Copy the frame to user's buffer. */
-                    len = (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK) - offset;
-                    if (len > rxBdRing->rxBuffSizeAlign)
-                    {
-                        memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
-                        offset += rxBdRing->rxBuffSizeAlign;
-                        memcpy(data + offset, (void *)rxDesc->buff2Addr, len - rxBdRing->rxBuffSizeAlign);
-                    }
-                    else
-                    {
-                        memcpy(data + offset, (void *)rxDesc->buff1Addr, len);
-                    }
-
-                    result = kStatus_Success;
-                }
-
-                /* Updates the receive buffer descriptors. */
-                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-                /* Store the rx timestamp which is in the next buffer descriptor of the last
-                 * descriptor of a frame. */
-                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
-
-                /* Reinit for the context descritor which has been updated by DMA. */
-                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
-                {
-                    if (ptp1588)
-                    {
-                        ENET_StoreRxFrameTime(base, handle, rxDesc, channel, &ptpTsData);
-                    }
-
-                    if (!handle->doubleBuffEnable)
-                    {
-                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
-                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
-                                                handle->doubleBuffEnable);
-                    }
-                    else
-                    {
-                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
-                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
-                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
-                                                handle->doubleBuffEnable);
-                    }
-                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
-                }
-                base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-            }
-            else
-            {
-                /* Store a frame on several buffer descriptors. */
-                isLastBuff = false;
-                /* Length check. */
-                if (offset >= length)
-                {
-                    /* Updates the receive buffer descriptors. */
-                    ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
-                    break;
-                }
-
-                memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
-                offset += rxBdRing->rxBuffSizeAlign;
-                if ((rxDesc->buff2Addr) && (handle->doubleBuffEnable))
-                {
-                    memcpy(data + offset, (void *)rxDesc->buff2Addr, rxBdRing->rxBuffSizeAlign);
-                    offset += rxBdRing->rxBuffSizeAlign;
-                }
-
-                /* Updates the receive buffer descriptors. */
-                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
-            }
-        }
-    }
-
-    /* Set command for rx when it is suspend. */
-    if (suspend)
-    {
-        base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
-    }
-
-    return result;
-}
-
-void ENET_UpdateRxDescriptor(
-    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable)
-{
-    assert(rxDesc);
-    uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
-
-    if (intEnable)
-    {
-        control |= ENET_RXDESCRIP_RD_IOC_MASK;
-    }
-
-    if (doubleBuffEnable)
-    {
-        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
-    }
-
-    /* Update the buffer if needed. */
-    if (buffer1)
-    {
-        rxDesc->buff1Addr = (uint32_t)buffer1;
-    }
-    if (buffer2)
-    {
-        rxDesc->buff2Addr = (uint32_t)buffer2;
-    }
-    else
-    {
-        rxDesc->buff2Addr = 0;
-    }
-
-    rxDesc->reserved = 0;
-    rxDesc->control = control;
-}
-
-void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
-                            void *buffer1,
-                            uint32_t bytes1,
-                            void *buffer2,
-                            uint32_t bytes2,
-                            uint32_t framelen,
-                            bool intEnable,
-                            bool tsEnable,
-                            enet_desc_flag flag,
-                            uint8_t slotNum)
-{
-    uint32_t control = ENET_TXDESCRIP_RD_BL1(bytes1) | ENET_TXDESCRIP_RD_BL2(bytes2);
-
-    if (tsEnable)
-    {
-        control |= ENET_TXDESCRIP_RD_TTSE_MASK;
-    }
-    else
-    {
-        control &= ~ENET_TXDESCRIP_RD_TTSE_MASK;
-    }
-
-    if (intEnable)
-    {
-        control |= ENET_TXDESCRIP_RD_IOC_MASK;
-    }
-    else
-    {
-        control &= ~ENET_TXDESCRIP_RD_IOC_MASK;
-    }
-
-    /* Preare the descriptor for transmit. */
-    txDesc->buff1Addr = (uint32_t)buffer1;
-    txDesc->buff2Addr = (uint32_t)buffer2;
-    txDesc->buffLen = control;
-
-    control = ENET_TXDESCRIP_RD_FL(framelen) | ENET_TXDESCRIP_RD_LDFD(flag) | ENET_TXDESCRIP_RD_OWN_MASK;
-
-    txDesc->controlStat = control;
-}
-
-void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel)
-{
-    enet_tx_bd_ring_t *txBdRing = &handle->txBdRing[channel];
-    enet_tx_bd_struct_t *txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
-
-    /* Need to update the first index for transmit buffer free. */
-    while ((txBdRing->txDescUsed > 0) && (!(txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK)))
-    {
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-        uint32_t nanosecond;
-        uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
-
-        if (txDesc->controlStat & ENET_TXDESCRIP_RD_LD_MASK)
-        {
-            enet_ptp_time_data_t *ptpTsData = txBdRing->txPtpTsDataRing.ptpTsData + txBdRing->txPtpTsDataRing.end;
-            if (txDesc->controlStat & ENET_TXDESCRIP_WB_TTSS_MASK)
-            {
-                /* Get transmit time stamp second. */
-                nanosecond = txDesc->buff2Addr | txDesc->buff1Addr;
-                if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
-                {
-                    /* Binary rollover. */
-                    nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
-                }
-                ptpTsData->timeStamp.second = nanosecond / nanoOverSize;
-                ptpTsData->timeStamp.nanosecond = nanosecond % nanoOverSize;
-
-                /* Store the timestamp to the transmit timestamp ring. */
-                ENET_Ptp1588UpdateTimeRing(&txBdRing->txPtpTsDataRing, ptpTsData);
-            }
-        }
-#endif  /* ENET_PTP1588FEATURE_REQUIRED */
-
-        /* For tx buffer free or requeue for each descriptor.
-         * The tx interrupt callback should free/requeue the tx buffer. */
-        if (handle->callback)
-        {
-            handle->callback(base, handle, kENET_TxIntEvent, channel, handle->userData);
-        }
-
-        txBdRing->txDescUsed--;
-
-        /* Update the txConsumIdx/txDesc. */
-        txBdRing->txConsumIdx = ENET_IncreaseIndex(txBdRing->txConsumIdx, txBdRing->txRingLen);
-        txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
-    }
-}
-
-status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
-{
-    assert(handle);
-    assert(data);
-
-    enet_tx_bd_ring_t *txBdRing;
-    enet_tx_bd_struct_t *txDesc;
-    uint8_t channel = 0;
-    bool ptp1588 = false;
-
-    if (length > 2 * ENET_TXDESCRIP_RD_BL1_MASK)
-    {
-        return kStatus_ENET_TxFrameOverLen;
-    }
-
-    /* Choose the transit queue. */
-    channel = ENET_GetTxRingId(data, handle);
-
-    /* Check if the DMA owns the descriptor. */
-    txBdRing = (enet_tx_bd_ring_t *)&handle->txBdRing[channel];
-    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
-    if (txBdRing->txRingLen == txBdRing->txDescUsed)
-    {
-        return kStatus_ENET_TxFrameBusy;
-    }
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    enet_ptp_time_data_t ptpTsData;
-
-    ptp1588 = ENET_Ptp1588ParseFrame(data, &ptpTsData, true);
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-    /* Fill the descriptor. */
-    if (length <= ENET_TXDESCRIP_RD_BL1_MASK)
-    {
-        ENET_SetupTxDescriptor(txDesc, data, length, NULL, 0, length, true, ptp1588, kENET_FirstLastFlag, 0);
-    }
-    else
-    {
-        ENET_SetupTxDescriptor(txDesc, data, ENET_TXDESCRIP_RD_BL1_MASK, data + ENET_TXDESCRIP_RD_BL1_MASK,
-                               (length - ENET_TXDESCRIP_RD_BL1_MASK), length, true, ptp1588, kENET_FirstLastFlag, 0);
-    }
-
-    /* Increase the index. */
-    txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen);
-    /* Disable interrupt first and then enable interrupt to avoid the race condition. */
-    DisableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
-    txBdRing->txDescUsed++;
-    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
-
-    /* Update the transmit tail address. */
-    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
-    if (!txBdRing->txGenIdx)
-    {
-        txDesc = txBdRing->txBdBase + txBdRing->txRingLen;
-    }
-    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_ADDR_ALIGNMENT;
-
-    return kStatus_Success;
-}
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond)
-{
-    assert(second);
-    assert(nanosecond);
-
-    uint32_t primask;
-
-    /* Disables the interrupt. */
-    primask = DisableGlobalIRQ();
-
-    /* Get the current PTP time. */
-    *second = ((uint64_t)(base->MAC_SYS_TIME_HWORD_SCND & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) << 32U) |
-              base->MAC_SYS_TIME_SCND;
-    *nanosecond = base->MAC_SYS_TIME_NSCND & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
-    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
-    {
-        /* Binary rollover, the unit of the increment is ~ 0.466 ns. */
-        *nanosecond = *nanosecond / 1000U * 466U;
-    }
-
-    /* Enables the interrupt. */
-    EnableGlobalIRQ(primask);
-}
-
-void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond)
-{
-    uint32_t corrSecond = second;
-    uint32_t corrNanosecond;
-
-    /* Set the system timer. */
-    if (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
-    {
-        if (operation == kENET_SystimeSubtract)
-        {
-            /* Set with the complement of the sub-second. */
-            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
-            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
-                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_NANOSECS_ONESECOND - nanosecond);
-        }
-        else
-        {
-            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
-        }
-    }
-    else
-    {
-        nanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK / ENET_NANOSECS_ONESECOND * nanosecond;
-        if (operation == kENET_SystimeSubtract)
-        {
-            /* Set with the complement of the sub-second. */
-            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
-            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
-                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK + 1 - nanosecond);
-        }
-        else
-        {
-            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
-        }
-    }
-
-    base->MAC_SYS_TIME_SCND_UPD = corrSecond;
-    base->MAC_SYS_TIME_NSCND_UPD = corrNanosecond;
-
-    /* Update the timer. */
-    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK;
-    while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
-        ;
-}
-
-status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
-{
-    assert(handle);
-    assert(ptpTimeData);
-
-    uint32_t result = kStatus_Success;
-    uint8_t count;
-    uint8_t index = handle->multiQueEnable ? 2 : 1;
-
-    for (count = 0; count < index; count++)
-    {
-        result = ENET_Ptp1588SearchTimeRing(&handle->txBdRing[count].txPtpTsDataRing, ptpTimeData);
-        if (result == kStatus_Success)
-        {
-            break;
-        }
-    }
-
-    return result;
-}
-
-status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
-{
-    assert(handle);
-    assert(ptpTimeData);
-
-    uint32_t result = kStatus_Success;
-    uint8_t count;
-    uint8_t index = handle->multiQueEnable ? 2 : 1;
-
-    for (count = 0; count < index; count++)
-    {
-        result = ENET_Ptp1588SearchTimeRing(&handle->rxBdRing[count].rxPtpTsDataRing, ptpTimeData);
-        if (result == kStatus_Success)
-        {
-            break;
-        }
-    }
-
-    return result;
-}
-
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle)
-{
-    /* Check for the interrupt source type. */
-    /* DMA CHANNEL 0. */
-    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC0IS_MASK)
-    {
-        uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT;
-        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
-        {
-            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
-            if (handle->callback)
-            {
-                handle->callback(base, handle, kENET_RxIntEvent, 0, handle->userData);
-            }
-        }
-        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
-        {
-            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
-            ENET_ReclaimTxDescriptor(base, handle, 0);
-        }
-    }
-
-    /* DMA CHANNEL 1. */
-    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC1IS_MASK)
-    {
-        uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT;
-        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
-        {
-            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
-            if (handle->callback)
-            {
-                handle->callback(base, handle, kENET_RxIntEvent, 1, handle->userData);
-            }
-        }
-        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
-        {
-            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
-            ENET_ReclaimTxDescriptor(base, handle, 1);
-        }
-    }
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    /* MAC TIMESTAMP. */
-    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_MACIS_MASK)
-    {
-        if (base->MAC_INTR_STAT & ENET_MAC_INTR_STAT_TSIS_MASK)
-        {
-            if (handle->callback)
-            {
-                handle->callback(base, handle, kENET_TimeStampIntEvent, 0, handle->userData);
-            }
-        }
-    }
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-}
-
-void ETHERNET_DriverIRQHandler(void)
-{
-    s_enetIsr(ENET, s_ENETHandle[0]);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1178 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_ENET_H_
-#define _FSL_ENET_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpc_enet
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-/*@}*/
-
-/*! @name Control and status region bit masks of the receive buffer descriptor. */
-/*@{*/
-/*! @brief Defines for read format. */
-#define ENET_RXDESCRIP_RD_BUFF1VALID_MASK (1U << 24) /*!< Buffer1 address valid. */
-#define ENET_RXDESCRIP_RD_BUFF2VALID_MASK (1U << 25) /*!< Buffer2 address valid. */
-#define ENET_RXDESCRIP_RD_IOC_MASK (1U << 30)        /*!< Interrupt enable on complete. */
-#define ENET_RXDESCRIP_RD_OWN_MASK (1U << 31)        /*!< Own bit. */
-
-/*! @brief Defines for write back format. */
-#define ENET_RXDESCRIP_WR_ERR_MASK ((1U << 3) | (1U << 7))
-#define ENET_RXDESCRIP_WR_PYLOAD_MASK (0x7U)
-#define ENET_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00U)
-#define ENET_RXDESCRIP_WR_PTPTYPE_MASK (1U << 12)
-#define ENET_RXDESCRIP_WR_PTPVERSION_MASK (1U << 13)
-#define ENET_RXDESCRIP_WR_PTPTSA_MASK (1U << 14)
-#define ENET_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFU)
-#define ENET_RXDESCRIP_WR_ERRSUM_MASK (1U << 15)
-#define ENET_RXDESCRIP_WR_TYPE_MASK (0x30000U)
-#define ENET_RXDESCRIP_WR_DE_MASK (1U << 19)
-#define ENET_RXDESCRIP_WR_RE_MASK (1U << 20)
-#define ENET_RXDESCRIP_WR_OE_MASK (1U << 21)
-#define ENET_RXDESCRIP_WR_RS0V_MASK (1U << 25)
-#define ENET_RXDESCRIP_WR_RS1V_MASK (1U << 26)
-#define ENET_RXDESCRIP_WR_RS2V_MASK (1U << 27)
-#define ENET_RXDESCRIP_WR_LD_MASK (1U << 28)
-#define ENET_RXDESCRIP_WR_FD_MASK (1U << 29)
-#define ENET_RXDESCRIP_WR_CTXT_MASK (1U << 30)
-#define ENET_RXDESCRIP_WR_OWN_MASK (1U << 31)
-/*@}*/
-
-/*! @name Control and status bit masks of the transmit buffer descriptor. */
-/*@{*/
-/*! @brief Defines for read format. */
-#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU)
-#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16)
-#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK)
-#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16)
-#define ENET_TXDESCRIP_RD_TTSE_MASK (1U << 30)
-#define ENET_TXDESCRIP_RD_IOC_MASK (1U << 31)
-
-#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU)
-#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK)
-#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3) << 16)
-#define ENET_TXDESCRIP_RD_TSE_MASK (1U << 18)
-#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0f) << 19)
-#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07) << 23)
-#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03) << 26)
-#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03) << 28)
-#define ENET_TXDESCRIP_RD_LD_MASK (1U << 28)
-#define ENET_TXDESCRIP_RD_FD_MASK (1U << 29)
-#define ENET_TXDESCRIP_RD_CTXT_MASK (1U << 30)
-#define ENET_TXDESCRIP_RD_OWN_MASK (1UL << 31)
-
-/*! @brief Defines for write back format. */
-#define ENET_TXDESCRIP_WB_TTSS_MASK (1UL << 17)
-/*@}*/
-
-/*! @name Bit mask for interrupt enable type. */
-/*@{*/
-#define ENET_ABNORM_INT_MASK                                                      \
-    (ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK | \
-     ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK | \
-     ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
-#define ENET_NORM_INT_MASK                                                        \
-    (ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK | \
-     ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
-/*@}*/
-
-/*! @name Defines some Ethernet parameters. */
-/*@{*/
-
-#define ENET_FRAME_MAX_FRAMELEN (1518U)/*!< Default maximum Ethernet frame size. */
-#define ENET_ADDR_ALIGNMENT (0x3U)     /*!< Recommended ethernet buffer alignment. */
-#define ENET_BUFF_ALIGNMENT (4U)       /*!< Receive buffer alignment shall be 4bytes-aligned. */
-#define ENET_RING_NUM_MAX (2U)         /*!< The Maximum number of tx/rx descriptor rings. */
-#define ENET_MTL_RXFIFOSIZE (2048U)    /*!< The rx fifo size. */
-#define ENET_MTL_TXFIFOSIZE (2048U)    /*!< The tx fifo size. */
-#define ENET_MACINT_ENUM_OFFSET (16U)  /*!< The offest for mac interrupt in enum type. */
-/*@}*/
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-/* Define the buffer length to store the rx buffers address.
- * because the context descriptor will be updated for store the time
- * stamp for rx frame. so we need to reinit the descriptors.
- * This macro shall at least equal to the rxRingLen
- * assigned in the enet_buffer_config. That means if the rx descriptor
- * length is larger than 5, please increse this macro.  */
-#define ENET_RXBUFFSTORE_NUM (6)
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-/*! @brief Defines the status return codes for transaction. */
-enum _enet_status
-{
-    kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U),  /*!< A frame received but data error happen. */
-    kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U),   /*!< Failed to receive a frame. */
-    kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U),  /*!< No frame arrive. */
-    kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 3U),   /*!< Transmit descriptors are under process. */
-    kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U),   /*!< Transmit frame fail. */
-    kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit oversize. */
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    ,
-    kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */
-    kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */
-#endif                                                               /* ENET_PTP1588FEATURE_REQUIRED */
-};
-
-/*! @brief Defines the MII/RMII mode for data interface between the MAC and the PHY. */
-typedef enum _enet_mii_mode {
-    kENET_MiiMode = 0U, /*!< MII mode for data interface. */
-    kENET_RmiiMode = 1U /*!< RMII mode for data interface. */
-} enet_mii_mode_t;
-
-/*! @brief Defines the 10/100 Mbps speed for the MII data interface. */
-typedef enum _enet_mii_speed {
-    kENET_MiiSpeed10M = 0U,  /*!< Speed 10 Mbps. */
-    kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */
-} enet_mii_speed_t;
-
-/*! @brief Defines the half or full duplex for the MII data interface. */
-typedef enum _enet_mii_duplex {
-    kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
-    kENET_MiiFullDuplex       /*!< Full duplex mode. */
-} enet_mii_duplex_t;
-
-/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
-typedef enum _enet_mii_normal_opcode {
-    kENET_MiiWriteFrame = 1U, /*!< Write frame operation for a valid MII management frame. */
-    kENET_MiiReadFrame = 3U   /*!< Read frame operation for a valid MII management frame. */
-} enet_mii_normal_opcode;
-
-/*! @brief Define the DMA maximum transmit burst length. */
-typedef enum _enet_dma_burstlen {
-    kENET_BurstLen1 = 0x00001U,   /*!< DMA burst length 1. */
-    kENET_BurstLen2 = 0x00002U,   /*!< DMA burst length 2. */
-    kENET_BurstLen4 = 0x00004U,   /*!< DMA burst length 4. */
-    kENET_BurstLen8 = 0x00008U,   /*!< DMA burst length 8. */
-    kENET_BurstLen16 = 0x00010U,  /*!< DMA burst length 16. */
-    kENET_BurstLen32 = 0x00020U,  /*!< DMA burst length 32. */
-    kENET_BurstLen64 = 0x10008U,  /*!< DMA burst length 64. eight times enabled. */
-    kENET_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
-    kENET_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
-} enet_dma_burstlen;
-
-/*! @brief Define the flag for the descriptor. */
-typedef enum _enet_desc_flag {
-    kENET_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
-    kENET_FirstFlagOnly,  /*!< It's the first descriptor of the frame. */
-    kENET_LastFlagOnly,   /*!< It's the last descriptor of the frame. */
-    kENET_FirstLastFlag   /*!< It's the first and last descriptor of the frame. */
-} enet_desc_flag;
-
-/*! @brief Define the system time adjust operation control. */
-typedef enum _enet_systime_op {
-    kENET_SystimeAdd = 0U,     /*!< System time add to. */
-    kENET_SystimeSubtract = 1U /*!< System time subtract. */
-} enet_systime_op;
-
-/*! @brief Define the system time rollover control. */
-typedef enum _enet_ts_rollover_type {
-    kENET_BinaryRollover = 0, /*!< System time binary rollover.*/
-    kENET_DigitalRollover = 1 /*!< System time digital rollover.*/
-} enet_ts_rollover_type;
-
-/*! @brief Defines some special configuration for ENET.
- *
- * These control flags are provided for special user requirements.
- * Normally, these is no need to set this control flags for ENET initialization.
- * But if you have some special requirements, set the flags to specialControl
- * in the enet_config_t.
- * @note "kENET_StoreAndForward" is recommended to be set when the
- * ENET_PTP1588FEATURE_REQUIRED is defined or else the timestamp will be mess-up
- * when the overflow happens.
- */
-typedef enum _enet_special_config {
-
-    /***********************DMA CONFGI**********************************************/
-    kENET_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
-    /**************************MTL************************************/
-    kENET_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
-    /***********************MAC****************************************/
-    kENET_PromiscuousEnable = 0x0004U,  /*!< The promiscuous enabled. */
-    kENET_FlowControlEnable = 0x0008U,  /*!< The flow control enabled. */
-    kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
-    kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
-    kENET_8023AS2KPacket = 0x0040U      /*!< 8023as support for 2K packets. */
-} enet_special_config_t;
-
-/*! @brief List of DMA interrupts supported by the ENET interrupt. This
- * enumeration uses one-bot encoding to allow a logical OR of multiple
- * members.
- */
-typedef enum _enet_dma_interrupt_enable {
-    kENET_DmaTx = ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK,                 /*!< Tx interrupt. */
-    kENET_DmaTxStop = ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK,             /*!< Tx stop interrupt. */
-    kENET_DmaTxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK,     /*!< Tx buffer unavailable. */
-    kENET_DmaRx = ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK,                 /*!< Rx interrupt. */
-    kENET_DmaRxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK,     /*!< Rx buffer unavailable. */
-    kENET_DmaRxStop = ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK,             /*!< Rx stop. */
-    kENET_DmaRxWatchdogTimeout = ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
-    kENET_DmaEarlyTx = ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK,           /*!< Early transmit. */
-    kENET_DmaEarlyRx = ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK,           /*!< Early receive. */
-    kENET_DmaBusErr = ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK,            /*!< Fatal bus error. */
-} enet_dma_interrupt_enable_t;
-
-/*! @brief List of mac interrupts supported by the ENET interrupt. This
- * enumeration uses one-bot encoding to allow a logical OR of multiple
- * members.
- */
-typedef enum _enet_mac_interrupt_enable {
-    kENET_MacPmt = (ENET_MAC_INTR_EN_PMTIE_MASK << ENET_MACINT_ENUM_OFFSET),
-    kENET_MacTimestamp = (ENET_MAC_INTR_EN_TSIE_MASK << ENET_MACINT_ENUM_OFFSET),
-} enet_mac_interrupt_enable_t;
-
-/*! @brief Defines the common interrupt event for callback use. */
-typedef enum _enet_event {
-    kENET_RxIntEvent,     /*!< Receive interrupt event. */
-    kENET_TxIntEvent,     /*!< Transmit interrupt event. */
-    kENET_WakeUpIntEvent, /*!< Wake up interrupt event. */
-    kENET_TimeStampIntEvent, /*!< Time stamp interrupt event. */
-} enet_event_t;
-
-/*! @brief Define the DMA transmit arbitration for multi-queue. */
-typedef enum _enet_dma_tx_sche {
-    kENET_FixPri = 0,      /*!< Fixed priority. channel 0 has lower priority than channel 1. */
-    kENET_WeightStrPri,    /*!< Weighted(burst length) strict priority. */
-    kENET_WeightRoundRobin /*!< Weighted (weight factor) round robin. */
-} enet_dma_tx_sche;
-
-/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
-typedef enum _enet_mtl_multiqueue_txsche {
-    kENET_txWeightRR = 0U, /*!< Tx weight round-robin. */
-    kENET_txStrPrio = 3U,  /*!< Tx strict priority. */
-} enet_mtl_multiqueue_txsche;
-
-/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
-typedef enum _enet_mtl_multiqueue_rxsche {
-    kENET_rxStrPrio = 0U,  /*!< Tx weight round-robin, rx strict priority. */
-    kENET_rxWeightStrPrio, /*!< Tx strict priority, rx weight strict priority. */
-} enet_mtl_multiqueue_rxsche;
-
-/*! @brief Define the MTL rx queue and DMA channel mapping. */
-typedef enum _enet_mtl_rxqueuemap {
-    kENET_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) direclty map to dma channel n. */
-    kENET_DynamicMap =
-        0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
-                    */
-} enet_mtl_rxqueuemap;
-
-/*! @brief Defines the ENET PTP message related constant. */
-typedef enum _enet_ptp_event_type {
-    kENET_PtpEventMsgType = 3U,  /*!< PTP event message type. */
-    kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
-    kENET_PtpEventPort = 319U,   /*!< PTP event port number. */
-    kENET_PtpGnrlPort = 320U     /*!< PTP general port number. */
-} enet_ptp_event_type_t;
-
-/*! @brief Defines the receive descriptor structure
- *  has the read-format and write-back format structure. They both
- *  has the same size with different region definition. so
- *  we define the read-format region as the recive descriptor structure
- *  Use the read-format region mask bits in the descriptor initialization
- *  Use the write-back format region mask bits in the receive data process.
- */
-typedef struct _enet_rx_bd_struct
-{
-    __IO uint32_t buff1Addr; /*!< Buffer 1 address */
-    __IO uint32_t reserved;  /*!< Reserved */
-    __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
-    __IO uint32_t control;   /*!< Buffer 1/2 byte counts and control */
-} enet_rx_bd_struct_t;
-
-/*! @brief Defines the transmit descriptor structure
- *  has the read-format and write-back format structure. They both
- *  has the same size with different region definition. so
- *  we define the read-format region as the transmit descriptor structure
- *  Use the read-format region mask bits in the descriptor initialization
- *  Use the write-back format region mask bits in the transmit data process.
- */
-typedef struct _enet_tx_bd_struct
-{
-    __IO uint32_t buff1Addr;   /*!< Buffer 1 address */
-    __IO uint32_t buff2Addr;   /*!< Buffer 2 address */
-    __IO uint32_t buffLen;     /*!< Buffer 1/2 byte counts */
-    __IO uint32_t controlStat; /*!< TDES control and status word */
-} enet_tx_bd_struct_t;
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-/*! @brief Defines the ENET PTP time stamp structure. */
-typedef struct _enet_ptp_time
-{
-    uint64_t second;     /*!< Second. */
-    uint32_t nanosecond; /*!< Nanosecond. */
-} enet_ptp_time_t;
-
-/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/
-typedef struct _enet_ptp_time_data
-{
-    uint8_t version;                             /*!< PTP version. */
-    uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */
-    uint16_t sequenceId;                         /*!< PTP sequence ID. */
-    uint8_t messageType;                         /*!< PTP message type. */
-    enet_ptp_time_t timeStamp;                   /*!< PTP timestamp. */
-} enet_ptp_time_data_t;
-
-/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/
-typedef struct _enet_ptp_time_data_ring
-{
-    uint32_t front;                  /*!< The first index of the ring. */
-    uint32_t end;                    /*!< The end index of the ring. */
-    uint32_t size;                   /*!< The size of the ring. */
-    enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */
-} enet_ptp_time_data_ring_t;
-
-/*! @brief Defines the ENET PTP configuration structure. */
-typedef struct _enet_ptp_config
-{
-    bool fineUpdateEnable;            /*!< Use the fine update. */
-    bool ptp1588V2Enable;             /*!< ptp 1588 version 2 is used. */
-    enet_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
-} enet_ptp_config_t;
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-
-/*! @brief Defines the buffer descriptor configure structure.
- *
- * Notes:
- * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
- * 2. The recommended minimum tx/rx ring length is 4.
- * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
- *    of the last last descriptor. because only the descriptors between the start address and the
- *    tail address will be used by DMA.
- * 4. The decriptor address is the start address of all used contiguous memory.
- *    for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memorise
- *    for rx descriptor ring 0.
- * 5. The "*rxBufferstartAddr" is the first element of  rxRingLen (2*rxRingLen for double buffers)
- *    rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
- *    the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
- *    the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
- *    address of a rxRingLen or 2*rxRingLen array.
- */
-typedef struct _enet_buffer_config
-{
-    uint8_t rxRingLen;                         /*!< The length of receive buffer descriptor ring. */
-    uint8_t txRingLen;                         /*!< The length of transmit buffer descriptor ring. */
-    enet_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
-    enet_tx_bd_struct_t *txDescTailAddrAlign;  /*!< Aligned transmit descriptor tail address. */
-    enet_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
-    enet_rx_bd_struct_t *rxDescTailAddrAlign;  /*!< Aligned receive descriptor tail address. */
-    uint32_t *rxBufferStartAddr;               /*!< Start address of the rx buffers. */
-    uint32_t rxBuffSizeAlign;                  /*!< Aligned receive data buffer size. */
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    uint8_t ptpTsRxBuffNum;            /*!< Receive 1588 timestamp buffer number*/
-    uint8_t ptpTsTxBuffNum;            /*!< Transmit 1588 timestamp buffer number*/
-    enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */
-    enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */
-#endif                                 /* ENET_PTP1588FEATURE_REQUIRED */
-} enet_buffer_config_t;
-
-/*! @brief Defines the configuration when multi-queue is used. */
-typedef struct enet_multiqueue_config
-{
-    /***********************DMA block*******************************/
-    enet_dma_tx_sche dmaTxSche;                /*!< Transmit arbitation. */
-    enet_dma_burstlen burstLen;                /*!< Burset len for the queue 1. */
-    uint8_t txdmaChnWeight[ENET_RING_NUM_MAX]; /*!< Transmit channel weight. */
-    /***********************MTL block*******************************/
-    enet_mtl_multiqueue_txsche mtltxSche;    /*!< Transmit schedule for multi-queue. */
-    enet_mtl_multiqueue_rxsche mtlrxSche;    /*!< Receive schedule for multi-queue. */
-    uint8_t rxqueweight[ENET_RING_NUM_MAX];  /*!< Refer to the MTL RxQ Control register. */
-    uint32_t txqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL TxQ Quantum Weight register. */
-    uint8_t rxqueuePrio[ENET_RING_NUM_MAX];  /*!< Receive queue priority. */
-    uint8_t txqueuePrio[ENET_RING_NUM_MAX];  /*!< Refer to Transmit Queue Priority Mapping register. */
-    enet_mtl_rxqueuemap mtlrxQuemap;         /*!< Rx queue DMA Channel mapping. */
-} enet_multiqueue_config_t;
-
-/*! @brief Defines the basic configuration structure for the ENET device.
- *
- * Note:
- *  1. Default the signal queue is used so the "*multiqueueCfg" is set default
- *  with NULL. Set the pointer with a valid configration pointer if the multiple
- *  queues are required. If multiple queue is enabled, please make sure the
- *  buffer configuration for all are prepared also.
- */
-typedef struct _enet_config
-{
-    uint16_t specialControl;                 /*!< The logicl or of enet_special_config_t */
-    enet_multiqueue_config_t *multiqueueCfg; /*!< Use both tx/rx queue(dma channel) 0 and 1. */
-    /* -----------------MAC block-------------------------------*/
-    enet_mii_mode_t miiMode;     /*!< MII mode. */
-    enet_mii_speed_t miiSpeed;   /*!< MII Speed. */
-    enet_mii_duplex_t miiDuplex; /*!< MII duplex. */
-    uint16_t pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_FlowControlEnable is set. */
-/* -----------------Timestamp -------------------------------*/
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    enet_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
-#endif                            /* ENET_PTP1588FEATURE_REQUIRED */
-} enet_config_t;
-
-/* Forward declaration of the handle typedef. */
-typedef struct _enet_handle enet_handle_t;
-
-/*! @brief ENET callback function. */
-typedef void (*enet_callback_t)(
-    ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *userData);
-
-/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
-typedef struct _enet_tx_bd_ring
-{
-    enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
-    uint16_t txGenIdx;             /*!< tx generate index. */
-    uint16_t txConsumIdx;          /*!< tx consum index. */
-    volatile uint16_t txDescUsed;  /*!< tx descriptor used number. */
-    uint16_t txRingLen;            /*!< tx ring length. */
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */
-#endif                                         /* ENET_PTP1588FEATURE_REQUIRED */
-} enet_tx_bd_ring_t;
-
-/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
-typedef struct _enet_rx_bd_ring
-{
-    enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
-    uint16_t rxGenIdx;             /*!< The current available receive buffer descriptor pointer. */
-    uint16_t rxRingLen;            /*!< Receive ring length. */
-    uint32_t rxBuffSizeAlign;      /*!< Receive buffer size. */
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */
-#endif                                         /* ENET_PTP1588FEATURE_REQUIRED*/
-} enet_rx_bd_ring_t;
-
-/*! @brief Defines the ENET handler structure. */
-struct _enet_handle
-{
-    bool multiQueEnable;                           /*!< Enable multi-queue. */
-    bool doubleBuffEnable;                         /*!< The double buffer is used in the descriptor. */
-    bool rxintEnable;                              /*!< Rx interrup enabled. */
-    enet_rx_bd_ring_t rxBdRing[ENET_RING_NUM_MAX]; /*!< Receive buffer descriptor.  */
-    enet_tx_bd_ring_t txBdRing[ENET_RING_NUM_MAX]; /*!< Transmit buffer descriptor.  */
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-    uint32_t rxbuffers[ENET_RXBUFFSTORE_NUM]; /*!< The Initi-rx buffers will be used for reInitialize. */
-#endif
-    enet_callback_t callback; /*!< Callback function. */
-    void *userData;           /*!< Callback function parameter.*/
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
-  * @name Initialization and De-initialization
-  * @{
-  */
-
-/*!
- * @brief Gets the ENET default configuration structure.
- *
- * The purpose of this API is to get the default ENET configure
- * structure for ENET_Init(). User may use the initialized
- * structure unchanged in ENET_Init(), or modify some fields of the
- * structure before calling ENET_Init().
- * Example:
-   @code
-   enet_config_t config;
-   ENET_GetDefaultConfig(&config);
-   @endcode
- * @param config The ENET mac controller configuration structure pointer.
- */
-void ENET_GetDefaultConfig(enet_config_t *config);
-
-/*!
- * @brief Initializes the ENET module.
- *
- * This function ungates the module clock and initializes it with the ENET basic
- * configuration.
- *
- * @param base    ENET peripheral base address.
- * @param config  ENET mac configuration structure pointer.
- *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
- *        can be used directly. It is also possible to verify the Mac configuration using other methods.
- * @param macAddr  ENET mac address of Ethernet device. This MAC address should be
- *        provided.
- * @param refclkSrc_Hz ENET input reference clock.
- */
-void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz);
-
-/*!
- * @brief Deinitializes the ENET module.
-
- * This function gates the module clock and disables the ENET module.
- *
- * @param base  ENET peripheral base address.
- */
-void ENET_Deinit(ENET_Type *base);
-
-/*!
- * @brief Initialize for all ENET descriptors.
- *
- * @note This function is do all tx/rx descriptors initialization. Because this API 
- *  read all interrupt registers first and then set the interrupt flag for all descriptos, 
- * if the interrupt register is set. so the descriptor initialization should be called
- * after ENET_Init(), ENET_EnableInterrupts() and ENET_CreateHandle()(if transactional APIs
- * are used).
- *
- * @param base  ENET peripheral base address.
- * @param config The configuration for ENET.
- * @param bufferConfig All buffers configuration.
- */
-status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig);
-
-/*!
- * @brief Starts the ENET rx/tx.
- *  This function enable the tx/rx and starts the rx/tx DMA.
- * This shall be set after ENET initialization and before
- * starting to receive the data.
- *
- * @param base  ENET peripheral base address.
- * @param rxRingNum  The number of the used rx rings. It shall not be
- * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
- * 1, the ring 0 will be used.
- * @param txRingNum  The number of the used tx rings. It shall not be
- * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
- * 1, the ring 0 will be used.
- *
- * @note This must be called after all the ENET initilization.
- * And should be called when the ENET receive/transmit is required.
- */
-void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
-
-/* @} */
-
-/*!
- * @name MII interface operation
- * @{
- */
-
-/*!
- * @brief Sets the ENET MII speed and duplex.
- *
- * This API is provided to dynamically change the speed and dulpex for MAC.
- *
- * @param base  ENET peripheral base address.
- * @param speed The speed of the RMII mode.
- * @param duplex The duplex of the RMII mode.
- */
-static inline void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
-{
-    uint32_t reg = base->MAC_CONFIG & ~(ENET_MAC_CONFIG_DM_MASK | ENET_MAC_CONFIG_FES_MASK);
-    reg |= ENET_MAC_CONFIG_DM(duplex) | ENET_MAC_CONFIG_FES(speed);
-
-    base->MAC_CONFIG = reg;
-}
-
-/*!
- * @brief Sets the ENET SMI(serial management interface)- MII management interface.
- *
- * @param base  ENET peripheral base address.
- */
-void ENET_SetSMI(ENET_Type *base);
-
-/*!
- * @brief Checks if the SMI is busy.
- *
- * @param base  ENET peripheral base address.
- * @return The status of MII Busy status.
- */
-static inline bool ENET_IsSMIBusy(ENET_Type *base)
-{
-    return (base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_MB_MASK) ? true : false;
-}
-
-/*!
- * @brief Reads data from the PHY register through SMI interface.
- *
- * @param base  ENET peripheral base address.
- * @return The data read from PHY
- */
-static inline uint16_t ENET_ReadSMIData(ENET_Type *base)
-{
-    return (uint16_t)(base->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_MD_MASK);
-}
-
-/*!
- * @brief Starts an SMI read command.
- * support both MDIO IEEE802.3 Clause 22 and clause 45.
- *
- * @param base  ENET peripheral base address.
- * @param phyAddr The PHY address.
- * @param phyReg The PHY register.
- */
-void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg);
-
-/*!
- * @brief Starts a SMI write command.
- * support both MDIO IEEE802.3 Clause 22 and clause 45.
- *
- * @param base  ENET peripheral base address.
- * @param phyAddr The PHY address.
- * @param phyReg The PHY register.
- * @param data The data written to PHY.
- */
-void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
-/* @} */
-
-/*!
- * @name Other basic operation
- * @{
- */
-
-/*!
- * @brief Sets the ENET module Mac address.
- *
- * @param base  ENET peripheral base address.
- * @param macAddr The six-byte Mac address pointer.
- *        The pointer is allocated by application and input into the API.
- */
-static inline void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
-{
-    assert(macAddr);
-
-    /* Set Macaddr */
-    base->MAC_ADDR_LOW = ((uint32_t)macAddr[3] << 24) | ((uint32_t)macAddr[2] << 16) | ((uint32_t)macAddr[1] << 8) |
-                         ((uint32_t)macAddr[0]);
-    base->MAC_ADDR_HIGH = ((uint32_t)macAddr[5] << 8) | ((uint32_t)macAddr[4]);
-}
-
-/*!
- * @brief Gets the ENET module Mac address.
- *
- * @param base  ENET peripheral base address.
- * @param macAddr The six-byte Mac address pointer.
- *        The pointer is allocated by application and input into the API.
- */
-void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr);
-
-/*!
- * @brief Set the MAC to enter into power down mode.
- * the remote power wake up frame and magic frame can wake up
- * the ENET from the power down mode.
- *
- * @param base    ENET peripheral base address.
- * @param wakeFilter  The wakeFilter provided to configure the wake up frame fitlter.
- *  Set the wakeFilter to NULL is not required. But if you have the filter requirement,
- *  please make sure the wakeFilter pointer shall be eight continous
- *  32-bits configuration.
- */
-void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter);
-
-/*!
- * @brief Set the MAC to exit power down mode.
- * Eixt from the power down mode and recover to noraml work mode.
- *
- * @param base    ENET peripheral base address.
- */
-static inline void ENET_ExitPowerDown(ENET_Type *base)
-{
-    /* Clear and status ans reset the power down. */
-    base->MAC_PMT_CRTL_STAT &= ~ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
-
-    /* Restore the tx which is disabled when enter power down mode. */
-    base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
-    base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
-    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
-}
-
-/* @} */
-
-/*!
- * @name Interrupts.
- * @{
- */
-
-/*!
- * @brief Enables the ENET DMA and MAC interrupts.
- *
- * This function enables the ENET interrupt according to the provided mask. The mask
- * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
- * For example, to enable the dma and mac interrupt, do the following.
- * @code
- *     ENET_EnableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
- * @endcode
- *
- * @param base  ENET peripheral base address.
- * @param mask  ENET interrupts to enable. This is a logical OR of both 
- *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
- */
-void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask);
-
-/*!
- * @brief Disables the ENET DMA and MAC interrupts.
- *
- * This function disables the ENET interrupt according to the provided mask. The mask
- * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
- * For example, to disable the dma and mac interrupt, do the following.
- * @code
- *     ENET_DisableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
- * @endcode
- *
- * @param base  ENET peripheral base address.
- * @param mask  ENET interrupts to disables. This is a logical OR of both 
- *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
- */
-void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask);
-    
-/*!
- * @brief Gets the ENET DMA interrupt status flag.
- *
- * @param base  ENET peripheral base address.
- * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
- * @return The event status of the interrupt source. This is the logical OR of members
- *         of the enumeration :: enet_dma_interrupt_enable_t.
- */
-static inline uint32_t ENET_GetDmaInterruptStatus(ENET_Type *base, uint8_t channel)
-{
-    return base->DMA_CH[channel].DMA_CHX_STAT;
-}
-
-/*!
- * @brief Clear the ENET DMA interrupt status flag.
- *
- * @param base  ENET peripheral base address.
- * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
- * @return The event status of the interrupt source. This is the logical OR of members
- *         of the enumeration :: enet_dma_interrupt_enable_t.
- */
-static inline void ENET_ClearDmaInterruptStatus(ENET_Type *base, uint8_t channel, uint32_t mask)
-{
-    /* Clear the dam interrupt status bit in dma channel interrupt status register. */
-    base->DMA_CH[channel].DMA_CHX_STAT = mask;
-}
-
-/*!
- * @brief Gets the ENET MAC interrupt status flag.
- *
- * @param base  ENET peripheral base address.
- * @return The event status of the interrupt source. 
- *       Use the enum in enet_mac_interrupt_enable_t and right shift
- *       ENET_MACINT_ENUM_OFFSET to mask the returned value to get the 
- *       exact interrupt status.
- */
-static inline uint32_t ENET_GetMacInterruptStatus(ENET_Type *base)
-{
-    return base->MAC_INTR_STAT;
-}
-
-/*!
- * @brief Clears the ENET mac interrupt events status flag.
- *
- * This function clears enabled ENET interrupts according to the provided mask. The mask
- * is a logical OR of enumeration members. See the @ref enet_mac_interrupt_enable_t.
- * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
- * @code
- *     ENET_ClearMacInterruptStatus(ENET, kENET_MacPmt);
- * @endcode
- *
- * @param base  ENET peripheral base address.
- * @param mask  ENET interrupt source to be cleared.
- * This is the logical OR of members of the enumeration :: enet_mac_interrupt_enable_t.
- */
-void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask);
-
-/* @} */
-
-/*!
- * @name Functional operation.
- * @{
- */
-
-/*!
- * @brief Get the tx descriptor DMA Own flag.
- *
- * @param txDesc  The given tx descriptor.
- * @retval True the dma own tx descriptor, false application own tx descriptor.
- *
- */
-static inline bool ENET_IsTxDescriptorDmaOwn(enet_tx_bd_struct_t *txDesc)
-{
-    return (txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK) ? true : false;
-}
-
-/*!
- * @brief Setup a given tx descriptor.
- *  This function is a low level functional API to setup or prepare
- *  a given tx descriptor.
- *
- * @param txDesc  The given tx descriptor.
- * @param buffer1  The first buffer address in the descriptor.
- * @param bytes1  The bytes in the fist buffer.
- * @param buffer2  The second buffer address in the descriptor.
- * @param bytes1  The bytes in the second buffer.
- * @param framelen  The length of the frame to be transmitted.
- * @param intEnable Interrupt enable flag.
- * @param tsEnable The timestamp enable.
- * @param flag The flag of this tx desciriptor, see "enet_desc_flag" .
- * @param slotNum The slot num used for AV  only.
- *
- * @note This must be called after all the ENET initilization.
- * And should be called when the ENET receive/transmit is required.
- * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
- * memory until the packet has been fully transmitted. The buffers
- * should be free or requeued in the transmit interrupt irq handler.
- */
-void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
-                            void *buffer1,
-                            uint32_t bytes1,
-                            void *buffer2,
-                            uint32_t bytes2,
-                            uint32_t framelen,
-                            bool intEnable,
-                            bool tsEnable,
-                            enet_desc_flag flag,
-                            uint8_t slotNum);
-
-/*!
- * @brief Update the tx descriptor tail pointer.
- *  This function is a low level functional API to update the
- *  the tx descriptor tail.
- *  This is called after you setup a new tx descriptor to update
- *  the tail pointer to make the new descritor accessable by DMA.
- *
- * @param base    ENET peripheral base address.
- * @param channel  The tx DMA channel.
- * @param txDescTailAddrAlign  The new tx tail pointer address.
- *
- */
-static inline void ENET_UpdateTxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
-{
-    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
-}
-
-/*!
- * @brief Update the rx descriptor tail pointer.
- *  This function is a low level functional API to update the
- *  the rx descriptor tail.
- *  This is called after you setup a new rx descriptor to update
- *  the tail pointer to make the new descritor accessable by DMA
- *  and to anouse the rx poll command for DMA.
- *
- * @param base    ENET peripheral base address.
- * @param channel  The rx DMA channel.
- * @param rxDescTailAddrAlign  The new rx tail pointer address.
- *
- */
-static inline void ENET_UpdateRxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
-{
-    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
-}
-
-/*!
- * @brief Gets the context in the ENET rx descriptor.
- *  This function is a low level functional API to get the
- *  the status flag from a given rx descriptor.
- *
- * @param rxDesc  The given rx descriptor.
- * @retval The RDES3 regions for write-back format rx buffer descriptor.
- *
- * @note This must be called after all the ENET initilization.
- * And should be called when the ENET receive/transmit is required.
- */
-static inline uint32_t ENET_GetRxDescriptor(enet_rx_bd_struct_t *rxDesc)
-{
-    assert(rxDesc);
-
-    return rxDesc->control;
-}
-/*!
- * @brief Updates the buffers and the own status for a given rx descriptor.
- *  This function is a low level functional API to Updates the
- *  buffers and the own status for a given rx descriptor.
- *
- * @param rxDesc  The given rx descriptor.
- * @param buffer1  The first buffer address in the descriptor.
- * @param buffer2  The second buffer address in the descriptor.
- * @param intEnable Interrupt enable flag.
- * @param doubleBuffEnable The double buffer enable flag.
- *
- * @note This must be called after all the ENET initilization.
- * And should be called when the ENET receive/transmit is required.
- */
-void ENET_UpdateRxDescriptor(
-    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
-
-/* @} */
-
-/*!
- * @name Transactional operation
- * @{
- */
-
-/*!
- * @brief Create ENET Handler 
- *
- * This is a transactional API and it's provided to store all datas which are needed
- * during the whole transactional process. This API should not be used when you use
- * functional APIs to do data tx/rx. This is funtion will store many data/flag for 
- * transactional use, so all configure API such as ENET_Init(), ENET_DescriptorInit(),
- * ENET_EnableInterrupts() etc.
- *
- * @note as our transactional transmit API use the zero-copy transmit buffer.
- * so there are two thing we emphasize here:
- *  1. tx buffer free/requeue for application should be done in the tx 
- *  interrupt handler. Please set callback: kENET_TxIntEvent with tx buffer free/requeue
- *  process APIs.
- *  2. the tx interrupt is forced to open.
- *
- * @param base  ENET peripheral base address.
- * @param handle ENET handler.
- * @param config ENET configuration.
- * @param bufferConfig ENET buffer configuration.
- * @param callback The callback function.
- * @param userData The application data.
- */
-void ENET_CreateHandler(ENET_Type *base,
-                        enet_handle_t *handle,
-                        enet_config_t *config,
-                        enet_buffer_config_t *bufferConfig,
-                        enet_callback_t callback,
-                        void *userData);
-
-/*!
-* @brief Gets the size of the read frame.
-* This function gets a received frame size from the ENET buffer descriptors.
-* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
-* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
-* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
-*
-* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
-* @param length The length of the valid frame received.
-* @param channel The DMAC channel for the rx.
-* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
-* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
-*         and NULL length to update the receive buffers.
-* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
-*         should be called with the right data buffer and the captured data length input.
-*/
-status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel);
-
-/*!
- * @brief Reads a frame from the ENET device.
- * This function reads a frame from the ENET DMA descriptors.
- * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
- * For example use rx dma channel 0:
- * @code
- *       uint32_t length;
- *       enet_handle_t g_handle;
- *       //Get the received frame size firstly.
- *       status = ENET_GetRxFrameSize(&g_handle, &length, 0);
- *       if (length != 0)
- *       {
- *           //Allocate memory here with the size of "length"
- *           uint8_t *data = memory allocate interface;
- *           if (!data)
- *           {
- *               ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
- *               //Add the console warning log.
- *           }
- *           else
- *           {
- *              status = ENET_ReadFrame(ENET, &g_handle, data, length, 0);
- *              //Call stack input API to deliver the data to stack
- *           }
- *       }
- *       else if (status == kStatus_ENET_RxFrameError)
- *       {
- *          //Update the received buffer when a error frame is received.
- *           ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
- *       }
- * @endcode
- * @param base  ENET peripheral base address.
- * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
- * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
- * @param length The size of the data buffer which is still the length of the received frame.
- * @param channel The rx DMA channel. shall not be larger than 2.
- * @return The execute status, successful or failure.
- */
-status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel);
-
-/*!
- * @brief Transmits an ENET frame.
- * @note The CRC is automatically appended to the data. Input the data
- * to send without the CRC.
- *
- * @param base  ENET peripheral base address.
- * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
- * @param data The data buffer provided by user to be send.
- * @param length The length of the data to be send.
- * @retval kStatus_Success  Send frame succeed.
- * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
- *         The transmit busy happens when the data send rate is over the MAC capacity.
- *         The waiting mechanism is recommended to be added after each call return with
- *         kStatus_ENET_TxFrameBusy.
- */
-status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length);
-
-/*!
- * @brief Reclaim tx descriptors.
- *  This function is used to update the tx descriptor status and
- *  store the tx timestamp when the 1588 feature is enabled.
- *  This is called by the transmit interupt IRQ handler after the
- *  complete of a frame transmission.
- *
- * @param base    ENET peripheral base address.
- * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
- * @param channel  The tx DMA channnel.
- *
- */
-void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel);
-
-/*!
- * @brief The ENET PMT IRQ handler.
- *
- * @param base  ENET peripheral base address.
- * @param handle The ENET handler pointer.
- */
-void ENET_PMTIRQHandler(ENET_Type *base, enet_handle_t *handle);
-
-/*!
- * @brief The ENET IRQ handler.
- *
- * @param base  ENET peripheral base address.
- * @param handle The ENET handler pointer.
- */
-void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle);
-
-/* @} */
-
-#ifdef ENET_PTP1588FEATURE_REQUIRED
-/*!
- * @name ENET Enhanced function operation
- * @{
- */
-
-/*!
- * @brief Starts the ENET PTP 1588 Timer.
- * This function is used to initialize the PTP timer. After the PTP starts,
- * the PTP timer starts running.
- *
- * @param base  ENET peripheral base address.
- * @param ptpClkSrc The clock source of the PTP timer.
- */
-void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc);
-
-/*!
- * @brief Coreect the ENET PTP 1588 timer in coarse method.
- *
- * @param base  ENET peripheral base address.
- * @param operation The system time operation, refer to "enet_systime_op"
- * @param second The correction second.
- * @param nanosecond The correction nanosecond.
- */
-void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond);
-
-/*!
- * @brief Coreect the ENET PTP 1588 timer in fine method.
- *
- *
- * @param base  ENET peripheral base address.
- * @param addend The addend value to be set in the fine method
- * @note Should take refer to the chapter "System time corretion" and
- * see the description for the "fine correction method".
- */
-static inline void ENET_Ptp1588CorrectTimerInFine(ENET_Type *base, uint32_t addend)
-{
-    /* Set the freqCompensation value. */
-    base->MAC_SYS_TIMESTMP_ADDEND = addend;
-    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
-}
-
-/*!
- * @brief Get the ENET Time stamp current addend value.
- *
- * @param base  ENET peripheral base address.
- * @return The addend value.
- */
-static inline uint32_t ENET_Ptp1588GetAddend(ENET_Type *base)
-{
-    return base->MAC_SYS_TIMESTMP_ADDEND;
-}
-
-/*!
- * @brief Gets the current ENET time from the PTP 1588 timer.
- *
- * @param base  ENET peripheral base address.
- * @param second The PTP 1588 system timer second.
- * @param nanosecond The PTP 1588 system timer nanosecond.
- * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
- */
-void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond);
-
-/*!
- * @brief Gets the time stamp of the received frame.
- *
- * This function is used for PTP stack to get the timestamp captured by the ENET driver.
- *
- * @param handle The ENET handler pointer.This is the same state pointer used in
- *        ENET_Init.
- * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
- * @retval kStatus_Success Get 1588 timestamp success.
- * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
- * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
- */
-status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
-
-/*!
- * @brief Gets the time stamp of the transmit frame.
- *
- * This function is used for PTP stack to get the timestamp captured by the ENET driver.
- *
- * @param handle The ENET handler pointer.This is the same state pointer used in
- *        ENET_Init.
- * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
- * @retval kStatus_Success Get 1588 timestamp success.
- * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
- * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
- */
-status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_ENET_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,127 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_flashiap.h"
-
-#define HZ_TO_KHZ_DIV 1000
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static status_t translate_iap_status(uint32_t status)
-{
-    /* Translate IAP return code to sdk status code */
-    if (status == kStatus_Success)
-    {
-        return status;
-    }
-    else
-    {
-        return MAKE_STATUS(kStatusGroup_FLASHIAP, status);
-    }
-}
-
-status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite;
-    command[1] = startSector;
-    command[2] = endSector;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}
-
-status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_CopyRamToFlash;
-    command[1] = dstAddr;
-    command[2] = (uint32_t)srcAddr;
-    command[3] = numOfBytes;
-    command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}
-
-status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_EraseSector;
-    command[1] = startSector;
-    command[2] = endSector;
-    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}
-
-status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_ErasePage;
-    command[1] = startPage;
-    command[2] = endPage;
-    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}
-
-status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_BlankCheckSector;
-    command[1] = startSector;
-    command[2] = endSector;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}
-
-status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
-{
-    uint32_t command[5], result[4];
-
-    command[0] = kIapCmd_FLASHIAP_Compare;
-    command[1] = dstAddr;
-    command[2] = (uint32_t)srcAddr;
-    command[3] = numOfBytes;
-    iap_entry(command, result);
-
-    return translate_iap_status(result[0]);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,264 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_FLASHIAP_H_
-#define _FSL_FLASHIAP_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup flashiap_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-                                                            /*@}*/
-
-/*!
- * @brief Flashiap status codes.
- */
-enum _flashiap_status
-{
-    kStatus_FLASHIAP_Success = kStatus_Success,                               /*!< Api is executed successfully */
-    kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */
-    kStatus_FLASHIAP_SrcAddrError =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */
-    kStatus_FLASHIAP_DstAddrError =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */
-    kStatus_FLASHIAP_SrcAddrNotMapped =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */
-    kStatus_FLASHIAP_DstAddrNotMapped =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */
-    kStatus_FLASHIAP_CountError =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */
-    kStatus_FLASHIAP_InvalidSector =
-        MAKE_STATUS(kStatusGroup_FLASHIAP,
-                    7), /*!< Sector number is invalid or end sector number is greater than start sector number */
-    kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */
-    kStatus_FLASHIAP_NotPrepared =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */
-    kStatus_FLASHIAP_CompareError =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */
-    kStatus_FLASHIAP_Busy =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */
-    kStatus_FLASHIAP_ParamError =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */
-    kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */
-    kStatus_FLASHIAP_AddrNotMapped =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 14U),                        /*!< Address is not mapped in the memory map */
-    kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */
-    kStatus_FLASHIAP_NoClock =
-        MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */
-};
-
-/*!
- * @brief Flashiap command codes.
- */
-enum _flashiap_commands
-{
-    kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */
-    kIapCmd_FLASHIAP_CopyRamToFlash = 51U,        /*!< Copy RAM to flash */
-    kIapCmd_FLASHIAP_EraseSector = 52U,           /*!< Erase Sector */
-    kIapCmd_FLASHIAP_BlankCheckSector = 53U,      /*!< Blank check sector */
-    kIapCmd_FLASHIAP_ReadPartId = 54U,            /*!< Read part id */
-    kIapCmd_FLASHIAP_Read_BootromVersion = 55U,   /*!< Read bootrom version */
-    kIapCmd_FLASHIAP_Compare = 56U,               /*!< Compare */
-    kIapCmd_FLASHIAP_ReinvokeISP = 57U,           /*!< Reinvoke ISP */
-    kIapCmd_FLASHIAP_ReadUid = 58U,               /*!< Read Uid isp */
-    kIapCmd_FLASHIAP_ErasePage = 59U,             /*!< Erase Page */
-    kIapCmd_FLASHIAP_ReadMisr = 70U,              /*!< Read Misr */
-    kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U      /*!< Reinvoke I2C/SPI isp */
-};
-
-/*! @brief IAP_ENTRY API function type */
-typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]);
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief IAP_ENTRY API function type
- *
- * Wrapper for rom iap call
- *
- * @param cmd_param IAP command and relevant parameter array.
- * @param status_result IAP status result array.
- *
- * @retval None. Status/Result is returned via status_result array.
- */
-static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
-{
-    ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
-}
-
-/*!
- * @brief	Prepare sector for write operation
-
- * This function prepares sector(s) for write/erase operation. This function must be
- * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or
- * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to
- * start sector number.
- *
- * @param startSector Start sector number.
- * @param endSector End sector number.
- *
- * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
- *         is greater than start sector number.
- * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
- */
-status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
-
-/*!
- * @brief	Copy RAM to flash.
-
- * This function programs the flash memory. Corresponding sectors must be prepared
- * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses
- * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
- *
- * @param dstAddr Destination flash address where data bytes are to be written.
- * @param srcAddr Source ram address from where data bytes are to be read.
- * @param numOfBytes Number of bytes to be written.
- * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
- *                        rom IAP function.
- *
- * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary.
- * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary.
- * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map.
- * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map.
- * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
- * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
- * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
- */
-status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock);
-
-/*!
- * @brief	Erase sector
-
- * This function erases sector(s). The end sector must be greater than or equal to
- * start sector number. FLASHIAP_PrepareSectorForWrite must be called before
- * calling this function.
- *
- * @param startSector Start sector number.
- * @param endSector End sector number.
- * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
- *                        rom IAP function.
- *
- * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
- *         is greater than start sector number.
- * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
- * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
- */
-status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
-
-/*!
-
- * This function erases page(s). The end page must be greater than or equal to
- * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite
- * before calling calling this function.
- *
- * @param startPage Start page number
- * @param endPage End page number
- * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
- *                        rom IAP function.
- *
- * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number
- *         is greater than start page number
- * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
- * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
- */
-status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock);
-
-/*!
- * @brief Blank check sector(s)
- *
- * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
- * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call.
- *
- * @param	startSector	: Start sector number. Must be greater than or equal to start sector number
- * @param	endSector	: End sector number
- * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank.
- */
-status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector);
-
-/*!
- * @brief Compare memory contents of flash with ram.
-
- * This function compares the contents of flash and ram. It can be used to verify the flash
- * memory contents after FLASHIAP_CopyRamToFlash call.
- *
- * @param dstAddr Destination flash address.
- * @param srcAddr Source ram address.
- * @param numOfBytes Number of bytes to be compared.
- *
- * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match.
- * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
- * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
- * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary.
- * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map.
- * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
- * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match.
- */
-status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _FSL_FLASHIAP_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,240 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_common.h"
-#include "fsl_flexcomm.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
-static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
-
-/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
-static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
-
-/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
-IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
-
-/*! @brief Array to map FLEXCOMM instance number to base address. */
-static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief IDs of clock for each FLEXCOMM module */
-static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* check whether flexcomm supports peripheral type */
-static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
-{
-    if (periph == FLEXCOMM_PERIPH_NONE)
-    {
-        return true;
-    }
-    else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX))
-    {
-        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false;
-    }
-    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
-    {
-        return (base->PSELID & (1 << 7)) > 0 ? true : false;
-    }
-    else
-    {
-        return false;
-    }
-}
-
-/* Get the index corresponding to the FLEXCOMM */
-uint32_t FLEXCOMM_GetInstance(void *base)
-{
-    int i;
-
-    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
-    {
-        if ((uint32_t)base == s_flexcommBaseAddrs[i])
-        {
-            return i;
-        }
-    }
-
-    assert(false);
-    return 0;
-}
-
-/* Changes FLEXCOMM mode */
-status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
-{
-    /* Check whether peripheral type is present */
-    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
-    {
-        return kStatus_OutOfRange;
-    }
-
-    /* Flexcomm is locked to different peripheral type than expected  */
-    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
-    {
-        return kStatus_Fail;
-    }
-
-    /* Check if we are asked to lock */
-    if (lock)
-    {
-        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
-    }
-    else
-    {
-        base->PSELID = (uint32_t)periph;
-    }
-
-    return kStatus_Success;
-}
-
-status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
-{
-    int idx = FLEXCOMM_GetInstance(base);
-
-    if (idx < 0)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the peripheral clock */
-    CLOCK_EnableClock(s_flexcommClocks[idx]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Set the FLEXCOMM to given peripheral */
-    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
-}
-
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
-{
-    uint32_t instance;
-
-    /* Look up instance number */
-    instance = FLEXCOMM_GetInstance(base);
-
-    /* Clear handler first to avoid execution of the handler with wrong handle */
-    s_flexcommIrqHandler[instance] = NULL;
-    s_flexcommHandle[instance] = handle;
-    s_flexcommIrqHandler[instance] = handler;
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(FLEXCOMM0)
-void FLEXCOMM0_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[0]);
-    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
-}
-#endif
-
-#if defined(FLEXCOMM1)
-void FLEXCOMM1_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[1]);
-    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
-}
-#endif
-
-#if defined(FLEXCOMM2)
-void FLEXCOMM2_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[2]);
-    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
-}
-#endif
-
-#if defined(FLEXCOMM3)
-void FLEXCOMM3_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[3]);
-    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
-}
-#endif
-
-#if defined(FLEXCOMM4)
-void FLEXCOMM4_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[4]);
-    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
-}
-
-#endif
-
-#if defined(FLEXCOMM5)
-void FLEXCOMM5_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[5]);
-    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
-}
-#endif
-
-#if defined(FLEXCOMM6)
-void FLEXCOMM6_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[6]);
-    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
-}
-#endif
-
-#if defined(FLEXCOMM7)
-void FLEXCOMM7_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[7]);
-    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
-}
-#endif
-
-#if defined(FLEXCOMM8)
-void FLEXCOMM8_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[8]);
-    s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
-}
-#endif
-
-#if defined(FLEXCOMM9)
-void FLEXCOMM9_DriverIRQHandler(void)
-{
-    assert(s_flexcommIrqHandler[9]);
-    s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_FLEXCOMM_H_
-#define _FSL_FLEXCOMM_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup flexcomm_driver
- * @{
- */
-
-/*! @brief FLEXCOMM peripheral modes. */
-typedef enum
-{
-    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
-    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
-    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
-    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
-    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
-    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
-} FLEXCOMM_PERIPH_T;
-
-/*! @brief Typedef for interrupt handler. */
-typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
-
-/*! @brief Array with IRQ number for each FLEXCOMM module. */
-extern IRQn_Type const kFlexcommIrqs[];
-
-/*! @brief Returns instance number for FLEXCOMM module with given base address. */
-uint32_t FLEXCOMM_GetInstance(void *base);
-
-/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
-status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
-
-/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
- * mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
-
-/*@}*/
-
-#endif /* _FSL_FLEXCOMM_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_fmc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void FMC_GetDefaultConfig(fmc_config_t *config)
-{
-    config->waitStates = 0x05;
-}
-
-void FMC_Init(FMC_Type *base, fmc_config_t *config)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* enable clock to FMC */
-    CLOCK_EnableClock(kCLOCK_Fmc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Set control register, FS_RD0 = 0, FS_RD1 = 1. */
-    base->FCTR &= ~(FMC_FCTR_FS_RD0_MASK | FMC_FCTR_FS_RD1_MASK);
-    base->FCTR |= FMC_FCTR_FS_RD1_MASK;
-
-    /* Set wait state, same as FLASHTIM in SYSCON->FLASHCFG register. */
-    base->FBWST &= ~FMC_FBWST_WAITSTATES_MASK;
-    base->FBWST |= config->waitStates;
-}
-
-void FMC_Denit(FMC_Type *base)
-{
-    /* Reset FMC module */
-    RESET_PeripheralReset(kFMC_RST_SHIFT_RSTn);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* enable clock to FMC */
-    CLOCK_DisableClock(kCLOCK_Fmc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void FMC_GenerateFlashSignature(FMC_Type *base,
-                                uint32_t startAddress,
-                                uint32_t length,
-                                fmc_flash_signature_t *flashSignature)
-{
-    uint32_t stopAddress;
-
-    /* Clear generation done flag. */
-    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
-
-    /* Calculate flash stop address */
-    stopAddress = ((startAddress + length - 1) >> 4) & FMC_FMSSTOP_STOP_MASK;
-
-    /* Calculate flash start address. */
-    startAddress = (startAddress >> 4) & FMC_FMSSTART_START_MASK;
-
-    /* Start flash signature generation. */
-    base->FMSSTART = startAddress;
-    base->FMSSTOP = stopAddress;
-
-    base->FMSSTOP |= FMC_FMSSTOP_SIG_START_MASK;
-
-    /* Wait for signature done. */
-    while ((base->FMSTAT & kFMC_SignatureGenerationDoneFlag) != kFMC_SignatureGenerationDoneFlag)
-    {
-    }
-
-    /* Clear generation done flag. */
-    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
-
-    /* Get the generated flash signature. */
-    flashSignature->word0 = base->FMSW[0];
-    flashSignature->word1 = base->FMSW[1];
-    flashSignature->word2 = base->FMSW[2];
-    flashSignature->word3 = base->FMSW[3];
-
-    return;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_FMC_H_
-#define _FSL_FMC_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup fmc
- * @{
- */
-
-/******************************************************************************
- * Definitions.
- *****************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Driver version 2.0.0. */
-#define FSL_FMC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
-/*@}*/
-
-/*!
- * @addtogroup fmc_driver
- * @{
- */
-
-/*!
- * @brief fmc peripheral flag.
- *
- */
-enum _fmc_flags
-{
-    kFMC_SignatureGenerationDoneFlag = FMC_FMSTAT_SIG_DONE_MASK, /*!< Flash signature generation done. */
-};
-
-/*! @brief Defines the generated 128-bit signature. */
-typedef struct _fmc_flash_signature
-{
-    uint32_t word0; /* Signature bits [31:0]. */
-    uint32_t word1; /* Signature bits [63:32]. */
-    uint32_t word2; /* Signature bits [95:64]. */
-    uint32_t word3; /* Signature bits [127:96]. */
-} fmc_flash_signature_t;
-
-/*! @brief fmc config structure. */
-typedef struct _fmc_config
-{
-    uint8_t waitStates; /* flash timing value for flash signature generation. */
-} fmc_config_t;
-
-/*! @} */
-
-/*******************************************************************************
- * API
- *******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Initialize FMC module.
- *
- * This function initialize FMC module with user configuration
- *
- * @param base The FMC peripheral base address.
- * @param config pointer to user configuration structure.
- */
-void FMC_Init(FMC_Type *base, fmc_config_t *config);
-
-/*!
- * @brief Deinit FMC module.
- *
- * This function De-initialize FMC module.
- *
- * @param base The FMC peripheral base address.
- */
-void FMC_Deinit(FMC_Type *base);
-
-/*!
- * @brief Provides default configuration for fmc module.
- *
- * This function provides default configuration for fmc module, the default wait states value is
- * 5.
- *
- * @param config pointer to user configuration structure.
- */
-void FMC_GetDefaultConfig(fmc_config_t *config);
-
-/*!
- * @brief Generate hardware flash signature.
- *
- * This function generates hardware flash signature for specified address range.
- *
- * @note This function needs to be excuted out of flash memory.
- * @param base The FMC peripheral base address.
- * @param startAddress Flash start address for signature generation.
- * @param length Length of address range.
- * @param flashSignature Pointer which stores the generated flash signarue.
- */
-void FMC_GenerateFlashSignature(FMC_Type *base,
-                                uint32_t startAddress,
-                                uint32_t length,
-                                fmc_flash_signature_t *flashSignature);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_fmeas.h"
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/*! @brief Target clock counter value.
- * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */
-#define TARGET_CLOCK_COUNT(base) \
-    ((uint32_t)(                 \
-        ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2))
-
-/*! @brief Reference clock counter value. */
-#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1))
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate)
-{
-    uint32_t targetClockCount = TARGET_CLOCK_COUNT(base);
-    uint64_t clkrate = 0;
-
-    if (targetClockCount > 0)
-    {
-        clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT;
-    }
-
-    return (uint32_t)clkrate;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_FMEAS_H_
-#define _FSL_FMEAS_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup fmeas
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Defines LPC Frequency Measure driver version 2.0.0.
- *
- * Change log:
- * - Version 2.0.0
- *   - initial version
- */
-#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*******************************************************************************
- * API
- *******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*!
- * @name FMEAS Functional Operation
- * @{
- */
-
-/*!
- * @brief    Starts a frequency measurement cycle.
- *
- * @param    base : SYSCON peripheral base address.
- */
-static inline void FMEAS_StartMeasure(SYSCON_Type *base)
-{
-    base->FREQMECTRL = 0;
-    base->FREQMECTRL = (1UL << 31);
-}
-
-/*!
- * @brief    Indicates when a frequency measurement cycle is complete.
- *
- * @param    base : SYSCON peripheral base address.
- * @return   true if a measurement cycle is active, otherwise false.
- */
-static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base)
-{
-    return (bool)((base->FREQMECTRL & (1UL << 31)) == 0);
-}
-
-/*!
- * @brief    Returns the computed value for a frequency measurement cycle
- *
- * @param    base         : SYSCON peripheral base address.
- * @param    refClockRate : Reference clock rate used during the frequency measurement cycle.
- *
- * @return   Frequency in Hz.
- */
-uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate);
-
-/*@}*/
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-/*! @}*/
-
-#endif /* _FSL_FMEAS_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_gint.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to GINT bases for each instance. */
-static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Clocks for each instance. */
-static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Resets for each instance. */
-static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
-
-/* @brief Irq number for each instance */
-static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
-
-/*! @brief Callback function array for GINT(s). */
-static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static uint32_t GINT_GetInstance(GINT_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
-    {
-        if (s_gintBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_gintBases));
-
-    return instance;
-}
-
-void GINT_Init(GINT_Type *base)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-
-    s_gintCallback[instance] = NULL;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the peripheral clock */
-    CLOCK_EnableClock(s_gintClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the peripheral */
-    RESET_PeripheralReset(s_gintResets[instance]);
-}
-
-void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-
-    base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
-
-    /* Save callback pointer */
-    s_gintCallback[instance] = callback;
-}
-
-void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-
-    *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
-    *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
-    *callback = s_gintCallback[instance];
-}
-
-void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
-{
-    base->PORT_POL[port] = polarityMask;
-    base->PORT_ENA[port] = enableMask;
-}
-
-void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
-{
-    *polarityMask = base->PORT_POL[port];
-    *enableMask = base->PORT_ENA[port];
-}
-
-void GINT_EnableCallback(GINT_Type *base)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-    /* If GINT is configured in "AND" mode a spurious interrupt is generated.
-       Clear status and pending interrupt before enabling the irq in NVIC. */
-    GINT_ClrStatus(base);
-    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
-    EnableIRQ(s_gintIRQ[instance]);
-}
-
-void GINT_DisableCallback(GINT_Type *base)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-    DisableIRQ(s_gintIRQ[instance]);
-    GINT_ClrStatus(base);
-    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
-}
-
-void GINT_Deinit(GINT_Type *base)
-{
-    uint32_t instance;
-
-    instance = GINT_GetInstance(base);
-
-    /* Cleanup */
-    GINT_DisableCallback(base);
-    s_gintCallback[instance] = NULL;
-
-    /* Reset the peripheral */
-    RESET_PeripheralReset(s_gintResets[instance]);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the peripheral clock */
-    CLOCK_DisableClock(s_gintClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-#if defined(GINT0)
-void GINT0_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[0] != NULL)
-    {
-        s_gintCallback[0]();
-    }
-}
-#endif
-
-#if defined(GINT1)
-void GINT1_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[1] != NULL)
-    {
-        s_gintCallback[1]();
-    }
-}
-#endif
-
-#if defined(GINT2)
-void GINT2_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[2] != NULL)
-    {
-        s_gintCallback[2]();
-    }
-}
-#endif
-
-#if defined(GINT3)
-void GINT3_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[3] != NULL)
-    {
-        s_gintCallback[3]();
-    }
-}
-#endif
-
-#if defined(GINT4)
-void GINT4_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[4] != NULL)
-    {
-        s_gintCallback[4]();
-    }
-}
-#endif
-
-#if defined(GINT5)
-void GINT5_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[5] != NULL)
-    {
-        s_gintCallback[5]();
-    }
-}
-#endif
-
-#if defined(GINT6)
-void GINT6_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[6] != NULL)
-    {
-        s_gintCallback[6]();
-    }
-}
-#endif
-
-#if defined(GINT7)
-void GINT7_DriverIRQHandler(void)
-{
-    /* Clear interrupt before callback */
-    s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
-    /* Call user function */
-    if (s_gintCallback[7] != NULL)
-    {
-        s_gintCallback[7]();
-    }
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,244 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_GINT_H_
-#define _FSL_GINT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup gint_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-/*@}*/
-
-/*! @brief GINT combine inputs type */
-typedef enum _gint_comb
-{
-    kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
-    kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
-} gint_comb_t;
-
-/*! @brief GINT trigger type */
-typedef enum _gint_trig
-{
-    kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
-    kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
-} gint_trig_t;
-
-/* @brief GINT port type */
-typedef enum _gint_port
-{
-    kGINT_Port0 = 0U,
-    kGINT_Port1 = 1U,
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
-    kGINT_Port2 = 2U,
-#endif
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
-    kGINT_Port3 = 3U,
-#endif
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
-    kGINT_Port4 = 4U,
-#endif
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
-    kGINT_Port5 = 5U,
-#endif
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
-    kGINT_Port6 = 6U,
-#endif
-#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
-    kGINT_Port7 = 7U,
-#endif
-} gint_port_t;
-
-/*! @brief GINT Callback function. */
-typedef void (*gint_cb_t)(void);
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief	Initialize GINT peripheral.
-
- * This function initializes the GINT peripheral and enables the clock.
- *
- * @param base Base address of the GINT peripheral.
- *
- * @retval None.
- */
-void GINT_Init(GINT_Type *base);
-
-/*!
- * @brief	Setup GINT peripheral control parameters.
-
- * This function sets the control parameters of GINT peripheral.
- *
- * @param base Base address of the GINT peripheral.
- * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
- * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
- * @param callback This function is called when configured group interrupt is generated.
- *
- * @retval None.
- */
-void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
-
-/*!
- * @brief	Get GINT peripheral control parameters.
-
- * This function returns the control parameters of GINT peripheral.
- *
- * @param base Base address of the GINT peripheral.
- * @param comb Pointer to store combine input value.
- * @param trig Pointer to store trigger value.
- * @param callback Pointer to store callback function.
- *
- * @retval None.
- */
-void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
-
-/*!
- * @brief	Configure GINT peripheral pins.
-
- * This function enables and controls the polarity of enabled pin(s) of a given port.
- *
- * @param base Base address of the GINT peripheral.
- * @param port Port number.
- * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
- *        0 = The pin is active LOW. 1 = The pin is active HIGH.
- * @param enableMask Each bit position selects if the corresponding pin is enabled or not.
- *        0 = The pin is disabled. 1 = The pin is enabled.
- *
- * @retval None.
- */
-void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
-
-/*!
- * @brief	Get GINT peripheral pin configuration.
-
- * This function returns the pin configuration of a given port.
- *
- * @param base Base address of the GINT peripheral.
- * @param port Port number.
- * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
- enabled pin.
- *        0 = The pin is active LOW. 1 = The pin is active HIGH.
- * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
- or not.
- *        0 = The pin is disabled. 1 = The pin is enabled.
- *
- * @retval None.
- */
-void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
-
-/*!
- * @brief	Enable callback.
-
- * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
- * as soon as they are enabled, the callback function is not enabled until this function is called.
- *
- * @param base Base address of the GINT peripheral.
- *
- * @retval None.
- */
-void GINT_EnableCallback(GINT_Type *base);
-
-/*!
- * @brief	Disable callback.
-
- * This function disables the interrupt for the selected GINT peripheral. Although the pins are still
- * being monitored but the callback function is not called.
- *
- * @param base Base address of the peripheral.
- *
- * @retval None.
- */
-void GINT_DisableCallback(GINT_Type *base);
-
-/*!
- * @brief	Clear GINT status.
-
- * This function clears the GINT status bit.
- *
- * @param base Base address of the GINT peripheral.
- *
- * @retval None.
- */
-static inline void GINT_ClrStatus(GINT_Type *base)
-{
-    base->CTRL |= GINT_CTRL_INT_MASK;
-}
-
-/*!
- * @brief	Get GINT status.
-
- * This function returns the GINT status.
- *
- * @param base Base address of the GINT peripheral.
- *
- * @retval status = 0 No group interrupt request.  = 1 Group interrupt request active.
- */
-static inline uint32_t GINT_GetStatus(GINT_Type *base)
-{
-    return (base->CTRL & GINT_CTRL_INT_MASK);
-}
-
-/*!
- * @brief	Deinitialize GINT peripheral.
-
- * This function disables the GINT clock.
- *
- * @param base Base address of the GINT peripheral.
- *
- * @retval None.
- */
-void GINT_Deinit(GINT_Type *base);
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _FSL_GINT_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_gpio.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
-* Prototypes
-************ ******************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
-{
-    if (config->pinDirection == kGPIO_DigitalInput)
-    {
-        base->DIR[port] &= ~(1U << pin);
-    }
-    else
-    {
-        /* Set default output value */
-        if (config->outputLogic == 0U)
-        {
-            base->CLR[port] = (1U << pin);
-        }
-        else
-        {
-            base->SET[port] = (1U << pin);
-        }
-        /* Set pin direction */
-        base->DIR[port] |= 1U << pin;
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,250 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _LPC_GPIO_H_
-#define _LPC_GPIO_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpc_gpio
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief LPC GPIO driver version 2.0.0. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief LPC GPIO direction definition */
-typedef enum _gpio_pin_direction
-{
-    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
-    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
-} gpio_pin_direction_t;
-
-/*!
- * @brief The GPIO pin configuration structure.
- *
- * Every pin can only be configured as either output pin or input pin at a time.
- * If configured as a input pin, then leave the outputConfig unused.
- */
-typedef struct _gpio_pin_config
-{
-    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
-    /* Output configurations, please ignore if configured as a input one */
-    uint8_t outputLogic; /*!< Set default output logic, no use in input */
-} gpio_pin_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*! @name GPIO Configuration */
-/*@{*/
-
-/*!
- * @brief Initializes a GPIO pin used by the board.
- *
- * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
- * Then, call the GPIO_PinInit() function.
- *
- * This is an example to define an input pin or output pin configuration:
- * @code
- * // Define a digital input pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalInput,
- *   0,
- * }
- * //Define a digital output pin configuration,
- * gpio_pin_config_t config =
- * {
- *   kGPIO_DigitalOutput,
- *   0,
- * }
- * @endcode
- *
- * @param base   GPIO peripheral base pointer(Typically GPIO)
- * @param port   GPIO port number
- * @param pin    GPIO pin number
- * @param config GPIO pin configuration pointer
- */
-void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
-
-/*@}*/
-
-/*! @name GPIO Output Operations */
-/*@{*/
-
-/*!
- * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
- *
- * @param base    GPIO peripheral base pointer(Typically GPIO)
- * @param port   GPIO port number
- * @param pin    GPIO pin number
- * @param output  GPIO pin output logic level.
- *        - 0: corresponding pin output low-logic level.
- *        - 1: corresponding pin output high-logic level.
- */
-static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
-{
-    base->B[port][pin] = output;
-}
-/*@}*/
-/*! @name GPIO Input Operations */
-/*@{*/
-
-/*!
- * @brief Reads the current input value of the GPIO PIN.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port   GPIO port number
- * @param pin    GPIO pin number
- * @retval GPIO port input value
- *        - 0: corresponding pin input low-logic level.
- *        - 1: corresponding pin input high-logic level.
- */
-static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
-{
-    return (uint32_t)base->B[port][pin];
-}
-/*@}*/
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 1.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port GPIO port number
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
-{
-    base->SET[port] = mask;
-}
-
-/*!
- * @brief Sets the output level of the multiple GPIO pins to the logic 0.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port GPIO port number
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
-{
-    base->CLR[port] = mask;
-}
-
-/*!
- * @brief Reverses current output logic of the multiple GPIO pins.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port GPIO port number
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
-{
-    base->NOT[port] = mask;
-}
-/*@}*/
-
-/*!
- * @brief Reads the current input value of the whole GPIO port.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port GPIO port number
- */
-static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
-{
-    return (uint32_t)base->PIN[port];
-}
-
-/*@}*/
-/*! @name GPIO Mask Operations */
-/*@{*/
-
-/*!
- * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
- *
- * @param base GPIO peripheral base pointer(Typically GPIO)
- * @param port GPIO port number
- * @param mask GPIO pin number macro
- */
-static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
-{
-    base->MASK[port] = mask;
-}
-
-/*!
- * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
- *
- * @param base    GPIO peripheral base pointer(Typically GPIO)
- * @param port   GPIO port number
- * @param output  GPIO port output value.
- */
-static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
-{
-    base->MPIN[port] = output;
-}
-
-/*!
- * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
- * affected.
- *
- * @param base   GPIO peripheral base pointer(Typically GPIO)
- * @param port   GPIO port number
- * @retval       masked GPIO port value
- */
-static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
-{
-    return (uint32_t)base->MPIN[port];
-}
-
-/*@}*/
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-
-#endif /* _LPC_GPIO_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1398 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_i2c.h"
-#include "fsl_flexcomm.h"
-#include <stdlib.h>
-#include <string.h>
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Common sets of flags used by the driver. */
-enum _i2c_flag_constants
-{
-    kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK,
-    kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK,
-};
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
-static void I2C_SlaveInternalStateMachineReset(I2C_Type *base);
-static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal);
-static uint32_t I2C_SlavePollPending(I2C_Type *base);
-static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event);
-static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
-static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
-                                                     i2c_slave_handle_t *handle,
-                                                     const void *txData,
-                                                     size_t txSize,
-                                                     void *rxData,
-                                                     size_t rxSize,
-                                                     uint32_t eventMask);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Array to map i2c instance number to base address. */
-static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS;
-
-/*! @brief IRQ name array */
-static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/*!
- * @brief Returns an instance number given a base address.
- *
- * If an invalid base address is passed, debug builds will assert. Release builds will just return
- * instance number 0.
- *
- * @param base The I2C peripheral base address.
- * @return I2C instance number starting from 0.
- */
-uint32_t I2C_GetInstance(I2C_Type *base)
-{
-    int i;
-    for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++)
-    {
-        if ((uint32_t)base == s_i2cBaseAddrs[i])
-        {
-            return i;
-        }
-    }
-    assert(false);
-    return 0;
-}
-
-void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
-{
-    masterConfig->enableMaster = true;
-    masterConfig->baudRate_Bps = 100000U;
-    masterConfig->enableTimeout = false;
-}
-
-void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
-{
-    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
-    I2C_MasterEnable(base, masterConfig->enableMaster);
-    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
-}
-
-void I2C_MasterDeinit(I2C_Type *base)
-{
-    I2C_MasterEnable(base, false);
-}
-
-void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
-{
-    uint32_t scl, divider;
-    uint32_t best_scl, best_div;
-    uint32_t err, best_err;
-
-    best_err = 0;
-
-    for (scl = 9; scl >= 2; scl--)
-    {
-        /* calculated ideal divider value for given scl */
-        divider = srcClock_Hz / (baudRate_Bps * scl * 2u);
-
-        /* adjust it if it is out of range */
-        divider = (divider > 0x10000u) ? 0x10000 : divider;
-
-        /* calculate error */
-        err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider);
-        if ((err < best_err) || (best_err == 0))
-        {
-            best_div = divider;
-            best_scl = scl;
-            best_err = err;
-        }
-
-        if ((err == 0) || (divider >= 0x10000u))
-        {
-            /* either exact value was found
-               or divider is at its max (it would even greater in the next iteration for sure) */
-            break;
-        }
-    }
-
-    base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1);
-    base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u);
-}
-
-static uint32_t I2C_PendingStatusWait(I2C_Type *base)
-{
-    uint32_t status;
-
-    do
-    {
-        status = I2C_GetStatusFlags(base);
-    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
-
-    /* Clear controller state. */
-    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-
-    return status;
-}
-
-status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
-{
-    I2C_PendingStatusWait(base);
-
-    /* Write Address and RW bit to data register */
-    base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u);
-    /* Start the transfer */
-    base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
-
-    return kStatus_Success;
-}
-
-status_t I2C_MasterStop(I2C_Type *base)
-{
-    I2C_PendingStatusWait(base);
-
-    base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-    return kStatus_Success;
-}
-
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)
-{
-    uint32_t status;
-    uint32_t master_state;
-    status_t err;
-
-    const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff;
-
-    assert(txBuff);
-
-    err = kStatus_Success;
-    while (txSize)
-    {
-        status = I2C_PendingStatusWait(base);
-
-        if (status & I2C_STAT_MSTARBLOSS_MASK)
-        {
-            return kStatus_I2C_ArbitrationLost;
-        }
-
-        if (status & I2C_STAT_MSTSTSTPERR_MASK)
-        {
-            return kStatus_I2C_StartStopError;
-        }
-
-        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-        switch (master_state)
-        {
-            case I2C_STAT_MSTCODE_TXREADY:
-                /* ready to send next byte */
-                base->MSTDAT = *buf++;
-                txSize--;
-                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
-                break;
-
-            case I2C_STAT_MSTCODE_NACKADR:
-            case I2C_STAT_MSTCODE_NACKDAT:
-                /* slave nacked the last byte */
-                err = kStatus_I2C_Nak;
-                break;
-
-            default:
-                /* unexpected state */
-                err = kStatus_I2C_UnexpectedState;
-                break;
-        }
-
-        if (err != kStatus_Success)
-        {
-            return err;
-        }
-    }
-
-    status = I2C_PendingStatusWait(base);
-
-    if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0)
-    {
-        if (!(flags & kI2C_TransferNoStopFlag))
-        {
-            /* Initiate stop */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-            status = I2C_PendingStatusWait(base);
-        }
-    }
-
-    if (status & I2C_STAT_MSTARBLOSS_MASK)
-    {
-        return kStatus_I2C_ArbitrationLost;
-    }
-
-    if (status & I2C_STAT_MSTSTSTPERR_MASK)
-    {
-        return kStatus_I2C_StartStopError;
-    }
-
-    return kStatus_Success;
-}
-
-status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
-{
-    uint32_t status = 0;
-    uint32_t master_state;
-    status_t err;
-
-    uint8_t *buf = (uint8_t *)(rxBuff);
-
-    assert(rxBuff);
-
-    err = kStatus_Success;
-    while (rxSize)
-    {
-        status = I2C_PendingStatusWait(base);
-
-        if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK))
-        {
-            break;
-        }
-
-        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-        switch (master_state)
-        {
-            case I2C_STAT_MSTCODE_RXREADY:
-                /* ready to send next byte */
-                *(buf++) = base->MSTDAT;
-                if (--rxSize)
-                {
-                    base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
-                }
-                else
-                {
-                    if ((flags & kI2C_TransferNoStopFlag) == 0)
-                    {
-                        /* initiate NAK and stop */
-                        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-                        status = I2C_PendingStatusWait(base);
-                    }
-                }
-                break;
-
-            case I2C_STAT_MSTCODE_NACKADR:
-            case I2C_STAT_MSTCODE_NACKDAT:
-                /* slave nacked the last byte */
-                err = kStatus_I2C_Nak;
-                break;
-
-            default:
-                /* unexpected state */
-                err = kStatus_I2C_UnexpectedState;
-                break;
-        }
-
-        if (err != kStatus_Success)
-        {
-            return err;
-        }
-    }
-
-    if (status & I2C_STAT_MSTARBLOSS_MASK)
-    {
-        return kStatus_I2C_ArbitrationLost;
-    }
-
-    if (status & I2C_STAT_MSTSTSTPERR_MASK)
-    {
-        return kStatus_I2C_StartStopError;
-    }
-
-    return kStatus_Success;
-}
-
-status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
-{
-    status_t result = kStatus_Success;
-    uint32_t subaddress;
-    uint8_t subaddrBuf[4];
-    int i;
-
-    assert(xfer);
-
-    /* If repeated start is requested, send repeated start. */
-    if (!(xfer->flags & kI2C_TransferNoStartFlag))
-    {
-        if (xfer->subaddressSize)
-        {
-            result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write);
-            if (result == kStatus_Success)
-            {
-                /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
-                subaddress = xfer->subaddress;
-                for (i = xfer->subaddressSize - 1; i >= 0; i--)
-                {
-                    subaddrBuf[i] = subaddress & 0xff;
-                    subaddress >>= 8;
-                }
-                /* Send subaddress. */
-                result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag);
-                if ((result == kStatus_Success) && (xfer->direction == kI2C_Read))
-                {
-                    result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
-                }
-            }
-        }
-        else if (xfer->flags & kI2C_TransferRepeatedStartFlag)
-        {
-            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
-        }
-        else
-        {
-            result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction);
-        }
-    }
-
-    if (result == kStatus_Success)
-    {
-        if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
-        {
-            /* Transmit data. */
-            result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
-        }
-        else
-        {
-            if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
-            {
-                /* Receive Data. */
-                result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
-            }
-        }
-    }
-
-    if (result == kStatus_I2C_Nak)
-    {
-        I2C_MasterStop(base);
-    }
-
-    return result;
-}
-
-void I2C_MasterTransferCreateHandle(I2C_Type *base,
-                                    i2c_master_handle_t *handle,
-                                    i2c_master_transfer_callback_t callback,
-                                    void *userData)
-{
-    uint32_t instance;
-
-    assert(handle);
-
-    /* Clear out the handle. */
-    memset(handle, 0, sizeof(*handle));
-
-    /* Look up instance number */
-    instance = I2C_GetInstance(base);
-
-    /* Save base and instance. */
-    handle->completionCallback = callback;
-    handle->userData = userData;
-
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle);
-
-    /* Clear internal IRQ enables and enable NVIC IRQ. */
-    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
-    EnableIRQ(s_i2cIRQ[instance]);
-}
-
-status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
-{
-    status_t result;
-
-    assert(handle);
-    assert(xfer);
-    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
-
-    /* Return busy if another transaction is in progress. */
-    if (handle->state != kIdleState)
-    {
-        return kStatus_I2C_Busy;
-    }
-
-    /* Disable I2C IRQ sources while we configure stuff. */
-    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
-
-    /* Prepare transfer state machine. */
-    result = I2C_InitTransferStateMachine(base, handle, xfer);
-
-    /* Clear error flags. */
-    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-
-    /* Enable I2C internal IRQ sources. */
-    I2C_EnableInterrupts(base, kI2C_MasterIrqFlags);
-
-    return result;
-}
-
-status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Catch when there is not an active transfer. */
-    if (handle->state == kIdleState)
-    {
-        *count = 0;
-        return kStatus_NoTransferInProgress;
-    }
-
-    /* There is no necessity to disable interrupts as we read a single integer value */
-    *count = handle->transferCount;
-    return kStatus_Success;
-}
-
-void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
-{
-    uint32_t status;
-    uint32_t master_state;
-
-    if (handle->state != kIdleState)
-    {
-        /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
-
-        /* Wait until module is ready */
-        status = I2C_PendingStatusWait(base);
-
-        /* Get the state of the I2C module */
-        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-
-        if (master_state != I2C_STAT_MSTCODE_IDLE)
-        {
-            /* Send a stop command to finalize the transfer. */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-
-            /* Wait until the STOP is completed */
-            I2C_PendingStatusWait(base);
-        }
-
-        /* Reset handle. */
-        handle->state = kIdleState;
-    }
-}
-
-/*!
- * @brief Prepares the transfer state machine and fills in the command buffer.
- * @param handle Master nonblocking driver handle.
- */
-static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
-{
-    struct _i2c_master_transfer *transfer;
-
-    handle->transfer = *xfer;
-    transfer = &(handle->transfer);
-
-    handle->transferCount = 0;
-    handle->remainingBytes = transfer->dataSize;
-    handle->buf = (uint8_t *)transfer->data;
-    handle->remainingSubaddr = 0;
-
-    if (transfer->flags & kI2C_TransferNoStartFlag)
-    {
-        /* Start condition shall be ommited, switch directly to next phase */
-        if (transfer->dataSize == 0)
-        {
-            handle->state = kStopState;
-        }
-        else if (handle->transfer.direction == kI2C_Write)
-        {
-            handle->state = kTransmitDataState;
-        }
-        else if (handle->transfer.direction == kI2C_Read)
-        {
-            handle->state = kReceiveDataState;
-        }
-        else
-        {
-            return kStatus_I2C_InvalidParameter;
-        }
-    }
-    else
-    {
-        if (transfer->subaddressSize != 0)
-        {
-            int i;
-            uint32_t subaddress;
-
-            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
-            {
-                return kStatus_I2C_InvalidParameter;
-            }
-
-            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
-            subaddress = xfer->subaddress;
-            for (i = xfer->subaddressSize - 1; i >= 0; i--)
-            {
-                handle->subaddrBuf[i] = subaddress & 0xff;
-                subaddress >>= 8;
-            }
-            handle->remainingSubaddr = transfer->subaddressSize;
-        }
-        handle->state = kStartState;
-    }
-
-    return kStatus_Success;
-}
-
-/*!
- * @brief Execute states until FIFOs are exhausted.
- * @param handle Master nonblocking driver handle.
- * @param[out] isDone Set to true if the transfer has completed.
- * @retval #kStatus_Success
- * @retval #kStatus_I2C_ArbitrationLost
- * @retval #kStatus_I2C_Nak
- */
-static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
-{
-    uint32_t status;
-    uint32_t master_state;
-    struct _i2c_master_transfer *transfer;
-    status_t err;
-
-    transfer = &(handle->transfer);
-
-    *isDone = false;
-
-    status = I2C_GetStatusFlags(base);
-
-    if (status & I2C_STAT_MSTARBLOSS_MASK)
-    {
-        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
-        return kStatus_I2C_ArbitrationLost;
-    }
-
-    if (status & I2C_STAT_MSTSTSTPERR_MASK)
-    {
-        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
-        return kStatus_I2C_StartStopError;
-    }
-
-    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
-    {
-        return kStatus_I2C_Busy;
-    }
-
-    /* Get the state of the I2C module */
-    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-
-    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
-    {
-        /* Slave NACKed last byte, issue stop and return error */
-        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-        handle->state = kWaitForCompletionState;
-        return kStatus_I2C_Nak;
-    }
-
-    err = kStatus_Success;
-    switch (handle->state)
-    {
-        case kStartState:
-            if (handle->remainingSubaddr)
-            {
-                /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */
-                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
-                handle->state = kTransmitSubaddrState;
-            }
-            else if (transfer->direction == kI2C_Write)
-            {
-                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
-                handle->state = handle->remainingBytes ? kTransmitDataState : kStopState;
-            }
-            else
-            {
-                base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
-                handle->state = handle->remainingBytes ? kReceiveDataState : kStopState;
-            }
-            /* Send start condition */
-            base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
-            break;
-
-        case kTransmitSubaddrState:
-            if (master_state != I2C_STAT_MSTCODE_TXREADY)
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-
-            /* Most significant subaddress byte comes first */
-            base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr];
-            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
-            if (--(handle->remainingSubaddr))
-            {
-                /* There are still subaddress bytes to be transmitted */
-                break;
-            }
-            if (handle->remainingBytes)
-            {
-                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
-                 * repeated start */
-                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
-            }
-            else
-            {
-                /* No more data, schedule stop condition */
-                handle->state = kStopState;
-            }
-            break;
-
-        case kTransmitDataState:
-            if (master_state != I2C_STAT_MSTCODE_TXREADY)
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-            base->MSTDAT = *(handle->buf)++;
-            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
-            if (--handle->remainingBytes == 0)
-            {
-                /* No more data, schedule stop condition */
-                handle->state = kStopState;
-            }
-            handle->transferCount++;
-            break;
-
-        case kReceiveDataState:
-            if (master_state != I2C_STAT_MSTCODE_RXREADY)
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-            *(handle->buf)++ = base->MSTDAT;
-            if (--handle->remainingBytes)
-            {
-                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
-            }
-            else
-            {
-                /* No more data expected, issue NACK and STOP right away */
-                base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-                handle->state = kWaitForCompletionState;
-            }
-            handle->transferCount++;
-            break;
-
-        case kStopState:
-            if (transfer->flags & kI2C_TransferNoStopFlag)
-            {
-                /* Stop condition is omitted, we are done */
-                *isDone = true;
-                handle->state = kIdleState;
-                break;
-            }
-            /* Send stop condition */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-            handle->state = kWaitForCompletionState;
-            break;
-
-        case kWaitForCompletionState:
-            *isDone = true;
-            handle->state = kIdleState;
-            break;
-
-        case kIdleState:
-        default:
-            /* State machine shall not be invoked again once it enters the idle state */
-            err = kStatus_I2C_UnexpectedState;
-            break;
-    }
-
-    return err;
-}
-
-void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle)
-{
-    bool isDone;
-    status_t result;
-
-    /* Don't do anything if we don't have a valid handle. */
-    if (!handle)
-    {
-        return;
-    }
-
-    result = I2C_RunTransferStateMachine(base, handle, &isDone);
-
-    if (isDone || (result != kStatus_Success))
-    {
-        /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
-
-        /* Invoke callback. */
-        if (handle->completionCallback)
-        {
-            handle->completionCallback(base, handle, result, handle->userData);
-        }
-    }
-}
-
-/*!
- * @brief Sets the hardware slave state machine to reset
- *
- * Per documentation, the only the state machine is reset, the configuration settings remain.
- *
- * @param base The I2C peripheral base address.
- */
-static void I2C_SlaveInternalStateMachineReset(I2C_Type *base)
-{
-    I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */
-}
-
-/*!
- * @brief Compute CLKDIV
- *
- * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency.
- * This setting is used by hardware during slave clock stretching.
- *
- * @param base The I2C peripheral base address.
- * @return status of the operation
- */
-static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal)
-{
-    uint32_t dataSetupTime_ns;
-
-    switch (busSpeed)
-    {
-        case kI2C_SlaveStandardMode:
-            dataSetupTime_ns = 250u;
-            break;
-
-        case kI2C_SlaveFastMode:
-            dataSetupTime_ns = 100u;
-            break;
-
-        case kI2C_SlaveFastModePlus:
-            dataSetupTime_ns = 50u;
-            break;
-
-        case kI2C_SlaveHsMode:
-            dataSetupTime_ns = 10u;
-            break;
-
-        default:
-            dataSetupTime_ns = 0;
-            break;
-    }
-
-    if (0 == dataSetupTime_ns)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */
-    *divVal = srcClock_Hz / 1000u;
-    *divVal = (*divVal) * dataSetupTime_ns;
-    *divVal = (*divVal) / 1000000u;
-
-    if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK)
-    {
-        *divVal = I2C_CLKDIV_DIVVAL_MASK;
-    }
-
-    return kStatus_Success;
-}
-
-/*!
- * @brief Poll wait for the SLVPENDING flag.
- *
- * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
- *
- * @param base The I2C peripheral base address.
- * @return status register at time the SLVPENDING bit is read as set
- */
-static uint32_t I2C_SlavePollPending(I2C_Type *base)
-{
-    uint32_t stat;
-
-    do
-    {
-        stat = base->STAT;
-    } while (0u == (stat & I2C_STAT_SLVPENDING_MASK));
-
-    return stat;
-}
-
-/*!
- * @brief Invoke event from I2C_SlaveTransferHandleIRQ().
- *
- * Sets the event type to transfer structure and invokes the event callback, if it has been
- * enabled by eventMask.
- *
- * @param base The I2C peripheral base address.
- * @param handle The I2C slave handle for non-blocking APIs.
- * @param event The I2C slave event to invoke.
- */
-static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event)
-{
-    handle->transfer.event = event;
-    if ((handle->callback) && (handle->transfer.eventMask & event))
-    {
-        handle->callback(base, &handle->transfer, handle->userData);
-
-        /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */
-        if (false == handle->isBusy)
-        {
-            if (((handle->transfer.txData) && (handle->transfer.txSize)) ||
-                ((handle->transfer.rxData) && (handle->transfer.rxSize)))
-            {
-                handle->isBusy = true;
-            }
-        }
-
-        /* Clear the transferred count now that we have a new buffer. */
-        if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent))
-        {
-            handle->transfer.transferredCount = 0;
-        }
-    }
-}
-
-/*!
- * @brief Handle slave address match event.
- *
- * Called by Slave interrupt routine to ACK or NACK the matched address.
- * It also determines master direction (read or write).
- *
- * @param base The I2C peripheral base address.
- * @return true if the matched address is ACK'ed
- * @return false if the matched address is NACK'ed
- */
-static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
-{
-    uint8_t addressByte0;
-
-    addressByte0 = (uint8_t)base->SLVDAT;
-
-    /* store the matched address */
-    handle->transfer.receivedAddress = addressByte0;
-
-    /* R/nW */
-    if (addressByte0 & 1u)
-    {
-        /* if we have no data in this transfer, call callback to get new */
-        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
-        {
-            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
-        }
-
-        /* NACK if we have no data in this transfer. */
-        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
-        {
-            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
-            return false;
-        }
-
-        /* master wants to read, so slave transmit is next state */
-        handle->slaveFsm = kI2C_SlaveFsmTransmit;
-    }
-    else
-    {
-        /* if we have no receive buffer in this transfer, call callback to get new */
-        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
-        {
-            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
-        }
-
-        /* NACK if we have no data in this transfer */
-        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
-        {
-            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
-            return false;
-        }
-
-        /* master wants write, so slave receive is next state */
-        handle->slaveFsm = kI2C_SlaveFsmReceive;
-    }
-
-    /* continue transaction */
-    base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-
-    return true;
-}
-
-/*!
- * @brief Starts accepting slave transfers.
- *
- * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
- * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
- * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
- * from the interrupt context.
- *
- * @param base The I2C peripheral base address.
- * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
- * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only.
- * @param txSize Size of txData buffer in bytes.
- * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL
- *               if slave TX only.
- * @param rxSize Size of rxData buffer in bytes.
- *
- * @retval #kStatus_Success Slave transfers were successfully started.
- * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
- */
-static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
-                                                     i2c_slave_handle_t *handle,
-                                                     const void *txData,
-                                                     size_t txSize,
-                                                     void *rxData,
-                                                     size_t rxSize,
-                                                     uint32_t eventMask)
-{
-    status_t status;
-
-    assert(handle);
-
-    status = kStatus_Success;
-
-    /* Disable I2C IRQ sources while we configure stuff. */
-    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
-
-    /* Return busy if another transaction is in progress. */
-    if (handle->isBusy)
-    {
-        status = kStatus_I2C_Busy;
-    }
-
-    /* Save transfer into handle. */
-    handle->transfer.txData = (const uint8_t *)(uintptr_t)txData;
-    handle->transfer.txSize = txSize;
-    handle->transfer.rxData = (uint8_t *)rxData;
-    handle->transfer.rxSize = rxSize;
-    handle->transfer.transferredCount = 0;
-    handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
-    handle->isBusy = true;
-
-    /* Set the SLVEN bit to 1 in the CFG register. */
-    I2C_SlaveEnable(base, true);
-
-    /* Clear w1c flags. */
-    base->STAT |= 0u;
-
-    /* Enable I2C internal IRQ sources. */
-    I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags);
-
-    return status;
-}
-
-status_t I2C_SlaveSetSendBuffer(
-    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask)
-{
-    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask);
-}
-
-status_t I2C_SlaveSetReceiveBuffer(
-    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask)
-{
-    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask);
-}
-
-void I2C_SlaveSetAddress(I2C_Type *base,
-                         i2c_slave_address_register_t addressRegister,
-                         uint8_t address,
-                         bool addressDisable)
-{
-    base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable);
-}
-
-void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
-{
-    assert(slaveConfig);
-
-    i2c_slave_config_t mySlaveConfig = {0};
-
-    /* default config enables slave address 0 match to general I2C call address zero */
-    mySlaveConfig.enableSlave = true;
-    mySlaveConfig.address1.addressDisable = true;
-    mySlaveConfig.address2.addressDisable = true;
-    mySlaveConfig.address3.addressDisable = true;
-
-    *slaveConfig = mySlaveConfig;
-}
-
-status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
-{
-    status_t status;
-    uint32_t divVal = 0;
-
-    /* configure data setup time used when slave stretches clock */
-    status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal);
-    if (kStatus_Success != status)
-    {
-        return status;
-    }
-
-    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
-
-    /* I2C Clock Divider register */
-    base->CLKDIV = divVal;
-
-    /* set Slave address */
-    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address,
-                        slaveConfig->address0.addressDisable);
-    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address,
-                        slaveConfig->address1.addressDisable);
-    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address,
-                        slaveConfig->address2.addressDisable);
-    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address,
-                        slaveConfig->address3.addressDisable);
-
-    /* set Slave address 0 qual */
-    base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress);
-
-    /* set Slave enable */
-    base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave);
-
-    return status;
-}
-
-void I2C_SlaveDeinit(I2C_Type *base)
-{
-    I2C_SlaveEnable(base, false);
-}
-
-status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
-{
-    const uint8_t *buf = txBuff;
-    uint32_t stat;
-    bool slaveAddress;
-    bool slaveTransmit;
-
-    /* Set the SLVEN bit to 1 in the CFG register. */
-    I2C_SlaveEnable(base, true);
-
-    /* wait for SLVPENDING */
-    stat = I2C_SlavePollPending(base);
-
-    /* Get slave machine state */
-    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
-    slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
-
-    /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */
-    if (!(slaveAddress || slaveTransmit))
-    {
-        I2C_SlaveInternalStateMachineReset(base);
-        return kStatus_Fail;
-    }
-
-    if (slaveAddress)
-    {
-        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
-        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-
-        /* wait for SLVPENDING */
-        stat = I2C_SlavePollPending(base);
-    }
-
-    /* send bytes up to txSize */
-    while (txSize)
-    {
-        slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
-
-        if (!slaveTransmit)
-        {
-            I2C_SlaveInternalStateMachineReset(base);
-            return kStatus_Fail;
-        }
-
-        /* Write 8 bits of data to the SLVDAT register */
-        base->SLVDAT = I2C_SLVDAT_DATA(*buf);
-
-        /* continue transaction */
-        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-
-        /* advance counters and pointers for next data */
-        buf++;
-        txSize--;
-
-        if (txSize)
-        {
-            /* wait for SLVPENDING */
-            stat = I2C_SlavePollPending(base);
-        }
-    }
-
-    return kStatus_Success;
-}
-
-status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
-{
-    uint8_t *buf = rxBuff;
-    uint32_t stat;
-    bool slaveAddress;
-    bool slaveReceive;
-
-    /* Set the SLVEN bit to 1 in the CFG register. */
-    I2C_SlaveEnable(base, true);
-
-    /* wait for SLVPENDING */
-    stat = I2C_SlavePollPending(base);
-
-    /* Get slave machine state */
-    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
-    slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
-
-    /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */
-    if (!(slaveAddress || slaveReceive))
-    {
-        I2C_SlaveInternalStateMachineReset(base);
-        return kStatus_Fail;
-    }
-
-    if (slaveAddress)
-    {
-        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
-        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-
-        /* wait for SLVPENDING */
-        stat = I2C_SlavePollPending(base);
-    }
-
-    /* receive bytes up to rxSize */
-    while (rxSize)
-    {
-        slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
-
-        if (!slaveReceive)
-        {
-            I2C_SlaveInternalStateMachineReset(base);
-            return kStatus_Fail;
-        }
-
-        /* Read 8 bits of data from the SLVDAT register */
-        *buf = (uint8_t)base->SLVDAT;
-
-        /* continue transaction */
-        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-
-        /* advance counters and pointers for next data */
-        buf++;
-        rxSize--;
-
-        if (rxSize)
-        {
-            /* wait for SLVPENDING */
-            stat = I2C_SlavePollPending(base);
-        }
-    }
-
-    return kStatus_Success;
-}
-
-void I2C_SlaveTransferCreateHandle(I2C_Type *base,
-                                   i2c_slave_handle_t *handle,
-                                   i2c_slave_transfer_callback_t callback,
-                                   void *userData)
-{
-    uint32_t instance;
-
-    assert(handle);
-
-    /* Clear out the handle. */
-    memset(handle, 0, sizeof(*handle));
-
-    /* Look up instance number */
-    instance = I2C_GetInstance(base);
-
-    /* Save base and instance. */
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* initialize fsm */
-    handle->slaveFsm = kI2C_SlaveFsmAddressMatch;
-
-    /* store pointer to handle into transfer struct */
-    handle->transfer.handle = handle;
-
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle);
-
-    /* Clear internal IRQ enables and enable NVIC IRQ. */
-    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
-    EnableIRQ(s_i2cIRQ[instance]);
-}
-
-status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
-{
-    return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask);
-}
-
-status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Catch when there is not an active transfer. */
-    if (!handle->isBusy)
-    {
-        *count = 0;
-        return kStatus_NoTransferInProgress;
-    }
-
-    /* For an active transfer, just return the count from the handle. */
-    *count = handle->transfer.transferredCount;
-
-    return kStatus_Success;
-}
-
-void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
-{
-    /* Disable I2C IRQ sources while we configure stuff. */
-    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
-
-    /* Set the SLVEN bit to 0 in the CFG register. */
-    I2C_SlaveEnable(base, false);
-
-    handle->isBusy = false;
-    handle->transfer.txSize = 0;
-    handle->transfer.rxSize = 0;
-}
-
-void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
-{
-    uint32_t i2cStatus = base->STAT;
-
-    if (i2cStatus & I2C_STAT_SLVDESEL_MASK)
-    {
-        I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent);
-        I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK);
-    }
-
-    /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */
-    if (i2cStatus & I2C_STAT_SLVPENDING_MASK)
-    {
-        bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
-
-        if (slaveAddress)
-        {
-            I2C_SlaveAddressIRQ(base, handle);
-            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent);
-        }
-        else
-        {
-            switch (handle->slaveFsm)
-            {
-                case kI2C_SlaveFsmReceive:
-                {
-                    bool slaveReceive =
-                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
-
-                    if (slaveReceive)
-                    {
-                        /* if we have no receive buffer in this transfer, call callback to get new */
-                        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
-                        {
-                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
-                        }
-
-                        /* receive a byte */
-                        if ((handle->transfer.rxData) && (handle->transfer.rxSize))
-                        {
-                            *(handle->transfer.rxData) = (uint8_t)base->SLVDAT;
-                            (handle->transfer.rxSize)--;
-                            (handle->transfer.rxData)++;
-                            (handle->transfer.transferredCount)++;
-
-                            /* continue transaction */
-                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-                        }
-
-                        /* is this last transaction for this transfer? allow next transaction */
-                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
-                        {
-                            handle->isBusy = false;
-                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
-                        }
-                    }
-                    else
-                    {
-                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
-                    }
-                }
-                break;
-
-                case kI2C_SlaveFsmTransmit:
-                {
-                    bool slaveTransmit =
-                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
-
-                    if (slaveTransmit)
-                    {
-                        /* if we have no data in this transfer, call callback to get new */
-                        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
-                        {
-                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
-                        }
-
-                        /* transmit a byte */
-                        if ((handle->transfer.txData) && (handle->transfer.txSize))
-                        {
-                            base->SLVDAT = *(handle->transfer.txData);
-                            (handle->transfer.txSize)--;
-                            (handle->transfer.txData)++;
-                            (handle->transfer.transferredCount)++;
-
-                            /* continue transaction */
-                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
-                        }
-
-                        /* is this last transaction for this transfer? allow next transaction */
-                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
-                        {
-                            handle->isBusy = false;
-                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
-                        }
-                    }
-                    else
-                    {
-                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
-                    }
-                }
-                break;
-
-                default:
-                    /* incorrect state, slv_abort()? */
-                    break;
-            }
-        }
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1039 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_I2C_H_
-#define _FSL_I2C_H_
-
-#include <stddef.h>
-#include "fsl_device_registers.h"
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-#define I2C_CFG_MASK 0x1f
-
-/*!
- * @addtogroup i2c_driver
- * @{
- */
-
-/*! @file */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief I2C driver version 1.0.0. */
-#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
-/*@}*/
-
-/* definitions for MSTCODE bits in I2C Status register STAT */
-#define I2C_STAT_MSTCODE_IDLE (0)    /*!< Master Idle State Code */
-#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
-#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
-#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
-#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
-
-/* definitions for SLVSTATE bits in I2C Status register STAT */
-#define I2C_STAT_SLVST_ADDR (0)
-#define I2C_STAT_SLVST_RX (1)
-#define I2C_STAT_SLVST_TX (2)
-
-/*! @brief I2C status return codes. */
-enum _i2c_status
-{
-    kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */
-    kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */
-    kStatus_I2C_Nak =
-        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */
-    kStatus_I2C_InvalidParameter =
-        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */
-    kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */
-    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */
-    kStatus_I2C_NoTransferInProgress =
-        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
-    kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
-    kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
-    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
-};
-
-/*! @} */
-
-/*!
- * @addtogroup i2c_master_driver
- * @{
- */
-
-/*!
- * @brief I2C master peripheral flags.
- *
- * @note These enums are meant to be OR'd together to form a bit mask.
- */
-enum _i2c_master_flags
-{
-    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
-    kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
-    kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
-};
-
-/*! @brief Direction of master and slave transfers. */
-typedef enum _i2c_direction
-{
-    kI2C_Write = 0U, /*!< Master transmit. */
-    kI2C_Read = 1U   /*!< Master receive. */
-} i2c_direction_t;
-
-/*!
- * @brief Structure with settings to initialize the I2C master module.
- *
- * This structure holds configuration settings for the I2C peripheral. To initialize this
- * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and
- * pass a pointer to your configuration structure instance.
- *
- * The configuration structure can be made constant so it resides in flash.
- */
-typedef struct _i2c_master_config
-{
-    bool enableMaster;     /*!< Whether to enable master mode. */
-    uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */
-    bool enableTimeout;    /*!< Enable internal timeout function. */
-} i2c_master_config_t;
-
-/* Forward declaration of the transfer descriptor and handle typedefs. */
-/*! @brief I2C master transfer typedef */
-typedef struct _i2c_master_transfer i2c_master_transfer_t;
-
-/*! @brief I2C master handle typedef */
-typedef struct _i2c_master_handle i2c_master_handle_t;
-
-/*!
- * @brief Master completion callback function pointer type.
- *
- * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use
- * in the call to I2C_MasterTransferCreateHandle().
- *
- * @param base The I2C peripheral base address.
- * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
- * @param userData Arbitrary pointer-sized value passed from the application.
- */
-typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
-                                               i2c_master_handle_t *handle,
-                                               status_t completionStatus,
-                                               void *userData);
-
-/*!
- * @brief Transfer option flags.
- *
- * @note These enumerations are intended to be OR'd together to form a bit mask of options for
- * the #_i2c_master_transfer::flags field.
- */
-enum _i2c_master_transfer_flags
-{
-    kI2C_TransferDefaultFlag = 0x00U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
-    kI2C_TransferNoStartFlag = 0x01U,       /*!< Don't send a start condition, address, and sub address */
-    kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
-    kI2C_TransferNoStopFlag = 0x04U,        /*!< Don't send a stop condition. */
-};
-
-/*! @brief States for the state machine used by transactional APIs. */
-enum _i2c_transfer_states
-{
-    kIdleState = 0,
-    kTransmitSubaddrState,
-    kTransmitDataState,
-    kReceiveDataState,
-    kReceiveLastDataState,
-    kStartState,
-    kStopState,
-    kWaitForCompletionState
-};
-
-/*!
- * @brief Non-blocking transfer descriptor structure.
- *
- * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API.
- */
-struct _i2c_master_transfer
-{
-    uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available
-                       options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */
-    uint16_t slaveAddress;     /*!< The 7-bit slave address. */
-    i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */
-    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
-    size_t subaddressSize;     /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
-    void *data;                /*!< Pointer to data to transfer. */
-    size_t dataSize;           /*!< Number of bytes to transfer. */
-};
-
-/*!
- * @brief Driver handle for master non-blocking APIs.
- * @note The contents of this structure are private and subject to change.
- */
-struct _i2c_master_handle
-{
-    uint8_t state;           /*!< Transfer state machine current state. */
-    uint32_t transferCount;  /*!< Indicates progress of the transfer */
-    uint32_t remainingBytes; /*!< Remaining byte count in current state. */
-    uint8_t *buf;            /*!< Buffer pointer for current state. */
-    uint32_t remainingSubaddr;
-    uint8_t subaddrBuf[4];
-    i2c_master_transfer_t transfer;                    /*!< Copy of the current transfer info. */
-    i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */
-    void *userData;                                    /*!< Application data passed to callback. */
-};
-
-/*! @} */
-
-/*!
- * @addtogroup i2c_slave_driver
- * @{
- */
-
- /*!
- * @brief I2C slave peripheral flags.
- *
- * @note These enums are meant to be OR'd together to form a bit mask.
- */
-enum _i2c_slave_flags
-{
-    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
-    kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
-    kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
-    kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
-};
- 
-/*! @brief I2C slave address register. */
-typedef enum _i2c_slave_address_register
-{
-    kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */
-    kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */
-    kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */
-    kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */
-} i2c_slave_address_register_t;
-
-/*! @brief Data structure with 7-bit Slave address and Slave address disable. */
-typedef struct _i2c_slave_address
-{
-    uint8_t address;     /*!< 7-bit Slave address SLVADR. */
-    bool addressDisable; /*!< Slave address disable SADISABLE. */
-} i2c_slave_address_t;
-
-/*! @brief I2C slave address match options. */
-typedef enum _i2c_slave_address_qual_mode
-{
-    kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */
-    kI2C_QualModeExtend =
-        1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */
-} i2c_slave_address_qual_mode_t;
-
-/*! @brief I2C slave bus speed options. */
-typedef enum _i2c_slave_bus_speed
-{
-    kI2C_SlaveStandardMode = 0U,
-    kI2C_SlaveFastMode = 1U,
-    kI2C_SlaveFastModePlus = 2U,
-    kI2C_SlaveHsMode = 3U,
-} i2c_slave_bus_speed_t;
-
-/*!
- * @brief Structure with settings to initialize the I2C slave module.
- *
- * This structure holds configuration settings for the I2C slave peripheral. To initialize this
- * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and
- * pass a pointer to your configuration structure instance.
- *
- * The configuration structure can be made constant so it resides in flash.
- */
-typedef struct _i2c_slave_config
-{
-    i2c_slave_address_t address0;           /*!< Slave's 7-bit address and disable. */
-    i2c_slave_address_t address1;           /*!< Alternate slave 7-bit address and disable. */
-    i2c_slave_address_t address2;           /*!< Alternate slave 7-bit address and disable. */
-    i2c_slave_address_t address3;           /*!< Alternate slave 7-bit address and disable. */
-    i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */
-    uint8_t qualAddress;                    /*!< Slave address qualifier for address 0. */
-    i2c_slave_bus_speed_t
-        busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must
-                       provide sufficient data setup time to the master before releasing the stretched clock.
-                       This is accomplished by inserting one clock time of CLKDIV at that point.
-                       The #busSpeed value is used to configure CLKDIV
-                       such that one clock time is greater than the tSU;DAT value noted
-                       in the I2C bus specification for the I2C mode that is being used.
-                       If the #busSpeed mode is unknown at compile time, use the longest data setup time
-                       kI2C_SlaveStandardMode (250 ns) */
-    bool enableSlave; /*!< Enable slave mode. */
-} i2c_slave_config_t;
-
-/*!
- * @brief Set of events sent to the callback for non blocking slave transfers.
- *
- * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
- * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
- * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
- * parameter.
- *
- * @note These enumerations are meant to be OR'd together to form a bit mask of events.
- */
-typedef enum _i2c_slave_transfer_event
-{
-    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
-    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
-                                                (slave-transmitter role). */
-    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
-                                                 data (slave-receiver role). */
-    kI2C_SlaveCompletionEvent = 0x20U,   /*!< All data in the active transfer have been consumed. */
-    kI2C_SlaveDeselectedEvent =
-        0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */
-
-    /*! Bit mask of all available events. */
-    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
-                          kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent,
-} i2c_slave_transfer_event_t;
-
-/*! @brief I2C slave handle typedef. */
-typedef struct _i2c_slave_handle i2c_slave_handle_t;
-
-/*! @brief I2C slave transfer structure */
-typedef struct _i2c_slave_transfer
-{
-    i2c_slave_handle_t *handle;       /*!< Pointer to handle that contains this transfer. */
-    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
-    uint8_t receivedAddress;          /*!< Matching address send by master. 7-bits plus R/nW bit0 */
-    uint32_t eventMask;               /*!< Mask of enabled events. */
-    uint8_t *rxData;                  /*!< Transfer buffer for receive data */
-    const uint8_t *txData;            /*!< Transfer buffer for transmit data */
-    size_t txSize;                    /*!< Transfer size */
-    size_t rxSize;                    /*!< Transfer size */
-    size_t transferredCount;          /*!< Number of bytes transferred during this transfer. */
-    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
-                                         #kI2C_SlaveCompletionEvent. */
-} i2c_slave_transfer_t;
-
-/*!
- * @brief Slave event callback function pointer type.
- *
- * This callback is used only for the slave non-blocking transfer API. To install a callback,
- * use the I2C_SlaveSetCallback() function after you have created a handle.
- *
- * @param base Base address for the I2C instance on which the event occurred.
- * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
- * @param userData Arbitrary pointer-sized value passed from the application.
- */
-typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData);
-
-/*!
- * @brief I2C slave software finite state machine states.
- */
-typedef enum _i2c_slave_fsm
-{
-    kI2C_SlaveFsmAddressMatch = 0u,
-    kI2C_SlaveFsmReceive = 2u,
-    kI2C_SlaveFsmTransmit = 3u,
-} i2c_slave_fsm_t;
-
-/*!
- * @brief I2C slave handle structure.
- * @note The contents of this structure are private and subject to change.
- */
-struct _i2c_slave_handle
-{
-    volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */
-    volatile bool isBusy;                   /*!< Whether transfer is busy. */
-    volatile i2c_slave_fsm_t slaveFsm;      /*!< slave transfer state machine. */
-    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
-    void *userData;                         /*!< Callback parameter passed to callback. */
-};
-
-/*! @} */
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @addtogroup i2c_master_driver
- * @{
- */
-
-/*! @name Initialization and deinitialization */
-/*@{*/
-
-/*!
- * @brief Provides a default configuration for the I2C master peripheral.
- *
- * This function provides the following default configuration for the I2C master peripheral:
- * @code
- *  masterConfig->enableMaster            = true;
- *  masterConfig->baudRate_Bps            = 100000U;
- *  masterConfig->enableTimeout           = false;
- * @endcode
- *
- * After calling this function, you can override any settings in order to customize the configuration,
- * prior to initializing the master driver with I2C_MasterInit().
- *
- * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t.
- */
-void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
-
-/*!
- * @brief Initializes the I2C master peripheral.
- *
- * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user
- * provided configuration. A software reset is performed prior to configuration.
- *
- * @param base The I2C peripheral base address.
- * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of
- * defaults
- *      that you can override.
- * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors,
- *      filter widths, and timeout periods.
- */
-void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
-
-/*!
-* @brief Deinitializes the I2C master peripheral.
-*
- * This function disables the I2C master peripheral and gates the clock. It also performs a software
- * reset to restore the peripheral to reset conditions.
- *
- * @param base The I2C peripheral base address.
- */
-void I2C_MasterDeinit(I2C_Type *base);
-
-/*!
- * @brief Performs a software reset.
- *
- * Restores the I2C master peripheral to reset conditions.
- *
- * @param base The I2C peripheral base address.
- */
-static inline void I2C_MasterReset(I2C_Type *base)
-{
-}
-
-/*!
- * @brief Enables or disables the I2C module as master.
- *
- * @param base The I2C peripheral base address.
- * @param enable Pass true to enable or false to disable the specified I2C as master.
- */
-static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
-    }
-    else
-    {
-        base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
-    }
-}
-
-/*@}*/
-
-/*! @name Status */
-/*@{*/
-
-/*!
- * @brief Gets the I2C status flags.
- *
- * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit
- * in the return value is set if the flag is asserted.
- *
- * @param base The I2C peripheral base address.
- * @return State of the status flags:
- *         - 1: related status flag is set.
- *         - 0: related status flag is not set.
- * @see _i2c_master_flags
- */
-static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
-{
-    return base->STAT;
-}
-
-/*!
- * @brief Clears the I2C master status flag state.
- *
- * The following status register flags can be cleared:
- * - #kI2C_MasterArbitrationLostFlag
- * - #kI2C_MasterStartStopErrorFlag
- *
- * Attempts to clear other flags has no effect.
- *
- * @param base The I2C peripheral base address.
- * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
- *  #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to
- *  I2C_GetStatusFlags().
- * @see _i2c_master_flags.
- */
-static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
-{
-    /* Allow clearing just master status flags */
-    base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-}
-
-/*@}*/
-
-/*! @name Interrupts */
-/*@{*/
-
-/*!
- * @brief Enables the I2C master interrupt requests.
- *
- * @param base The I2C peripheral base address.
- * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set
- *      of constants that should be OR'd together to form the bit mask.
- */
-static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
-{
-    base->INTENSET = interruptMask;
-}
-
-/*!
- * @brief Disables the I2C master interrupt requests.
- *
- * @param base The I2C peripheral base address.
- * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set
- *      of constants that should be OR'd together to form the bit mask.
- */
-static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
-{
-    base->INTENCLR = interruptMask;
-}
-
-/*!
- * @brief Returns the set of currently enabled I2C master interrupt requests.
- *
- * @param base The I2C peripheral base address.
- * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the
- *      set of enabled interrupts.
- */
-static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
-{
-    return base->INTSTAT;
-}
-
-/*@}*/
-
-/*! @name Bus operations */
-/*@{*/
-
-/*!
- * @brief Sets the I2C bus frequency for master transactions.
- *
- * The I2C master is automatically disabled and re-enabled as necessary to configure the baud
- * rate. Do not call this function during a transfer, or the transfer is aborted.
- *
- * @param base The I2C peripheral base address.
- * @param srcClock_Hz I2C functional clock frequency in Hertz.
- * @param baudRate_Bps Requested bus frequency in bits per second.
- */
-void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
-
-/*!
- * @brief Returns whether the bus is idle.
- *
- * Requires the master mode to be enabled.
- *
- * @param base The I2C peripheral base address.
- * @retval true Bus is busy.
- * @retval false Bus is idle.
- */
-static inline bool I2C_MasterGetBusIdleState(I2C_Type *base)
-{
-    /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */
-    return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK);
-}
-
-/*!
- * @brief Sends a START on the I2C bus.
- *
- * This function is used to initiate a new master mode transfer by sending the START signal.
- * The slave address is sent following the I2C START signal.
- *
- * @param base I2C peripheral base pointer
- * @param address 7-bit slave device address.
- * @param direction Master transfer directions(transmit/receive).
- * @retval kStatus_Success Successfully send the start signal.
- * @retval kStatus_I2C_Busy Current bus is busy.
- */
-status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
-
-/*!
- * @brief Sends a STOP signal on the I2C bus.
- *
- * @retval kStatus_Success Successfully send the stop signal.
- * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
- */
-status_t I2C_MasterStop(I2C_Type *base);
-
-/*!
- * @brief Sends a REPEATED START on the I2C bus.
- *
- * @param base I2C peripheral base pointer
- * @param address 7-bit slave device address.
- * @param direction Master transfer directions(transmit/receive).
- * @retval kStatus_Success Successfully send the start signal.
- * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
- */
-static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
-{
-    return I2C_MasterStart(base, address, direction);
-}
-
-/*!
- * @brief Performs a polling send transfer on the I2C bus.
- *
- * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
- * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
- * function returns #kStatus_I2C_Nak.
- *
- * @param base  The I2C peripheral base address.
- * @param txBuff The pointer to the data to be transferred.
- * @param txSize The length in bytes of the data to be transferred.
- * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
- * @retval kStatus_Success Data was sent successfully.
- * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
- * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
- * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
- */
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
-
-/*!
- * @brief Performs a polling receive transfer on the I2C bus.
- *
- * @param base  The I2C peripheral base address.
- * @param rxBuff The pointer to the data to be transferred.
- * @param rxSize The length in bytes of the data to be transferred.
- * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
- * @retval kStatus_Success Data was received successfully.
- * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
- * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
- * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
- */
-status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
-
-/*!
- * @brief Performs a master polling transfer on the I2C bus.
- *
- * @note The API does not return until the transfer succeeds or fails due
- * to arbitration lost or receiving a NAK.
- *
- * @param base I2C peripheral base address.
- * @param xfer Pointer to the transfer structure.
- * @retval kStatus_Success Successfully complete the data transmission.
- * @retval kStatus_I2C_Busy Previous transmission still not finished.
- * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
- * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
- * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
- */
-status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
-
-/*@}*/
-
-/*! @name Non-blocking */
-/*@{*/
-
-/*!
- * @brief Creates a new handle for the I2C master non-blocking APIs.
- *
- * The creation of a handle is for use with the non-blocking APIs. Once a handle
- * is created, there is not a corresponding destroy handle. If the user wants to
- * terminate a transfer, the I2C_MasterTransferAbort() API shall be called.
- *
- * @param base The I2C peripheral base address.
- * @param[out] handle Pointer to the I2C master driver handle.
- * @param callback User provided pointer to the asynchronous callback function.
- * @param userData User provided pointer to the application callback data.
- */
-void I2C_MasterTransferCreateHandle(I2C_Type *base,
-                                    i2c_master_handle_t *handle,
-                                    i2c_master_transfer_callback_t callback,
-                                    void *userData);
-
-/*!
- * @brief Performs a non-blocking transaction on the I2C bus.
- *
- * @param base The I2C peripheral base address.
- * @param handle Pointer to the I2C master driver handle.
- * @param xfer The pointer to the transfer descriptor.
- * @retval kStatus_Success The transaction was started successfully.
- * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking
- *      transaction is already in progress.
- */
-status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
-
-/*!
- * @brief Returns number of bytes transferred so far.
- * @param base The I2C peripheral base address.
- * @param handle Pointer to the I2C master driver handle.
- * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
- * @retval kStatus_Success
- * @retval #kStatus_I2C_Busy
- */
-status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
-
-/*!
- * @brief Terminates a non-blocking I2C master transmission early.
- *
- * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
- *      I2C peripheral's IRQ priority.
- *
- * @param base The I2C peripheral base address.
- * @param handle Pointer to the I2C master driver handle.
- * @retval kStatus_Success A transaction was successfully aborted.
- * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress.
- */
-void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
-
-/*@}*/
-
-/*! @name IRQ handler */
-/*@{*/
-
-/*!
- * @brief Reusable routine to handle master interrupts.
- * @note This function does not need to be called unless you are reimplementing the
- *  nonblocking API's interrupt handler routines to add special functionality.
- * @param base The I2C peripheral base address.
- * @param handle Pointer to the I2C master driver handle.
- */
-void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle);
-
-/*@}*/
-
-/*! @} */ /* end of i2c_master_driver */
-
-/*!
- * @addtogroup i2c_slave_driver
- * @{
- */
-
-/*! @name Slave initialization and deinitialization */
-/*@{*/
-
-/*!
- * @brief Provides a default configuration for the I2C slave peripheral.
- *
- * This function provides the following default configuration for the I2C slave peripheral:
- * @code
- *  slaveConfig->enableSlave = true;
- *  slaveConfig->address0.disable = false;
- *  slaveConfig->address0.address = 0u;
- *  slaveConfig->address1.disable = true;
- *  slaveConfig->address2.disable = true;
- *  slaveConfig->address3.disable = true;
- *  slaveConfig->busSpeed = kI2C_SlaveStandardMode;
- * @endcode
- *
- * After calling this function, override any settings  to customize the configuration,
- * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a
- * address0.address member of the configuration structure with the desired slave address.
- *
- * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
- *      #i2c_slave_config_t.
- */
-void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
-
-/*!
- * @brief Initializes the I2C slave peripheral.
- *
- * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user
- * provided configuration.
- *
- * @param base The I2C peripheral base address.
- * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults
- *      that you can override.
- * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide
- * enough
- *                       data setup time for master when slave stretches the clock.
- */
-status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
-
-/*!
- * @brief Configures Slave Address n register.
- *
- * This function writes new value to Slave Address register.
- *
- * @param base The I2C peripheral base address.
- * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed.
- * @param address The slave address to be stored to the address register for matching.
- * @param addressDisable Disable matching of the specified address register.
-  */
-void I2C_SlaveSetAddress(I2C_Type *base,
-                         i2c_slave_address_register_t addressRegister,
-                         uint8_t address,
-                         bool addressDisable);
-
-/*!
-* @brief Deinitializes the I2C slave peripheral.
-*
- * This function disables the I2C slave peripheral and gates the clock. It also performs a software
- * reset to restore the peripheral to reset conditions.
- *
- * @param base The I2C peripheral base address.
- */
-void I2C_SlaveDeinit(I2C_Type *base);
-
-/*!
- * @brief Enables or disables the I2C module as slave.
- *
- * @param base The I2C peripheral base address.
- * @param enable True to enable or flase to disable.
- */
-static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)
-{
-    /* Set or clear the SLVEN bit in the CFG register. */
-    base->CFG = I2C_CFG_SLVEN(enable);
-}
-
-/*@}*/ /* end of Slave initialization and deinitialization */
-
-/*! @name Slave status */
-/*@{*/
-
-/*!
- * @brief Clears the I2C status flag state.
- *
- * The following status register flags can be cleared:
- * - slave deselected flag
- *
- * Attempts to clear other flags has no effect.
- *
- * @param base The I2C peripheral base address.
- * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
- *  #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
- *  I2C_SlaveGetStatusFlags().
- * @see _i2c_slave_flags.
- */
-static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
-{
-    /* Allow clearing just slave status flags */
-    base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK;
-}
-
-/*@}*/ /* end of Slave status */
-
-/*! @name Slave bus operations */
-/*@{*/
-
-/*!
- * @brief Performs a polling send transfer on the I2C bus.
- *
- * The function executes blocking address phase and blocking data phase.
- *
- * @param base  The I2C peripheral base address.
- * @param txBuff The pointer to the data to be transferred.
- * @param txSize The length in bytes of the data to be transferred.
- * @return kStatus_Success Data has been sent.
- * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected).
- */
-status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
-
-/*!
- * @brief Performs a polling receive transfer on the I2C bus.
- *
- * The function executes blocking address phase and blocking data phase.
- *
- * @param base  The I2C peripheral base address.
- * @param rxBuff The pointer to the data to be transferred.
- * @param rxSize The length in bytes of the data to be transferred.
- * @return kStatus_Success Data has been received.
- * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected).
- */
-status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
-
-/*@}*/ /* end of Slave bus operations */
-
-/*! @name Slave non-blocking */
-/*@{*/
-
-/*!
- * @brief Creates a new handle for the I2C slave non-blocking APIs.
- *
- * The creation of a handle is for use with the non-blocking APIs. Once a handle
- * is created, there is not a corresponding destroy handle. If the user wants to
- * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called.
- *
- * @param base The I2C peripheral base address.
- * @param[out] handle Pointer to the I2C slave driver handle.
- * @param callback User provided pointer to the asynchronous callback function.
- * @param userData User provided pointer to the application callback data.
- */
-void I2C_SlaveTransferCreateHandle(I2C_Type *base,
-                                   i2c_slave_handle_t *handle,
-                                   i2c_slave_transfer_callback_t callback,
-                                   void *userData);
-
-/*!
- * @brief Starts accepting slave transfers.
- *
- * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
- * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
- * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
- * from the interrupt context.
- *
- * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback.
- * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback.
- *
- * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
- * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
- * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
- * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
- * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
- * a convenient way to enable all events.
- *
- * @param base The I2C peripheral base address.
- * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
- * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
- *      which events to send to the callback. Other accepted values are 0 to get a default set of
- *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
- *
- * @retval kStatus_Success Slave transfers were successfully started.
- * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
- */
-status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
-
-/*!
- * @brief Starts accepting master read from slave requests.
- *
- * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer
- * from within the transfer callback.
- *
- * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
- * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
- * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
- * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
- * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
- * a convenient way to enable all events.
- *
- * @param base The I2C peripheral base address.
- * @param transfer Pointer to #i2c_slave_transfer_t structure.
- * @param txData Pointer to data to send to master.
- * @param txSize Size of txData in bytes.
- * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
- *      which events to send to the callback. Other accepted values are 0 to get a default set of
- *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
- *
- * @retval kStatus_Success Slave transfers were successfully started.
- * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
- */
-status_t I2C_SlaveSetSendBuffer(
-    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask);
-
-/*!
- * @brief Starts accepting master write to slave requests.
-  *
- * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer
- * from within the transfer callback.
- *
- * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
- * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
- * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
- * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
- * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
- * a convenient way to enable all events.
- *
- * @param base The I2C peripheral base address.
- * @param transfer Pointer to #i2c_slave_transfer_t structure.
- * @param rxData Pointer to data to store data from master.
- * @param rxSize Size of rxData in bytes.
- * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
- *      which events to send to the callback. Other accepted values are 0 to get a default set of
- *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
- *
- * @retval kStatus_Success Slave transfers were successfully started.
- * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
- */
-status_t I2C_SlaveSetReceiveBuffer(
-    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask);
-
-/*!
- * @brief Returns the slave address sent by the I2C master.
- *
- * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent.
- *
- * @param base The I2C peripheral base address.
- * @param transfer The I2C slave transfer.
- * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and
- *      the 7-bit slave address is in the upper 7 bits.
- */
-static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer)
-{
-    return transfer->receivedAddress;
-}
-
-/*!
- * @brief Aborts the slave non-blocking transfers.
- * @note This API could be called at any time to stop slave for handling the bus events.
- * @param base The I2C peripheral base address.
- * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
- * @retval kStatus_Success
- * @retval #kStatus_I2C_Idle
- */
-void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
-
-/*!
- * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
- *
- * @param base I2C base pointer.
- * @param handle pointer to i2c_slave_handle_t structure.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
- * @retval kStatus_InvalidArgument count is Invalid.
- * @retval kStatus_Success Successfully return the count.
- */
-status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
-
-/*@}*/ /* end of Slave non-blocking */
-
-/*! @name Slave IRQ handler */
-/*@{*/
-
-/*!
- * @brief Reusable routine to handle slave interrupts.
- * @note This function does not need to be called unless you are reimplementing the
- *  non blocking API's interrupt handler routines to add special functionality.
- * @param base The I2C peripheral base address.
- * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
- */
-void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
-
-/*@}*/ /* end of Slave IRQ handler */
-
-/*! @} */ /* end of i2c_slave_driver */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* _FSL_I2C_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,579 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_i2c_dma.h"
-#include "fsl_flexcomm.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
-typedef struct _i2c_master_dma_private_handle
-{
-    I2C_Type *base;
-    i2c_master_dma_handle_t *handle;
-} i2c_master_dma_private_handle_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief DMA callback for I2C master DMA driver.
- *
- * @param handle DMA handler for I2C master DMA driver
- * @param userData user param passed to the callback function
- */
-static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
-
-/*!
- * @brief Set up master transfer, send slave address and sub address(if any), wait until the
- * wait until address sent status return.
- *
- * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
- * @param xfer pointer to i2c_master_transfer_t structure.
- */
-static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
-                                                i2c_master_dma_handle_t *handle,
-                                                i2c_master_transfer_t *xfer);
-
-/*!
- * @brief Get the I2C instance from peripheral base address.
- *
- * @param base I2C peripheral base address.
- * @return I2C instance.
- */
-extern uint32_t I2C_GetInstance(I2C_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*<! Private handle only used for internally. */
-static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
-
-/*! @brief IRQ name array */
-static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
-
-/*******************************************************************************
- * Codes
- ******************************************************************************/
-
-/*!
- * @brief Prepares the transfer state machine and fills in the command buffer.
- * @param handle Master nonblocking driver handle.
- */
-static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
-                                                i2c_master_dma_handle_t *handle,
-                                                i2c_master_transfer_t *xfer)
-{
-    struct _i2c_master_transfer *transfer;
-
-    handle->transfer = *xfer;
-    transfer = &(handle->transfer);
-
-    handle->transferCount = 0;
-    handle->remainingBytesDMA = 0;
-    handle->buf = (uint8_t *)transfer->data;
-    handle->remainingSubaddr = 0;
-
-    if (transfer->flags & kI2C_TransferNoStartFlag)
-    {
-        /* Start condition shall be ommited, switch directly to next phase */
-        if (transfer->dataSize == 0)
-        {
-            handle->state = kStopState;
-        }
-        else if (handle->transfer.direction == kI2C_Write)
-        {
-            handle->state = xfer->dataSize = kTransmitDataState;
-        }
-        else if (handle->transfer.direction == kI2C_Read)
-        {
-            handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
-        }
-        else
-        {
-            return kStatus_I2C_InvalidParameter;
-        }
-    }
-    else
-    {
-        if (transfer->subaddressSize != 0)
-        {
-            int i;
-            uint32_t subaddress;
-
-            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
-            {
-                return kStatus_I2C_InvalidParameter;
-            }
-
-            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
-            subaddress = xfer->subaddress;
-            for (i = xfer->subaddressSize - 1; i >= 0; i--)
-            {
-                handle->subaddrBuf[i] = subaddress & 0xff;
-                subaddress >>= 8;
-            }
-            handle->remainingSubaddr = transfer->subaddressSize;
-        }
-
-        handle->state = kStartState;
-    }
-
-    return kStatus_Success;
-}
-
-static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
-{
-    int transfer_size;
-    dma_transfer_config_t xferConfig;
-
-    /* Update transfer count */
-    handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
-
-    /* Check if there is anything to be transferred at all */
-    if (handle->remainingBytesDMA == 0)
-    {
-        /* No data to be transferrred, disable DMA */
-        base->MSTCTL = 0;
-        return;
-    }
-
-    /* Calculate transfer size */
-    transfer_size = handle->remainingBytesDMA;
-    if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
-    {
-        transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
-    }
-
-    switch (handle->transfer.direction)
-    {
-        case kI2C_Write:
-            DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
-                                kDMA_MemoryToPeripheral, NULL);
-            break;
-
-        case kI2C_Read:
-            DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
-                                kDMA_PeripheralToMemory, NULL);
-            break;
-
-        default:
-            /* This should never happen */
-            assert(0);
-            break;
-    }
-
-    DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-    DMA_StartTransfer(handle->dmaHandle);
-
-    handle->remainingBytesDMA -= transfer_size;
-    handle->buf += transfer_size;
-}
-
-/*!
- * @brief Execute states until the transfer is done.
- * @param handle Master nonblocking driver handle.
- * @param[out] isDone Set to true if the transfer has completed.
- * @retval #kStatus_Success
- * @retval #kStatus_I2C_ArbitrationLost
- * @retval #kStatus_I2C_Nak
- */
-static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
-{
-    uint32_t status;
-    uint32_t master_state;
-    struct _i2c_master_transfer *transfer;
-    dma_transfer_config_t xferConfig;
-    status_t err;
-    uint32_t start_flag = 0;
-
-    transfer = &(handle->transfer);
-
-    *isDone = false;
-
-    status = I2C_GetStatusFlags(base);
-
-    if (status & I2C_STAT_MSTARBLOSS_MASK)
-    {
-        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
-        DMA_AbortTransfer(handle->dmaHandle);
-        base->MSTCTL = 0;
-        return kStatus_I2C_ArbitrationLost;
-    }
-
-    if (status & I2C_STAT_MSTSTSTPERR_MASK)
-    {
-        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
-        DMA_AbortTransfer(handle->dmaHandle);
-        base->MSTCTL = 0;
-        return kStatus_I2C_StartStopError;
-    }
-
-    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
-    {
-        return kStatus_I2C_Busy;
-    }
-
-    /* Get the state of the I2C module */
-    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-
-    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
-    {
-        /* Slave NACKed last byte, issue stop and return error */
-        DMA_AbortTransfer(handle->dmaHandle);
-        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-        handle->state = kWaitForCompletionState;
-        return kStatus_I2C_Nak;
-    }
-
-    err = kStatus_Success;
-
-    if (handle->state == kStartState)
-    {
-        /* set start flag for later use */
-        start_flag = I2C_MSTCTL_MSTSTART_MASK;
-
-        if (handle->remainingSubaddr)
-        {
-            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
-            handle->state = kTransmitSubaddrState;
-        }
-        else if (transfer->direction == kI2C_Write)
-        {
-            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
-            if (transfer->dataSize == 0)
-            {
-                /* No data to be transferred, initiate start and schedule stop */
-                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
-                handle->state = kStopState;
-                return err;
-            }
-            handle->state = kTransmitDataState;
-        }
-        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
-        {
-            base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
-            if (transfer->dataSize == 1)
-            {
-                /* The very last byte is always received by means of SW */
-                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
-                handle->state = kReceiveLastDataState;
-                return err;
-            }
-            handle->state = kReceiveDataState;
-        }
-        else
-        {
-            handle->state = kIdleState;
-            err = kStatus_I2C_UnexpectedState;
-            return err;
-        }
-    }
-
-    switch (handle->state)
-    {
-        case kTransmitSubaddrState:
-            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-
-            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
-
-            /* Prepare and submit DMA transfer. */
-            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
-                                handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
-            DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-
-            handle->remainingSubaddr = 0;
-            if (transfer->dataSize)
-            {
-                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
-                 * repeated start */
-                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
-            }
-            else
-            {
-                /* No more data, schedule stop condition */
-                handle->state = kStopState;
-            }
-            break;
-
-        case kTransmitDataState:
-            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-
-            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
-            handle->remainingBytesDMA = handle->transfer.dataSize;
-
-            I2C_RunDMATransfer(base, handle);
-
-            /* Schedule stop condition */
-            handle->state = kStopState;
-            break;
-
-        case kReceiveDataState:
-            if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-
-            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
-            handle->remainingBytesDMA = handle->transfer.dataSize - 1;
-
-            I2C_RunDMATransfer(base, handle);
-
-            /* Schedule reception of last data byte */
-            handle->state = kReceiveLastDataState;
-            break;
-
-        case kReceiveLastDataState:
-            if (master_state != I2C_STAT_MSTCODE_RXREADY)
-            {
-                return kStatus_I2C_UnexpectedState;
-            }
-
-            ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
-            handle->transferCount++;
-
-            /* No more data expected, issue NACK and STOP right away */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-            handle->state = kWaitForCompletionState;
-            break;
-
-        case kStopState:
-            if (transfer->flags & kI2C_TransferNoStopFlag)
-            {
-                /* Stop condition is omitted, we are done */
-                *isDone = true;
-                handle->state = kIdleState;
-                break;
-            }
-            /* Send stop condition */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-            handle->state = kWaitForCompletionState;
-            break;
-
-        case kWaitForCompletionState:
-            *isDone = true;
-            handle->state = kIdleState;
-            break;
-
-        case kStartState:
-        case kIdleState:
-        default:
-            /* State machine shall not be invoked again once it enters the idle state */
-            err = kStatus_I2C_UnexpectedState;
-            break;
-    }
-
-    return err;
-}
-
-void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
-{
-    bool isDone;
-    status_t result;
-
-    /* Don't do anything if we don't have a valid handle. */
-    if (!handle)
-    {
-        return;
-    }
-
-    result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
-
-    if (isDone || (result != kStatus_Success))
-    {
-        /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base,
-                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
-
-        /* Invoke callback. */
-        if (handle->completionCallback)
-        {
-            handle->completionCallback(base, handle, result, handle->userData);
-        }
-    }
-}
-
-static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
-{
-    i2c_master_dma_private_handle_t *dmaPrivateHandle;
-
-    /* Don't do anything if we don't have a valid handle. */
-    if (!handle)
-    {
-        return;
-    }
-
-    dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
-    I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
-}
-
-void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
-                                       i2c_master_dma_handle_t *handle,
-                                       i2c_master_dma_transfer_callback_t callback,
-                                       void *userData,
-                                       dma_handle_t *dmaHandle)
-{
-    uint32_t instance;
-
-    assert(handle);
-    assert(dmaHandle);
-
-    /* Zero handle. */
-    memset(handle, 0, sizeof(*handle));
-
-    /* Look up instance number */
-    instance = I2C_GetInstance(base);
-
-    /* Set the user callback and userData. */
-    handle->completionCallback = callback;
-    handle->userData = userData;
-
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle);
-
-    /* Clear internal IRQ enables and enable NVIC IRQ. */
-    I2C_DisableInterrupts(base,
-                          I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
-    EnableIRQ(s_i2cIRQ[instance]);
-
-    /* Set the handle for DMA. */
-    handle->dmaHandle = dmaHandle;
-
-    s_dmaPrivateHandle[instance].base = base;
-    s_dmaPrivateHandle[instance].handle = handle;
-
-    DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
-}
-
-status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
-{
-    status_t result;
-
-    assert(handle);
-    assert(xfer);
-    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
-
-    /* Return busy if another transaction is in progress. */
-    if (handle->state != kIdleState)
-    {
-        return kStatus_I2C_Busy;
-    }
-
-    /* Prepare transfer state machine. */
-    result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
-
-    /* Clear error flags. */
-    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-
-    /* Enable I2C internal IRQ sources */
-    I2C_EnableInterrupts(base,
-                         I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
-
-    return result;
-}
-
-status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Catch when there is not an active transfer. */
-    if (handle->state == kIdleState)
-    {
-        *count = 0;
-        return kStatus_NoTransferInProgress;
-    }
-
-    /* There is no necessity to disable interrupts as we read a single integer value */
-    *count = handle->transferCount;
-    return kStatus_Success;
-}
-
-void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
-{
-    uint32_t status;
-    uint32_t master_state;
-
-    if (handle->state != kIdleState)
-    {
-        DMA_AbortTransfer(handle->dmaHandle);
-
-        /* Disable DMA */
-        base->MSTCTL = 0;
-
-        /* Disable internal IRQ enables. */
-        I2C_DisableInterrupts(base,
-                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
-
-        /* Wait until module is ready */
-        do
-        {
-            status = I2C_GetStatusFlags(base);
-        } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
-
-        /* Clear controller state. */
-        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-
-        /* Get the state of the I2C module */
-        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
-
-        if (master_state != I2C_STAT_MSTCODE_IDLE)
-        {
-            /* Send a stop command to finalize the transfer. */
-            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
-
-            /* Wait until module is ready */
-            do
-            {
-                status = I2C_GetStatusFlags(base);
-            } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
-
-            /* Clear controller state. */
-            I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
-        }
-
-        /* Reset the state to idle. */
-        handle->state = kIdleState;
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_I2C_DMA_H_
-#define _FSL_I2C_DMA_H_
-
-#include "fsl_i2c.h"
-#include "fsl_dma.h"
-
-/*!
- * @addtogroup i2c_dma_driver
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
-#define I2C_MAX_DMA_TRANSFER_COUNT 1024
-
-/*! @brief I2C master dma handle typedef. */
-typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
-
-/*! @brief I2C master dma transfer callback typedef. */
-typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
-                                                   i2c_master_dma_handle_t *handle,
-                                                   status_t status,
-                                                   void *userData);
-
-/*! @brief I2C master dma transfer structure. */
-struct _i2c_master_dma_handle
-{
-    uint8_t state;              /*!< Transfer state machine current state. */
-    uint32_t transferCount;     /*!< Indicates progress of the transfer */
-    uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
-    uint8_t *buf;               /*!< Buffer pointer for current state. */
-    uint32_t remainingSubaddr;
-    uint8_t subaddrBuf[4];
-    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
-    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
-    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
-    void *userData;                                        /*!< Callback parameter passed to callback function. */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /*_cplusplus. */
-
-/*!
- * @name I2C Block DMA Transfer Operation
- * @{
- */
-
-/*!
- * @brief Init the I2C handle which is used in transcational functions
- *
- * @param base I2C peripheral base address
- * @param handle pointer to i2c_master_dma_handle_t structure
- * @param callback pointer to user callback function
- * @param userData user param passed to the callback function
- * @param dmaHandle DMA handle pointer
- */
-void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
-                                       i2c_master_dma_handle_t *handle,
-                                       i2c_master_dma_transfer_callback_t callback,
-                                       void *userData,
-                                       dma_handle_t *dmaHandle);
-
-/*!
- * @brief Performs a master dma non-blocking transfer on the I2C bus
- *
- * @param base I2C peripheral base address
- * @param handle pointer to i2c_master_dma_handle_t structure
- * @param xfer pointer to transfer structure of i2c_master_transfer_t
- * @retval kStatus_Success Sucessully complete the data transmission.
- * @retval kStatus_I2C_Busy Previous transmission still not finished.
- * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
- * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
- * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
- */
-status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
-
-/*!
- * @brief Get master transfer status during a dma non-blocking transfer
- *
- * @param base I2C peripheral base address
- * @param handle pointer to i2c_master_dma_handle_t structure
- * @param count Number of bytes transferred so far by the non-blocking transaction.
- */
-status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
-
-/*!
- * @brief Abort a master dma non-blocking transfer in a early time
- *
- * @param base I2C peripheral base address
- * @param handle pointer to i2c_master_dma_handle_t structure
- */
-void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
-
-/* @} */
-#if defined(__cplusplus)
-}
-#endif /*_cplusplus. */
-/*@}*/
-#endif /*_FSL_I2C_DMA_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,825 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_i2s.h"
-#include "fsl_flexcomm.h"
-#include <string.h>
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* TODO - absent in device header files, should be there */
-#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
-#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
-#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
-#define I2S_FIFOCFG_PACK48_MASK (0x8U)
-#define I2S_FIFOCFG_PACK48_SHIFT (3U)
-#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
-
-/*! @brief I2S states. */
-enum _i2s_state
-{
-    kI2S_StateIdle = 0x0,             /*!< Not performing transfer */
-    kI2S_StateTx,                     /*!< Performing transmit */
-    kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */
-    kI2S_StateTxWaitForEmptyFifo,     /*!< Wait for FIFO to be flushed */
-    kI2S_StateRx,                     /*!< Performing receive */
-};
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-static void I2S_Config(I2S_Type *base, const i2s_config_t *config);
-static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void I2S_TxInit(I2S_Type *base, const i2s_config_t *config)
-{
-    uint32_t cfg = 0U;
-    uint32_t trig = 0U;
-
-    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX);
-    I2S_Config(base, config);
-
-    /* Configure FIFO */
-
-    cfg |= I2S_FIFOCFG_ENABLETX(1U);                 /* enable TX FIFO */
-    cfg |= I2S_FIFOCFG_EMPTYTX(1U);                  /* empty TX FIFO */
-    cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */
-    cfg |= I2S_FIFOCFG_PACK48(config->pack48);       /* set pack 48-bit format or not */
-    trig |= I2S_FIFOTRIG_TXLVLENA(1U);               /* enable TX FIFO trigger */
-    trig |= I2S_FIFOTRIG_TXLVL(config->watermark);   /* set TX FIFO trigger level */
-
-    base->FIFOCFG = cfg;
-    base->FIFOTRIG = trig;
-}
-
-void I2S_RxInit(I2S_Type *base, const i2s_config_t *config)
-{
-    uint32_t cfg = 0U;
-    uint32_t trig = 0U;
-
-    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX);
-    I2S_Config(base, config);
-
-    /* Configure FIFO */
-
-    cfg |= I2S_FIFOCFG_ENABLERX(1U);               /* enable RX FIFO */
-    cfg |= I2S_FIFOCFG_EMPTYRX(1U);                /* empty RX FIFO */
-    cfg |= I2S_FIFOCFG_PACK48(config->pack48);     /* set pack 48-bit format or not */
-    trig |= I2S_FIFOTRIG_RXLVLENA(1U);             /* enable RX FIFO trigger */
-    trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */
-
-    base->FIFOCFG = cfg;
-    base->FIFOTRIG = trig;
-}
-
-void I2S_TxGetDefaultConfig(i2s_config_t *config)
-{
-    config->masterSlave = kI2S_MasterSlaveNormalMaster;
-    config->mode = kI2S_ModeI2sClassic;
-    config->rightLow = false;
-    config->leftJust = false;
-    config->pdmData = false;
-    config->sckPol = false;
-    config->wsPol = false;
-    config->divider = 1U;
-    config->oneChannel = false;
-    config->dataLength = 16U;
-    config->frameLength = 32U;
-    config->position = 0U;
-    config->watermark = 4U;
-    config->txEmptyZero = true;
-    config->pack48 = false;
-}
-
-void I2S_RxGetDefaultConfig(i2s_config_t *config)
-{
-    config->masterSlave = kI2S_MasterSlaveNormalSlave;
-    config->mode = kI2S_ModeI2sClassic;
-    config->rightLow = false;
-    config->leftJust = false;
-    config->pdmData = false;
-    config->sckPol = false;
-    config->wsPol = false;
-    config->divider = 1U;
-    config->oneChannel = false;
-    config->dataLength = 16U;
-    config->frameLength = 32U;
-    config->position = 0U;
-    config->watermark = 4U;
-    config->txEmptyZero = false;
-    config->pack48 = false;
-}
-
-static void I2S_Config(I2S_Type *base, const i2s_config_t *config)
-{
-    assert(config);
-
-    uint32_t cfg1 = 0U;
-    uint32_t cfg2 = 0U;
-
-    /* set master/slave configuration */
-    cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave);
-
-    /* set I2S mode */
-    cfg1 |= I2S_CFG1_MODE(config->mode);
-
-    /* set right low (channel swap) */
-    cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow);
-
-    /* set data justification */
-    cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust);
-
-    /* set source to PDM dmic */
-    cfg1 |= I2S_CFG1_PDMDATA(config->pdmData);
-
-    /* set SCLK polarity */
-    cfg1 |= I2S_CFG1_SCK_POL(config->sckPol);
-
-    /* set WS polarity */
-    cfg1 |= I2S_CFG1_WS_POL(config->wsPol);
-
-    /* set mono mode */
-    cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel);
-
-    /* set data length */
-    cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U);
-
-    /* set frame length */
-    cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U);
-
-    /* set data position of this channel pair within the frame */
-    cfg2 |= I2S_CFG2_POSITION(config->position);
-
-    /* write to registers */
-    base->CFG1 = cfg1;
-    base->CFG2 = cfg2;
-
-    /* set the clock divider */
-    base->DIV = I2S_DIV_DIV(config->divider - 1U);
-}
-
-void I2S_Deinit(I2S_Type *base)
-{
-    /* TODO gate FLEXCOMM clock via FLEXCOMM driver */
-}
-
-void I2S_TxEnable(I2S_Type *base, bool enable)
-{
-    if (enable)
-    {
-        I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
-        I2S_Enable(base);
-    }
-    else
-    {
-        I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
-        I2S_Disable(base);
-        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
-    }
-}
-
-void I2S_RxEnable(I2S_Type *base, bool enable)
-{
-    if (enable)
-    {
-        I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
-        I2S_Enable(base);
-    }
-    else
-    {
-        I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
-        I2S_Disable(base);
-        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
-    }
-}
-
-static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer)
-{
-    assert(transfer->data);
-    if (!transfer->data)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    assert(transfer->dataSize > 0U);
-    if (transfer->dataSize <= 0U)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    if (handle->dataLength == 4U)
-    {
-        /* No alignment and data length requirements */
-    }
-    else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U))
-    {
-        assert((((uint32_t)transfer->data) % 2U) == 0U);
-        if ((((uint32_t)transfer->data) % 2U) != 0U)
-        {
-            /* Data not 2-bytes aligned */
-            return kStatus_InvalidArgument;
-        }
-
-        assert((transfer->dataSize % 2U) == 0U);
-        if ((transfer->dataSize % 2U) != 0U)
-        {
-            /* Data not in pairs of left/right channel bytes */
-            return kStatus_InvalidArgument;
-        }
-    }
-    else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U))
-    {
-        assert((((uint32_t)transfer->data) % 4U) == 0U);
-        if ((((uint32_t)transfer->data) % 4U) != 0U)
-        {
-            /* Data not 4-bytes aligned */
-            return kStatus_InvalidArgument;
-        }
-
-        assert((transfer->dataSize % 4U) == 0U);
-        if ((transfer->dataSize % 4U) != 0U)
-        {
-            /* Data lenght not multiply of 4 */
-            return kStatus_InvalidArgument;
-        }
-    }
-    else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U))
-    {
-        assert((transfer->dataSize % 6U) == 0U);
-        if ((transfer->dataSize % 6U) != 0U)
-        {
-            /* Data lenght not multiply of 6 */
-            return kStatus_InvalidArgument;
-        }
-
-        assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)));
-        if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))
-        {
-            /* Data not 4-bytes aligned */
-            return kStatus_InvalidArgument;
-        }
-    }
-    else /* if (handle->dataLength >= 25U) */
-    {
-        assert((((uint32_t)transfer->data) % 4U) == 0U);
-        if ((((uint32_t)transfer->data) % 4U) != 0U)
-        {
-            /* Data not 4-bytes aligned */
-            return kStatus_InvalidArgument;
-        }
-
-        if (handle->oneChannel)
-        {
-            assert((transfer->dataSize % 4U) == 0U);
-            if ((transfer->dataSize % 4U) != 0U)
-            {
-                /* Data lenght not multiply of 4 */
-                return kStatus_InvalidArgument;
-            }
-        }
-        else
-        {
-            assert((transfer->dataSize % 8U) == 0U);
-            if ((transfer->dataSize % 8U) != 0U)
-            {
-                /* Data lenght not multiply of 8 */
-                return kStatus_InvalidArgument;
-            }
-        }
-    }
-
-    return kStatus_Success;
-}
-
-void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
-{
-    assert(handle);
-
-    /* Clear out the handle */
-    memset(handle, 0U, sizeof(*handle));
-
-    /* Save callback and user data */
-    handle->completionCallback = callback;
-    handle->userData = userData;
-
-    /* Remember some items set previously by configuration */
-    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT);
-    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
-    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
-    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
-
-    handle->useFifo48H = false;
-
-    /* Register IRQ handling */
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle);
-}
-
-status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
-{
-    assert(handle);
-    if (!handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    status_t result;
-
-    result = I2S_ValidateBuffer(handle, &transfer);
-    if (result != kStatus_Success)
-    {
-        return result;
-    }
-
-    if (handle->i2sQueue[handle->queueUser].dataSize)
-    {
-        /* Previously prepared buffers not processed yet */
-        return kStatus_I2S_Busy;
-    }
-
-    handle->state = kI2S_StateTx;
-    handle->i2sQueue[handle->queueUser].data = transfer.data;
-    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
-    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
-
-    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark);
-    I2S_TxEnable(base, true);
-
-    return kStatus_Success;
-}
-
-void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
-{
-    assert(handle);
-
-    /* Disable I2S operation and interrupts */
-    I2S_TxEnable(base, false);
-
-    /* Reset state */
-    handle->state = kI2S_StateIdle;
-
-    /* Clear transfer queue */
-    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
-    handle->queueDriver = 0U;
-    handle->queueUser = 0U;
-}
-
-void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
-{
-    assert(handle);
-
-    /* Clear out the handle */
-    memset(handle, 0U, sizeof(*handle));
-
-    /* Save callback and user data */
-    handle->completionCallback = callback;
-    handle->userData = userData;
-
-    /* Remember some items set previously by configuration */
-    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT);
-    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
-    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
-    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
-
-    handle->useFifo48H = false;
-
-    /* Register IRQ handling */
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle);
-}
-
-status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
-{
-    assert(handle);
-    if (!handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    status_t result;
-
-    result = I2S_ValidateBuffer(handle, &transfer);
-    if (result != kStatus_Success)
-    {
-        return result;
-    }
-
-    if (handle->i2sQueue[handle->queueUser].dataSize)
-    {
-        /* Previously prepared buffers not processed yet */
-        return kStatus_I2S_Busy;
-    }
-
-    handle->state = kI2S_StateRx;
-    handle->i2sQueue[handle->queueUser].data = transfer.data;
-    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
-    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
-
-    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark);
-    I2S_RxEnable(base, true);
-
-    return kStatus_Success;
-}
-
-void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
-{
-    assert(handle);
-
-    /* Disable I2S operation and interrupts */
-    I2S_RxEnable(base, false);
-
-    /* Reset state */
-    handle->state = kI2S_StateIdle;
-
-    /* Clear transfer queue */
-    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
-    handle->queueDriver = 0U;
-    handle->queueUser = 0U;
-}
-
-status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
-{
-    assert(handle);
-    if (!handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    assert(count);
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    if (handle->state == kI2S_StateIdle)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->transferCount;
-
-    return kStatus_Success;
-}
-
-status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
-{
-    assert(handle);
-    if (!handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    assert(count);
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    if (handle->state == kI2S_StateIdle)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->errorCount;
-
-    return kStatus_Success;
-}
-
-void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
-{
-    uint32_t intstat = base->FIFOINTSTAT;
-    uint32_t data;
-
-    if (intstat & I2S_FIFOINTSTAT_TXERR_MASK)
-    {
-        handle->errorCount++;
-
-        /* Clear TX error interrupt flag */
-        base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U);
-    }
-
-    if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK)
-    {
-        if (handle->state == kI2S_StateTx)
-        {
-            /* Send data */
-
-            while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) &&
-                   (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
-            {
-                /* Write output data */
-                if (handle->dataLength == 4U)
-                {
-                    data = *(handle->i2sQueue[handle->queueDriver].data);
-                    base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU);
-                    handle->i2sQueue[handle->queueDriver].data++;
-                    handle->transferCount++;
-                    handle->i2sQueue[handle->queueDriver].dataSize--;
-                }
-                else if (handle->dataLength <= 8U)
-                {
-                    data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data);
-                    base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU);
-                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
-                    handle->transferCount += sizeof(uint16_t);
-                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
-                }
-                else if (handle->dataLength <= 16U)
-                {
-                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
-                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                    handle->transferCount += sizeof(uint32_t);
-                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-                }
-                else if (handle->dataLength <= 24U)
-                {
-                    if (handle->pack48)
-                    {
-                        if (handle->useFifo48H)
-                        {
-                            base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data));
-                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
-                            handle->transferCount += sizeof(uint16_t);
-                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
-                            handle->useFifo48H = false;
-                        }
-                        else
-                        {
-                            base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
-                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                            handle->transferCount += sizeof(uint32_t);
-                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-                            handle->useFifo48H = true;
-                        }
-                    }
-                    else
-                    {
-                        data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++));
-                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U;
-                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U;
-                        if (handle->useFifo48H)
-                        {
-                            base->FIFOWR48H = data;
-                            handle->useFifo48H = false;
-                        }
-                        else
-                        {
-                            base->FIFOWR = data;
-                            handle->useFifo48H = true;
-                        }
-                        handle->transferCount += 3U;
-                        handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
-                    }
-                }
-                else /* if (handle->dataLength <= 32U) */
-                {
-                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
-                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                    handle->transferCount += sizeof(uint32_t);
-                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-                }
-
-                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
-                {
-                    /* Actual data buffer sent out, switch to a next one */
-                    handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
-
-                    /* Notify user */
-                    if (handle->completionCallback)
-                    {
-                        handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
-                    }
-
-                    /* Check if the next buffer contains anything to send */
-                    if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
-                    {
-                        /* Everything has been written to FIFO */
-                        handle->state = kI2S_StateTxWaitToWriteDummyData;
-                        break;
-                    }
-                }
-            }
-        }
-        else if (handle->state == kI2S_StateTxWaitToWriteDummyData)
-        {
-            /* Write dummy data */
-            if ((handle->dataLength > 16U) && (handle->dataLength < 25U))
-            {
-                if (handle->useFifo48H)
-                {
-                    base->FIFOWR48H = 0U;
-                    handle->useFifo48H = false;
-                }
-                else
-                {
-                    base->FIFOWR = 0U;
-                    base->FIFOWR48H = 0U;
-                }
-            }
-            else
-            {
-                base->FIFOWR = 0U;
-            }
-
-            /* Next time invoke this handler when FIFO becomes empty (TX level 0) */
-            base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK;
-            handle->state = kI2S_StateTxWaitForEmptyFifo;
-        }
-        else if (handle->state == kI2S_StateTxWaitForEmptyFifo)
-        {
-            /* FIFO, including additional dummy data, has been emptied now,
-             * all relevant data should have been output from peripheral */
-
-            /* Stop transfer */
-            I2S_Disable(base);
-            I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
-            base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
-
-            /* Reset state */
-            handle->state = kI2S_StateIdle;
-
-            /* Notify user */
-            if (handle->completionCallback)
-            {
-                handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
-            }
-        }
-        else
-        {
-            /* Do nothing */
-        }
-
-        /* Clear TX level interrupt flag */
-        base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U);
-    }
-}
-
-void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
-{
-    uint32_t intstat = base->FIFOINTSTAT;
-    uint32_t data;
-
-    if (intstat & I2S_FIFOINTSTAT_RXERR_MASK)
-    {
-        handle->errorCount++;
-
-        /* Clear RX error interrupt flag */
-        base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U);
-    }
-
-    if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK)
-    {
-        while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
-        {
-            /* Read input data */
-            if (handle->dataLength == 4U)
-            {
-                data = base->FIFORD;
-                *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU);
-                handle->i2sQueue[handle->queueDriver].data++;
-                handle->transferCount++;
-                handle->i2sQueue[handle->queueDriver].dataSize--;
-            }
-            else if (handle->dataLength <= 8U)
-            {
-                data = base->FIFORD;
-                *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU);
-                handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
-                handle->transferCount += sizeof(uint16_t);
-                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
-            }
-            else if (handle->dataLength <= 16U)
-            {
-                data = base->FIFORD;
-                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
-                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                handle->transferCount += sizeof(uint32_t);
-                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-            }
-            else if (handle->dataLength <= 24U)
-            {
-                if (handle->pack48)
-                {
-                    if (handle->useFifo48H)
-                    {
-                        data = base->FIFORD48H;
-                        handle->useFifo48H = false;
-
-                        *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data;
-                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
-                        handle->transferCount += sizeof(uint16_t);
-                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
-                    }
-                    else
-                    {
-                        data = base->FIFORD;
-                        handle->useFifo48H = true;
-
-                        *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
-                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                        handle->transferCount += sizeof(uint32_t);
-                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-                    }
-                }
-                else
-                {
-                    if (handle->useFifo48H)
-                    {
-                        data = base->FIFORD48H;
-                        handle->useFifo48H = false;
-                    }
-                    else
-                    {
-                        data = base->FIFORD;
-                        handle->useFifo48H = true;
-                    }
-
-                    *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU;
-                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU;
-                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU;
-                    handle->transferCount += 3U;
-                    handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
-                }
-            }
-            else /* if (handle->dataLength <= 32U) */
-            {
-                data = base->FIFORD;
-                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
-                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
-                handle->transferCount += sizeof(uint32_t);
-                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
-            }
-
-            if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
-            {
-                /* Actual data buffer filled with input data, switch to a next one */
-                handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
-
-                /* Notify user */
-                if (handle->completionCallback)
-                {
-                    handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
-                }
-
-                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
-                {
-                    /* No other buffer prepared to receive data into */
-
-                    /* Disable I2S operation and interrupts */
-                    I2S_Disable(base);
-                    I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
-                    base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
-
-                    /* Reset state */
-                    handle->state = kI2S_StateIdle;
-
-                    /* Notify user */
-                    if (handle->completionCallback)
-                    {
-                        handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
-                    }
-
-                    /* Clear RX level interrupt flag */
-                    base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
-
-                    return;
-                }
-            }
-        }
-
-        /* Clear RX level interrupt flag */
-        base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_I2S_H_
-#define _FSL_I2S_H_
-
-#include "fsl_device_registers.h"
-#include "fsl_common.h"
-#include "fsl_flexcomm.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*!
- * @addtogroup i2s_driver
- * @{
- */
-
-/*! @file */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief I2S driver version 2.0.0.
- *
- * Current version: 2.0.0
- *
- * Change log:
- * - Version 2.0.0
- *   - initial version
- */
-#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-#ifndef I2S_NUM_BUFFERS
-
-/*! @brief Number of buffers . */
-#define I2S_NUM_BUFFERS (4)
-
-#endif
-
-/*! @brief I2S status codes. */
-enum _i2s_status
-{
-    kStatus_I2S_BufferComplete =
-        MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
-    kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */
-    kStatus_I2S_Busy =
-        MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */
-};
-
-/*!
- * @brief I2S flags.
- *
- * @note These enums are meant to be OR'd together to form a bit mask.
- */
-typedef enum _i2s_flags
-{
-    kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */
-    kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */
-    kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */
-    kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK  /*!< RX level interrupt */
-} i2s_flags_t;
-
-/*! @brief Master / slave mode. */
-typedef enum _i2s_master_slave
-{
-    kI2S_MasterSlaveNormalSlave = 0x0,  /*!< Normal slave */
-    kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */
-    kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */
-    kI2S_MasterSlaveNormalMaster = 0x3  /*!< Normal master */
-} i2s_master_slave_t;
-
-/*! @brief I2S mode. */
-typedef enum _i2s_mode
-{
-    kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */
-    kI2S_ModeDspWs50 = 0x1,    /*!< DSP mode, WS having 50% duty cycle */
-    kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */
-    kI2S_ModeDspWsLong = 0x3   /*!< DSP mode, WS having one data slot long pulse */
-} i2s_mode_t;
-
-/*! @brief I2S configuration structure. */
-typedef struct _i2s_config
-{
-    i2s_master_slave_t masterSlave; /*!< Master / slave configuration */
-    i2s_mode_t mode;                /*!< I2S mode */
-    bool rightLow;                  /*!< Right channel data in low portion of FIFO */
-    bool leftJust;                  /*!< Left justify data in FIFO */
-    bool pdmData;                   /*!< Data source is the D-Mic subsystem */
-    bool sckPol;                    /*!< SCK polarity */
-    bool wsPol;                     /*!< WS polarity */
-    uint16_t divider;               /*!< Flexcomm function clock divider (1 - 4096) */
-    bool oneChannel;                /*!< true mono, false stereo */
-    uint8_t dataLength;             /*!< Data length (4 - 32) */
-    uint16_t frameLength;           /*!< Frame width (4 - 512) */
-    uint16_t position;              /*!< Data position in the frame */
-    uint8_t watermark;              /*!< FIFO trigger level */
-    bool txEmptyZero;               /*!< Transmit zero when buffer becomes empty or last item */
-    bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
-                    values) */
-} i2s_config_t;
-
-/*! @brief Buffer to transfer from or receive audio data into. */
-typedef struct _i2s_transfer
-{
-    volatile uint8_t *data;   /*!< Pointer to data buffer. */
-    volatile size_t dataSize; /*!< Buffer size in bytes. */
-} i2s_transfer_t;
-
-/*! @brief Transactional state of the intialized transfer or receive I2S operation. */
-typedef struct _i2s_handle i2s_handle_t;
-
-/*!
- * @brief Callback function invoked from transactional API
- *        on completion of a single buffer transfer.
- *
- * @param base I2S base pointer.
- * @param handle pointer to I2S transaction.
- * @param completionStatus status of the transaction.
- * @param userData optional pointer to user arguments data.
- */
-typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
-                                        i2s_handle_t *handle,
-                                        status_t completionStatus,
-                                        void *userData);
-
-/*! @brief Members not to be accessed / modified outside of the driver. */
-struct _i2s_handle
-{
-    uint32_t state;                             /*!< State of transfer */
-    i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
-    void *userData;                             /*!< Application data passed to callback */
-    bool oneChannel;                            /*!< true mono, false stereo */
-    uint8_t dataLength;                         /*!< Data length (4 - 32) */
-    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
-                        values) */
-    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
-    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
-    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
-    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
-    volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
-    volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
-    volatile uint8_t watermark;                        /*!< FIFO trigger level */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality.
- *
- * Ungates the FLEXCOMM clock and configures the module
- * for I2S transmission using a configuration structure.
- * The configuration structure can be custom filled or set with default values by
- * I2S_TxGetDefaultConfig().
- *
- * @note This API should be called at the beginning of the application to use
- * the I2S driver.
- *
- * @param base I2S base pointer.
- * @param config pointer to I2S configuration structure.
- */
-void I2S_TxInit(I2S_Type *base, const i2s_config_t *config);
-
-/*!
- * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality.
- *
- * Ungates the FLEXCOMM clock and configures the module
- * for I2S receive using a configuration structure.
- * The configuration structure can be custom filled or set with default values by
- * I2S_RxGetDefaultConfig().
- *
- * @note This API should be called at the beginning of the application to use
- * the I2S driver.
- *
- * @param base I2S base pointer.
- * @param config pointer to I2S configuration structure.
- */
-void I2S_RxInit(I2S_Type *base, const i2s_config_t *config);
-
-/*!
- * @brief Sets the I2S Tx configuration structure to default values.
- *
- * This API initializes the configuration structure for use in I2S_TxInit().
- * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified
- * before calling I2S_TxInit().
- * Example:
-   @code
-   i2s_config_t config;
-   I2S_TxGetDefaultConfig(&config);
-   @endcode
- *
- * Default values:
- * @code
- *   config->masterSlave = kI2S_MasterSlaveNormalMaster;
- *   config->mode = kI2S_ModeI2sClassic;
- *   config->rightLow = false;
- *   config->leftJust = false;
- *   config->pdmData = false;
- *   config->sckPol = false;
- *   config->wsPol = false;
- *   config->divider = 1;
- *   config->oneChannel = false;
- *   config->dataLength = 16;
- *   config->frameLength = 32;
- *   config->position = 0;
- *   config->watermark = 4;
- *   config->txEmptyZero = true;
- *   config->pack48 = false;
- * @endcode
- *
- * @param config pointer to I2S configuration structure.
- */
-void I2S_TxGetDefaultConfig(i2s_config_t *config);
-
-/*!
- * @brief Sets the I2S Rx configuration structure to default values.
- *
- * This API initializes the configuration structure for use in I2S_RxInit().
- * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified
- * before calling I2S_RxInit().
- * Example:
-   @code
-   i2s_config_t config;
-   I2S_RxGetDefaultConfig(&config);
-   @endcode
- *
- * Default values:
- * @code
- *   config->masterSlave = kI2S_MasterSlaveNormalSlave;
- *   config->mode = kI2S_ModeI2sClassic;
- *   config->rightLow = false;
- *   config->leftJust = false;
- *   config->pdmData = false;
- *   config->sckPol = false;
- *   config->wsPol = false;
- *   config->divider = 1;
- *   config->oneChannel = false;
- *   config->dataLength = 16;
- *   config->frameLength = 32;
- *   config->position = 0;
- *   config->watermark = 4;
- *   config->txEmptyZero = false;
- *   config->pack48 = false;
- * @endcode
- *
- * @param config pointer to I2S configuration structure.
- */
-void I2S_RxGetDefaultConfig(i2s_config_t *config);
-
-/*!
- * @brief De-initializes the I2S peripheral.
- *
- * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit
- * or I2S_RxInit is called to enable the clock.
- *
- * @param base I2S base pointer.
- */
-void I2S_Deinit(I2S_Type *base);
-
-/*! @} */
-
-/*!
- * @name Non-blocking API
- * @{
- */
-
-/*!
- * @brief Initializes handle for transfer of audio data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param callback function to be called back when transfer is done or fails.
- * @param userData pointer to data passed to callback.
- */
-void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
-
-/*!
- * @brief Begins or queue sending of the given data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param transfer data buffer.
- *
- * @retval kStatus_Success
- * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
- */
-status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
-
-/*!
- * @brief Aborts sending of data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- */
-void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
-
-/*!
- * @brief Initializes handle for reception of audio data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param callback function to be called back when transfer is done or fails.
- * @param userData pointer to data passed to callback.
- */
-void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
-
-/*!
- * @brief Begins or queue reception of data into given buffer.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param transfer data buffer.
- *
- * @retval kStatus_Success
- * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full.
- */
-status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
-
-/*!
- * @brief Aborts receiving of data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- */
-void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
-
-/*!
- * @brief Returns number of bytes transferred so far.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param[out] count number of bytes transferred so far by the non-blocking transaction.
- *
- * @retval kStatus_Success
- * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
- */
-status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
-
-/*!
- * @brief Returns number of buffer underruns or overruns.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param[out] count number of transmit errors encountered so far by the non-blocking transaction.
- *
- * @retval kStatus_Success
- * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
- */
-status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
-
-/*! @} */
-
-/*!
- * @name Enable / disable
- * @{
- */
-
-/*!
- * @brief Enables I2S operation.
- *
- * @param base I2S base pointer.
- */
-static inline void I2S_Enable(I2S_Type *base)
-{
-    base->CFG1 |= I2S_CFG1_MAINENABLE(1U);
-}
-
-/*!
- * @brief Disables I2S operation.
- *
- * @param base I2S base pointer.
- */
-static inline void I2S_Disable(I2S_Type *base)
-{
-    base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U));
-}
-
-/*! @} */
-
-/*!
- * @name Interrupts
- * @{
- */
-
-/*!
- * @brief Enables I2S FIFO interrupts.
- *
- * @param base I2S base pointer.
- * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
- *      of constants that should be OR'd together to form the bit mask.
- */
-static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask)
-{
-    base->FIFOINTENSET = interruptMask;
-}
-
-/*!
- * @brief Disables I2S FIFO interrupts.
- *
- * @param base I2S base pointer.
- * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
- *      of constants that should be OR'd together to form the bit mask.
- */
-static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask)
-{
-    base->FIFOINTENCLR = interruptMask;
-}
-
-/*!
- * @brief Returns the set of currently enabled I2S FIFO interrupts.
- *
- * @param base I2S base pointer.
- *
- * @return A bitmask composed of #i2s_flags_t enumerators OR'd together
- *         to indicate the set of enabled interrupts.
- */
-static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
-{
-    return base->FIFOINTENSET;
-}
-
-/*!
- * @brief Invoked from interrupt handler when transmit FIFO level decreases.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- */
-void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
-
-/*!
- * @brief Invoked from interrupt handler when receive FIFO level decreases.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- */
-void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
-
-/*! @} */
-
-/*! @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* _FSL_I2S_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,626 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_dma.h"
-#include "fsl_i2s_dma.h"
-#include "fsl_flexcomm.h"
-#include <string.h>
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
-#define DMA_DESCRIPTORS (2U)
-
-/*<! @brief Structure for statically allocated private data. */
-typedef struct _i2s_dma_private_handle
-{
-    I2S_Type *base;           /*!< I2S base address */
-    i2s_dma_handle_t *handle; /*!< I2S handle */
-
-    volatile uint16_t enqueuedBytes[DMA_DESCRIPTORS]; /*!< Number of bytes being transferred by DMA descriptors */
-    volatile uint8_t enqueuedBytesStart;              /*!< First item in enqueuedBytes (for reading) */
-    volatile uint8_t enqueuedBytesEnd;                /*!< Last item in enqueuedBytes (for adding) */
-
-    volatile uint8_t
-        dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
-    volatile uint8_t
-        descriptor; /*!< Index of next DMA descriptor in s_DmaDescriptors to be configured with data (does not include
-                       I2S instance offset) */
-
-    volatile uint8_t queueDescriptor;                         /*!< Queue index of buffer to be actually consumed by DMA
-                                                                * (queueUser - advanced when user adds a buffer,
-                                                                *  queueDescriptor - advanced when user buffer queued to DMA,
-                                                                *  queueDriver - advanced when DMA queued buffer sent out to I2S) */
-    volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data to be queued to DMA */
-
-    volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */
-} i2s_dma_private_handle_t;
-
-/*! @brief I2S DMA transfer private state. */
-enum _i2s_dma_state
-{
-    kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
-    kI2S_DmaStateTx,          /*!< I2S is busy transmitting data */
-    kI2S_DmaStateRx,          /*!< I2S is busy receiving data */
-};
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
-static uint32_t I2S_GetInstance(I2S_Type *base);
-static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle);
-static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle);
-static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
-static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
-static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer);
-static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
-static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*<! @brief DMA transfer descriptors. */
-#if defined(__ICCARM__)
-#pragma data_alignment = 16
-static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
-#elif defined(__CC_ARM)
-__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
-#elif defined(__GNUC__)
-__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
-#endif
-
-/*<! @brief Buffer with dummy TX data. */
-#if defined(__ICCARM__)
-#pragma data_alignment = 4
-static uint32_t s_DummyBufferTx = 0U;
-#elif defined(__CC_ARM)
-__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
-#elif defined(__GNUC__)
-__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
-#endif
-
-/*<! @brief Buffer to fill with RX data to discard. */
-#if defined(__ICCARM__)
-#pragma data_alignment = 4
-static uint32_t s_DummyBufferRx = 0U;
-#elif defined(__CC_ARM)
-__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
-#elif defined(__GNUC__)
-__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
-#endif
-
-/*<! @brief Private array of data associated with available I2S peripherals. */
-static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
-
-/*<! @brief Base addresses of available I2S peripherals. */
-static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
-{
-    uint32_t instance = I2S_GetInstance(base);
-    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
-
-    /* Validate input data and tranfer buffer */
-
-    assert(handle);
-    if (!handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    assert((((uint32_t)transfer.data) % 4U) == 0U);
-    if ((((uint32_t)transfer.data) % 4U) != 0U)
-    {
-        /* Data not 4-bytes aligned */
-        return kStatus_InvalidArgument;
-    }
-
-    assert(transfer.dataSize != 0U);
-    if (transfer.dataSize == 0U)
-    {
-        /* No data to send or receive */
-        return kStatus_InvalidArgument;
-    }
-
-    assert((transfer.dataSize % 4U) == 0U);
-    if ((transfer.dataSize % 4U) != 0U)
-    {
-        /* Data length not multiply of 4 bytes */
-        return kStatus_InvalidArgument;
-    }
-
-    if (handle->i2sQueue[handle->queueUser].dataSize)
-    {
-        /* Previously prepared buffers not processed yet, reject request */
-        return kStatus_I2S_Busy;
-    }
-
-    /* Enqueue data */
-    privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
-    privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
-    handle->i2sQueue[handle->queueUser].data = transfer.data;
-    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
-    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
-
-    return kStatus_Success;
-}
-
-static uint32_t I2S_GetInstance(I2S_Type *base)
-{
-    uint32_t i;
-
-    for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++)
-    {
-        if ((uint32_t)base == s_I2sBaseAddrs[i])
-        {
-            return i;
-        }
-    }
-
-    assert(false);
-    return 0U;
-}
-
-static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
-{
-    DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
-}
-
-static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
-{
-    if (handle->state != kI2S_DmaStateIdle)
-    {
-        DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
-    }
-}
-
-void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
-                                   i2s_dma_handle_t *handle,
-                                   dma_handle_t *dmaHandle,
-                                   i2s_dma_transfer_callback_t callback,
-                                   void *userData)
-{
-    assert(handle);
-    assert(dmaHandle);
-
-    uint32_t instance = I2S_GetInstance(base);
-    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
-
-    memset(handle, 0U, sizeof(*handle));
-    handle->state = kI2S_DmaStateIdle;
-    handle->dmaHandle = dmaHandle;
-    handle->completionCallback = callback;
-    handle->userData = userData;
-
-    memset(privateHandle, 0U, sizeof(*privateHandle));
-    privateHandle->base = base;
-    privateHandle->handle = handle;
-
-    DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
-}
-
-status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
-{
-    status_t status;
-
-    I2S_DisableDMAInterrupts(handle);
-
-    /* Enqueue transfer buffer */
-    status = I2S_EnqueueUserBuffer(base, handle, transfer);
-    if (status != kStatus_Success)
-    {
-        I2S_EnableDMAInterrupts(handle);
-        return status;
-    }
-
-    /* Initialize DMA transfer */
-    if (handle->state == kI2S_DmaStateIdle)
-    {
-        handle->state = kI2S_DmaStateTx;
-        status = I2S_StartTransferDMA(base, handle);
-        if (status != kStatus_Success)
-        {
-            I2S_EnableDMAInterrupts(handle);
-            return status;
-        }
-    }
-
-    I2S_AddTransferDMA(base, handle);
-    I2S_EnableDMAInterrupts(handle);
-
-    return kStatus_Success;
-}
-
-void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
-{
-    assert(handle);
-    assert(handle->dmaHandle);
-
-    uint32_t instance = I2S_GetInstance(base);
-    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
-
-    I2S_DisableDMAInterrupts(handle);
-
-    /* Abort operation */
-    DMA_AbortTransfer(handle->dmaHandle);
-
-    if (handle->state == kI2S_DmaStateTx)
-    {
-        /* Wait until all transmitted data get out of FIFO */
-        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
-        {
-        }
-        /* The last piece of valid data can be still being transmitted from I2S at this moment */
-
-        /* Write additional data to FIFO */
-        base->FIFOWR = 0U;
-        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
-        {
-        }
-        /* At this moment the additional data are out of FIFO, starting being transmitted.
-         * This means the preceding valid data has been just transmitted and we can stop I2S. */
-        I2S_TxEnableDMA(base, false);
-    }
-    else
-    {
-        I2S_RxEnableDMA(base, false);
-    }
-
-    I2S_Disable(base);
-
-    /* Reset state */
-    handle->state = kI2S_DmaStateIdle;
-
-    /* Clear transfer queue */
-    memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
-    handle->queueDriver = 0U;
-    handle->queueUser = 0U;
-
-    /* Clear internal state */
-    memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
-    memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
-    privateHandle->enqueuedBytesStart = 0U;
-    privateHandle->enqueuedBytesEnd = 0U;
-    privateHandle->dmaDescriptorsUsed = 0U;
-    privateHandle->descriptor = 0U;
-    privateHandle->queueDescriptor = 0U;
-    privateHandle->intA = false;
-}
-
-void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
-                                   i2s_dma_handle_t *handle,
-                                   dma_handle_t *dmaHandle,
-                                   i2s_dma_transfer_callback_t callback,
-                                   void *userData)
-{
-    I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
-}
-
-status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
-{
-    status_t status;
-
-    I2S_DisableDMAInterrupts(handle);
-
-    /* Enqueue transfer buffer */
-    status = I2S_EnqueueUserBuffer(base, handle, transfer);
-    if (status != kStatus_Success)
-    {
-        I2S_EnableDMAInterrupts(handle);
-        return status;
-    }
-
-    /* Initialize DMA transfer */
-    if (handle->state == kI2S_DmaStateIdle)
-    {
-        handle->state = kI2S_DmaStateRx;
-        status = I2S_StartTransferDMA(base, handle);
-        if (status != kStatus_Success)
-        {
-            I2S_EnableDMAInterrupts(handle);
-            return status;
-        }
-    }
-
-    I2S_AddTransferDMA(base, handle);
-    I2S_EnableDMAInterrupts(handle);
-
-    return kStatus_Success;
-}
-
-static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
-        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
-    }
-}
-
-static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
-        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
-    }
-}
-
-static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
-{
-    assert(transfer);
-
-    uint16_t transferBytes;
-
-    if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
-    {
-        transferBytes = DMA_MAX_TRANSFER_BYTES;
-    }
-    else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
-    {
-        transferBytes = transfer->dataSize / 2U;
-        if ((transferBytes % 4U) != 0U)
-        {
-            transferBytes -= (transferBytes % 4U);
-        }
-    }
-    else
-    {
-        transferBytes = transfer->dataSize;
-    }
-
-    return transferBytes;
-}
-
-static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
-{
-    status_t status;
-    dma_transfer_config_t xferConfig = {0};
-    i2s_dma_private_handle_t *privateHandle;
-    volatile i2s_transfer_t *transfer;
-    uint16_t transferBytes;
-    uint32_t instance;
-    int i;
-    dma_descriptor_t *descriptor;
-    dma_descriptor_t *nextDescriptor;
-    dma_xfercfg_t xfercfg;
-
-    instance = I2S_GetInstance(base);
-    privateHandle = &(s_DmaPrivateHandle[instance]);
-    transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
-
-    transferBytes = I2S_GetTransferBytes(transfer);
-
-    /* Prepare transfer of data via initial DMA transfer descriptor */
-    DMA_PrepareTransfer(
-        &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
-        (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t),
-        transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
-        (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
-
-    /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
-    privateHandle->dmaDescriptorsUsed = 1U;
-    privateHandle->intA = false;
-
-    privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
-    privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
-
-    transfer->dataSize -= transferBytes;
-    transfer->data += transferBytes;
-
-    if (transfer->dataSize == 0U)
-    {
-        transfer->data = NULL;
-        privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
-    }
-
-    /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */
-    for (i = 0; i < DMA_DESCRIPTORS; i++)
-    {
-        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]);
-        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]);
-
-        xfercfg.valid = true;
-        xfercfg.reload = true;
-        xfercfg.swtrig = false;
-        xfercfg.clrtrig = false;
-        xfercfg.intA = false;
-        xfercfg.intB = false;
-        xfercfg.byteWidth = sizeof(uint32_t);
-        xfercfg.srcInc = 0U;
-        xfercfg.dstInc = 0U;
-        xfercfg.transferCount = 8U;
-
-        DMA_CreateDescriptor(descriptor, &xfercfg,
-                             (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD),
-                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx,
-                             (void *)nextDescriptor);
-    }
-
-    /* Submit and start initial DMA transfer */
-
-    if (handle->state == kI2S_DmaStateTx)
-    {
-        I2S_TxEnableDMA(base, true);
-    }
-    else
-    {
-        I2S_RxEnableDMA(base, true);
-    }
-
-    status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-    if (status != kStatus_Success)
-    {
-        return status;
-    }
-
-    DMA_StartTransfer(handle->dmaHandle);
-
-    I2S_Enable(base);
-    return kStatus_Success;
-}
-
-static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
-{
-    dma_xfercfg_t xfercfg;
-    volatile i2s_transfer_t *transfer;
-    uint16_t transferBytes;
-    uint32_t instance;
-    i2s_dma_private_handle_t *privateHandle;
-    dma_descriptor_t *descriptor;
-    dma_descriptor_t *nextDescriptor;
-
-    instance = I2S_GetInstance(base);
-    privateHandle = &(s_DmaPrivateHandle[instance]);
-
-    while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
-    {
-        transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
-
-        if (transfer->dataSize == 0U)
-        {
-            /* Nothing to be added */
-            return;
-        }
-
-        /* Determine currently configured descriptor and the other which it will link to */
-        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
-        privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
-        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
-
-        transferBytes = I2S_GetTransferBytes(transfer);
-        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
-        privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
-
-        /* Configure descriptor */
-
-        xfercfg.valid = true;
-        xfercfg.reload = true;
-        xfercfg.swtrig = false;
-        xfercfg.clrtrig = false;
-        xfercfg.intA = privateHandle->intA;
-        xfercfg.intB = !privateHandle->intA;
-        xfercfg.byteWidth = sizeof(uint32_t);
-        xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
-        xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
-        xfercfg.transferCount = transferBytes / sizeof(uint32_t);
-
-        DMA_CreateDescriptor(descriptor, &xfercfg,
-                             (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
-                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data,
-                             (void *)nextDescriptor);
-
-        /* Advance internal state */
-
-        privateHandle->dmaDescriptorsUsed++;
-        privateHandle->intA = !privateHandle->intA;
-
-        transfer->dataSize -= transferBytes;
-        transfer->data += transferBytes;
-        if (transfer->dataSize == 0U)
-        {
-            transfer->data = NULL;
-            privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
-        }
-    }
-}
-
-void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
-{
-    i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
-    i2s_dma_handle_t *i2sHandle = privateHandle->handle;
-    I2S_Type *base = privateHandle->base;
-
-    if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle))
-    {
-        return;
-    }
-
-    if (privateHandle->dmaDescriptorsUsed > 0U)
-    {
-        /* Finished descriptor, decrease amount of data to be processed */
-
-        i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
-            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
-        i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
-            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
-        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
-        privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
-
-        privateHandle->dmaDescriptorsUsed--;
-
-        if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
-        {
-            /* Entire user buffer sent or received - advance to next one */
-            i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
-            i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
-
-            /* Notify user about buffer completion */
-            if (i2sHandle->completionCallback)
-            {
-                (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
-            }
-        }
-    }
-
-    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
-    {
-        /* All user buffers processed */
-        I2S_TransferAbortDMA(base, i2sHandle);
-
-        /* Notify user about completion of the final buffer */
-        if (i2sHandle->completionCallback)
-        {
-            (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
-        }
-    }
-    else
-    {
-        /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
-        I2S_AddTransferDMA(base, i2sHandle);
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_I2S_DMA_H_
-#define _FSL_I2S_DMA_H_
-
-#include "fsl_device_registers.h"
-#include "fsl_common.h"
-#include "fsl_flexcomm.h"
-
-#include "fsl_dma.h"
-#include "fsl_i2s.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*!
- * @addtogroup i2s_dma_driver
- * @{
- */
-
-/*! @file */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief I2S DMA driver version 2.0.0.
- *
- * Current version: 2.0.0
- *
- * Change log:
- * - Version 2.0.0
- *   - initial version
- */
-#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief Members not to be accessed / modified outside of the driver. */
-typedef struct _i2s_dma_handle i2s_dma_handle_t;
-
-/*!
- * @brief Callback function invoked from DMA API on completion.
- *
- * @param base I2S base pointer.
- * @param handle pointer to I2S transaction.
- * @param completionStatus status of the transaction.
- * @param userData optional pointer to user arguments data.
- */
-typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base,
-                                            i2s_dma_handle_t *handle,
-                                            status_t completionStatus,
-                                            void *userData);
-
-struct _i2s_dma_handle
-{
-    uint32_t state;                                    /*!< Internal state of I2S DMA transfer */
-    i2s_dma_transfer_callback_t completionCallback;    /*!< Callback function pointer */
-    void *userData;                                    /*!< Application data passed to callback */
-    dma_handle_t *dmaHandle;                           /*!< DMA handle */
-    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
-    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
-    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*! @} */
-
-/*!
- * @name DMA API
- * @{
- */
-
-/*!
- * @brief Initializes handle for transfer of audio data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param dmaHandle pointer to dma handle structure.
- * @param callback function to be called back when transfer is done or fails.
- * @param userData pointer to data passed to callback.
- */
-void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
-                                   i2s_dma_handle_t *handle,
-                                   dma_handle_t *dmaHandle,
-                                   i2s_dma_transfer_callback_t callback,
-                                   void *userData);
-
-/*!
- * @brief Begins or queue sending of the given data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param transfer data buffer.
- *
- * @retval kStatus_Success
- * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
- */
-status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
-
-/*!
- * @brief Aborts transfer of data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- */
-void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle);
-
-/*!
- * @brief Initializes handle for reception of audio data.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param dmaHandle pointer to dma handle structure.
- * @param callback function to be called back when transfer is done or fails.
- * @param userData pointer to data passed to callback.
- */
-void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
-                                   i2s_dma_handle_t *handle,
-                                   dma_handle_t *dmaHandle,
-                                   i2s_dma_transfer_callback_t callback,
-                                   void *userData);
-
-/*!
- * @brief Begins or queue reception of data into given buffer.
- *
- * @param base I2S base pointer.
- * @param handle pointer to handle structure.
- * @param transfer data buffer.
- *
- * @retval kStatus_Success
- * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers
- *         which are not full.
- */
-status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
-
-/*!
- * @brief Invoked from DMA interrupt handler.
- *
- * @param handle pointer to DMA handle structure.
- * @param userData argument for user callback.
- * @param transferDone if transfer was done.
- * @param tcds
- */
-void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
-
-/*! @} */
-
-/*! @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* _FSL_I2S_DMA_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_inputmux.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void INPUTMUX_Init(INPUTMUX_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_EnableClock(kCLOCK_InputMux);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
-{
-    uint32_t pmux_id;
-    uint32_t output_id;
-
-    /* extract pmux to be used */
-    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
-    /*  extract function number */
-    output_id = ((uint32_t)(connection)) & 0xffffU;
-    /* programm signal */
-    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
-}
-
-void INPUTMUX_Deinit(INPUTMUX_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_DisableClock(kCLOCK_InputMux);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_INPUTMUX_H_
-#define _FSL_INPUTMUX_H_
-
-#include "fsl_inputmux_connections.h"
-#include "fsl_common.h"
-
-/*!
- * @addtogroup inputmux_driver
- * @{
- */
-
-/*! @file */
-/*! @file fsl_inputmux_connections.h */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Group interrupt driver version for SDK */
-#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-                                                            /*@}*/
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*!
- * @brief	Initialize INPUTMUX peripheral.
-
- * This function enables the INPUTMUX clock.
- *
- * @param base Base address of the INPUTMUX peripheral.
- *
- * @retval None.
- */
-void INPUTMUX_Init(INPUTMUX_Type *base);
-
-/*!
- * @brief Attaches a signal
- *
- * This function gates the INPUTPMUX clock.
- *
- * @param base Base address of the INPUTMUX peripheral.
- * @param index Destination peripheral to attach the signal to.
- * @param connection Selects connection.
- *
- * @retval None.
-*/
-void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
-
-/*!
- * @brief	Deinitialize INPUTMUX peripheral.
-
- * This function disables the INPUTMUX clock.
- *
- * @param base Base address of the INPUTMUX peripheral.
- *
- * @retval None.
- */
-void INPUTMUX_Deinit(INPUTMUX_Type *base);
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _FSL_INPUTMUX_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,216 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_INPUTMUX_CONNECTIONS_
-#define _FSL_INPUTMUX_CONNECTIONS_
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*!
- * @addtogroup inputmux_driver
- * @{
- */
-
-/*!
- * @name Input multiplexing connections
- * @{
- */
-
-/*! @brief Periphinmux IDs */
-#define SCT0_PMUX_ID 0x00U
-#define PINTSEL_PMUX_ID 0xC0U
-#define DMA_TRIG0_PMUX_ID 0xE0U
-#define DMA_OTRIG_PMUX_ID 0x160U
-#define FREQMEAS_PMUX_ID 0x180U
-#define PMUX_SHIFT 20U
-
-/*! @brief INPUTMUX connections type */
-typedef enum _inputmux_connection_t
-{
-    /*!< SCT INMUX. */
-    kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT),
-
-    /*!< Frequency measure. */
-    kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
-
-    /*!< Pin Interrupt. */
-    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
-    /*!< DMA ITRIG. */
-    kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
-    /*!< DMA OTRIG. */
-    kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-    kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
-} inputmux_connection_t;
-
-/*@}*/
-
-#endif /* _FSL_INPUTMUX_CONNECTIONS_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_IOCON_H_
-#define _FSL_IOCON_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpc_iocon
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief IOCON driver version 2.0.0. */
-#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/**
- * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
- */
-typedef struct _iocon_group
-{
-    uint32_t port : 8;      /* Pin port */
-    uint32_t pin : 8;       /* Pin number */
-    uint32_t modefunc : 16; /* Function and mode */
-} iocon_group_t;
-
-/**
- * @brief IOCON function and mode selection definitions
- * @note See the User Manual for specific modes and functions supported by the various pins.
- */
-    #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4)
-    #define IOCON_FUNC0             0x0             /*!< Selects pin function 0 */
-    #define IOCON_FUNC1             0x1             /*!< Selects pin function 1 */
-    #define IOCON_FUNC2             0x2             /*!< Selects pin function 2 */
-    #define IOCON_FUNC3             0x3             /*!< Selects pin function 3 */
-    #define IOCON_FUNC4             0x4             /*!< Selects pin function 4 */
-    #define IOCON_FUNC5             0x5             /*!< Selects pin function 5 */
-    #define IOCON_FUNC6             0x6             /*!< Selects pin function 6 */
-    #define IOCON_FUNC7             0x7             /*!< Selects pin function 7 */
-    #define IOCON_FUNC8             0x8             /*!< Selects pin function 8 */
-    #define IOCON_FUNC9             0x9             /*!< Selects pin function 9 */
-    #define IOCON_FUNC10            0xA             /*!< Selects pin function 10 */
-    #define IOCON_FUNC11            0xB             /*!< Selects pin function 11 */
-    #define IOCON_FUNC12            0xC             /*!< Selects pin function 12 */
-    #define IOCON_FUNC13            0xD             /*!< Selects pin function 13 */
-    #define IOCON_FUNC14            0xE             /*!< Selects pin function 14 */
-    #define IOCON_FUNC15            0xF             /*!< Selects pin function 15 */
-    #define IOCON_MODE_INACT        (0x0 << 4)      /*!< No addition pin function */
-    #define IOCON_MODE_PULLDOWN     (0x1 << 4)      /*!< Selects pull-down function */
-    #define IOCON_MODE_PULLUP       (0x2 << 4)      /*!< Selects pull-up function */
-    #define IOCON_MODE_REPEATER     (0x3 << 4)      /*!< Selects pin repeater function */
-    #define IOCON_HYS_EN            (0x1 << 6)      /*!< Enables hysteresis */
-    #define IOCON_GPIO_MODE         (0x1 << 6)      /*!< GPIO Mode */
-    #define IOCON_I2C_SLEW          (0x1 << 6)      /*!< I2C Slew Rate Control */
-    #define IOCON_INV_EN            (0x1 << 7)      /*!< Enables invert function on input */
-    #define IOCON_ANALOG_EN         (0x0 << 8)      /*!< Enables analog function by setting 0 to bit 7 */
-    #define IOCON_DIGITAL_EN        (0x1 << 8)      /*!< Enables digital function by setting 1 to bit 7(default) */
-    #define IOCON_STDI2C_EN         (0x1 << 9)      /*!< I2C standard mode/fast-mode */
-    #define IOCON_FASTI2C_EN        (0x3 << 9)      /*!< I2C Fast-mode Plus and high-speed slave */
-    #define IOCON_INPFILT_OFF       (0x1 << 9)      /*!< Input filter Off for GPIO pins */
-    #define IOCON_INPFILT_ON        (0x0 << 9)      /*!< Input filter On for GPIO pins */
-    #define IOCON_OPENDRAIN_EN      (0x1 << 11)      /*!< Enables open-drain function */
-    #define IOCON_S_MODE_0CLK       (0x0 << 12)      /*!< Bypass input filter */
-    #define IOCON_S_MODE_1CLK       (0x1 << 12)      /*!< Input pulses shorter than 1 filter clock are rejected */
-    #define IOCON_S_MODE_2CLK       (0x2 << 12)      /*!< Input pulses shorter than 2 filter clock2 are rejected */
-    #define IOCON_S_MODE_3CLK       (0x3 << 12)      /*!< Input pulses shorter than 3 filter clock2 are rejected */
-    #define IOCON_S_MODE(clks)      ((clks) << 12)   /*!< Select clocks for digital input filter mode */
-    #define IOCON_CLKDIV(div)       ((div) << 14)    /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
-#else
-    #define IOCON_FUNC0 0x0                   /*!< Selects pin function 0 */
-    #define IOCON_FUNC1 0x1                   /*!< Selects pin function 1 */
-    #define IOCON_FUNC2 0x2                   /*!< Selects pin function 2 */
-    #define IOCON_FUNC3 0x3                   /*!< Selects pin function 3 */
-    #define IOCON_FUNC4 0x4                   /*!< Selects pin function 4 */
-    #define IOCON_FUNC5 0x5                   /*!< Selects pin function 5 */
-    #define IOCON_FUNC6 0x6                   /*!< Selects pin function 6 */
-    #define IOCON_FUNC7 0x7                   /*!< Selects pin function 7 */
-    #define IOCON_MODE_INACT (0x0 << 3)       /*!< No addition pin function */
-    #define IOCON_MODE_PULLDOWN (0x1 << 3)    /*!< Selects pull-down function */
-    #define IOCON_MODE_PULLUP (0x2 << 3)      /*!< Selects pull-up function */
-    #define IOCON_MODE_REPEATER (0x3 << 3)    /*!< Selects pin repeater function */
-    #define IOCON_HYS_EN (0x1 << 5)           /*!< Enables hysteresis */
-    #define IOCON_GPIO_MODE (0x1 << 5)        /*!< GPIO Mode */
-    #define IOCON_I2C_SLEW (0x1 << 5)         /*!< I2C Slew Rate Control */
-    #define IOCON_INV_EN (0x1 << 6)           /*!< Enables invert function on input */
-    #define IOCON_ANALOG_EN (0x0 << 7)        /*!< Enables analog function by setting 0 to bit 7 */
-    #define IOCON_DIGITAL_EN (0x1 << 7)       /*!< Enables digital function by setting 1 to bit 7(default) */
-    #define IOCON_STDI2C_EN (0x1 << 8)        /*!< I2C standard mode/fast-mode */
-    #define IOCON_FASTI2C_EN (0x3 << 8)       /*!< I2C Fast-mode Plus and high-speed slave */
-    #define IOCON_INPFILT_OFF (0x1 << 8)      /*!< Input filter Off for GPIO pins */
-    #define IOCON_INPFILT_ON (0x0 << 8)       /*!< Input filter On for GPIO pins */
-    #define IOCON_OPENDRAIN_EN (0x1 << 10)    /*!< Enables open-drain function */
-    #define IOCON_S_MODE_0CLK (0x0 << 11)     /*!< Bypass input filter */
-    #define IOCON_S_MODE_1CLK (0x1 << 11)     /*!< Input pulses shorter than 1 filter clock are rejected */
-    #define IOCON_S_MODE_2CLK (0x2 << 11)     /*!< Input pulses shorter than 2 filter clock2 are rejected */
-    #define IOCON_S_MODE_3CLK (0x3 << 11)     /*!< Input pulses shorter than 3 filter clock2 are rejected */
-    #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
-    #define IOCON_CLKDIV(div) \
-        ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
-#endif
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/**
- * @brief   Sets I/O Control pin mux
- * @param   base        : The base of IOCON peripheral on the chip
- * @param   port        : GPIO port to mux
- * @param   pin         : GPIO pin to mux
- * @param   modefunc    : OR'ed values of type IOCON_*
- * @return  Nothing
- */
-__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
-{
-    base->PIO[port][pin] = modefunc;
-}
-
-/**
- * @brief   Set all I/O Control pin muxing
- * @param   base        : The base of IOCON peripheral on the chip
- * @param   pinArray    : Pointer to array of pin mux selections
- * @param   arrayLength : Number of entries in pinArray
- * @return  Nothing
- */
-__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
-{
-    uint32_t i;
-
-    for (i = 0; i < arrayLength; i++)
-    {
-        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
-    }
-}
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* _FSL_IOCON_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,508 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_lcdc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Max value of LCD_POL[PCD]. */
-#define LCD_PCD_MAX                                  \
-    ((LCD_POL_PCD_LO_MASK >> LCD_POL_PCD_LO_SHIFT) | \
-     (LCD_POL_PCD_HI_MASK >> (LCD_POL_PCD_HI_SHIFT - LCD_POL_PCD_LO_SHIFT)))
-
-/* Macro to contruct the LCD_POL[PCD]. */
-#if (LCD_POL_PCD_LO_MASK != 0x1F)
-#error LCD_POL_PCD_LO is not 5-bit. The macro LCD_POL_PCD_LO_WIDTH should be updated.
-#endif
-#define LCD_POL_PCD_LO_WIDTH 5U
-#define LCD_POL_PCD(pcd) (LCD_POL_PCD_LO(pcd) | LCD_POL_PCD_HI((pcd) >> LCD_POL_PCD_LO_WIDTH))
-
-/* Cursor interrupt. */
-#define LCDC_CURSOR_INT_MASK LCD_CRSR_INTMSK_CRSRIM_MASK
-
-/* Interrupts except cursor interrupt. */
-#define LCDC_NORMAL_INT_MASK \
-    (LCD_INTMSK_FUFIM_MASK | LCD_INTMSK_LNBUIM_MASK | LCD_INTMSK_VCOMPIM_MASK | LCD_INTMSK_BERIM_MASK)
-
-/* Detect the cursor interrupt and normal interrupt bits overlap. */
-#if (LCDC_CURSOR_INT_MASK & LCDC_NORMAL_INT_MASK)
-#error Cursor interrupt and normal interrupt overlap. The driver should be updated.
-#endif
-
-/* The max cursor clip value. */
-#define LCDC_CLIP_MAX (LCD_CRSR_CLIP_CRSRCLIPX_MASK >> LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-static LCD_Type *const s_lcdBases[] = LCD_BASE_PTRS;
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-static const clock_ip_name_t s_lcdClocks[] = LCD_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-static const reset_ip_name_t s_lcdResets[] = LCD_RSTS;
-
-/*******************************************************************************
-* Prototypes
-******************************************************************************/
-
-/*!
- * @brief Gets the LCD instance according to the LCD base
- *
- * @param base LCD peripheral base address.
- * @return LCD instance.
- */
-static uint32_t LCDC_GetInstance(LCD_Type *base);
-
-/*!
- * @brief Calculate the clock divider to generate desired panel clock.
- *
- * @param config Pointer to the LCD configuration.
- * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
- * @param divider The divider result.
- * @return Return false if no divider available to generate the desired clock,
- * otherwise return true;
- */
-static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t LCDC_GetInstance(LCD_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_lcdBases); instance++)
-    {
-        if (s_lcdBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_lcdBases));
-
-    return instance;
-}
-
-static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider)
-{
-    uint16_t cpl;
-    uint32_t pcd;
-
-    *divider = 0U;
-
-    /* Find the PCD. */
-    pcd = (srcClock_Hz + (config->panelClock_Hz / 2U)) / config->panelClock_Hz;
-
-    if (pcd <= 1U)
-    {
-        if (kLCDC_DisplayTFT == config->display)
-        {
-            pcd = 0U;
-            *divider = LCD_POL_BCD_MASK;
-        }
-        else
-        {
-            return false;
-        }
-    }
-    else
-    {
-        pcd -= 2U;
-
-        /* Verify the PCD value. */
-        if (pcd > LCD_PCD_MAX)
-        {
-            return false;
-        }
-
-        if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) ||
-            ((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) ||
-            ((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) ||
-            ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) ||
-            ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) ||
-            ((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U)))
-        {
-            return false;
-        }
-    }
-
-    if (config->display & LCD_CTRL_LCDTFT_MASK)
-    {
-        /* TFT panel. */
-        cpl = config->ppl - 1U;
-    }
-    else
-    {
-        if (config->display & LCD_CTRL_LCDBW_MASK)
-        {
-            if (config->display & LCD_CTRL_LCDMONO8_MASK)
-            {
-                /* 8-bit monochrome STN panel. */
-                cpl = (config->ppl / 8U) - 1U;
-            }
-            else
-            {
-                /* 4-bit monochrome STN panel. */
-                cpl = (config->ppl / 4U) - 1U;
-            }
-        }
-        else
-        {
-            /* Color STN panel. */
-            cpl = ((config->ppl * 3U) / 8U) - 1U;
-        }
-    }
-
-    *divider |= (LCD_POL_CPL(cpl) | LCD_POL_PCD(pcd));
-
-    return true;
-}
-
-status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz)
-{
-    assert(config);
-    assert(srcClock_Hz);
-    assert((config->ppl & 0xFU) == 0U);
-    assert((config->upperPanelAddr & 0x07U) == 0U);
-    assert((config->lowerPanelAddr & 0x07U) == 0U);
-
-    uint32_t reg;
-    uint32_t divider;
-    uint32_t instance;
-
-    /* Verify the clock here. */
-    if (!LCDC_GetClockDivider(config, srcClock_Hz, &divider))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    instance = LCDC_GetInstance(base);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_EnableClock(s_lcdClocks[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the module */
-    RESET_PeripheralReset(s_lcdResets[instance]);
-
-    /* Set register CTRL. */
-    reg = base->CTRL & (LCD_CTRL_LCDVCOMP_MASK | LCD_CTRL_WATERMARK_MASK);
-    reg |= (uint32_t)(config->dataFormat) | (uint32_t)(config->display) | LCD_CTRL_LCDBPP(config->bpp);
-
-    if (config->swapRedBlue)
-    {
-        reg |= LCD_CTRL_BGR_MASK;
-    }
-
-    base->CTRL = reg;
-
-    /* Clean pending interrupts and disable all interrupts. */
-    base->INTCLR = LCDC_NORMAL_INT_MASK;
-    base->CRSR_INTCLR = LCDC_CURSOR_INT_MASK;
-    base->INTMSK = 0U;
-    base->CRSR_INTMSK = 0U;
-
-    /* Configure timing. */
-    base->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) |
-                 LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U);
-
-    base->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) |
-                 LCD_TIMV_VBP(config->vbp - 1U);
-
-    base->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | divider;
-
-    /* Line end configuration. */
-    if (config->enableLineEnd)
-    {
-        base->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK;
-    }
-    else
-    {
-        base->LE = 0U;
-    }
-
-    /* Set panel frame base address. */
-    base->UPBASE = config->upperPanelAddr;
-    base->LPBASE = config->lowerPanelAddr;
-
-    return kStatus_Success;
-}
-
-void LCDC_Deinit(LCD_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_EnableClock(s_lcdClocks[LCDC_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void LCDC_GetDefaultConfig(lcdc_config_t *config)
-{
-    config->panelClock_Hz = 0U;
-    config->ppl = 0U;
-    config->hsw = 0U;
-    config->hfp = 0U;
-    config->hbp = 0U;
-    config->lpp = 0U;
-    config->vsw = 0U;
-    config->vfp = 0U;
-    config->vbp = 0U;
-    config->acBiasFreq = 1U;
-    config->polarityFlags = 0U;
-    config->enableLineEnd = false;
-    config->lineEndDelay = 0U;
-    config->upperPanelAddr = 0U;
-    config->lowerPanelAddr = 0U;
-    config->bpp = kLCDC_1BPP;
-    config->dataFormat = kLCDC_LittleEndian;
-    config->swapRedBlue = false;
-    config->display = kLCDC_DisplayTFT;
-}
-
-void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr)
-{
-    /* The base address must be doubleword aligned. */
-    assert((addr & 0x07U) == 0U);
-
-    if (kLCDC_UpperPanel == panel)
-    {
-        base->UPBASE = addr;
-    }
-    else
-    {
-        base->LPBASE = addr;
-    }
-}
-
-void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words)
-{
-    assert(count_words <= ARRAY_SIZE(base->PAL));
-
-    uint32_t i;
-
-    for (i = 0; i < count_words; i++)
-    {
-        base->PAL[i] = palette[i];
-    }
-}
-
-void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask)
-{
-    uint32_t reg;
-
-    reg = mask & LCDC_CURSOR_INT_MASK;
-    if (reg)
-    {
-        base->CRSR_INTMSK |= reg;
-    }
-
-    reg = mask & LCDC_NORMAL_INT_MASK;
-    if (reg)
-    {
-        base->INTMSK |= reg;
-    }
-}
-
-void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask)
-{
-    uint32_t reg;
-
-    reg = mask & LCDC_CURSOR_INT_MASK;
-    if (reg)
-    {
-        base->CRSR_INTMSK &= ~reg;
-    }
-
-    reg = mask & LCDC_NORMAL_INT_MASK;
-    if (reg)
-    {
-        base->INTMSK &= ~reg;
-    }
-}
-
-uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base)
-{
-    uint32_t reg;
-
-    reg = base->CRSR_INTRAW;
-    reg |= base->INTRAW;
-
-    return reg;
-}
-
-uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base)
-{
-    uint32_t reg;
-
-    reg = base->CRSR_INTSTAT;
-    reg |= base->INTSTAT;
-
-    return reg;
-}
-
-void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask)
-{
-    uint32_t reg;
-
-    reg = mask & LCDC_CURSOR_INT_MASK;
-    if (reg)
-    {
-        base->CRSR_INTCLR = reg;
-    }
-
-    reg = mask & LCDC_NORMAL_INT_MASK;
-    if (reg)
-    {
-        base->INTCLR = reg;
-    }
-}
-
-void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config)
-{
-    assert(config);
-
-    uint32_t i;
-
-    base->CRSR_CFG = LCD_CRSR_CFG_CRSRSIZE(config->size) | LCD_CRSR_CFG_FRAMESYNC(config->syncMode);
-
-    /* Set position. */
-    LCDC_SetCursorPosition(base, 0, 0);
-
-    /* Palette. */
-    base->CRSR_PAL0 = ((uint32_t)config->palette0.red << LCD_CRSR_PAL0_RED_SHIFT) |
-                      ((uint32_t)config->palette0.blue << LCD_CRSR_PAL0_BLUE_SHIFT) |
-                      ((uint32_t)config->palette0.green << LCD_CRSR_PAL0_GREEN_SHIFT);
-    base->CRSR_PAL1 = ((uint32_t)config->palette1.red << LCD_CRSR_PAL1_RED_SHIFT) |
-                      ((uint32_t)config->palette1.blue << LCD_CRSR_PAL1_BLUE_SHIFT) |
-                      ((uint32_t)config->palette1.green << LCD_CRSR_PAL1_GREEN_SHIFT);
-
-    /* Image of cursors. */
-    if (kLCDC_CursorSize64 == config->size)
-    {
-        assert(config->image[0]);
-        LCDC_SetCursorImage(base, config->size, 0, config->image[0]);
-    }
-    else
-    {
-        for (i = 0; i < LCDC_CURSOR_COUNT; i++)
-        {
-            if (config->image[i])
-            {
-                LCDC_SetCursorImage(base, config->size, i, config->image[i]);
-            }
-        }
-    }
-}
-
-void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config)
-{
-    uint32_t i;
-
-    config->size = kLCDC_CursorSize32;
-    config->syncMode = kLCDC_CursorAsync;
-    config->palette0.red = 0U;
-    config->palette0.green = 0U;
-    config->palette0.blue = 0U;
-    config->palette1.red = 255U;
-    config->palette1.green = 255U;
-    config->palette1.blue = 255U;
-
-    for (i = 0; i < LCDC_CURSOR_COUNT; i++)
-    {
-        config->image[i] = (uint32_t *)0;
-    }
-}
-
-void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY)
-{
-    uint32_t clipX;
-    uint32_t clipY;
-
-    if (positionX < 0)
-    {
-        clipX = -positionX;
-        positionX = 0U;
-
-        /* If clip value too large, set to the max value. */
-        if (clipX > LCDC_CLIP_MAX)
-        {
-            clipX = LCDC_CLIP_MAX;
-        }
-    }
-    else
-    {
-        clipX = 0U;
-    }
-
-    if (positionY < 0)
-    {
-        clipY = -positionY;
-        positionY = 0U;
-
-        /* If clip value too large, set to the max value. */
-        if (clipY > LCDC_CLIP_MAX)
-        {
-            clipY = LCDC_CLIP_MAX;
-        }
-    }
-    else
-    {
-        clipY = 0U;
-    }
-
-    base->CRSR_CLIP = LCD_CRSR_CLIP_CRSRCLIPX(clipX) | LCD_CRSR_CLIP_CRSRCLIPY(clipY);
-    base->CRSR_XY = LCD_CRSR_XY_CRSRX(positionX) | LCD_CRSR_XY_CRSRY(positionY);
-}
-
-void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image)
-{
-    uint32_t regStart;
-    uint32_t i;
-    uint32_t len;
-
-    if (kLCDC_CursorSize64 == size)
-    {
-        regStart = 0U;
-        len = LCDC_CURSOR_IMG_64X64_WORDS;
-    }
-    else
-    {
-        regStart = index * LCDC_CURSOR_IMG_32X32_WORDS;
-        len = LCDC_CURSOR_IMG_32X32_WORDS;
-    }
-
-    for (i = 0U; i < len; i++)
-    {
-        base->CRSR_IMG[regStart + i] = image[i];
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,608 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __FSL_LCDC_H__
-#define __FSL_LCDC_H__
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup lpc_lcdc
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief LCDC driver version 2.0.0. */
-#define LPC_LCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*!@brief How many hardware cursors supports. */
-#define LCDC_CURSOR_COUNT 4
-
-/*!@brief LCD cursor image bits per pixel. */
-#define LCDC_CURSOR_IMG_BPP 2
-
-/*!@brief LCD 32x32 cursor image size in word(32-bit). */
-#define LCDC_CURSOR_IMG_32X32_WORDS (32 * 32 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
-
-/*!@brief LCD 64x64 cursor image size in word(32-bit). */
-#define LCDC_CURSOR_IMG_64X64_WORDS (64 * 64 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
-
-/*!@brief LCD palette size in words(32-bit). */
-#define LCDC_PALETTE_SIZE_WORDS (ARRAY_SIZE(((LCD_Type *)0)->PAL))
-
-/*!
- * @brief LCD sigal polarity flags.
- */
-enum _lcdc_polarity_flags
-{
-    kLCDC_InvertVsyncPolarity = LCD_POL_IVS_MASK, /*!< Invert the VSYNC polarity, set to active low. */
-    kLCDC_InvertHsyncPolarity = LCD_POL_IHS_MASK, /*!< Invert the HSYNC polarity, set to active low. */
-    kLCDC_InvertClkPolarity = LCD_POL_IPC_MASK,   /*!< Invert the panel clock polarity, set to
-                                                      drive data on falling edge. */
-    kLCDC_InvertDePolarity = LCD_POL_IOE_MASK,    /*!< Invert the data enable (DE) polarity, set to active low. */
-};
-
-/*!
- * @brief LCD bits per pixel.
- */
-typedef enum _lcdc_bpp
-{
-    kLCDC_1BPP = 0U,     /*!< 1 bpp. */
-    kLCDC_2BPP = 1U,     /*!< 2 bpp. */
-    kLCDC_4BPP = 2U,     /*!< 4 bpp. */
-    kLCDC_8BPP = 3U,     /*!< 8 bpp. */
-    kLCDC_16BPP = 4U,    /*!< 16 bpp. */
-    kLCDC_24BPP = 5U,    /*!< 24 bpp, TFT panel only. */
-    kLCDC_16BPP565 = 6U, /*!< 16 bpp, 5:6:5 mode. */
-    kLCDC_12BPP = 7U,    /*!< 12 bpp, 4:4:4 mode. */
-} lcdc_bpp_t;
-
-/*!
- * @brief The types of display panel.
- */
-typedef enum _lcdc_display
-{
-    kLCDC_DisplayTFT = LCD_CTRL_LCDTFT_MASK, /*!< Active matrix TFT panels with up to 24-bit bus interface. */
-    kLCDC_DisplaySingleMonoSTN4Bit = LCD_CTRL_LCDBW_MASK, /*!< Single-panel monochrome STN (4-bit bus interface). */
-    kLCDC_DisplaySingleMonoSTN8Bit =
-        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK, /*!< Single-panel monochrome STN (8-bit bus interface). */
-    kLCDC_DisplayDualMonoSTN4Bit =
-        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */
-    kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK |
-                                  LCD_CTRL_LCDDUAL_MASK,  /*!< Dual-panel monochrome STN (8-bit bus interface). */
-    kLCDC_DisplaySingleColorSTN8Bit = 0U,                  /*!< Single-panel color STN (8-bit bus interface). */
-    kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */
-} lcdc_display_t;
-
-/*!
- * @brief LCD panel buffer data format.
- */
-typedef enum _lcdc_data_format
-{
-    kLCDC_LittleEndian = 0U,                                   /*!< Little endian byte, little endian pixel. */
-    kLCDC_BigEndian = LCD_CTRL_BEPO_MASK | LCD_CTRL_BEBO_MASK, /*!< Big endian byte, big endian pixel. */
-    kLCDC_WinCeMode = LCD_CTRL_BEPO_MASK, /*!< little-endian byte, big-endian pixel for Windows CE mode. */
-} lcdc_data_format_t;
-
-/*!
- * @brief LCD configuration structure.
- */
-typedef struct _lcdc_config
-{
-    uint32_t panelClock_Hz;  /*!< Panel clock in Hz. */
-    uint16_t ppl;            /*!< Pixels per line, it must could be divided by 16. */
-    uint8_t hsw;             /*!< HSYNC pulse width. */
-    uint8_t hfp;             /*!< Horizontal front porch. */
-    uint8_t hbp;             /*!< Horizontal back porch. */
-    uint16_t lpp;            /*!< Lines per panal. */
-    uint8_t vsw;             /*!< VSYNC pulse width. */
-    uint8_t vfp;             /*!< Vrtical front porch. */
-    uint8_t vbp;             /*!< Vertical back porch. */
-    uint8_t acBiasFreq;      /*!< The number of line clocks between AC bias pin toggling. Only used for STN display. */
-    uint16_t polarityFlags;  /*!< OR'ed value of @ref _lcdc_polarity_flags, used to contol the signal polarity. */
-    bool enableLineEnd;      /*!< Enable line end or not, the line end is a positive pulse with 4 panel clock. */
-    uint8_t lineEndDelay;    /*!< The panel clocks between the last pixel of line and the start of line end. */
-    uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */
-    uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */
-    lcdc_bpp_t bpp;           /*!< LCD bits per pixel. */
-    lcdc_data_format_t dataFormat; /*!< Data format. */
-    bool swapRedBlue;             /*!< Set true to use BGR format, set false to choose RGB format. */
-    lcdc_display_t display;        /*!< The display type. */
-} lcdc_config_t;
-
-/*!
- * @brief LCD vertical compare interrupt mode.
- */
-typedef enum _lcdc_vertical_compare_interrupt_mode
-{
-    kLCDC_StartOfVsync,       /*!< Generate vertical compare interrupt at start of VSYNC. */
-    kLCDC_StartOfBackPorch,   /*!< Generate vertical compare interrupt at start of back porch. */
-    kLCDC_StartOfActiveVideo, /*!< Generate vertical compare interrupt at start of active video. */
-    kLCDC_StartOfFrontPorch,  /*!< Generate vertical compare interrupt at start of front porch. */
-} lcdc_vertical_compare_interrupt_mode_t;
-
-/*!
- * @brief LCD interrupts.
- */
-enum _lcdc_interrupts
-{
-    kLCDC_CursorInterrupt = LCD_CRSR_INTMSK_CRSRIM_MASK,      /*!< Cursor image read finished interrupt. */
-    kLCDC_FifoUnderflowInterrupt = LCD_INTMSK_FUFIM_MASK,     /*!< FIFO underflow interrupt. */
-    kLCDC_BaseAddrUpdateInterrupt = LCD_INTMSK_LNBUIM_MASK,   /*!< Panel frame base address update interrupt. */
-    kLCDC_VerticalCompareInterrupt = LCD_INTMSK_VCOMPIM_MASK, /*!< Vertical compare interrupt. */
-    kLCDC_AhbErrorInterrupt = LCD_INTMSK_BERIM_MASK,          /*!< AHB master error interrupt. */
-};
-
-/*!
- * @brief LCD panel frame.
- */
-typedef enum _lcdc_panel
-{
-    kLCDC_UpperPanel, /*!< Upper panel frame. */
-    kLCDC_LowerPanel  /*!< Lower panel frame. */
-} lcdc_panel_t;
-
-/*!
- * @brief LCD hardware cursor size
- */
-typedef enum _lcdc_cursor_size
-{
-    kLCDC_CursorSize32, /*!< 32x32 pixel cursor. */
-    kLCDC_CursorSize64, /*!< 64x64 pixel cursor. */
-} lcdc_cursor_size_t;
-
-/*!
- * @brief LCD hardware cursor palette
- */
-typedef struct _lcdc_cursor_palette
-{
-    uint8_t red;   /*!< Red color component. */
-    uint8_t green; /*!< Red color component. */
-    uint8_t blue;  /*!< Red color component. */
-} lcdc_cursor_palette_t;
-
-/*!
- * @brief LCD hardware cursor frame synchronization mode.
- */
-typedef enum _lcdc_cursor_sync_mode
-{
-    kLCDC_CursorAsync, /*!< Cursor change will be displayed immediately. */
-    kLCDC_CursorSync,  /*!< Cursor change will be displayed in next frame. */
-} lcdc_cursor_sync_mode_t;
-
-/*!
- * @brief LCD hardware cursor configuration structure.
- */
-typedef struct _lcdc_cursor_config
-{
-    lcdc_cursor_size_t size;            /*!< Cursor size. */
-    lcdc_cursor_sync_mode_t syncMode;   /*!< Cursor synchronization mode. */
-    lcdc_cursor_palette_t palette0;     /*!< Cursor palette 0. */
-    lcdc_cursor_palette_t palette1;     /*!< Cursor palette 1. */
-    uint32_t *image[LCDC_CURSOR_COUNT]; /*!< Pointer to cursor image data. */
-} lcdc_cursor_config_t;
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-/*!
- * @name Initialization and Deinitialization
- * @{
- */
-
-/*!
- * @brief Initialize the LCD module.
- *
- * @param base LCD peripheral base address.
- * @param config Pointer to configuration structure, see to @ref lcdc_config_t.
- * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
- * @retval kStatus_Success LCD is initialized successfully.
- * @retval kStatus_InvalidArgument Initlialize failed because of invalid argument.
- */
-status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz);
-
-/*!
- * @brief Deinitialize the LCD module.
- *
- * @param base LCD peripheral base address.
- */
-void LCDC_Deinit(LCD_Type *base);
-
-/*!
- * @brief Gets default pre-defined settings for initial configuration.
- *
- * This function initializes the configuration structure. The default values are:
- *
-   @code
-    config->panelClock_Hz = 0U;
-    config->ppl = 0U;
-    config->hsw = 0U;
-    config->hfp = 0U;
-    config->hbp = 0U;
-    config->lpp = 0U;
-    config->vsw = 0U;
-    config->vfp = 0U;
-    config->vbp = 0U;
-    config->acBiasFreq = 1U;
-    config->polarityFlags = 0U;
-    config->enableLineEnd = false;
-    config->lineEndDelay = 0U;
-    config->upperPanelAddr = 0U;
-    config->lowerPanelAddr = 0U;
-    config->bpp = kLCDC_1BPP;
-    config->dataFormat = kLCDC_LittleEndian;
-    config->swapRedBlue = false;
-    config->display = kLCDC_DisplayTFT;
-   @endcode
- *
- * @param config Pointer to configuration structure.
- */
-void LCDC_GetDefaultConfig(lcdc_config_t *config);
-
-/* @} */
-
-/*!
- * @name Start and stop
- * @{
- */
-
-/*!
- * @brief Start to output LCD timing signal.
- *
- * The LCD power up sequence should be:
- * 1. Apply power to LCD, here all output signals are held low.
- * 2. When LCD power stablized, call @ref LCDC_Start to output the timing signals.
- * 3. Apply contrast voltage to LCD panel. Delay if the display requires.
- * 4. Call @ref LCDC_PowerUp.
- *
- * @param base LCD peripheral base address.
- */
-static inline void LCDC_Start(LCD_Type *base)
-{
-    base->CTRL |= LCD_CTRL_LCDEN_MASK;
-}
-
-/*!
- * @brief Stop the LCD timing signal.
- *
- * The LCD power down sequence should be:
- * 1. Call @ref LCDC_PowerDown.
- * 2. Delay if the display requires. Disable contrast voltage to LCD panel.
- * 3. Call @ref LCDC_Stop to disable the timing signals.
- * 4. Disable power to LCD.
- *
- * @param base LCD peripheral base address.
- */
-static inline void LCDC_Stop(LCD_Type *base)
-{
-    base->CTRL &= ~LCD_CTRL_LCDEN_MASK;
-}
-
-/*!
- * @brief Power up the LCD and output the pixel signal.
- *
- * @param base LCD peripheral base address.
- */
-static inline void LCDC_PowerUp(LCD_Type *base)
-{
-    base->CTRL |= LCD_CTRL_LCDPWR_MASK;
-}
-
-/*!
- * @brief Power down the LCD and disable the output pixel signal.
- *
- * @param base LCD peripheral base address.
- */
-static inline void LCDC_PowerDown(LCD_Type *base)
-{
-    base->CTRL &= ~LCD_CTRL_LCDPWR_MASK;
-}
-
-/* @} */
-
-/*!
- * @name LCD control
- * @{
- */
-
-/*!
- * @brief Sets panel frame base address
- *
- * @param base LCD peripheral base address.
- * @param panel Which panel to set.
- * @param addr Frame base address, must be doubleword(64-bit) aligned.
- */
-void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr);
-
-/*!
- * @brief Sets palette
- *
- * @param base LCD peripheral base address.
- * @param palette Pointer to the palette array.
- * @param count_words Length of the palette array to set (how many words), it should
- * not be larger than LCDC_PALETTE_SIZE_WORDS.
- */
-void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words);
-
-/* @} */
-
-/*!
- * @name Interrupts
- * @{
- */
-
-/*!
- * @brief Sets the vertical compare interrupt mode.
- *
- * @param base LCD peripheral base address.
- * @param mode The vertical compare interrupt mode.
- */
-static inline void LCDC_SetVerticalInterruptMode(LCD_Type *base, lcdc_vertical_compare_interrupt_mode_t mode)
-{
-    base->CTRL = (base->CTRL & ~LCD_CTRL_LCDVCOMP_MASK) | LCD_CTRL_LCDVCOMP(mode);
-}
-
-/*!
- * @brief Enable LCD interrupts.
- *
- * Example to enable LCD base address update interrupt and vertical compare
- * interrupt:
- *
- * @code
-   LCDC_EnableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
-   @endcode
- *
- * @param base LCD peripheral base address.
- * @param mask Interrupts to enable, it is OR'ed value of @ref _lcdc_interrupts.
- */
-void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask);
-
-/*!
- * @brief Disable LCD interrupts.
- *
- * Example to disable LCD base address update interrupt and vertical compare
- * interrupt:
- *
- * @code
-   LCDC_DisableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
-   @endcode
- *
- * @param base LCD peripheral base address.
- * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
- */
-void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask);
-
-/*!
- * @brief Get LCD interrupt pending status.
- *
- * Example:
- *
- * @code
-   uint32_t status;
-
-   status = LCDC_GetInterruptsPendingStatus(LCD);
-
-   if (kLCDC_BaseAddrUpdateInterrupt & status)
-   {
-       // LCD base address update interrupt occurred.
-   }
-
-   if (kLCDC_VerticalCompareInterrupt & status)
-   {
-       // LCD vertical compare interrupt occurred.
-   }
-   @endcode
- *
- * @param base LCD peripheral base address.
- * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
- */
-uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base);
-
-/*!
- * @brief Get LCD enabled interrupt pending status.
- *
- * This function is similar with @ref LCDC_GetInterruptsPendingStatus, the only
- * difference is, this function only returns the pending status of the
- * interrupts that have been enabled using @ref LCDC_EnableInterrupts.
- *
- * @param base LCD peripheral base address.
- * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
- */
-uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base);
-
-/*!
- * @brief Clear LCD interrupts pending status.
- *
- * Example to clear LCD base address update interrupt and vertical compare
- * interrupt pending status:
- *
- * @code
-   LCDC_ClearInterruptsStatus(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
-   @endcode
- *
- * @param base LCD peripheral base address.
- * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
- */
-void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask);
-
-/* @} */
-
-/*!
- * @name Hardware cursor
- * @{
- */
-
-/*!
- * @brief Set the hardware cursor configuration
- *
- * This function should be called before enabling the hardware cursor.
- * It supports initializing multiple cursor images at a time when using
- * 32x32 pixels cursor.
- *
- * For example:
- *
- * @code
-   uint32_t cursor0Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
-   uint32_t cursor2Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
-
-   lcdc_cursor_config_t cursorConfig;
-
-   LCDC_CursorGetDefaultConfig(&cursorConfig);
-
-   cursorConfig.image[0] = cursor0Img;
-   cursorConfig.image[2] = cursor2Img;
-
-   LCDC_SetCursorConfig(LCD, &cursorConfig);
-
-   LCDC_ChooseCursor(LCD, 0);
-   LCDC_SetCursorPosition(LCD, 0, 0);
-
-   LCDC_EnableCursor(LCD);
-   @endcode
- *
- * In this example, cursor 0 and cursor 2 image data are initialized, but cursor 1
- * and cursor 3 image data are not initialized because image[1] and image[2] are
- * all NULL. With this, application could initializes all cursor images it will
- * use at the beginning and call @ref LCDC_SetCursorImage directly to display the
- * one which it needs.
- *
- * @param base LCD peripheral base address.
- * @param config Pointer to the hardware cursor configuration structure.
- */
-void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config);
-
-/*!
- * @brief Get the hardware cursor default configuration
- *
- * The default configuration values are:
- *
- * @code
-    config->size = kLCDC_CursorSize32;
-    config->syncMode = kLCDC_CursorAsync;
-    config->palette0.red = 0U;
-    config->palette0.green = 0U;
-    config->palette0.blue = 0U;
-    config->palette1.red = 255U;
-    config->palette1.green = 255U;
-    config->palette1.blue = 255U;
-    config->image[0] = (uint32_t *)0;
-    config->image[1] = (uint32_t *)0;
-    config->image[2] = (uint32_t *)0;
-    config->image[3] = (uint32_t *)0;
-   @endcode
- *
- * @param config Pointer to the hardware cursor configuration structure.
- */
-void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config);
-
-/*!
- * @brief Enable or disable the cursor.
- *
- * @param base LCD peripheral base address.
- * @param enable True to enable, false to disable.
- */
-static inline void LCDC_EnableCursor(LCD_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CRSR_CTRL |= LCD_CRSR_CTRL_CRSRON_MASK;
-    }
-    else
-    {
-        base->CRSR_CTRL &= ~LCD_CRSR_CTRL_CRSRON_MASK;
-    }
-}
-
-/*!
- * @brief Choose which cursor to display.
- *
- * When using 32x32 cursor, the number of cursors supports is @ref LCDC_CURSOR_COUNT.
- * When using 64x64 cursor, the LCD only supports one cursor.
- * This function selects which cursor to display when using 32x32 cursor.
- * When synchronization mode is @ref kLCDC_CursorSync, the change effects in the
- * next frame. When synchronization mode is @ref * kLCDC_CursorAsync, change effects
- * immediately.
- *
- * @param base LCD peripheral base address.
- * @param index Index of the cursor to display.
- * @note The function @ref LCDC_SetCursorPosition must be called after this function
- * to show the new cursor.
- */
-static inline void LCDC_ChooseCursor(LCD_Type *base, uint8_t index)
-{
-    base->CRSR_CTRL = (base->CRSR_CTRL & ~LCD_CRSR_CTRL_CRSRNUM1_0_MASK) | LCD_CRSR_CTRL_CRSRNUM1_0(index);
-}
-
-/*!
- * @brief Set the position of cursor
- *
- * When synchronization mode is @ref kLCDC_CursorSync, position change effects
- * in the next frame. When synchronization mode is @ref kLCDC_CursorAsync,
- * position change effects immediately.
- *
- * @param base LCD peripheral base address.
- * @param positionX X ordinate of the cursor top-left measured in pixels
- * @param positionY Y ordinate of the cursor top-left measured in pixels
- */
-void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY);
-
-/*!
- * @brief Set the cursor image.
- *
- * The interrupt @ref kLCDC_CursorInterrupt indicates that last cursor pixel is
- * displayed. When the hardware cursor is enabled,
- *
- * @param base LCD peripheral base address.
- * @param size The cursor size.
- * @param index Index of the cursor to set when using 32x32 cursor.
- * @param image Pointer to the cursor image. When using 32x32 cursor, the image
- * size should be LCDC_CURSOR_IMG_32X32_WORDS. When using 64x64 cursor, the image
- * size should be LCDC_CURSOR_IMG_64X64_WORDS.
- */
-void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __FSL_LCDC_H__ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,862 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_mcan.h"
-
-/*******************************************************************************
- * Definitons
- ******************************************************************************/
-
-#define MCAN_TIME_QUANTA_NUM (16U)
-
-/*! @brief MCAN Internal State. */
-enum _mcan_state
-{
-    kMCAN_StateIdle = 0x0,     /*!< MB/RxFIFO idle.*/
-    kMCAN_StateRxData = 0x1,   /*!< MB receiving.*/
-    kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
-    kMCAN_StateTxData = 0x3,   /*!< MB transmitting.*/
-    kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
-    kMCAN_StateRxFifo = 0x5,   /*!< RxFIFO receiving.*/
-};
-
-/* Typedef for interrupt handler. */
-typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle);
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get the MCAN instance from peripheral base address.
- *
- * @param base MCAN peripheral base address.
- * @return MCAN instance.
- */
-uint32_t MCAN_GetInstance(CAN_Type *base);
-
-/*!
- * @brief Reset the MCAN instance.
- *
- * @param base MCAN peripheral base address.
- */
-static void MCAN_Reset(CAN_Type *base);
-
-/*!
- * @brief Set Baud Rate of MCAN.
- *
- * This function set the baud rate of MCAN.
- *
- * @param base MCAN peripheral base address.
- * @param sourceClock_Hz Source Clock in Hz.
- * @param baudRate_Bps Baud Rate in Bps.
- */
-static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps);
-
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-/*!
- * @brief Set Baud Rate of MCAN FD.
- *
- * This function set the baud rate of MCAN FD.
- *
- * @param base MCAN peripheral base address.
- * @param sourceClock_Hz Source Clock in Hz.
- * @param baudRateD_Bps Baud Rate in Bps.
- */
-static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps);
-#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
-
-/*!
- * @brief Get the element's address when read receive fifo 0.
- *
- * @param base MCAN peripheral base address.
- * @return Address of the element in receive fifo 0.
- */
-static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base);
-
-/*!
- * @brief Get the element's address when read receive fifo 1.
- *
- * @param base MCAN peripheral base address.
- * @return Address of the element in receive fifo 1.
- */
-static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base);
-
-/*!
- * @brief Get the element's address when read receive buffer.
- *
- * @param base MCAN peripheral base address.
- * @param idx Number of the erceive buffer element.
- * @return Address of the element in receive buffer.
- */
-static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx);
-
-/*!
- * @brief Get the element's address when read transmit buffer.
- *
- * @param base MCAN peripheral base address.
- * @param idx Number of the transmit buffer element.
- * @return Address of the element in transmit buffer.
- */
-static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* Array of MCAN handle. */
-static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT];
-
-/* Array of MCAN peripheral base address. */
-static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS;
-
-/* Array of MCAN IRQ number. */
-static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/* Array of MCAN clock name. */
-static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/* MCAN ISR for transactional APIs. */
-static mcan_isr_t s_mcanIsr;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-uint32_t MCAN_GetInstance(CAN_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++)
-    {
-        if (s_mcanBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_mcanBases));
-
-    return instance;
-}
-
-static void MCAN_Reset(CAN_Type *base)
-{
-    /* Set INIT bit. */
-    base->CCCR |= CAN_CCCR_INIT_MASK;
-    /* Confirm the value has been accepted. */
-    while (!((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
-    {
-    }
-
-    /* Set CCE bit to have access to the protected configuration registers,
-       and clear some status registers. */
-    base->CCCR |= CAN_CCCR_CCE_MASK;
-}
-
-static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps)
-{
-    mcan_timing_config_t timingConfigA;
-    uint32_t preDivA = baudRateA_Bps * MCAN_TIME_QUANTA_NUM;
-
-    if (0 == preDivA)
-    {
-        preDivA = 1U;
-    }
-
-    preDivA = (sourceClock_Hz / preDivA) - 1U;
-
-    /* Desired baud rate is too low. */
-    if (preDivA > 0x1FFU)
-    {
-        preDivA = 0x1FFU;
-    }
-
-    /* MCAN timing setting formula:
-     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
-     */
-    timingConfigA.preDivider = preDivA;
-    timingConfigA.seg1 = 0xAU;
-    timingConfigA.seg2 = 0x3U;
-    timingConfigA.rJumpwidth = 0x3U;
-
-    /* Update actual timing characteristic. */
-    MCAN_SetArbitrationTimingConfig(base, &timingConfigA);
-}
-
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps)
-{
-    mcan_timing_config_t timingConfigD;
-    uint32_t preDivD = baudRateD_Bps * MCAN_TIME_QUANTA_NUM;
-
-    if (0 == preDivD)
-    {
-        preDivD = 1U;
-    }
-
-    preDivD = (sourceClock_Hz / preDivD) - 1U;
-
-    /* Desired baud rate is too low. */
-    if (preDivD > 0x1FU)
-    {
-        preDivD = 0x1FU;
-    }
-
-    /* MCAN timing setting formula:
-     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
-     */
-    timingConfigD.preDivider = preDivD;
-    timingConfigD.seg1 = 0xAU;
-    timingConfigD.seg2 = 0x3U;
-    timingConfigD.rJumpwidth = 0x3U;
-
-    /* Update actual timing characteristic. */
-    MCAN_SetDataTimingConfig(base, &timingConfigD);
-}
-#endif
-
-void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable MCAN clock. */
-    CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    MCAN_Reset(base);
-
-    if (config->enableLoopBackInt)
-    {
-        base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK;
-        base->TEST |= CAN_TEST_LBCK_MASK;
-    }
-    if (config->enableLoopBackExt)
-    {
-        base->CCCR |= CAN_CCCR_TEST_MASK;
-        base->TEST |= CAN_TEST_LBCK_MASK;
-    }
-    if (config->enableBusMon)
-    {
-        base->CCCR |= CAN_CCCR_MON_MASK;
-    }
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-    if (config->enableCanfdNormal)
-    {
-        base->CCCR |= CAN_CCCR_FDOE_MASK;
-    }
-    if (config->enableCanfdSwitch)
-    {
-        base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK;
-    }
-#endif
-
-    /* Set baud rate of arbitration and data phase. */
-    MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA);
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-    MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD);
-#endif
-}
-
-void MCAN_Deinit(CAN_Type *base)
-{
-    /* Reset all Register Contents. */
-    MCAN_Reset(base);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable MCAN clock. */
-    CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void MCAN_EnterNormalMode(CAN_Type *base)
-{
-    /* Reset INIT bit to enter normal mode. */
-    base->CCCR &= ~CAN_CCCR_INIT_MASK;
-    while (((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
-    {
-    }
-}
-
-void MCAN_GetDefaultConfig(mcan_config_t *config)
-{
-    /* Assertion. */
-    assert(config);
-
-    /* Initialize MCAN Module config struct with default value. */
-    config->baudRateA = 500000U;
-    config->baudRateD = 500000U;
-    config->enableCanfdNormal = false;
-    config->enableCanfdSwitch = false;
-    config->enableLoopBackInt = false;
-    config->enableLoopBackExt = false;
-    config->enableBusMon = false;
-}
-
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
-{
-    /* Assertion. */
-    assert(config);
-
-    /* Cleaning previous Timing Setting. */
-    base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK);
-
-    /* Updating Timing Setting according to configuration structure. */
-    base->DBTP |= (CAN_DBTP_DBRP(config->preDivider) | CAN_DBTP_DSJW(config->rJumpwidth) |
-                   CAN_DBTP_DTSEG1(config->seg1) | CAN_DBTP_DTSEG2(config->seg2));
-}
-#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
-
-void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
-{
-    /* Assertion. */
-    assert(config);
-
-    /* Cleaning previous Timing Setting. */
-    base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK);
-
-    /* Updating Timing Setting according to configuration structure. */
-    base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) |
-                   CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2));
-}
-
-void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config)
-{
-    /* Set global configuration of remote/nonmasking frames, set filter address and list size. */
-    if (config->idFormat == kMCAN_FrameIDStandard)
-    {
-        base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame);
-        base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize);
-    }
-    else
-    {
-        base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame);
-        base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize);
-    }
-}
-
-void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
-{
-    /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */
-    base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) |
-                   CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode);
-    /* Set Rx FIFO 0 data field size */
-    base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize);
-}
-
-void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
-{
-    /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */
-    base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) |
-                   CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode);
-    /* Set Rx FIFO 1 data field size */
-    base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize);
-}
-
-void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config)
-{
-    /* Set Rx Buffer start address. */
-    base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT);
-    /* Set Rx Buffer data field size */
-    base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize);
-}
-
-void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config)
-{
-    /* Set TX Event FIFO start address, element size, watermark. */
-    base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) |
-                   CAN_TXEFC_EFWM(config->watermark);
-}
-
-void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config)
-{
-    assert((config->dedicatedSize + config->fqSize) <= 32U);
-
-    /* Set Tx Buffer start address, size, fifo/queue mode. */
-    base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) |
-                  CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode);
-    /* Set Tx Buffer data field size */
-    base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize);
-}
-
-void MCAN_SetSTDFilterElement(CAN_Type *base,
-                              const mcan_frame_filter_config_t *config,
-                              const mcan_std_filter_element_config_t *filter,
-                              uint8_t idx)
-{
-    uint8_t *elementAddress = 0;
-    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U);
-    memcpy(elementAddress, filter, sizeof(filter));
-}
-
-void MCAN_SetEXTFilterElement(CAN_Type *base,
-                              const mcan_frame_filter_config_t *config,
-                              const mcan_ext_filter_element_config_t *filter,
-                              uint8_t idx)
-{
-    uint8_t *elementAddress = 0;
-    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U);
-    memcpy(elementAddress, filter, sizeof(filter));
-}
-
-static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base)
-{
-    uint32_t eSize;
-    eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT;
-    if (eSize < 5U)
-    {
-        eSize += 4U;
-    }
-    else
-    {
-        eSize = eSize * 4U - 10U;
-    }
-    return (base->RXF0C & CAN_RXF0C_F0SA_MASK) +
-           ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U;
-}
-
-static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base)
-{
-    uint32_t eSize;
-    eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT;
-    if (eSize < 5U)
-    {
-        eSize += 4U;
-    }
-    else
-    {
-        eSize = eSize * 4U - 10U;
-    }
-    return (base->RXF1C & CAN_RXF1C_F1SA_MASK) +
-           ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U;
-}
-
-static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx)
-{
-    assert(idx <= 63U);
-    uint32_t eSize;
-    eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT;
-    if (eSize < 5U)
-    {
-        eSize += 4U;
-    }
-    else
-    {
-        eSize = eSize * 4U - 10U;
-    }
-    return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U;
-}
-
-static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx)
-{
-    assert(idx <= 31U);
-    uint32_t eSize;
-    eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT;
-    if (eSize < 5U)
-    {
-        eSize += 4U;
-    }
-    else
-    {
-        eSize = eSize * 4U - 10U;
-    }
-    return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U;
-}
-
-uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx)
-{
-    return (base->TXBRP & (uint32_t)(1U << idx)) >> (uint32_t)idx;
-}
-
-uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx)
-{
-    return (base->TXBTO & (uint32_t)(1U << idx)) >> (uint32_t)idx;
-}
-
-status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame)
-{
-    if (!MCAN_IsTransmitRequestPending(base, idx))
-    {
-        uint8_t *elementAddress = 0;
-        elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx));
-
-        /* Write 2 words configuration field. */
-        memcpy(elementAddress, (uint8_t *)txFrame, 8U);
-        /* Write data field. */
-        memcpy(elementAddress + 8U, txFrame->data, txFrame->size);
-        return kStatus_Success;
-    }
-    else
-    {
-        return kStatus_Fail;
-    }
-}
-
-status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *rxFrame)
-{
-    mcan_rx_buffer_frame_t *elementAddress = 0;
-    elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx));
-    memcpy(rxFrame, elementAddress, (rxFrame->size + 8U) * 4U);
-    return kStatus_Success;
-}
-
-status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
-{
-    assert((fifoBlock == 0) || (fifoBlock == 1U));
-    mcan_rx_buffer_frame_t *elementAddress = 0;
-    if (0 == fifoBlock)
-    {
-        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base));
-    }
-    else
-    {
-        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base));
-    }
-    memcpy(rxFrame, elementAddress, 8U);
-    rxFrame->data = (uint8_t *)elementAddress + 8U;
-    /* Acknowledge the read. */
-    if (0 == fifoBlock)
-    {
-        base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT;
-    }
-    else
-    {
-        base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT;
-    }
-    return kStatus_Success;
-}
-
-status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame)
-{
-    if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, txFrame))
-    {
-        MCAN_TransmitAddRequest(base, idx);
-
-        /* Wait until message sent out. */
-        while (!MCAN_IsTransmitOccurred(base, idx))
-        {
-        }
-        return kStatus_Success;
-    }
-    else
-    {
-        return kStatus_Fail;
-    }
-}
-
-status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t bufferIdx, mcan_rx_buffer_frame_t *rxFrame)
-{
-    assert(bufferIdx <= 63U);
-
-    while (!MCAN_GetRxBufferStatusFlag(base, bufferIdx))
-    {
-    }
-    MCAN_ClearRxBufferStatusFlag(base, bufferIdx);
-    return MCAN_ReadRxBuffer(base, bufferIdx, rxFrame);
-}
-
-status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
-{
-    assert((fifoBlock == 0) || (fifoBlock == 1U));
-    if (0 == fifoBlock)
-    {
-        while (!MCAN_GetStatusFlag(base, CAN_IR_RF0N_MASK))
-        {
-        }
-        MCAN_ClearStatusFlag(base, CAN_IR_RF0N_MASK);
-    }
-    else
-    {
-        while (!MCAN_GetStatusFlag(base, CAN_IR_RF1N_MASK))
-        {
-        }
-        MCAN_ClearStatusFlag(base, CAN_IR_RF1N_MASK);
-    }
-    return MCAN_ReadRxFifo(base, fifoBlock, rxFrame);
-}
-
-void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData)
-{
-    assert(handle);
-
-    uint8_t instance;
-
-    /* Clean MCAN transfer handle. */
-    memset(handle, 0, sizeof(*handle));
-
-    /* Get instance from peripheral base address. */
-    instance = MCAN_GetInstance(base);
-
-    /* Save the context in global variables to support the double weak mechanism. */
-    s_mcanHandle[instance] = handle;
-
-    /* Register Callback function. */
-    handle->callback = callback;
-    handle->userData = userData;
-
-    s_mcanIsr = MCAN_TransferHandleIRQ;
-
-    /* We Enable Error & Status interrupt here, because this interrupt just
-     * report current status of MCAN module through Callback function.
-     * It is insignificance without a available callback function.
-     */
-    if (handle->callback != NULL)
-    {
-        MCAN_EnableInterrupts(base, 0,
-                              kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
-    }
-    else
-    {
-        MCAN_DisableInterrupts(base,
-                               kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
-    }
-
-    /* Enable interrupts in NVIC. */
-    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0]));
-    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1]));
-}
-
-status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer)
-{
-    /* Assertion. */
-    assert(handle);
-    assert(xfer);
-    assert(xfer->bufferIdx <= 63U);
-
-    /* Check if Tx Buffer is idle. */
-    if (kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx])
-    {
-        handle->txbufferIdx = xfer->bufferIdx;
-        /* Distinguish transmit type. */
-        if (kMCAN_FrameTypeRemote == xfer->frame->xtd)
-        {
-            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxRemote;
-
-            /* Register user Frame buffer to receive remote Frame. */
-            handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame;
-        }
-        else
-        {
-            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxData;
-        }
-
-        if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame))
-        {
-            /* Enable Buffer Interrupt. */
-            MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx);
-            MCAN_EnableInterrupts(base, 0, CAN_IE_TCE_MASK);
-
-            MCAN_TransmitAddRequest(base, xfer->bufferIdx);
-
-            return kStatus_Success;
-        }
-        else
-        {
-            handle->bufferState[xfer->bufferIdx] = kMCAN_StateIdle;
-            return kStatus_Fail;
-        }
-    }
-    else
-    {
-        return kStatus_MCAN_TxBusy;
-    }
-}
-
-status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
-                                             uint8_t fifoBlock,
-                                             mcan_handle_t *handle,
-                                             mcan_fifo_transfer_t *xfer)
-{
-    /* Assertion. */
-    assert((fifoBlock == 0) || (fifoBlock == 1U));
-    assert(handle);
-    assert(xfer);
-
-    /* Check if Message Buffer is idle. */
-    if (kMCAN_StateIdle == handle->rxFifoState)
-    {
-        handle->rxFifoState = kMCAN_StateRxFifo;
-
-        /* Register Message Buffer. */
-        handle->rxFifoFrameBuf = xfer->frame;
-
-        /* Enable FIFO Interrupt. */
-        if (fifoBlock)
-        {
-            MCAN_EnableInterrupts(base, 0, CAN_IE_RF1NE_MASK);
-        }
-        else
-        {
-            MCAN_EnableInterrupts(base, 0, CAN_IE_RF0NE_MASK);
-        }
-        return kStatus_Success;
-    }
-    else
-    {
-        return fifoBlock ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy;
-    }
-}
-
-void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx)
-{
-    /* Assertion. */
-    assert(handle);
-    assert(bufferIdx <= 63U);
-
-    /* Disable Buffer Interrupt. */
-    MCAN_DisableTransmitBufferInterrupts(base, bufferIdx);
-    MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK);
-
-    /* Cancel send request. */
-    MCAN_TransmitCancelRequest(base, bufferIdx);
-
-    /* Un-register handle. */
-    handle->bufferFrameBuf[bufferIdx] = 0x0;
-
-    handle->bufferState[bufferIdx] = kMCAN_StateIdle;
-}
-
-void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle)
-{
-    /* Assertion. */
-    assert(handle);
-    assert((fifoBlock == 0) || (fifoBlock == 1));
-
-    /* Check if Rx FIFO is enabled. */
-    if (fifoBlock)
-    {
-        /* Disable Rx Message FIFO Interrupts. */
-        MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK);
-    }
-    else
-    {
-        MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK);
-    }
-    /* Un-register handle. */
-    handle->rxFifoFrameBuf = 0x0;
-
-    handle->rxFifoState = kMCAN_StateIdle;
-}
-
-void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle)
-{
-    /* Assertion. */
-    assert(handle);
-
-    status_t status = kStatus_MCAN_UnHandled;
-    uint32_t result;
-
-    /* Store Current MCAN Module Error and Status. */
-    result = base->IR;
-
-    do
-    {
-        /* Solve Rx FIFO, Tx interrupt. */
-        if (result & kMCAN_TxTransmitCompleteFlag)
-        {
-            status = kStatus_MCAN_TxIdle;
-            MCAN_TransferAbortSend(base, handle, handle->txbufferIdx);
-        }
-        else if (result & kMCAN_RxFifo0NewFlag)
-        {
-            MCAN_ReadRxFifo(base, 0, handle->rxFifoFrameBuf);
-            status = kStatus_MCAN_RxFifo0Idle;
-            MCAN_TransferAbortReceiveFifo(base, 0, handle);
-        }
-        else if (result & kMCAN_RxFifo0LostFlag)
-        {
-            status = kStatus_MCAN_RxFifo0Lost;
-        }
-        else if (result & kMCAN_RxFifo1NewFlag)
-        {
-            MCAN_ReadRxFifo(base, 1, handle->rxFifoFrameBuf);
-            status = kStatus_MCAN_RxFifo1Idle;
-            MCAN_TransferAbortReceiveFifo(base, 1, handle);
-        }
-        else if (result & kMCAN_RxFifo1LostFlag)
-        {
-            status = kStatus_MCAN_RxFifo0Lost;
-        }
-        else
-        {
-            ;
-        }
-
-        /* Clear resolved Rx FIFO, Tx Buffer IRQ. */
-        MCAN_ClearStatusFlag(base, result);
-
-        /* Calling Callback Function if has one. */
-        if (handle->callback != NULL)
-        {
-            handle->callback(base, handle, status, result, handle->userData);
-        }
-
-        /* Reset return status */
-        status = kStatus_MCAN_UnHandled;
-
-        /* Store Current MCAN Module Error and Status. */
-        result = base->IR;
-    } while ((0 != MCAN_GetStatusFlag(base, 0xFFFFFFFFU)) ||
-             (0 != (result & (kMCAN_ErrorWarningIntFlag | kMCAN_BusOffIntFlag | kMCAN_ErrorPassiveIntFlag))));
-}
-
-#if defined(CAN0)
-void CAN0_IRQ0_DriverIRQHandler(void)
-{
-    assert(s_mcanHandle[0]);
-
-    s_mcanIsr(CAN0, s_mcanHandle[0]);
-}
-
-void CAN0_IRQ1_DriverIRQHandler(void)
-{
-    assert(s_mcanHandle[0]);
-
-    s_mcanIsr(CAN0, s_mcanHandle[0]);
-}
-#endif
-
-#if defined(CAN1)
-void CAN1_IRQ0_DriverIRQHandler(void)
-{
-    assert(s_mcanHandle[1]);
-
-    s_mcanIsr(CAN1, s_mcanHandle[1]);
-}
-
-void CAN1_IRQ1_DriverIRQHandler(void)
-{
-    assert(s_mcanHandle[1]);
-
-    s_mcanIsr(CAN1, s_mcanHandle[1]);
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,966 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_MCAN_H_
-#define _FSL_MCAN_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup mcan
- * @{
- */
-
-/******************************************************************************
- * Definitions
- *****************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief MCAN driver version 2.0.0. */
-#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief MCAN transfer status. */
-enum _mcan_status
-{
-    kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0),            /*!< Tx Buffer is Busy. */
-    kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1),            /*!< Tx Buffer is Idle. */
-    kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2),            /*!< Rx Buffer is Busy. */
-    kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3),            /*!< Rx Buffer is Idle. */
-    kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4),        /*!< New message written to Rx FIFO 0. */
-    kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5),       /*!< Rx FIFO 0 is Idle. */
-    kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6),  /*!< Rx FIFO 0 fill level reached watermark. */
-    kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7),       /*!< Rx FIFO 0 full. */
-    kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8),       /*!< Rx FIFO 0 message lost. */
-    kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9),        /*!< New message written to Rx FIFO 1. */
-    kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10),      /*!< Rx FIFO 1 is Idle. */
-    kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */
-    kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12),      /*!< Rx FIFO 1 full. */
-    kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13),      /*!< Rx FIFO 1 message lost. */
-    kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14),      /*!< Rx FIFO 0 is busy. */
-    kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15),      /*!< Rx FIFO 1 is busy. */
-    kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16),      /*!< MCAN Module Error and Status. */
-    kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17),        /*!< UnHadled Interrupt asserted. */
-};
-
-/*!
- * @brief MCAN status flags.
- *
- * This provides constants for the MCAN status flags for use in the MCAN functions.
- * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to
- * read MCAN_ErrorFlag and distinguish which error is occur using
- * @ref _mcan_error_flags enumerations.
- */
-enum _mcan_flags
-{
-    kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK,    /*!< CAN Synchronization Status. */
-    kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */
-    kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */
-    kMCAN_BusOffIntFlag = CAN_IR_BO_MASK,        /*!< Tx Error Warning Status. */
-    kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK,  /*!< Rx Error Warning Status. */
-    kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK,  /*!< Rx Error Warning Status. */
-};
-
-/*!
- * @brief MCAN Rx FIFO status flags.
- *
- * The MCAN Rx FIFO Status enumerations are used to determine the status of the
- * Rx FIFO.
- */
-enum _mcan_rx_fifo_flags
-{
-    kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK,       /*!< Rx FIFO 0 new message flag. */
-    kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
-    kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK,      /*!< Rx FIFO 0 full flag. */
-    kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK,      /*!< Rx FIFO 0 message lost flag. */
-    kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK,       /*!< Rx FIFO 0 new message flag. */
-    kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
-    kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK,      /*!< Rx FIFO 0 full flag. */
-    kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK,      /*!< Rx FIFO 0 message lost flag. */
-};
-
-/*!
- * @brief MCAN Tx status flags.
- *
- * The MCAN Tx Status enumerations are used to determine the status of the
- * Tx Buffer/Event FIFO.
- */
-enum _mcan_tx_flags
-{
-    kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK,      /*!< Transmission completed flag. */
-    kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */
-    kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK,       /*!< Tx Event FIFO element lost. */
-    kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK,       /*!< Tx Event FIFO full. */
-    kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK,  /*!< Tx Event FIFO fill level reached watermark. */
-    kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK,        /*!< Tx Handler wrote Tx Event FIFO element flag. */
-    kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK,       /*!< Tx FIFO empty flag. */
-};
-
-/*!
- * @brief MCAN interrupt configuration structure, default settings all disabled.
- *
- * This structure contains the settings for all of the MCAN Module interrupt configurations.
- */
-enum _mcan_interrupt_enable
-{
-    kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK,  /*!< Bus Off interrupt. */
-    kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK,   /*!< Error interrupt. */
-    kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */
-};
-
-/*! @brief MCAN frame format. */
-typedef enum _mcan_frame_idformat
-{
-    kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */
-    kMCAN_FrameIDExtend = 0x1U,   /*!< Extend frame format attribute. */
-} mcan_frame_idformat_t;
-
-/*! @brief MCAN frame type. */
-typedef enum _mcan_frame_type
-{
-    kMCAN_FrameTypeData = 0x0U,   /*!< Data frame type attribute. */
-    kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
-} mcan_frame_type_t;
-
-/*! @brief MCAN frame datafield size. */
-typedef enum _mcan_bytes_in_datafield
-{
-    kMCAN_8ByteDatafield = 0x0U,  /*!< 8 byte data field. */
-    kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */
-    kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */
-    kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */
-    kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */
-    kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */
-    kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */
-    kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */
-} mcan_bytes_in_datafield_t;
-
-#if defined(__CC_ARM)
-#pragma anon_unions
-#endif
-/*! @brief MCAN Tx Buffer structure. */
-typedef struct _mcan_tx_buffer_frame
-{
-    struct
-    {
-        uint32_t id : 29; /*!< CAN Frame Identifier. */
-        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
-        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
-        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
-    };
-    struct
-    {
-        uint32_t : 16;
-        uint32_t dlc : 4; /*!< Data Length Code. */
-        uint32_t brs : 1; /*!< Bit Rate Switch. */
-        uint32_t fdf : 1; /*!< CAN FD format. */
-        uint32_t : 1;     /*!< Reserved. */
-        uint32_t efc : 1; /*!< Event FIFO control. */
-        uint32_t mm : 8;  /*!< Message Marker. */
-    };
-    uint8_t *data;
-    uint8_t size;
-} mcan_tx_buffer_frame_t;
-
-/*! @brief MCAN Rx FIFO/Buffer structure. */
-typedef struct _mcan_rx_buffer_frame
-{
-    struct
-    {
-        uint32_t id : 29; /*!< CAN Frame Identifier. */
-        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
-        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
-        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
-    };
-    struct
-    {
-        uint32_t rxts : 16; /*!< Rx Timestamp. */
-        uint32_t dlc : 4;   /*!< Data Length Code. */
-        uint32_t brs : 1;   /*!< Bit Rate Switch. */
-        uint32_t fdf : 1;   /*!< CAN FD format. */
-        uint32_t : 2;       /*!< Reserved. */
-        uint32_t fidx : 7;  /*!< Filter Index. */
-        uint32_t anmf : 1;  /*!< Accepted Non-matching Frame. */
-    };
-    uint8_t *data;
-    uint8_t size;
-} mcan_rx_buffer_frame_t;
-
-/*! @brief MCAN Rx FIFO block number. */
-typedef enum _mcan_fifo_type
-{
-    kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */
-    kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */
-} mcan_fifo_type_t;
-
-/*! @brief MCAN FIFO Operation Mode. */
-typedef enum _mcan_fifo_opmode_config
-{
-    kMCAN_FifoBlocking = 0,  /*!< FIFO blocking mode. */
-    kMCAN_FifoOverwrite = 1, /*!< FIFO overwrite mode. */
-} mcan_fifo_opmode_config_t;
-
-/*! @brief MCAN Tx FIFO/Queue Mode. */
-typedef enum _mcan_txmode_config
-{
-    kMCAN_txFifo = 0,  /*!< Tx FIFO operation. */
-    kMCAN_txQueue = 1, /*!< Tx Queue operation. */
-} mcan_txmode_config_t;
-
-/*! @brief MCAN remote frames treatment. */
-typedef enum _mcan_remote_frame_config
-{
-    kMCAN_filterFrame = 0, /*!< Filter remote frames. */
-    kMCAN_rejectFrame = 1, /*!< Reject all remote frames. */
-} mcan_remote_frame_config_t;
-
-/*! @brief MCAN non-masking frames treatment. */
-typedef enum _mcan_nonmasking_frame_config
-{
-    kMCAN_acceptinFifo0 = 0, /*!< Accept non-masking frames in Rx FIFO 0. */
-    kMCAN_acceptinFifo1 = 1, /*!< Accept non-masking frames in Rx FIFO 1. */
-    kMCAN_reject0 = 2,       /*!< Reject non-masking frames. */
-    kMCAN_reject1 = 3,       /*!< Reject non-masking frames. */
-} mcan_nonmasking_frame_config_t;
-
-/*! @brief MCAN Filter Element Configuration. */
-typedef enum _mcan_fec_config
-{
-    kMCAN_disable = 0,       /*!< Disable filter element. */
-    kMCAN_storeinFifo0 = 1,  /*!< Store in Rx FIFO 0 if filter matches. */
-    kMCAN_storeinFifo1 = 2,  /*!< Store in Rx FIFO 1 if filter matches. */
-    kMCAN_reject = 3,        /*!< Reject ID if filter matches. */
-    kMCAN_setprio = 4,       /*!< Set priority if filter matches. */
-    kMCAN_setpriofifo0 = 5,  /*!< Set priority and store in FIFO 0 if filter matches. */
-    kMCAN_setpriofifo1 = 6,  /*!< Set priority and store in FIFO 1 if filter matches. */
-    kMCAN_storeinbuffer = 7, /*!< Store into Rx Buffer or as debug message. */
-} mcan_fec_config_t;
-
-/*! @brief MCAN Rx FIFO configuration. */
-typedef struct _mcan_rx_fifo_config
-{
-    uint32_t address;                        /*!< FIFOn start address. */
-    uint32_t elementSize;                    /*!< FIFOn element number. */
-    uint32_t watermark;                      /*!< FIFOn watermark level. */
-    mcan_fifo_opmode_config_t opmode;        /*!< FIFOn blocking/overwrite mode. */
-    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
-} mcan_rx_fifo_config_t;
-
-/*! @brief MCAN Rx Buffer configuration. */
-typedef struct _mcan_rx_buffer_config
-{
-    uint32_t address;                        /*!< Rx Buffer start address. */
-    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
-} mcan_rx_buffer_config_t;
-
-/*! @brief MCAN Tx Event FIFO configuration. */
-typedef struct _mcan_tx_fifo_config
-{
-    uint32_t address;     /*!< Event fifo start address. */
-    uint32_t elementSize; /*!< FIFOn element number. */
-    uint32_t watermark;   /*!< FIFOn watermark level. */
-} mcan_tx_fifo_config_t;
-
-/*! @brief MCAN Tx Buffer configuration. */
-typedef struct _mcan_tx_buffer_config
-{
-    uint32_t address;                        /*!< Tx Buffers Start Address. */
-    uint32_t dedicatedSize;                  /*!< Number of Dedicated Transmit Buffers. */
-    uint32_t fqSize;                         /*!< Transmit FIFO/Queue Size. */
-    mcan_txmode_config_t mode;               /*!< Tx FIFO/Queue Mode.*/
-    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
-} mcan_tx_buffer_config_t;
-
-/*! @brief MCAN Filter Type. */
-typedef enum _mcan_std_filter_type
-{
-    kMCAN_range = 0,           /*!< Range filter from SFID1 to SFID2. */
-    kMCAN_dual = 1,            /*!< Dual ID filter for SFID1 or SFID2. */
-    kMCAN_classic = 2,         /*!< Classic filter: SFID1 = filter, SFID2 = mask. */
-    kMCAN_disableORrange2 = 3, /*!< Filter element disabled for standard filter
-                                    or Range filter, XIDAM mask not applied for extended filter. */
-} mcan_filter_type_t;
-
-/*! @brief MCAN Standard Message ID Filter Element. */
-typedef struct _mcan_std_filter_element_config
-{
-    uint32_t sfid2 : 11;        /*!< Standard Filter ID 2. */
-    uint32_t : 5;               /*!< Reserved. */
-    uint32_t sfid1 : 11;        /*!< Standard Filter ID 1. */
-    mcan_fec_config_t sfec : 3; /*!< Standard Filter Element Configuration. */
-    mcan_filter_type_t sft : 2; /*!<  Standard Filter Type/ */
-} mcan_std_filter_element_config_t;
-
-/*! @brief MCAN Extended Message ID Filter Element. */
-typedef struct _mcan_ext_filter_element_config
-{
-    uint32_t efid1 : 29;        /*!< Extended Filter ID 1. */
-    mcan_fec_config_t efec : 3; /*!< Extended Filter Element Configuration. */
-    uint32_t efid2 : 29;        /*!< Extended Filter ID 2. */
-    uint32_t : 1;               /*!< Reserved. */
-    mcan_filter_type_t eft : 2; /*!< Extended Filter Type. */
-} mcan_ext_filter_element_config_t;
-
-/*! @brief MCAN Rx filter configuration. */
-typedef struct _mcan_frame_filter_config
-{
-    uint32_t address;                       /*!< Filter start address. */
-    uint32_t listSize;                      /*!< Filter list size. */
-    mcan_frame_idformat_t idFormat;         /*!< Frame format. */
-    mcan_remote_frame_config_t remFrame;    /*!< Remote frame treatment. */
-    mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */
-} mcan_frame_filter_config_t;
-
-/*! @brief MCAN module configuration structure. */
-typedef struct _mcan_config
-{
-    uint32_t baudRateA;     /*!< Baud rate of Arbitration phase in bps. */
-    uint32_t baudRateD;     /*!< Baud rate of Data phase in bps. */
-    bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */
-    bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */
-    bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */
-    bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */
-    bool enableBusMon;      /*!< Enable or Disable Bus Monitoring Mode. */
-} mcan_config_t;
-
-/*! @brief MCAN protocol timing characteristic configuration structure. */
-typedef struct _mcan_timing_config
-{
-    uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
-    uint8_t rJumpwidth;  /*!< Re-sync Jump Width. */
-    uint8_t seg1;        /*!< Data Time Segment 1. */
-    uint8_t seg2;        /*!< Data Time Segment 2. */
-} mcan_timing_config_t;
-
-/*! @brief MCAN Buffer transfer. */
-typedef struct _mcan_buffer_transfer
-{
-    mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
-    uint8_t bufferIdx;             /*!< The index of Message buffer used to transfer Message. */
-} mcan_buffer_transfer_t;
-
-/*! @brief MCAN Rx FIFO transfer. */
-typedef struct _mcan_fifo_transfer
-{
-    mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */
-} mcan_fifo_transfer_t;
-
-/*! @brief MCAN handle structure definition. */
-typedef struct _mcan_handle mcan_handle_t;
-
-/*! @brief MCAN transfer callback function.
- *
- *  The MCAN transfer callback returns a value from the underlying layer.
- *  If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of
- *  MCAN status register which can be used to get the working status(or error status) of MCAN module.
- *  If the status equals to other MCAN Message Buffer transfer status, the result is the index of
- *  Message Buffer that generate transfer event.
- *  If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be
- *  Ignored.
- */
-typedef void (*mcan_transfer_callback_t)(
-    CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData);
-
-/*! @brief MCAN handle structure. */
-struct _mcan_handle
-{
-    mcan_transfer_callback_t callback;                   /*!< Callback function. */
-    void *userData;                                      /*!< MCAN callback function parameter.*/
-    mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */
-    mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf;     /*!< The buffer for received data from Rx FIFO. */
-    volatile uint8_t txbufferIdx;                        /*!< Message Buffer transfer state. */
-    volatile uint8_t bufferState[64];                    /*!< Message Buffer transfer state. */
-    volatile uint8_t rxFifoState;                        /*!< Rx FIFO transfer state. */
-};
-
-/******************************************************************************
- * API
- *****************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes an MCAN instance.
- *
- * This function initializes the MCAN module with user-defined settings.
- * This example shows how to set up the mcan_config_t parameters and how
- * to call the MCAN_Init function by passing in these parameters.
- *  @code
- *   mcan_config_t config;
- *   config->baudRateA = 500000U;
- *   config->baudRateD = 500000U;
- *   config->enableCanfdNormal = false;
- *   config->enableCanfdSwitch = false;
- *   config->enableLoopBackInt = false;
- *   config->enableLoopBackExt = false;
- *   config->enableBusMon = false;
- *   MCAN_Init(CANFD0, &config, 8000000UL);
- *   @endcode
- *
- * @param base MCAN peripheral base address.
- * @param config Pointer to the user-defined configuration structure.
- * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz.
- */
-void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz);
-
-/*!
- * @brief Deinitializes an MCAN instance.
- *
- * This function deinitializes the MCAN module.
- *
- * @param base MCAN peripheral base address.
- */
-void MCAN_Deinit(CAN_Type *base);
-
-/*!
- * @brief Gets the default configuration structure.
- *
- * This function initializes the MCAN configuration structure to default values. The default
- * values are as follows.
- *   config->baudRateA = 500000U;
- *   config->baudRateD = 500000U;
- *   config->enableCanfdNormal = false;
- *   config->enableCanfdSwitch = false;
- *   config->enableLoopBackInt = false;
- *   config->enableLoopBackExt = false;
- *   config->enableBusMon = false;
- *
- * @param config Pointer to the MCAN configuration structure.
- */
-void MCAN_GetDefaultConfig(mcan_config_t *config);
-
-/*!
- * @brief MCAN enters normal mode.
- *
- * After initialization, INIT bit in CCCR register must be cleared to enter
- * normal mode thus synchronizes to the CAN bus and ready for communication.
- *
- * @param base MCAN peripheral base address.
- */
-void MCAN_EnterNormalMode(CAN_Type *base);
-
-/*!
- * @name Configuration.
- * @{
- */
-
-/*!
- * @brief Sets the MCAN Message RAM base address.
- *
- * This function sets the Message RAM base address.
- *
- * @param base MCAN peripheral base address.
- * @param value Desired Message RAM base.
- */
-static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value)
-{
-    assert((value >= 0x20000000U) && (value <= 0x20027FFFU));
-
-    base->MRBA = CAN_MRBA_BA(value);
-}
-
-/*!
- * @brief Gets the MCAN Message RAM base address.
- *
- * This function gets the Message RAM base address.
- *
- * @param base MCAN peripheral base address.
- * @return Message RAM base address.
- */
-static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base)
-{
-    return base->MRBA;
-}
-
-/*!
- * @brief Sets the MCAN protocol arbitration phase timing characteristic.
- *
- * This function gives user settings to CAN bus timing characteristic.
- * The function is for an experienced user. For less experienced users, call
- * the MCAN_Init() and fill the baud rate field with a desired value.
- * This provides the default arbitration phase timing characteristics.
- *
- * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
- * set in MCAN_Init().
- *
- * @param base MCAN peripheral base address.
- * @param config Pointer to the timing configuration structure.
- */
-void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
-
-#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
-/*!
- * @brief Sets the MCAN protocol data phase timing characteristic.
- *
- * This function gives user settings to CAN bus timing characteristic.
- * The function is for an experienced user. For less experienced users, call
- * the MCAN_Init() and fill the baud rate field with a desired value.
- * This provides the default data phase timing characteristics.
- *
- * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
- * set in MCAN_Init().
- *
- * @param base MCAN peripheral base address.
- * @param config Pointer to the timing configuration structure.
- */
-void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
-#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
-
-/*!
- * @brief Configures an MCAN receive fifo 0 buffer.
- *
- * This function sets start address, element size, watermark, operation mode
- * and datafield size of the recieve fifo 0.
- *
- * @param base MCAN peripheral base address.
- * @param config The receive fifo 0 configuration structure.
- */
-void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
-
-/*!
- * @brief Configures an MCAN receive fifo 1 buffer.
- *
- * This function sets start address, element size, watermark, operation mode
- * and datafield size of the recieve fifo 1.
- *
- * @param base MCAN peripheral base address.
- * @param config The receive fifo 1 configuration structure.
- */
-void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
-
-/*!
- * @brief Configures an MCAN receive buffer.
- *
- * This function sets start address and datafield size of the recieve buffer.
- *
- * @param base MCAN peripheral base address.
- * @param config The receive buffer configuration structure.
- */
-void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config);
-
-/*!
- * @brief Configures an MCAN transmit event fifo.
- *
- * This function sets start address, element size, watermark of the transmit event fifo.
- *
- * @param base MCAN peripheral base address.
- * @param config The transmit event fifo configuration structure.
- */
-void MCAN_SetTxEventfifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config);
-
-/*!
- * @brief Configures an MCAN transmit buffer.
- *
- * This function sets start address, element size, fifo/queue mode and datafield
- * size of the transmit buffer.
- *
- * @param base MCAN peripheral base address.
- * @param config The transmit buffer configuration structure.
- */
-void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config);
-
-/*!
- * @brief Set filter configuration.
- *
- * This function sets remote and non masking frames in global filter configuration,
- * also the start address, list size in standard/extended ID filter configuration.
- *
- * @param base MCAN peripheral base address.
- * @param config The MCAN filter configuration.
- */
-void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config);
-
-/*!
- * @brief Set filter configuration.
- *
- * This function sets remote and non masking frames in global filter configuration,
- * also the start address, list size in standard/extended ID filter configuration.
- *
- * @param base MCAN peripheral base address.
- * @param config The MCAN filter configuration.
- */
-void MCAN_SetSTDFilterElement(CAN_Type *base,
-                              const mcan_frame_filter_config_t *config,
-                              const mcan_std_filter_element_config_t *filter,
-                              uint8_t idx);
-
-/*!
- * @brief Set filter configuration.
- *
- * This function sets remote and non masking frames in global filter configuration,
- * also the start address, list size in standard/extended ID filter configuration.
- *
- * @param base MCAN peripheral base address.
- * @param config The MCAN filter configuration.
- */
-void MCAN_SetEXTFilterElement(CAN_Type *base,
-                              const mcan_frame_filter_config_t *config,
-                              const mcan_ext_filter_element_config_t *filter,
-                              uint8_t idx);
-
-/*!
- * @name Status
- * @{
- */
-
-/*!
- * @brief Gets the MCAN module interrupt flags.
- *
- * This function gets all MCAN interrupt status flags.
- *
- * @param base MCAN peripheral base address.
- * @param mask The ORed MCAN interrupt mask.
- * @return MCAN status flags which are ORed.
- */
-static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask)
-{
-    return (bool)(base->IR & mask);
-}
-
-/*!
- * @brief Clears the MCAN module interrupt flags.
- *
- * This function clears MCAN interrupt status flags.
- *
- * @param base MCAN peripheral base address.
- * @param mask The ORed MCAN interrupt mask.
- */
-static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask)
-{
-    /* Write 1 to clear status flag. */
-    base->IR |= mask;
-}
-
-/*!
- * @brief Gets the new data flag of specific Rx Buffer.
- *
- * This function gets new data flag of specific Rx Buffer.
- *
- * @param base MCAN peripheral base address.
- * @param idx Rx Buffer index.
- * @return Rx Buffer new data status flag.
- */
-static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
-{
-    assert(idx <= 63U);
-
-    if (idx <= 31U)
-    {
-        return (bool)(base->NDAT1 & (1U << idx));
-    }
-    else
-    {
-        return (bool)(base->NDAT2 & (1U << (idx - 31U)));
-    }
-}
-
-/*!
- * @brief Clears the new data flag of specific Rx Buffer.
- *
- * This function clears new data flag of specific Rx Buffer.
- *
- * @param base MCAN peripheral base address.
- * @param idx Rx Buffer index.
- */
-static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
-{
-    assert(idx <= 63U);
-
-    if (idx <= 31U)
-    {
-        base->NDAT1 &= ~(1U << idx);
-    }
-    else
-    {
-        base->NDAT2 &= ~(1U << (idx - 31U));
-    }
-}
-
-/* @} */
-
-/*!
- * @name Interrupts
- * @{
- */
-
-/*!
- * @brief Enables MCAN interrupts according to the provided interrupt line and mask.
- *
- * This function enables the MCAN interrupts according to the provided interrupt line and mask.
- * The mask is a logical OR of enumeration members.
- *
- * @param base MCAN peripheral base address.
- * @param line Interrupt line number, 0 or 1.
- * @param mask The interrupts to enable.
- */
-static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask)
-{
-    base->ILE |= (1U << line);
-    if (0 == line)
-    {
-        base->ILS &= ~mask;
-    }
-    else
-    {
-        base->ILS |= mask;
-    }
-    base->IE |= mask;
-}
-
-/*!
- * @brief Enables MCAN Tx Buffer interrupts according to the provided index.
- *
- * This function enables the MCAN Tx Buffer interrupts.
- *
- * @param base MCAN peripheral base address.
- * @param idx Tx Buffer index.
- */
-static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
-{
-    base->TXBTIE |= (uint32_t)(1U << idx);
-}
-
-/*!
- * @brief Disables MCAN Tx Buffer interrupts according to the provided index.
- *
- * This function disables the MCAN Tx Buffer interrupts.
- *
- * @param base MCAN peripheral base address.
- * @param idx Tx Buffer index.
- */
-static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
-{
-    base->TXBTIE &= (uint32_t)(~(1U << idx));
-}
-
-/*!
- * @brief Disables MCAN interrupts according to the provided mask.
- *
- * This function disables the MCAN interrupts according to the provided mask.
- * The mask is a logical OR of enumeration members.
- *
- * @param base MCAN peripheral base address.
- * @param mask The interrupts to disable.
- */
-static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
-{
-    base->IE &= ~mask;
-}
-
-/* @} */
-
-/*!
- * @name Bus Operations
- * @{
- */
-
-/*!
- * @brief Writes an MCAN Message to the Transmit Buffer.
- *
- * This function writes a CAN Message to the specified Transmit Message Buffer
- * and changes the Message Buffer state to start CAN Message transmit. After
- * that the function returns immediately.
- *
- * @param base MCAN peripheral base address.
- * @param idx The MCAN Tx Buffer index.
- * @param txFrame Pointer to CAN message frame to be sent.
- */
-status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame);
-
-/*!
- * @brief Reads an MCAN Message from Rx FIFO.
- *
- * This function reads a CAN message from the Rx FIFO in the Message RAM.
- *
- * @param base MCAN peripheral base address.
- * @param fifoBlock Rx FIFO block 0 or 1.
- * @param rxFrame Pointer to CAN message frame structure for reception.
- * @retval kStatus_Success - Read Message from Rx FIFO successfully.
- */
-status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
-
-/* @} */
-
-/*!
- * @name Transactional
- * @{
- */
-
-/*!
- * @brief Tx Buffer add request to send message out.
- *
- * This function add sending request to corresponding Tx Buffer.
- *
- * @param base MCAN peripheral base address.
- * @param idx Tx Buffer index.
- */
-static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx)
-{
-    base->TXBAR |= (uint32_t)(1U << idx);
-}
-
-/*!
- * @brief Tx Buffer cancel sending request.
- *
- * This function clears Tx buffer request pending bit.
- *
- * @param base MCAN peripheral base address.
- * @param idx Tx Buffer index.
- */
-static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx)
-{
-    base->TXBCR |= (uint32_t)(1U << idx);
-}
-
-/*!
- * @brief Performs a polling send transaction on the CAN bus.
- *
- * Note that a transfer handle does not need to be created  before calling this API.
- *
- * @param base MCAN peripheral base pointer.
- * @param idx The MCAN buffer index.
- * @param txFrame Pointer to CAN message frame to be sent.
- * @retval kStatus_Success - Write Tx Message Buffer Successfully.
- * @retval kStatus_Fail    - Tx Message Buffer is currently in use.
- */
-status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame);
-
-/*!
- * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
- *
- * Note that a transfer handle does not need to be created before calling this API.
- *
- * @param base MCAN peripheral base pointer.
- * @param fifoBlock Rx FIFO block, 0 or 1.
- * @param rxFrame Pointer to CAN message frame structure for reception.
- * @retval kStatus_Success - Read Message from Rx FIFO successfully.
- * @retval kStatus_Fail    - No new message in Rx FIFO.
- */
-status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
-
-/*!
- * @brief Initializes the MCAN handle.
- *
- * This function initializes the MCAN handle, which can be used for other MCAN
- * transactional APIs. Usually, for a specified MCAN instance,
- * call this API once to get the initialized handle.
- *
- * @param base MCAN peripheral base address.
- * @param handle MCAN handle pointer.
- * @param callback The callback function.
- * @param userData The parameter of the callback function.
- */
-void MCAN_TransferCreateHandle(CAN_Type *base,
-                               mcan_handle_t *handle,
-                               mcan_transfer_callback_t callback,
-                               void *userData);
-
-/*!
- * @brief Sends a message using IRQ.
- *
- * This function sends a message using IRQ. This is a non-blocking function, which returns
- * right away. When messages have been sent out, the send callback function is called.
- *
- * @param base MCAN peripheral base address.
- * @param handle MCAN handle pointer.
- * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t.
- * @retval kStatus_Success        Start Tx Buffer sending process successfully.
- * @retval kStatus_Fail           Write Tx Buffer failed.
- * @retval kStatus_MCAN_TxBusy Tx Buffer is in use.
- */
-status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer);
-
-/*!
- * @brief Receives a message from Rx FIFO using IRQ.
- *
- * This function receives a message using IRQ. This is a non-blocking function, which returns
- * right away. When all messages have been received, the receive callback function is called.
- *
- * @param base MCAN peripheral base address.
- * @param handle MCAN handle pointer.
- * @param fifoBlock Rx FIFO block, 0 or 1.
- * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t.
- * @retval kStatus_Success            - Start Rx FIFO receiving process successfully.
- * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use.
- * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use.
- */
-status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
-                                             uint8_t fifoBlock,
-                                             mcan_handle_t *handle,
-                                             mcan_fifo_transfer_t *xfer);
-
-/*!
- * @brief Aborts the interrupt driven message send process.
- *
- * This function aborts the interrupt driven message send process.
- *
- * @param base MCAN peripheral base address.
- * @param handle MCAN handle pointer.
- * @param bufferIdx The MCAN Buffer index.
- */
-void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx);
-
-/*!
- * @brief Aborts the interrupt driven message receive from Rx FIFO process.
- *
- * This function aborts the interrupt driven message receive from Rx FIFO process.
- *
- * @param base MCAN peripheral base address.
- * @param fifoBlock MCAN Fifo block, 0 or 1.
- * @param handle MCAN handle pointer.
- */
-void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle);
-
-/*!
- * @brief MCAN IRQ handle function.
- *
- * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request.
- *
- * @param base MCAN peripheral base address.
- * @param handle MCAN handle pointer.
- */
-void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_MCAN_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_mrt.h"
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Gets the instance from the base address
- *
- * @param base Multi-Rate timer peripheral base address
- *
- * @return The MRT instance
- */
-static uint32_t MRT_GetInstance(MRT_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to MRT bases for each instance. */
-static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to MRT clocks for each instance. */
-static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to MRT resets for each instance. */
-static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t MRT_GetInstance(MRT_Type *base)
-{
-    uint32_t instance;
-    uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < mrtArrayCount; instance++)
-    {
-        if (s_mrtBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < mrtArrayCount);
-
-    return instance;
-}
-
-void MRT_Init(MRT_Type *base, const mrt_config_t *config)
-{
-    assert(config);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate the MRT clock */
-    CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the module */
-    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
-
-    /* Set timer operating mode */
-    base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
-}
-
-void MRT_Deinit(MRT_Type *base)
-{
-    /* Stop all the timers */
-    MRT_StopTimer(base, kMRT_Channel_0);
-    MRT_StopTimer(base, kMRT_Channel_1);
-    MRT_StopTimer(base, kMRT_Channel_2);
-    MRT_StopTimer(base, kMRT_Channel_3);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Gate the MRT clock*/
-    CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
-{
-    uint32_t newValue = count;
-    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
-    {
-        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
-        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
-    }
-
-    /* Update the timer interval value */
-    base->CHANNEL[channel].INTVAL = newValue;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,371 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_MRT_H_
-#define _FSL_MRT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup mrt
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/*! @brief List of MRT channels */
-typedef enum _mrt_chnl
-{
-    kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
-    kMRT_Channel_1,      /*!< MRT channel number 1 */
-    kMRT_Channel_2,      /*!< MRT channel number 2 */
-    kMRT_Channel_3       /*!< MRT channel number 3 */
-} mrt_chnl_t;
-
-/*! @brief List of MRT timer modes */
-typedef enum _mrt_timer_mode
-{
-    kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT),      /*!< Repeat Interrupt mode */
-    kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT),     /*!< One-shot Interrupt mode */
-    kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
-} mrt_timer_mode_t;
-
-/*! @brief List of MRT interrupts */
-typedef enum _mrt_interrupt_enable
-{
-    kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
-} mrt_interrupt_enable_t;
-
-/*! @brief List of MRT status flags */
-typedef enum _mrt_status_flags
-{
-    kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
-    kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK,           /*!< Indicates state of the timer */
-} mrt_status_flags_t;
-
-/*!
- * @brief MRT configuration structure
- *
- * This structure holds the configuration settings for the MRT peripheral. To initialize this
- * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
- * pointer to your config structure instance.
- *
- * The config struct can be made const so it resides in flash
- */
-typedef struct _mrt_config
-{
-    bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
-} mrt_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Ungates the MRT clock and configures the peripheral for basic operation.
- *
- * @note This API should be called at the beginning of the application using the MRT driver.
- *
- * @param base   Multi-Rate timer peripheral base address
- * @param config Pointer to user's MRT config structure
- */
-void MRT_Init(MRT_Type *base, const mrt_config_t *config);
-
-/*!
- * @brief Gate the MRT clock
- *
- * @param base Multi-Rate timer peripheral base address
- */
-void MRT_Deinit(MRT_Type *base);
-
-/*!
- * @brief Fill in the MRT config struct with the default settings
- *
- * The default values are:
- * @code
- *     config->enableMultiTask = false;
- * @endcode
- * @param config Pointer to user's MRT config structure.
- */
-static inline void MRT_GetDefaultConfig(mrt_config_t *config)
-{
-    assert(config);
-
-    /* Use hardware status operating mode */
-    config->enableMultiTask = false;
-}
-
-/*!
- * @brief Sets up an MRT channel mode.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Channel that is being configured.
- * @param mode    Timer mode to use for the channel.
- */
-static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
-{
-    uint32_t reg = base->CHANNEL[channel].CTRL;
-
-    /* Clear old value */
-    reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
-    /* Add the new mode */
-    reg |= mode;
-
-    base->CHANNEL[channel].CTRL = reg;
-}
-
-/*! @}*/
-
-/*!
- * @name Interrupt Interface
- * @{
- */
-
-/*!
- * @brief Enables the MRT interrupt.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- * @param mask    The interrupts to enable. This is a logical OR of members of the
- *                enumeration ::mrt_interrupt_enable_t
- */
-static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
-{
-    base->CHANNEL[channel].CTRL |= mask;
-}
-
-/*!
- * @brief Disables the selected MRT interrupt.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- * @param mask    The interrupts to disable. This is a logical OR of members of the
- *                enumeration ::mrt_interrupt_enable_t
- */
-static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
-{
-    base->CHANNEL[channel].CTRL &= ~mask;
-}
-
-/*!
- * @brief Gets the enabled MRT interrupts.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- *
- * @return The enabled interrupts. This is the logical OR of members of the
- *         enumeration ::mrt_interrupt_enable_t
- */
-static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
-{
-    return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
-}
-
-/*! @}*/
-
-/*!
- * @name Status Interface
- * @{
- */
-
-/*!
- * @brief Gets the MRT status flags
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- *
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::mrt_status_flags_t
- */
-static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
-{
-    return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
-}
-
-/*!
- * @brief Clears the MRT status flags.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- * @param mask    The status flags to clear. This is a logical OR of members of the
- *                enumeration ::mrt_status_flags_t
- */
-static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
-{
-    base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
-}
-
-/*! @}*/
-
-/*!
- * @name Read and Write the timer period
- * @{
- */
-
-/*!
- * @brief Used to update the timer period in units of count.
- *
- * The new value will be immediately loaded or will be loaded at the end of the current time
- * interval. For one-shot interrupt mode the new value will be immediately loaded.
- *
- * @note User can call the utility macros provided in fsl_common.h to convert to ticks
- *
- * @param base          Multi-Rate timer peripheral base address
- * @param channel       Timer channel number
- * @param count         Timer period in units of ticks
- * @param immediateLoad true: Load the new value immediately into the TIMER register;
- *                      false: Load the new value at the end of current timer interval
- */
-void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
-
-/*!
- * @brief Reads the current timer counting value.
- *
- * This function returns the real-time timer counting value, in a range from 0 to a
- * timer period.
- *
- * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number
- *
- * @return Current timer counting value in ticks
- */
-static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
-{
-    return base->CHANNEL[channel].TIMER;
-}
-
-/*! @}*/
-
-/*!
- * @name Timer Start and Stop
- * @{
- */
-
-/*!
- * @brief Starts the timer counting.
- *
- * After calling this function, timers load period value, counts down to 0 and
- * depending on the timer mode it will either load the respective start value again or stop.
- *
- * @note User can call the utility macros provided in fsl_common.h to convert to ticks
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number.
- * @param count   Timer period in units of ticks
- */
-static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
-{
-    /* Write the timer interval value */
-    base->CHANNEL[channel].INTVAL = count;
-}
-
-/*!
- * @brief Stops the timer counting.
- *
- * This function stops the timer from counting.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number.
- */
-static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
-{
-    /* Stop the timer immediately */
-    base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
-}
-
-/*! @}*/
-
-/*!
- * @name Get & release channel
- * @{
- */
-
-/*!
- * @brief Find the available channel.
- *
- * This function returns the lowest available channel number.
- *
- * @param base Multi-Rate timer peripheral base address
- */
-static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
-{
-    return base->IDLE_CH;
-}
-
-/*!
- * @brief Release the channel when the timer is using the multi-task mode.
- *
- * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
- * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
- * long as it is needed and release it by calling this function. This removes the need to ask for
- * an available channel for every use.
- *
- * @param base    Multi-Rate timer peripheral base address
- * @param channel Timer channel number.
- */
-static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
-{
-    uint32_t reg = base->CHANNEL[channel].STAT;
-
-    /* Clear flag bits to prevent accidentally clearing anything when writing back */
-    reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
-    reg |= MRT_CHANNEL_STAT_INUSE_MASK;
-
-    base->CHANNEL[channel].STAT = reg;
-}
-
-/*! @}*/
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_MRT_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,220 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_OTP_H_
-#define _FSL_OTP_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup otp
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief OTP driver version 2.0.0.
- *
- * Current version: 2.0.0
- *
- * Change log:
- * - Version 2.0.0
- *   - Initial version.
- */
-#define FSL_OTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief Bank bit flags. */
-typedef enum _otp_bank
-{
-    kOTP_Bank0 = 0x1U, /*!< Bank 0. */
-    kOTP_Bank1 = 0x2U, /*!< Bank 1. */
-    kOTP_Bank2 = 0x4U, /*!< Bank 2. */
-    kOTP_Bank3 = 0x8U  /*!< Bank 3. */
-} otp_bank_t;
-
-/*! @brief Bank word bit flags. */
-typedef enum _otp_word
-{
-    kOTP_Word0 = 0x1U, /*!< Word 0. */
-    kOTP_Word1 = 0x2U, /*!< Word 1. */
-    kOTP_Word2 = 0x4U, /*!< Word 2. */
-    kOTP_Word3 = 0x8U  /*!< Word 3. */
-} otp_word_t;
-
-/*! @brief Lock modifications of a read or write access to a bank register. */
-typedef enum _otp_lock
-{
-    kOTP_LockDontLock = 0U, /*!< Do not lock. */
-    kOTP_LockLock = 1U      /*!< Lock till reset. */
-} otp_lock_t;
-
-/*! @brief OTP error codes. */
-enum _otp_status
-{
-    kStatus_OTP_WrEnableInvalid = MAKE_STATUS(kStatusGroup_OTP, 0x1U),           /*!< Write enable invalid. */
-    kStatus_OTP_SomeBitsAlreadyProgrammed = MAKE_STATUS(kStatusGroup_OTP, 0x2U), /*!< Some bits already programmed. */
-    kStatus_OTP_AllDataOrMaskZero = MAKE_STATUS(kStatusGroup_OTP, 0x3U),         /*!< All data or mask zero. */
-    kStatus_OTP_WriteAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0x4U),         /*!< Write access locked. */
-    kStatus_OTP_ReadDataMismatch = MAKE_STATUS(kStatusGroup_OTP, 0x5U),          /*!< Read data mismatch. */
-    kStatus_OTP_UsbIdEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x6U),              /*!< USB ID enabled. */
-    kStatus_OTP_EthMacEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x7U),             /*!< Ethernet MAC enabled. */
-    kStatus_OTP_AesKeysEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x8U),            /*!< AES keys enabled. */
-    kStatus_OTP_IllegalBank = MAKE_STATUS(kStatusGroup_OTP, 0x9U),               /*!< Illegal bank. */
-    kStatus_OTP_ShufflerConfigNotValid = MAKE_STATUS(kStatusGroup_OTP, 0xAU),    /*!< Shuffler config not valid. */
-    kStatus_OTP_ShufflerNotEnabled = MAKE_STATUS(kStatusGroup_OTP, 0xBU),        /*!< Shuffler not enabled. */
-    kStatus_OTP_ShufflerCanOnlyProgSingleKey =
-        MAKE_STATUS(kStatusGroup_OTP, 0xBU),                              /*!< Shuffler can only program single key. */
-    kStatus_OTP_IllegalProgramData = MAKE_STATUS(kStatusGroup_OTP, 0xCU), /*!< Illegal program data. */
-    kStatus_OTP_ReadAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0xDU),   /*!< Read access locked. */
-};
-
-#define _OTP_ERR_BASE (0x70000U)
-#define _OTP_MAKE_STATUS(errorCode) \
-    ((errorCode == 0U) ? kStatus_Success : MAKE_STATUS(kStatusGroup_OTP, ((errorCode)-_OTP_ERR_BASE)))
-
-/*******************************************************************************
- * API
- *******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Initializes OTP controller.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_Init(void)
-{
-    uint32_t status = OTP_API->otpInit();
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Unlock one or more OTP banks for write access.
- *
- * @param bankMask bit flag that specifies which banks to unlock.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_EnableBankWriteMask(otp_bank_t bankMask)
-{
-    uint32_t status = OTP_API->otpEnableBankWriteMask(bankMask);
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Lock one or more OTP banks for write access.
- *
- * @param bankMask bit flag that specifies which banks to lock.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_DisableBankWriteMask(otp_bank_t bankMask)
-{
-    uint32_t status = OTP_API->otpDisableBankWriteMask(bankMask);
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Locks or unlocks write access to a register of an OTP bank and possibly lock un/locking of it.
- *
- * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
- * @param regEnableMask bit flag that specifies for which words to enable writing.
- * @param regDisableMask bit flag that specifies for which words to disable writing.
- * @param lockWrite specifies if access set can be modified or is locked till reset.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_EnableBankWriteLock(uint32_t bankIndex,
-                                               otp_word_t regEnableMask,
-                                               otp_word_t regDisableMask,
-                                               otp_lock_t lockWrite)
-{
-    uint32_t status = OTP_API->otpEnableBankWriteLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Locks or unlocks read access to a register of an OTP bank and possibly lock un/locking of it.
- *
- * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
- * @param regEnableMask bit flag that specifies for which words to enable reading.
- * @param regDisableMask bit flag that specifies for which words to disable reading.
- * @param lockWrite specifies if access set can be modified or is locked till reset.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_EnableBankReadLock(uint32_t bankIndex,
-                                              otp_word_t regEnableMask,
-                                              otp_word_t regDisableMask,
-                                              otp_lock_t lockWrite)
-{
-    uint32_t status = OTP_API->otpEnableBankReadLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Program a single register in an OTP bank.
- *
- * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
- * @param regIndex OTP register index.
- * @param value value to write.
- *
- * @return kStatus_Success upon successful execution, error status otherwise.
- */
-static inline status_t OTP_ProgramRegister(uint32_t bankIndex, uint32_t regIndex, uint32_t value)
-{
-    uint32_t status = OTP_API->otpProgramReg(bankIndex, regIndex, value);
-    return _OTP_MAKE_STATUS(status);
-}
-
-/*!
- * @brief Returns the version of the OTP driver in ROM.
- *
- * @return version.
- */
-static inline uint32_t OTP_GetDriverVersion(void)
-{
-    return OTP_API->otpGetDriverVersion();
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_OTP_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,411 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_pint.h"
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief Irq number array */
-static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
-
-/*! @brief Callback function array for PINT(s). */
-static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void PINT_Init(PINT_Type *base)
-{
-    uint32_t i;
-    uint32_t pmcfg;
-
-    assert(base);
-
-    pmcfg = 0;
-    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
-    {
-        s_pintCallback[i] = NULL;
-    }
-
-    /* Disable all bit slices */
-    for (i = 0; i < PINT_PIN_INT_COUNT; i++)
-    {
-        pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
-    }
-
-    /* Enable the peripheral clock */
-    CLOCK_EnableClock(kCLOCK_Pint);
-
-    /* Reset the peripheral */
-    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
-
-    /* Disable all pattern match bit slices */
-    base->PMCFG = pmcfg;
-}
-
-void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
-{
-    assert(base);
-
-    /* Clear Rise and Fall flags first */
-    PINT_PinInterruptClrRiseFlag(base, intr);
-    PINT_PinInterruptClrFallFlag(base, intr);
-
-    /* select level or edge sensitive */
-    base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
-
-    /* enable rising or level interrupt */
-    if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
-    {
-        base->SIENR = 1U << intr;
-    }
-    else
-    {
-        base->CIENR = 1U << intr;
-    }
-
-    /* Enable falling or select high level */
-    if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
-    {
-        base->SIENF = 1U << intr;
-    }
-    else
-    {
-        base->CIENF = 1U << intr;
-    }
-
-    s_pintCallback[intr] = callback;
-}
-
-void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
-{
-    uint32_t mask;
-    bool level;
-
-    assert(base);
-
-    *enable = kPINT_PinIntEnableNone;
-    level = false;
-
-    mask = 1U << pintr;
-    if (base->ISEL & mask)
-    {
-        /* Pin interrupt is level sensitive */
-        level = true;
-    }
-
-    if (base->IENR & mask)
-    {
-        if (level)
-        {
-            /* Level interrupt is enabled */
-            *enable = kPINT_PinIntEnableLowLevel;
-        }
-        else
-        {
-            /* Rising edge interrupt */
-            *enable = kPINT_PinIntEnableRiseEdge;
-        }
-    }
-
-    if (base->IENF & mask)
-    {
-        if (level)
-        {
-            /* Level interrupt is active high */
-            *enable = kPINT_PinIntEnableHighLevel;
-        }
-        else
-        {
-            /* Either falling or both edge */
-            if (*enable == kPINT_PinIntEnableRiseEdge)
-            {
-                /* Rising and faling edge */
-                *enable = kPINT_PinIntEnableBothEdges;
-            }
-            else
-            {
-                /* Falling edge */
-                *enable = kPINT_PinIntEnableFallEdge;
-            }
-        }
-    }
-
-    *callback = s_pintCallback[pintr];
-}
-
-void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
-{
-    uint32_t src_shift;
-    uint32_t cfg_shift;
-    uint32_t pmcfg;
-
-    assert(base);
-
-    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
-    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
-
-    /* Input source selection for selected bit slice */
-    base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
-
-    /* Bit slice configuration */
-    pmcfg = base->PMCFG;
-    pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
-
-    /* If end point is true, enable the bits */
-    if (bslice != 7U)
-    {
-        if (cfg->end_point)
-        {
-            pmcfg |= (0x1U << bslice);
-        }
-        else
-        {
-            pmcfg &= ~(0x1U << bslice);
-        }
-    }
-
-    base->PMCFG = pmcfg;
-
-    /* Save callback pointer */
-    s_pintCallback[bslice] = cfg->callback;
-}
-
-void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
-{
-    uint32_t src_shift;
-    uint32_t cfg_shift;
-
-    assert(base);
-
-    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
-    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
-
-    cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
-    cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
-
-    if (bslice == 7U)
-    {
-        cfg->end_point = true;
-    }
-    else
-    {
-        cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
-    }
-    cfg->callback = s_pintCallback[bslice];
-}
-
-uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
-{
-    uint32_t pmctrl;
-    uint32_t pmstatus;
-    uint32_t pmsrc;
-
-    pmctrl = PINT->PMCTRL;
-    pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
-    if (pmstatus)
-    {
-        /* Reset Pattern match engine detection logic */
-        pmsrc = base->PMSRC;
-        base->PMSRC = pmsrc;
-    }
-    return (pmstatus);
-}
-
-void PINT_EnableCallback(PINT_Type *base)
-{
-    uint32_t i;
-
-    assert(base);
-
-    PINT_PinInterruptClrStatusAll(base);
-    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
-    {
-        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
-        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
-        EnableIRQ(s_pintIRQ[i]);
-    }
-}
-
-void PINT_DisableCallback(PINT_Type *base)
-{
-    uint32_t i;
-
-    assert(base);
-
-    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
-    {
-        DisableIRQ(s_pintIRQ[i]);
-        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
-        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
-    }
-}
-
-void PINT_Deinit(PINT_Type *base)
-{
-    uint32_t i;
-
-    assert(base);
-
-    /* Cleanup */
-    PINT_DisableCallback(base);
-    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
-    {
-        s_pintCallback[i] = NULL;
-    }
-
-    /* Reset the peripheral */
-    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
-
-    /* Disable the peripheral clock */
-    CLOCK_DisableClock(kCLOCK_Pint);
-}
-
-/* IRQ handler functions overloading weak symbols in the startup */
-void PIN_INT0_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt0] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
-    }
-}
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
-void PIN_INT1_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt1] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
-void PIN_INT2_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt2] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
-void PIN_INT3_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt3] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
-void PIN_INT4_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt4] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
-void PIN_INT5_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt5] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
-void PIN_INT6_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt6] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
-    }
-}
-#endif
-
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
-void PIN_INT7_DriverIRQHandler(void)
-{
-    uint32_t pmstatus;
-
-    /* Reset pattern match detection */
-    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
-    /* Call user function */
-    if (s_pintCallback[kPINT_PinInt7] != NULL)
-    {
-        s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
-    }
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,568 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_PINT_H_
-#define _FSL_PINT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup pint_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/* Number of interrupt line supported by PINT */
-#define PINT_PIN_INT_COUNT 8U
-
-/* Number of input sources supported by PINT */
-#define PINT_INPUT_COUNT 8U
-
-/* PININT Bit slice source register bits */
-#define PININT_BITSLICE_SRC_START 8U
-#define PININT_BITSLICE_SRC_MASK 7U
-
-/* PININT Bit slice configuration register bits */
-#define PININT_BITSLICE_CFG_START 8U
-#define PININT_BITSLICE_CFG_MASK 7U
-#define PININT_BITSLICE_ENDP_MASK 7U
-
-#define PINT_PIN_INT_LEVEL 0x10U
-#define PINT_PIN_INT_EDGE 0x00U
-#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U
-#define PINT_PIN_INT_RISE 0x01U
-#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE)
-#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
-#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
-#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL)
-#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
-
-/*! @brief PINT Pin Interrupt enable type */
-typedef enum _pint_pin_enable
-{
-    kPINT_PinIntEnableNone = 0U,                      /*!< Do not generate Pin Interrupt */
-    kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE,  /*!< Generate Pin Interrupt on rising edge */
-    kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE,  /*!< Generate Pin Interrupt on falling edge */
-    kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */
-    kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL,  /*!< Generate Pin Interrupt on low level */
-    kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */
-} pint_pin_enable_t;
-
-/*! @brief PINT Pin Interrupt type */
-typedef enum _pint_int
-{
-    kPINT_PinInt0 = 0U, /*!< Pin Interrupt  0 */
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
-    kPINT_PinInt1 = 1U, /*!< Pin Interrupt  1 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
-    kPINT_PinInt2 = 2U, /*!< Pin Interrupt  2 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
-    kPINT_PinInt3 = 3U, /*!< Pin Interrupt  3 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
-    kPINT_PinInt4 = 4U, /*!< Pin Interrupt  4 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
-    kPINT_PinInt5 = 5U, /*!< Pin Interrupt  5 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
-    kPINT_PinInt6 = 6U, /*!< Pin Interrupt  6 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
-    kPINT_PinInt7 = 7U, /*!< Pin Interrupt  7 */
-#endif
-} pint_pin_int_t;
-
-/*! @brief PINT Pattern Match bit slice input source type */
-typedef enum _pint_pmatch_input_src
-{
-    kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */
-    kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */
-    kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */
-    kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */
-    kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */
-    kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */
-    kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */
-    kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */
-} pint_pmatch_input_src_t;
-
-/*! @brief PINT Pattern Match bit slice type */
-typedef enum _pint_pmatch_bslice
-{
-    kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
-    kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
-    kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
-    kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
-    kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
-    kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
-    kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */
-#endif
-#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
-    kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
-#endif
-} pint_pmatch_bslice_t;
-
-/*! @brief PINT Pattern Match configuration type */
-typedef enum _pint_pmatch_bslice_cfg
-{
-    kPINT_PatternMatchAlways = 0U,          /*!< Always Contributes to product term match */
-    kPINT_PatternMatchStickyRise = 1U,      /*!< Sticky Rising edge */
-    kPINT_PatternMatchStickyFall = 2U,      /*!< Sticky Falling edge */
-    kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */
-    kPINT_PatternMatchHigh = 4U,            /*!< High level */
-    kPINT_PatternMatchLow = 5U,             /*!< Low level */
-    kPINT_PatternMatchNever = 6U,           /*!< Never contributes to product term match */
-    kPINT_PatternMatchBothEdges = 7U,       /*!< Either rising or falling edge */
-} pint_pmatch_bslice_cfg_t;
-
-/*! @brief PINT Callback function. */
-typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status);
-
-typedef struct _pint_pmatch_cfg
-{
-    pint_pmatch_input_src_t bs_src;
-    pint_pmatch_bslice_cfg_t bs_cfg;
-    bool end_point;
-    pint_cb_t callback;
-} pint_pmatch_cfg_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief	Initialize PINT peripheral.
-
- * This function initializes the PINT peripheral and enables the clock.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-void PINT_Init(PINT_Type *base);
-
-/*!
- * @brief	Configure PINT peripheral pin interrupt.
-
- * This function configures a given pin interrupt.
- *
- * @param base Base address of the PINT peripheral.
- * @param intr Pin interrupt.
- * @param enable Selects detection logic.
- * @param callback Callback.
- *
- * @retval None.
- */
-void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback);
-
-/*!
- * @brief	Get PINT peripheral pin interrupt configuration.
-
- * This function returns the configuration of a given pin interrupt.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- * @param enable Pointer to store the detection logic.
- * @param callback Callback.
- *
- * @retval None.
- */
-void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback);
-
-/*!
- * @brief	Clear Selected pin interrupt status.
-
- * This function clears the selected pin interrupt status.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
-{
-    base->IST = (1U << pintr);
-}
-
-/*!
- * @brief	Get Selected pin interrupt status.
-
- * This function returns the selected pin interrupt status.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval status = 0 No pin interrupt request.  = 1 Selected Pin interrupt request active.
- */
-static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr)
-{
-    return ((base->IST & (1U << pintr)) ? 1U : 0U);
-}
-
-/*!
- * @brief	Clear all pin interrupts status.
-
- * This function clears the status of all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base)
-{
-    base->IST = PINT_IST_PSTAT_MASK;
-}
-
-/*!
- * @brief	Get all pin interrupts status.
-
- * This function returns the status of all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval status Each bit position indicates the status of corresponding pin interrupt.
- * = 0 No pin interrupt request. = 1 Pin interrupt request active.
- */
-static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base)
-{
-    return (base->IST);
-}
-
-/*!
- * @brief	Clear Selected pin interrupt fall flag.
-
- * This function clears the selected pin interrupt fall flag.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr)
-{
-    base->FALL = (1U << pintr);
-}
-
-/*!
- * @brief	Get selected pin interrupt fall flag.
-
- * This function returns the selected pin interrupt fall flag.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval flag = 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
- */
-static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr)
-{
-    return ((base->FALL & (1U << pintr)) ? 1U : 0U);
-}
-
-/*!
- * @brief	Clear all pin interrupt fall flags.
-
- * This function clears the fall flag for all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base)
-{
-    base->FALL = PINT_FALL_FDET_MASK;
-}
-
-/*!
- * @brief	Get all pin interrupt fall flags.
-
- * This function returns the fall flag of all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt.
- * 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
- */
-static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base)
-{
-    return (base->FALL);
-}
-
-/*!
- * @brief	Clear Selected pin interrupt rise flag.
-
- * This function clears the selected pin interrupt rise flag.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
-{
-    base->RISE = (1U << pintr);
-}
-
-/*!
- * @brief	Get selected pin interrupt rise flag.
-
- * This function returns the selected pin interrupt rise flag.
- *
- * @param base Base address of the PINT peripheral.
- * @param pintr Pin interrupt.
- *
- * @retval flag = 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
- */
-static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
-{
-    return ((base->RISE & (1U << pintr)) ? 1U : 0U);
-}
-
-/*!
- * @brief	Clear all pin interrupt rise flags.
-
- * This function clears the rise flag for all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base)
-{
-    base->RISE = PINT_RISE_RDET_MASK;
-}
-
-/*!
- * @brief	Get all pin interrupt rise flags.
-
- * This function returns the rise flag of all pin interrupts.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt.
- * 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
- */
-static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base)
-{
-    return (base->RISE);
-}
-
-/*!
- * @brief	Configure PINT pattern match.
-
- * This function configures a given pattern match bit slice.
- *
- * @param base Base address of the PINT peripheral.
- * @param bslice Pattern match bit slice number.
- * @param cfg Pointer to bit slice configuration.
- *
- * @retval None.
- */
-void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
-
-/*!
- * @brief	Get PINT pattern match configuration.
-
- * This function returns the configuration of a given pattern match bit slice.
- *
- * @param base Base address of the PINT peripheral.
- * @param bslice Pattern match bit slice number.
- * @param cfg Pointer to bit slice configuration.
- *
- * @retval None.
- */
-void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
-
-/*!
- * @brief	Get pattern match bit slice status.
-
- * This function returns the status of selected bit slice.
- *
- * @param base Base address of the PINT peripheral.
- * @param bslice Pattern match bit slice number.
- *
- * @retval status = 0 Match has not been detected.  = 1 Match has been detected.
- */
-static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice)
-{
-    return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice;
-}
-
-/*!
- * @brief	Get status of all pattern match bit slices.
-
- * This function returns the status of all bit slices.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval status Each bit position indicates the match status of corresponding bit slice.
- * = 0 Match has not been detected.  = 1 Match has been detected.
- */
-static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base)
-{
-    return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT;
-}
-
-/*!
- * @brief	Reset pattern match detection logic.
-
- * This function resets the pattern match detection logic if any of the product term is matching.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval pmstatus Each bit position indicates the match status of corresponding bit slice.
- * = 0 Match was detected.  = 1 Match was not detected.
- */
-uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base);
-
-/*!
- * @brief	Enable pattern match function.
-
- * This function enables the pattern match function.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval	None.
- */
-static inline void PINT_PatternMatchEnable(PINT_Type *base)
-{
-    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK;
-}
-
-/*!
- * @brief	Disable pattern match function.
-
- * This function disables the pattern match function.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval	None.
- */
-static inline void PINT_PatternMatchDisable(PINT_Type *base)
-{
-    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK;
-}
-
-/*!
- * @brief	Enable RXEV output.
-
- * This function enables the pattern match RXEV output.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval	None.
- */
-static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base)
-{
-    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK;
-}
-
-/*!
- * @brief	Disable RXEV output.
-
- * This function disables the pattern match RXEV output.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval	None.
- */
-static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base)
-{
-    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK;
-}
-
-/*!
- * @brief	Enable callback.
-
- * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
- * as soon as they are enabled, the callback function is not enabled until this function is called.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-void PINT_EnableCallback(PINT_Type *base);
-
-/*!
- * @brief	Disable callback.
-
- * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
- * being monitored but the callback function is not called.
- *
- * @param base Base address of the peripheral.
- *
- * @retval None.
- */
-void PINT_DisableCallback(PINT_Type *base);
-
-/*!
- * @brief	Deinitialize PINT peripheral.
-
- * This function disables the PINT clock.
- *
- * @param base Base address of the PINT peripheral.
- *
- * @retval None.
- */
-void PINT_Deinit(PINT_Type *base);
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _FSL_PINT_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "fsl_common.h"
-#include "fsl_power.h"
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* Empty file since implementation is in header file and power library */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,254 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_POWER_H_
-#define _FSL_POWER_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
-#define PDRCFG0 0x0U
-#define PDRCFG1 0x1U
-
-typedef enum pd_bits
-{
-    kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
-    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
-    kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
-    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
-    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
-    kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
-    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
-    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
-    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
-    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
-    kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
-    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
-    kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
-    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
-    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
-    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
-    kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
-    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
-    kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
-    kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
-    kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
-    kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
-    kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
-    kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
-
-    kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
-    kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
-    kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
-    kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
-    kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
-    kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
-
-    kPDRUNCFG_ForceUnsigned = 0x80000000U,
-} pd_bit_t;
-
-/* Power mode configuration API parameter */
-typedef enum _power_mode_config
-{
-    kPmu_Sleep = 0U,
-    kPmu_Deep_Sleep = 1U,
-    kPmu_Deep_PowerDown = 2U,
-} power_mode_cfg_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*!
-* @name Power Configuration
-* @{
-*/
-
-/*!
- * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
- *
- * @param en    peripheral for which to enable the PDRUNCFG bit
- * @return none
- */
-static inline void POWER_EnablePD(pd_bit_t en)
-{
-    /* PDRUNCFGSET */
-    SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU));
-}
-
-/*!
- * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
- *
- * @param en    peripheral for which to disable the PDRUNCFG bit
- * @return none
- */
-static inline void POWER_DisablePD(pd_bit_t en)
-{
-    /* PDRUNCFGCLR */
-    SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU));
-}
-
-/*!
- * @brief API to enable deep sleep bit in the ARM Core.
- *
- * @param none
- * @return none
- */
-static inline void POWER_EnableDeepSleep(void)
-{
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-}
-
-/*!
- * @brief API to disable deep sleep bit in the ARM Core.
- *
- * @param none
- * @return none
- */
-static inline void POWER_DisableDeepSleep(void)
-{
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-}
-
-/*!
- * @brief API to power down flash controller.
- *
- * @param none
- * @return none
- */
-static inline void POWER_PowerDownFlash(void)
-{
-    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
-    CLOCK_DisableClock(kCLOCK_Flash);
-
-    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
-    CLOCK_DisableClock(kCLOCK_Fmc);
-}
-
-/*!
- * @brief API to power up flash controller.
- *
- * @param none
- * @return none
- */
-static inline void POWER_PowerUpFlash(void)
-{
-    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
-    CLOCK_EnableClock(kCLOCK_Fmc);
-}
-
-/*!
- * @brief Power Library API to power the PLLs.
- *
- * @param none
- * @return none
- */
-void POWER_SetPLL(void);
-
-/*!
- * @brief Power Library API to power the USB PHY.
- *
- * @param none
- * @return none
- */
-void POWER_SetUsbPhy(void);
-
-/*!
- * @brief Power Library API to enter different power mode.
- *
- * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during power mode selected.
- * @return none
- */
-void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
-
-/*!
- * @brief Power Library API to enter sleep mode.
- *
- * @return none
- */
-void POWER_EnterSleep(void);
-
-/*!
- * @brief Power Library API to enter deep sleep mode.
- *
- * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be powered on during deep sleep
- * @return none
- */
-void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
-
-/*!
- * @brief Power Library API to enter deep power down mode.
- *
- * @param exclude_from_pd   Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during deep power 
- *                          down mode, but this is has no effect as the voltages are cut off.
- 
- * @return none
- */
-void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
-
-/*!
- * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
- *
- * @param freq  - The desired frequency at which the part would like to operate, 
- *                note that the voltage and flash wait states should be set before changing frequency
- * @return none
- */
-void POWER_SetVoltageForFreq(uint32_t freq);
-
-/*!
- * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
- *
- * @param freq  - The desired frequency at which the part would like to operate, 
- *                note that the voltage and flash wait states should be set before changing frequency
- * @return none
- */
-void POWER_SetVoltageForFreq(uint32_t freq);
-
-/*!
- * @brief Power Library API to return the library version.
- *
- * @param none
- * @return version number of the power library
- */
-uint32_t POWER_GetLibVersion(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FSL_POWER_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_common.h"
-#include "fsl_reset.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
-     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-
-void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
-{
-    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
-    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
-    const uint32_t bitMask = 1u << bitPos;
-
-    assert(bitPos < 32u);
-
-    /* ASYNC_SYSCON registers have offset 1024 */
-    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
-    {
-        /* reset register is in ASYNC_SYSCON */
-
-        /* set bit */
-        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
-        /* wait until it reads 0b1 */
-        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
-        {
-        }
-    }
-    else
-    {
-        /* reset register is in SYSCON */
-
-        /* set bit */
-        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
-        /* wait until it reads 0b1 */
-        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
-        {
-        }
-    }
-}
-
-void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
-{
-    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
-    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
-    const uint32_t bitMask = 1u << bitPos;
-
-    assert(bitPos < 32u);
-
-    /* ASYNC_SYSCON registers have offset 1024 */
-    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
-    {
-        /* reset register is in ASYNC_SYSCON */
-
-        /* clear bit */
-        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
-        /* wait until it reads 0b0 */
-        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
-        {
-        }
-    }
-    else
-    {
-        /* reset register is in SYSCON */
-
-        /* clear bit */
-        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
-        /* wait until it reads 0b0 */
-        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
-        {
-        }
-    }
-}
-
-void RESET_PeripheralReset(reset_ip_name_t peripheral)
-{
-    RESET_SetPeripheralReset(peripheral);
-    RESET_ClearPeripheralReset(peripheral);
-}
-
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_RESET_H_
-#define _FSL_RESET_H_
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-#include "fsl_device_registers.h"
-
-/*!
- * @addtogroup ksdk_common
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*!
- * @brief Enumeration for peripheral reset control bits
- *
- * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
- */
-typedef enum _SYSCON_RSTn
-{
-    kFLASH_RST_SHIFT_RSTn = 0 | 7U,          /**< Flash controller reset control */
-    kFMC_RST_SHIFT_RSTn = 0 | 8U,            /**< Flash accelerator reset control */
-    kEEPROM_RST_SHIFT_RSTn = 0 | 9U,         /**< EEPROM reset control */
-    kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
-    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
-    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
-    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
-    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
-    kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
-    kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
-    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
-    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
-    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
-    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
-    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
-    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
-    
-    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
-    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
-    kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
-    kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
-    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
-    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
-    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
-    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
-    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
-    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
-    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
-    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
-    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
-    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
-    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
-    kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
-    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
-    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
-    
-    kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
-    kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
-    kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
-    kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */    
-    kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
-    kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
-    kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
-    kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */ 
-    kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
-    kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
-    kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
-    kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */ 
-    kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
-    kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
-    kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
-    kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
-    kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
-    kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
-    kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
-    
-    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
-    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
-} SYSCON_RSTn_t;
-
-/** Array initializers with peripheral reset bits **/
-#define ADC_RSTS             \
-    {                        \
-        kADC0_RST_SHIFT_RSTn \
-    } /* Reset bits for ADC peripheral */
-#define AES_RSTS             \
-    {                        \
-        kAES_RST_SHIFT_RSTn  \
-    } /* Reset bits for AES peripheral */
-#define CRC_RSTS            \
-    {                       \
-        kCRC_RST_SHIFT_RSTn \
-    } /* Reset bits for CRC peripheral */
-#define CTIMER_RSTS                                                                                     \
-    {                                                                                                   \
-        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
-            kCT32B4_RST_SHIFT_RSTn                                                                      \
-    } /* Reset bits for CTIMER peripheral */
-#define DMA_RSTS            \
-    {                       \
-        kDMA_RST_SHIFT_RSTn \
-    } /* Reset bits for DMA peripheral */
-#define DMIC_RSTS            \
-    {                        \
-        kDMIC_RST_SHIFT_RSTn \
-    } /* Reset bits for DMIC peripheral */
-#define EMC_RSTS             \
-    {                        \
-        kEMC_RST_SHIFT_RSTn  \
-    } /* Reset bits for EMC peripheral */
-#define ETH_RST              \
-    {                        \
-        kETH_RST_SHIFT_RSTn  \
-    } /* Reset bits for EMC peripheral */
-#define FLEXCOMM_RSTS                                                                                            \
-    {                                                                                                            \
-        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
-            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn                                       \
-    } /* Reset bits for FLEXCOMM peripheral */
-#define GINT_RSTS                                  \
-    {                                              \
-        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
-    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
-#define GPIO_RSTS                                    \
-    {                                                \
-        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
-        kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
-    } /* Reset bits for GPIO peripheral */
-#define INPUTMUX_RSTS       \
-    {                       \
-        kMUX_RST_SHIFT_RSTn \
-    } /* Reset bits for INPUTMUX peripheral */
-#define IOCON_RSTS            \
-    {                         \
-        kIOCON_RST_SHIFT_RSTn \
-    } /* Reset bits for IOCON peripheral */
-#define FLASH_RSTS                                 \
-    {                                              \
-        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
-    } /* Reset bits for Flash peripheral */
-#define LCD_RSTS                                 \
-    {                                            \
-        kLCD_RST_SHIFT_RSTn                      \
-    } /* Reset bits for LCD peripheral */
-#define MRT_RSTS            \
-    {                       \
-        kMRT_RST_SHIFT_RSTn \
-    } /* Reset bits for MRT peripheral */
-#define MCAN_RSTS                                   \
-    {                                               \
-        kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
-    } /* Reset bits for MCAN0&MACN1 peripheral */
-#define OTP_RSTS            \
-    {                       \
-        kOTP_RST_SHIFT_RSTn \
-    } /* Reset bits for OTP peripheral */
-#define PINT_RSTS            \
-    {                        \
-        kPINT_RST_SHIFT_RSTn \
-    } /* Reset bits for PINT peripheral */
-#define RNG_RSTS             \
-    {                        \
-        kRNG_RST_SHIFT_RSTn  \
-    } /* Reset bits for RNG peripheral */
-#define SDIO_RST             \
-    {                        \
-        kSDIO_RST_SHIFT_RSTn \
-    } /* Reset bits for SDIO peripheral */
-#define SCT_RSTS             \
-    {                        \
-        kSCT0_RST_SHIFT_RSTn \
-    } /* Reset bits for SCT peripheral */
-#define SHA_RST              \
-    {                        \
-        kSHA_RST_SHIFT_RSTn  \
-    } /* Reset bits for SHA peripheral */
-#define USB0D_RST             \
-    {                         \
-        kUSB0D_RST_SHIFT_RSTn \
-    } /* Reset bits for USB0D peripheral */
-#define USB0HMR_RST             \
-    {                           \
-        kUSB0HMR_RST_SHIFT_RSTn \
-    } /* Reset bits for USB0HMR peripheral */
-#define USB0HSL_RST             \
-    {                           \
-        kUSB0HSL_RST_SHIFT_RSTn \
-    } /* Reset bits for USB0HSL peripheral */
-#define USB1H_RST             \
-    {                         \
-        kUSB1H_RST_SHIFT_RSTn \
-    } /* Reset bits for USB1H peripheral */
-#define USB1D_RST             \
-    {                         \
-        kUSB1D_RST_SHIFT_RSTn \
-    } /* Reset bits for USB1D peripheral */
-#define USB1RAM_RST             \
-    {                           \
-        kUSB1RAM_RST_SHIFT_RSTn \
-    } /* Reset bits for USB1RAM peripheral */
-#define UTICK_RSTS            \
-    {                         \
-        kUTICK_RST_SHIFT_RSTn \
-    } /* Reset bits for UTICK peripheral */
-#define WWDT_RSTS            \
-    {                        \
-        kWWDT_RST_SHIFT_RSTn \
-    } /* Reset bits for WWDT peripheral */
-
-typedef SYSCON_RSTn_t reset_ip_name_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Assert reset to peripheral.
- *
- * Asserts reset signal to specified peripheral module.
- *
- * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
-
-/*!
- * @brief Clear reset to peripheral.
- *
- * Clears reset signal to specified peripheral module, allows it to operate.
- *
- * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
-
-/*!
- * @brief Reset peripheral module.
- *
- * Reset peripheral module.
- *
- * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
- *                   and reset bit position in the reset register.
- */
-void RESET_PeripheralReset(reset_ip_name_t peripheral);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @} */
-
-#endif /* _FSL_RESET_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_rit.h"
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Gets the instance from the base address to be used to gate or ungate the module clock
- *
- * @param base RIT peripheral base address
- *
- * @return The RIT instance
- */
-static uint32_t RIT_GetInstance(RIT_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to RIT bases for each instance. */
-static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to PIT clocks for each instance. */
-static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t RIT_GetInstance(RIT_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++)
-    {
-        if (s_ritBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_ritBases));
-
-    return instance;
-}
-
-void RIT_GetDefaultConfig(rit_config_t *config)
-{
-    assert(config);
-    /* Timer operation are no effect in Debug mode */
-    config->enableRunInDebug = false;
-}
-
-void RIT_Init(RIT_Type *base, const rit_config_t *config)
-{
-    assert(config);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Ungate the RIT clock*/
-    CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Enable RIT timers */
-    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
-
-    /* Config timer operation is no effect in debug mode */
-    if (!config->enableRunInDebug)
-    {
-        base->CTRL &= ~RIT_CTRL_RITENBR_MASK;
-    }
-    else
-    {
-        base->CTRL |= RIT_CTRL_RITENBR_MASK;
-    }
-}
-
-void RIT_Deinit(RIT_Type *base)
-{
-    /* Disable RIT timers */
-    base->CTRL |= ~RIT_CTRL_RITEN_MASK;
-#ifdef FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
-    /* Gate the RIT clock*/
-    CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void RIT_SetTimerCompare(RIT_Type *base, uint64_t count)
-{
-    /* Disable RIT timers */
-    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
-    base->COMPVAL = (uint32_t)count;
-    base->COMPVAL_H = (uint16_t)(count >> 32U);
-}
-
-void RIT_SetMaskBit(RIT_Type *base, uint64_t count)
-{
-    base->MASK = (uint32_t)count;
-    base->MASK_H = (uint16_t)(count >> 32U);
-}
-
-uint64_t RIT_GetCompareTimerCount(RIT_Type *base)
-{
-    uint16_t valueH = 0U;
-    uint32_t valueL = 0U;
-
-    /* COMPVAL_H should be read before COMPVAL */
-    valueH = base->COMPVAL_H;
-    valueL = base->COMPVAL;
-
-    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
-}
-
-uint64_t RIT_GetCounterTimerCount(RIT_Type *base)
-{
-    uint16_t valueH = 0U;
-    uint32_t valueL = 0U;
-
-    /* COUNTER_H should be read before COUNTER */
-    valueH = base->COUNTER_H;
-    valueL = base->COUNTER;
-
-    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
-}
-
-uint64_t RIT_GetMaskTimerCount(RIT_Type *base)
-{
-    uint16_t valueH = 0U;
-    uint32_t valueL = 0U;
-
-    /* MASK_H should be read before MASK */
-    valueH = base->MASK_H;
-    valueL = base->MASK;
-
-    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,276 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_RIT_H_
-#define _FSL_RIT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup rit
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_RIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/*! @brief List of RIT status flags */
-typedef enum _rit_status_flags
-{
-    kRIT_TimerFlag = RIT_CTRL_RITINT_MASK, /*!< Timer flag */
-} rit_status_flags_t;
-
-/*!
- * @brief RIT config structure
- *
- * This structure holds the configuration settings for the RIT peripheral. To initialize this
- * structure to reasonable defaults, call the RIT_GetDefaultConfig() function and pass a
- * pointer to your config structure instance.
- *
- * The config struct can be made const so it resides in flash
- */
-typedef struct _rit_config
-{
-    bool enableRunInDebug; /*!< true: The timer is halted when the processor is halted for debugging.; false: Debug has
-                              no effect on the timer operation. */
-} rit_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations.
- *
- * @note This API should be called at the beginning of the application using the RIT driver.
- *
- * @param base   RIT peripheral base address
- * @param config Pointer to the user's RIT config structure
- */
-void RIT_Init(RIT_Type *base, const rit_config_t *config);
-
-/*!
- * @brief Gates the RIT clock and disables the RIT module.
- *
- * @param base RIT peripheral base address
- */
-void RIT_Deinit(RIT_Type *base);
-
-/*!
- * @brief Fills in the RIT configuration structure with the default settings.
- *
- * The default values are as follows.
- * @code
- *     config->enableRunInDebug = false;
- * @endcode
- * @param config Pointer to the onfiguration structure.
- */
-void RIT_GetDefaultConfig(rit_config_t *config);
-
-/*! @}*/
-
-/*!
- * @name Status Interface
- * @{
- */
-
-/*!
- * @brief Gets the RIT status flags.
- *
- * @param base    RIT peripheral base address
- *
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::rit_status_flags_t
- */
-static inline uint32_t RIT_GetStatusFlags(RIT_Type *base)
-{
-    return (base->CTRL);
-}
-
-/*!
- * @brief  Clears the RIT status flags.
- *
- * @param base    RIT peripheral base address
- * @param mask    The status flags to clear. This is a logical OR of members of the
- *                enumeration ::rit_status_flags_t
- */
-static inline void RIT_ClearStatusFlags(RIT_Type *base, uint32_t mask)
-{
-    base->CTRL |= mask;
-}
-
-/*! @}*/
-
-/*!
- * @name Read and Write the timer period
- * @{
- */
-
-/*!
- * @brief Sets the timer period in units of count.
- *
- * Timers begin counting from the value set by this function until it XXXXXXX,
- * then it counting the value again.
- * Software must stop the counter before reloading it with a new value..
- *
- * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
- *
- * @param base    RIT peripheral base address
- * @param count   Timer period in units of ticks
- */
-void RIT_SetTimerCompare(RIT_Type *base, uint64_t count);
-
-/*!
- * @brief Sets the mask bit of count compare.
- *
- * Timers begin counting from the value set by this function until it XXXXXXX,
- * then it counting the value again.
- * Software must stop the counter before reloading it with a new value..
- *
- * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
- *
- * @param base    RIT peripheral base address
- * @param count   Timer period in units of ticks
- */
-void RIT_SetMaskBit(RIT_Type *base, uint64_t count);
-
-/*!
- * @brief Reads the current timer counting value of compare register.
- *
- * This function returns the real-time timer counting value, in a range from 0 to a
- * timer period.
- *
- * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
- *
- * @param base    RIT peripheral base address
- *
- * @return Current timer counting value in ticks
- */
-uint64_t RIT_GetCompareTimerCount(RIT_Type *base);
-
-/*!
- * @brief Reads the current timer counting value of counter register.
- *
- * This function returns the real-time timer counting value, in a range from 0 to a
- * timer period.
- *
- * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
- *
- * @param base    RIT peripheral base address
- *
- * @return Current timer counting value in ticks
- */
-uint64_t RIT_GetCounterTimerCount(RIT_Type *base);
-
-/*!
- * @brief Reads the current timer counting value of mask register.
- *
- * This function returns the real-time timer counting value, in a range from 0 to a
- * timer period.
- *
- * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
- *
- * @param base    RIT peripheral base address
- *
- * @return Current timer counting value in ticks
- */
-uint64_t RIT_GetMaskTimerCount(RIT_Type *base);
-
-/*! @}*/
-
-/*!
- * @name Timer Start and Stop
- * @{
- */
-
-/*!
- * @brief Starts the timer counting.
- *
- * After calling this function, timers load initial value(0U), count up to desired value or over-flow
- * then the counter will count up again. Each time a timer reaches desired value,
- * it generates a XXXXXXX and sets XXXXXXX.
- *
- * @param base    RIT peripheral base address
- */
-static inline void RIT_StartTimer(RIT_Type *base)
-{
-    base->CTRL |= RIT_CTRL_RITEN_MASK;
-}
-
-/*!
- * @brief Stops the timer counting.
- *
- * This function stop timer counting. Timer reload their new value
- * after the next time they call the RIT_StartTimer.
- *
- * @param base    RIT peripheral base address
- * @param channel Timer channel number.
- */
-static inline void RIT_StopTimer(RIT_Type *base)
-{
-    /* Disable RIT timers */
-    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
-}
-
-/*! @}*/
-
-static inline void RIT_ClearCounter(RIT_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CTRL |= RIT_CTRL_RITENCLR_MASK;
-    }
-    else
-    {
-        base->CTRL &= ~RIT_CTRL_RITENCLR_MASK;
-    }
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_RIT_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_RNG_DRIVER_H_
-#define _FSL_RNG_DRIVER_H_
-
-#include "fsl_common.h"
-
-#if defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && FSL_FEATURE_SOC_LPC_RNG_COUNT
-
-/*!
- * @addtogroup rng
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief RNG driver version 2.0.0.
- *
- * Current version: 2.0.0
- *
- * Change log:
- * - Version 2.0.0
- *   - Initial version.
- */
-#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*******************************************************************************
- * API
- *******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Gets random data.
- *
- * This function returns single 32 bit random number.
- *
- * @return random data
- */
-static inline uint32_t RNG_GetRandomData(void)
-{
-    return OTP_API->rngRead();
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* FSL_FEATURE_SOC_LPC_RNG_COUNT */
-#endif /*_FSL_TRNG_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,288 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_rtc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define SECONDS_IN_A_DAY (86400U)
-#define SECONDS_IN_A_HOUR (3600U)
-#define SECONDS_IN_A_MINUTE (60U)
-#define DAYS_IN_A_YEAR (365U)
-#define YEAR_RANGE_START (1970U)
-#define YEAR_RANGE_END (2099U)
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Checks whether the date and time passed in is valid
- *
- * @param datetime Pointer to structure where the date and time details are stored
- *
- * @return Returns false if the date & time details are out of range; true if in range
- */
-static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
-
-/*!
- * @brief Converts time data from datetime to seconds
- *
- * @param datetime Pointer to datetime structure where the date and time details are stored
- *
- * @return The result of the conversion in seconds
- */
-static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
-
-/*!
- * @brief Converts time data from seconds to a datetime structure
- *
- * @param seconds  Seconds value that needs to be converted to datetime format
- * @param datetime Pointer to the datetime structure where the result of the conversion is stored
- */
-static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    /* Table of days in a month for a non leap year. First entry in the table is not used,
-     * valid months start from 1
-     */
-    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
-
-    /* Check year, month, hour, minute, seconds */
-    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
-        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
-    {
-        /* If not correct then error*/
-        return false;
-    }
-
-    /* Adjust the days in February for a leap year */
-    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
-    {
-        daysPerMonth[2] = 29U;
-    }
-
-    /* Check the validity of the day */
-    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
-    {
-        return false;
-    }
-
-    return true;
-}
-
-static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    /* Number of days from begin of the non Leap-year*/
-    /* Number of days from begin of the non Leap-year*/
-    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
-    uint32_t seconds;
-
-    /* Compute number of days from 1970 till given year*/
-    seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
-    /* Add leap year days */
-    seconds += ((datetime->year / 4) - (1970U / 4));
-    /* Add number of days till given month*/
-    seconds += monthDays[datetime->month];
-    /* Add days in given month. We subtract the current day as it is
-     * represented in the hours, minutes and seconds field*/
-    seconds += (datetime->day - 1);
-    /* For leap year if month less than or equal to Febraury, decrement day counter*/
-    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
-    {
-        seconds--;
-    }
-
-    seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
-              (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
-
-    return seconds;
-}
-
-static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    uint32_t x;
-    uint32_t secondsRemaining, days;
-    uint16_t daysInYear;
-    /* Table of days in a month for a non leap year. First entry in the table is not used,
-     * valid months start from 1
-     */
-    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
-
-    /* Start with the seconds value that is passed in to be converted to date time format */
-    secondsRemaining = seconds;
-
-    /* Calcuate the number of days, we add 1 for the current day which is represented in the
-     * hours and seconds field
-     */
-    days = secondsRemaining / SECONDS_IN_A_DAY + 1;
-
-    /* Update seconds left*/
-    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
-
-    /* Calculate the datetime hour, minute and second fields */
-    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
-    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
-    datetime->minute = secondsRemaining / 60U;
-    datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
-
-    /* Calculate year */
-    daysInYear = DAYS_IN_A_YEAR;
-    datetime->year = YEAR_RANGE_START;
-    while (days > daysInYear)
-    {
-        /* Decrease day count by a year and increment year by 1 */
-        days -= daysInYear;
-        datetime->year++;
-
-        /* Adjust the number of days for a leap year */
-        if (datetime->year & 3U)
-        {
-            daysInYear = DAYS_IN_A_YEAR;
-        }
-        else
-        {
-            daysInYear = DAYS_IN_A_YEAR + 1;
-        }
-    }
-
-    /* Adjust the days in February for a leap year */
-    if (!(datetime->year & 3U))
-    {
-        daysPerMonth[2] = 29U;
-    }
-
-    for (x = 1U; x <= 12U; x++)
-    {
-        if (days <= daysPerMonth[x])
-        {
-            datetime->month = x;
-            break;
-        }
-        else
-        {
-            days -= daysPerMonth[x];
-        }
-    }
-
-    datetime->day = days;
-}
-
-void RTC_Init(RTC_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the RTC peripheral clock */
-    CLOCK_EnableClock(kCLOCK_Rtc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Make sure the reset bit is cleared */
-    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
-
-    /* Make sure the RTC OSC is powered up */
-    base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
-}
-
-status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    /* Return error if the time provided is not valid */
-    if (!(RTC_CheckDatetimeFormat(datetime)))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Set time in seconds */
-    base->COUNT = RTC_ConvertDatetimeToSeconds(datetime);
-
-    return kStatus_Success;
-}
-
-void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    uint32_t seconds = 0;
-
-    seconds = base->COUNT;
-    RTC_ConvertSecondsToDatetime(seconds, datetime);
-}
-
-status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
-{
-    assert(alarmTime);
-
-    uint32_t alarmSeconds = 0;
-    uint32_t currSeconds = 0;
-
-    /* Return error if the alarm time provided is not valid */
-    if (!(RTC_CheckDatetimeFormat(alarmTime)))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
-
-    /* Get the current time */
-    currSeconds = base->COUNT;
-
-    /* Return error if the alarm time has passed */
-    if (alarmSeconds < currSeconds)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Set alarm in seconds*/
-    base->MATCH = alarmSeconds;
-
-    return kStatus_Success;
-}
-
-void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
-{
-    assert(datetime);
-
-    uint32_t alarmSeconds = 0;
-
-    /* Get alarm in seconds  */
-    alarmSeconds = base->MATCH;
-
-    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,340 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_RTC_H_
-#define _FSL_RTC_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup rtc
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/*! @brief List of RTC interrupts */
-typedef enum _rtc_interrupt_enable
-{
-    kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/
-    kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK  /*!< Wake-up interrupt.*/
-} rtc_interrupt_enable_t;
-
-/*! @brief List of RTC flags */
-typedef enum _rtc_status_flags
-{
-    kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/
-    kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/
-} rtc_status_flags_t;
-
-/*! @brief Structure is used to hold the date and time */
-typedef struct _rtc_datetime
-{
-    uint16_t year;  /*!< Range from 1970 to 2099.*/
-    uint8_t month;  /*!< Range from 1 to 12.*/
-    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
-    uint8_t hour;   /*!< Range from 0 to 23.*/
-    uint8_t minute; /*!< Range from 0 to 59.*/
-    uint8_t second; /*!< Range from 0 to 59.*/
-} rtc_datetime_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Ungates the RTC clock and enables the RTC oscillator.
- *
- * @note This API should be called at the beginning of the application using the RTC driver.
- *
- * @param base RTC peripheral base address
- */
-void RTC_Init(RTC_Type *base);
-
-/*!
- * @brief Stop the timer and gate the RTC clock
- *
- * @param base RTC peripheral base address
- */
-static inline void RTC_Deinit(RTC_Type *base)
-{
-    /* Stop the RTC timer */
-    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Gate the module clock */
-    CLOCK_DisableClock(kCLOCK_Rtc);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-/*! @}*/
-
-/*!
- * @name Current Time & Alarm
- * @{
- */
-
-/*!
- * @brief Sets the RTC date and time according to the given time structure.
- *
- * The RTC counter must be stopped prior to calling this function as writes to the RTC
- * seconds register will fail if the RTC counter is running.
- *
- * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details to set are stored
- *
- * @return kStatus_Success: Success in setting the time and starting the RTC
- *         kStatus_InvalidArgument: Error because the datetime format is incorrect
- */
-status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
-
-/*!
- * @brief Gets the RTC time and stores it in the given time structure.
- *
- * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details are stored.
- */
-void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
-
-/*!
- * @brief Sets the RTC alarm time
- *
- * The function checks whether the specified alarm time is greater than the present
- * time. If not, the function does not set the alarm and returns an error.
- *
- * @param base      RTC peripheral base address
- * @param alarmTime Pointer to structure where the alarm time is stored.
- *
- * @return kStatus_Success: success in setting the RTC alarm
- *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
- *         kStatus_Fail: Error because the alarm time has already passed
- */
-status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
-
-/*!
- * @brief Returns the RTC alarm time.
- *
- * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the alarm date and time details are stored.
- */
-void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
-
-/*! @}*/
-
-/*!
- * @brief Enable the RTC high resolution timer and set the wake-up time.
- *
- * @param base        RTC peripheral base address
- * @param wakeupValue The value to be loaded into the RTC WAKE register
- */
-static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue)
-{
-    /* Enable the 1kHz RTC timer */
-    base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK;
-
-    /* Set the start count value into the wake-up timer */
-    base->WAKE = wakeupValue;
-}
-
-/*!
- * @brief Read actual RTC counter value.
- *
- * @param base        RTC peripheral base address
- */
-static inline uint16_t RTC_GetWakeupCount(RTC_Type *base)
-{
-    /* Read wake-up counter */
-    return RTC_WAKE_VAL(base->WAKE);
-}
-
-/*!
- * @name Interrupt Interface
- * @{
- */
-
-/*!
- * @brief Enables the selected RTC interrupts.
- *
- * @param base RTC peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::rtc_interrupt_enable_t
- */
-static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
-{
-    uint32_t reg = base->CTRL;
-
-    /* Clear flag bits to prevent accidentally clearing anything when writing back */
-    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
-    reg |= mask;
-
-    base->CTRL = reg;
-}
-
-/*!
- * @brief Disables the selected RTC interrupts.
- *
- * @param base RTC peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::rtc_interrupt_enable_t
- */
-static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
-{
-    uint32_t reg = base->CTRL;
-
-    /* Clear flag bits to prevent accidentally clearing anything when writing back */
-    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask);
-
-    base->CTRL = reg;
-}
-
-/*!
- * @brief Gets the enabled RTC interrupts.
- *
- * @param base RTC peripheral base address
- *
- * @return The enabled interrupts. This is the logical OR of members of the
- *         enumeration ::rtc_interrupt_enable_t
- */
-static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
-{
-    return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK));
-}
-
-/*! @}*/
-
-/*!
- * @name Status Interface
- * @{
- */
-
-/*!
- * @brief Gets the RTC status flags
- *
- * @param base RTC peripheral base address
- *
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::rtc_status_flags_t
- */
-static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
-{
-    return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK));
-}
-
-/*!
- * @brief  Clears the RTC status flags.
- *
- * @param base RTC peripheral base address
- * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::rtc_status_flags_t
- */
-static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
-{
-    uint32_t reg = base->CTRL;
-
-    /* Clear flag bits to prevent accidentally clearing anything when writing back */
-    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
-
-    /* Write 1 to the flags we wish to clear */
-    reg |= mask;
-
-    base->CTRL = reg;
-}
-
-/*! @}*/
-
-/*!
- * @name Timer Start and Stop
- * @{
- */
-
-/*!
- * @brief Starts the RTC time counter.
- *
- * After calling this function, the timer counter increments once a second provided SR[TOF] or
- * SR[TIF] are not set.
- *
- * @param base RTC peripheral base address
- */
-static inline void RTC_StartTimer(RTC_Type *base)
-{
-    base->CTRL |= RTC_CTRL_RTC_EN_MASK;
-}
-
-/*!
- * @brief Stops the RTC time counter.
- *
- * RTC's seconds register can be written to only when the timer is stopped.
- *
- * @param base RTC peripheral base address
- */
-static inline void RTC_StopTimer(RTC_Type *base)
-{
-    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
-}
-
-/*! @}*/
-
-/*!
- * @brief Performs a software reset on the RTC module.
- *
- * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it.
- *
- * @param base RTC peripheral base address
- */
-static inline void RTC_Reset(RTC_Type *base)
-{
-    base->CTRL |= RTC_CTRL_SWRESET_MASK;
-    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
-}
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_RTC_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,535 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_sctimer.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief Typedef for interrupt handler. */
-typedef void (*sctimer_isr_t)(SCT_Type *base);
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Gets the instance from the base address
- *
- * @param base SCTimer peripheral base address
- *
- * @return The SCTimer instance
- */
-static uint32_t SCTIMER_GetInstance(SCT_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to SCT bases for each instance. */
-static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to SCT clocks for each instance. */
-static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to SCT resets for each instance. */
-static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
-
-/*!< @brief SCTimer event Callback function. */
-static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
-
-/*!< @brief Keep track of SCTimer event number */
-static uint32_t s_currentEvent;
-
-/*!< @brief Keep track of SCTimer state number */
-static uint32_t s_currentState;
-
-/*!< @brief Keep track of SCTimer match/capture register number */
-static uint32_t s_currentMatch;
-
-/*! @brief Pointer to SCTimer IRQ handler */
-static sctimer_isr_t s_sctimerIsr;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t SCTIMER_GetInstance(SCT_Type *base)
-{
-    uint32_t instance;
-    uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < sctArrayCount; instance++)
-    {
-        if (s_sctBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < sctArrayCount);
-
-    return instance;
-}
-
-status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
-{
-    assert(config);
-    uint32_t i;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the SCTimer clock*/
-    CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the module */
-    RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
-
-    /* Setup the counter operation */
-    base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
-                   SCT_CONFIG_UNIFY(config->enableCounterUnify);
-
-    /* Write to the control register, clear the counter and keep the counters halted */
-    base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
-                 SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
-
-    if (!(config->enableCounterUnify))
-    {
-        base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
-                      SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
-    }
-
-    /* Initial state of channel output */
-    base->OUTPUT = config->outInitState;
-
-    /* Clear the global variables */
-    s_currentEvent = 0;
-    s_currentState = 0;
-    s_currentMatch = 0;
-
-    /* Clear the callback array */
-    for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
-    {
-        s_eventCallback[i] = NULL;
-    }
-
-    /* Save interrupt handler */
-    s_sctimerIsr = SCTIMER_EventHandleIRQ;
-
-    return kStatus_Success;
-}
-
-void SCTIMER_Deinit(SCT_Type *base)
-{
-    /* Halt the counters */
-    base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the SCTimer clock*/
-    CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
-{
-    assert(config);
-
-    /* SCT operates as a unified 32-bit counter */
-    config->enableCounterUnify = true;
-    /* System clock clocks the entire SCT module */
-    config->clockMode = kSCTIMER_System_ClockMode;
-    /* This is used only by certain clock modes */
-    config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
-    /* Up count mode only for the unified counter */
-    config->enableBidirection_l = false;
-    /* Up count mode only for Counte_H */
-    config->enableBidirection_h = false;
-    /* Prescale factor of 1 */
-    config->prescale_l = 0;
-    /* Prescale factor of 1 for Counter_H*/
-    config->prescale_h = 0;
-    /* Clear outputs */
-    config->outInitState = 0;
-}
-
-status_t SCTIMER_SetupPwm(SCT_Type *base,
-                          const sctimer_pwm_signal_param_t *pwmParams,
-                          sctimer_pwm_mode_t mode,
-                          uint32_t pwmFreq_Hz,
-                          uint32_t srcClock_Hz,
-                          uint32_t *event)
-{
-    assert(pwmParams);
-    assert(srcClock_Hz);
-    assert(pwmFreq_Hz);
-
-    uint32_t period, pulsePeriod = 0;
-    uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
-    uint32_t periodEvent, pulseEvent;
-    uint32_t reg;
-
-    /* This function will create 2 events, return an error if we do not have enough events available */
-    if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
-    {
-        return kStatus_Fail;
-    }
-
-    if (pwmParams->dutyCyclePercent == 0)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Set unify bit to operate in 32-bit counter mode */
-    base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
-
-    /* Use bi-directional mode for center-aligned PWM */
-    if (mode == kSCTIMER_CenterAlignedPwm)
-    {
-        base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
-    }
-
-    /* Calculate PWM period match value */
-    if (mode == kSCTIMER_EdgeAlignedPwm)
-    {
-        period = (sctClock / pwmFreq_Hz) - 1;
-    }
-    else
-    {
-        period = sctClock / (pwmFreq_Hz * 2);
-    }
-
-    /* Calculate pulse width match value */
-    pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
-
-    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
-    if (pwmParams->dutyCyclePercent >= 100)
-    {
-        pulsePeriod = period + 2;
-    }
-
-    /* Schedule an event when we reach the PWM period */
-    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
-
-    /* Schedule an event when we reach the pulse width */
-    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
-
-    /* Reset the counter when we reach the PWM period */
-    SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
-
-    /* Return the period event to the user */
-    *event = periodEvent;
-
-    /* For high-true level */
-    if (pwmParams->level == kSCTIMER_HighTrue)
-    {
-        /* Set the initial output level to low which is the inactive state */
-        base->OUTPUT &= ~(1U << pwmParams->output);
-
-        if (mode == kSCTIMER_EdgeAlignedPwm)
-        {
-            /* Set the output when we reach the PWM period */
-            SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
-            /* Clear the output when we reach the PWM pulse value */
-            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
-        }
-        else
-        {
-            /* Clear the output when we reach the PWM pulse event */
-            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
-            /* Reverse output when down counting */
-            reg = base->OUTPUTDIRCTRL;
-            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
-            reg |= (1U << (2 * pwmParams->output));
-            base->OUTPUTDIRCTRL = reg;
-        }
-    }
-    /* For low-true level */
-    else
-    {
-        /* Set the initial output level to high which is the inactive state */
-        base->OUTPUT |= (1U << pwmParams->output);
-
-        if (mode == kSCTIMER_EdgeAlignedPwm)
-        {
-            /* Clear the output when we reach the PWM period */
-            SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
-            /* Set the output when we reach the PWM pulse value */
-            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
-        }
-        else
-        {
-            /* Set the output when we reach the PWM pulse event */
-            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
-            /* Reverse output when down counting */
-            reg = base->OUTPUTDIRCTRL;
-            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
-            reg |= (1U << (2 * pwmParams->output));
-            base->OUTPUTDIRCTRL = reg;
-        }
-    }
-
-    return kStatus_Success;
-}
-
-void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
-
-{
-    assert(dutyCyclePercent > 0);
-
-    uint32_t periodMatchReg, pulseMatchReg;
-    uint32_t pulsePeriod = 0, period;
-
-    /* Retrieve the match register number for the PWM period */
-    periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
-
-    /* Retrieve the match register number for the PWM pulse period */
-    pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
-
-    period = base->SCTMATCH[periodMatchReg];
-
-    /* Calculate pulse width match value */
-    pulsePeriod = (period * dutyCyclePercent) / 100;
-
-    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
-    if (dutyCyclePercent >= 100)
-    {
-        pulsePeriod = period + 2;
-    }
-
-    /* Stop the counter before updating match register */
-    SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
-
-    /* Update dutycycle */
-    base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
-    base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
-
-    /* Restart the counter */
-    SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
-}
-
-status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
-                                        sctimer_event_t howToMonitor,
-                                        uint32_t matchValue,
-                                        uint32_t whichIO,
-                                        sctimer_counter_t whichCounter,
-                                        uint32_t *event)
-{
-    uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
-    uint32_t currentCtrlVal = howToMonitor;
-
-    /* Return an error if we have hit the limit in terms of number of events created */
-    if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
-    {
-        return kStatus_Fail;
-    }
-
-    /* IO only mode */
-    if (combMode == 0x2U)
-    {
-        base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
-    }
-    /* Match mode only */
-    else if (combMode == 0x1U)
-    {
-        /* Return an error if we have hit the limit in terms of number of number of match registers */
-        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
-        {
-            return kStatus_Fail;
-        }
-
-        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
-        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-        {
-            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
-            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
-        }
-        else
-        {
-            /* Select the counter, no need for this if operating in 32-bit mode */
-            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
-            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
-            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
-        }
-        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
-        /* Increment the match register number */
-        s_currentMatch++;
-    }
-    /* Use both Match & IO */
-    else
-    {
-        /* Return an error if we have hit the limit in terms of number of number of match registers */
-        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
-        {
-            return kStatus_Fail;
-        }
-
-        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
-        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-        {
-            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
-            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
-        }
-        else
-        {
-            /* Select the counter, no need for this if operating in 32-bit mode */
-            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
-            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
-            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
-        }
-        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
-        /* Increment the match register number */
-        s_currentMatch++;
-    }
-
-    /* Enable the event in the current state */
-    base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
-
-    /* Return the event number */
-    *event = s_currentEvent;
-
-    /* Increment the event number */
-    s_currentEvent++;
-
-    return kStatus_Success;
-}
-
-void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
-{
-    /* Enable event in the current state */
-    base->EVENT[event].STATE |= (1U << s_currentState);
-}
-
-status_t SCTIMER_IncreaseState(SCT_Type *base)
-{
-    /* Return an error if we have hit the limit in terms of states used */
-    if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
-    {
-        return kStatus_Fail;
-    }
-
-    s_currentState++;
-
-    return kStatus_Success;
-}
-
-uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
-{
-    return s_currentState;
-}
-
-void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
-{
-    uint32_t reg;
-
-    /* Set the same event to set and clear the output */
-    base->OUT[whichIO].CLR |= (1U << event);
-    base->OUT[whichIO].SET |= (1U << event);
-
-    /* Set the conflict resolution to toggle output */
-    reg = base->RES;
-    reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
-    reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
-    base->RES = reg;
-}
-
-status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
-                                    sctimer_counter_t whichCounter,
-                                    uint32_t *captureRegister,
-                                    uint32_t event)
-{
-    /* Return an error if we have hit the limit in terms of number of capture/match registers used */
-    if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-    {
-        /* Set the bit to enable event */
-        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
-
-        /* Set this resource to be a capture rather than match */
-        base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
-    }
-    else
-    {
-        /* Set bit to enable event */
-        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
-
-        /* Set this resource to be a capture rather than match */
-        base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
-    }
-
-    /* Return the match register number */
-    *captureRegister = s_currentMatch;
-
-    /* Increase the match register number */
-    s_currentMatch++;
-
-    return kStatus_Success;
-}
-
-void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
-{
-    s_eventCallback[event] = callback;
-}
-
-void SCTIMER_EventHandleIRQ(SCT_Type *base)
-{
-    uint32_t eventFlag = SCT0->EVFLAG;
-    /* Only clear the flags whose interrupt field is enabled */
-    uint32_t clearFlag = (eventFlag & SCT0->EVEN);
-    uint32_t mask = eventFlag;
-    int i = 0;
-
-    /* Invoke the callback for certain events */
-    for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
-    {
-        if (mask & 0x1)
-        {
-            if (s_eventCallback[i] != NULL)
-            {
-                s_eventCallback[i]();
-            }
-        }
-        mask >>= 1;
-    }
-
-    /* Clear event interrupt flag */
-    SCT0->EVFLAG = clearFlag;
-}
-
-void SCT0_IRQHandler(void)
-{
-    s_sctimerIsr(SCT0);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,822 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SCTIMER_H_
-#define _FSL_SCTIMER_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup sctimer
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
-
-/*! @brief SCTimer PWM operation modes */
-typedef enum _sctimer_pwm_mode
-{
-    kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
-    kSCTIMER_CenterAlignedPwm     /*!< Center-aligned PWM */
-} sctimer_pwm_mode_t;
-
-/*! @brief SCTimer counters when working as two independent 16-bit counters */
-typedef enum _sctimer_counter
-{
-    kSCTIMER_Counter_L = 0U, /*!< Counter L */
-    kSCTIMER_Counter_H       /*!< Counter H */
-} sctimer_counter_t;
-
-/*! @brief List of SCTimer input pins */
-typedef enum _sctimer_input
-{
-    kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */
-    kSCTIMER_Input_1,      /*!< SCTIMER input 1 */
-    kSCTIMER_Input_2,      /*!< SCTIMER input 2 */
-    kSCTIMER_Input_3,      /*!< SCTIMER input 3 */
-    kSCTIMER_Input_4,      /*!< SCTIMER input 4 */
-    kSCTIMER_Input_5,      /*!< SCTIMER input 5 */
-    kSCTIMER_Input_6,      /*!< SCTIMER input 6 */
-    kSCTIMER_Input_7       /*!< SCTIMER input 7 */
-} sctimer_input_t;
-
-/*! @brief List of SCTimer output pins */
-typedef enum _sctimer_out
-{
-    kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/
-    kSCTIMER_Out_1,      /*!< SCTIMER output 1 */
-    kSCTIMER_Out_2,      /*!< SCTIMER output 2 */
-    kSCTIMER_Out_3,      /*!< SCTIMER output 3 */
-    kSCTIMER_Out_4,      /*!< SCTIMER output 4 */
-    kSCTIMER_Out_5,      /*!< SCTIMER output 5 */
-    kSCTIMER_Out_6,      /*!< SCTIMER output 6 */
-    kSCTIMER_Out_7       /*!< SCTIMER output 7 */
-} sctimer_out_t;
-
-/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */
-typedef enum _sctimer_pwm_level_select
-{
-    kSCTIMER_LowTrue = 0U, /*!< Low true pulses */
-    kSCTIMER_HighTrue      /*!< High true pulses */
-} sctimer_pwm_level_select_t;
-
-/*! @brief Options to configure a SCTimer PWM signal */
-typedef struct _sctimer_pwm_signal_param
-{
-    sctimer_out_t output;             /*!< The output pin to use to generate the PWM signal */
-    sctimer_pwm_level_select_t level; /*!< PWM output active level select. */
-    uint8_t dutyCyclePercent;         /*!< PWM pulse width, value should be between 1 to 100
-                                           100 = always active signal (100% duty cycle).*/
-} sctimer_pwm_signal_param_t;
-
-/*! @brief SCTimer clock mode options */
-typedef enum _sctimer_clock_mode
-{
-    kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */
-    kSCTIMER_Sampled_ClockMode,     /*!< Sampled System Clock Mode */
-    kSCTIMER_Input_ClockMode,       /*!< SCT Input Clock Mode */
-    kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */
-} sctimer_clock_mode_t;
-
-/*! @brief SCTimer clock select options */
-typedef enum _sctimer_clock_select
-{
-    kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */
-    kSCTIMER_Clock_On_Fall_Input_0,      /*!< Falling edges on input 0 */
-    kSCTIMER_Clock_On_Rise_Input_1,      /*!< Rising edges on input 1 */
-    kSCTIMER_Clock_On_Fall_Input_1,      /*!< Falling edges on input 1 */
-    kSCTIMER_Clock_On_Rise_Input_2,      /*!< Rising edges on input 2 */
-    kSCTIMER_Clock_On_Fall_Input_2,      /*!< Falling edges on input 2 */
-    kSCTIMER_Clock_On_Rise_Input_3,      /*!< Rising edges on input 3 */
-    kSCTIMER_Clock_On_Fall_Input_3,      /*!< Falling edges on input 3 */
-    kSCTIMER_Clock_On_Rise_Input_4,      /*!< Rising edges on input 4 */
-    kSCTIMER_Clock_On_Fall_Input_4,      /*!< Falling edges on input 4 */
-    kSCTIMER_Clock_On_Rise_Input_5,      /*!< Rising edges on input 5 */
-    kSCTIMER_Clock_On_Fall_Input_5,      /*!< Falling edges on input 5 */
-    kSCTIMER_Clock_On_Rise_Input_6,      /*!< Rising edges on input 6 */
-    kSCTIMER_Clock_On_Fall_Input_6,      /*!< Falling edges on input 6 */
-    kSCTIMER_Clock_On_Rise_Input_7,      /*!< Rising edges on input 7 */
-    kSCTIMER_Clock_On_Fall_Input_7       /*!< Falling edges on input 7 */
-} sctimer_clock_select_t;
-
-/*!
- * @brief SCTimer output conflict resolution options.
- *
- * Specifies what action should be taken if multiple events dictate that a given output should be
- * both set and cleared at the same time
- */
-typedef enum _sctimer_conflict_resolution
-{
-    kSCTIMER_ResolveNone = 0U, /*!< No change */
-    kSCTIMER_ResolveSet,       /*!< Set output */
-    kSCTIMER_ResolveClear,     /*!< Clear output */
-    kSCTIMER_ResolveToggle     /*!< Toggle output */
-} sctimer_conflict_resolution_t;
-
-/*! @brief List of SCTimer event types */
-typedef enum _sctimer_event
-{
-    kSCTIMER_InputLowOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputRiseOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputFallOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputHighOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_MatchEventOnly =
-        (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_InputLowEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputRiseEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputFallEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputHighEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_InputLowAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputRiseAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputFallAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_InputHighAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_OutputLowOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputRiseOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputFallOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputHighOrMatchEvent =
-        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_OutputLowEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputRiseEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputFallEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputHighEvent =
-        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-
-    kSCTIMER_OutputLowAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputRiseAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputFallAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
-    kSCTIMER_OutputHighAndMatchEvent =
-        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT)
-} sctimer_event_t;
-
-/*! @brief SCTimer callback typedef. */
-typedef void (*sctimer_event_callback_t)(void);
-
-/*! @brief List of SCTimer interrupts */
-typedef enum _sctimer_interrupt_enable
-{
-    kSCTIMER_Event0InterruptEnable = (1U << 0),   /*!< Event 0 interrupt */
-    kSCTIMER_Event1InterruptEnable = (1U << 1),   /*!< Event 1 interrupt */
-    kSCTIMER_Event2InterruptEnable = (1U << 2),   /*!< Event 2 interrupt */
-    kSCTIMER_Event3InterruptEnable = (1U << 3),   /*!< Event 3 interrupt */
-    kSCTIMER_Event4InterruptEnable = (1U << 4),   /*!< Event 4 interrupt */
-    kSCTIMER_Event5InterruptEnable = (1U << 5),   /*!< Event 5 interrupt */
-    kSCTIMER_Event6InterruptEnable = (1U << 6),   /*!< Event 6 interrupt */
-    kSCTIMER_Event7InterruptEnable = (1U << 7),   /*!< Event 7 interrupt */
-    kSCTIMER_Event8InterruptEnable = (1U << 8),   /*!< Event 8 interrupt */
-    kSCTIMER_Event9InterruptEnable = (1U << 9),   /*!< Event 9 interrupt */
-    kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */
-    kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */
-    kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */
-} sctimer_interrupt_enable_t;
-
-/*! @brief List of SCTimer flags */
-typedef enum _sctimer_status_flags
-{
-    kSCTIMER_Event0Flag = (1U << 0),   /*!< Event 0 Flag */
-    kSCTIMER_Event1Flag = (1U << 1),   /*!< Event 1 Flag */
-    kSCTIMER_Event2Flag = (1U << 2),   /*!< Event 2 Flag */
-    kSCTIMER_Event3Flag = (1U << 3),   /*!< Event 3 Flag */
-    kSCTIMER_Event4Flag = (1U << 4),   /*!< Event 4 Flag */
-    kSCTIMER_Event5Flag = (1U << 5),   /*!< Event 5 Flag */
-    kSCTIMER_Event6Flag = (1U << 6),   /*!< Event 6 Flag */
-    kSCTIMER_Event7Flag = (1U << 7),   /*!< Event 7 Flag */
-    kSCTIMER_Event8Flag = (1U << 8),   /*!< Event 8 Flag */
-    kSCTIMER_Event9Flag = (1U << 9),   /*!< Event 9 Flag */
-    kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */
-    kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */
-    kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */
-    kSCTIMER_BusErrorLFlag =
-        (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */
-    kSCTIMER_BusErrorHFlag =
-        (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */
-} sctimer_status_flags_t;
-
-/*!
- * @brief SCTimer configuration structure
- *
- * This structure holds the configuration settings for the SCTimer peripheral. To initialize this
- * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a
- * pointer to the configuration structure instance.
- *
- * The configuration structure can be made constant so as to reside in flash.
- */
-typedef struct _sctimer_config
-{
-    bool enableCounterUnify;            /*!< true: SCT operates as a unified 32-bit counter;
-                                             false: SCT operates as two 16-bit counters */
-    sctimer_clock_mode_t clockMode;     /*!< SCT clock mode value */
-    sctimer_clock_select_t clockSelect; /*!< SCT clock select value */
-    bool enableBidirection_l;           /*!< true: Up-down count mode for the L or unified counter
-                                             false: Up count mode only for the L or unified counter */
-    bool enableBidirection_h;           /*!< true: Up-down count mode for the H or unified counter
-                                             false: Up count mode only for the H or unified counter.
-                                             This field is used only if the enableCounterUnify is set
-                                             to false */
-    uint8_t prescale_l;                 /*!< Prescale value to produce the L or unified counter clock */
-    uint8_t prescale_h;                 /*!< Prescale value to produce the H counter clock.
-                                             This field is used only if the enableCounterUnify is set
-                                             to false */
-    uint8_t outInitState;               /*!< Defines the initial output value */
-} sctimer_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Ungates the SCTimer clock and configures the peripheral for basic operation.
- *
- * @note This API should be called at the beginning of the application using the SCTimer driver.
- *
- * @param base   SCTimer peripheral base address
- * @param config Pointer to the user configuration structure.
- *
- * @return kStatus_Success indicates success; Else indicates failure.
- */
-status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config);
-
-/*!
- * @brief Gates the SCTimer clock.
- *
- * @param base SCTimer peripheral base address
- */
-void SCTIMER_Deinit(SCT_Type *base);
-
-/*!
- * @brief  Fills in the SCTimer configuration structure with the default settings.
- *
- * The default values are:
- * @code
- *  config->enableCounterUnify = true;
- *  config->clockMode = kSCTIMER_System_ClockMode;
- *  config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
- *  config->enableBidirection_l = false;
- *  config->enableBidirection_h = false;
- *  config->prescale_l = 0;
- *  config->prescale_h = 0;
- *  config->outInitState = 0;
- * @endcode
- * @param config Pointer to the user configuration structure.
- */
-void SCTIMER_GetDefaultConfig(sctimer_config_t *config);
-
-/*! @}*/
-
-/*!
- * @name PWM setup operations
- * @{
- */
-
-/*!
- * @brief Configures the PWM signal parameters.
- *
- * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
- * function will create 2 events; one of the events will trigger on match with the pulse value
- * and the other will trigger when the counter matches the PWM period. The PWM period event is
- * also used as a limit event to reset the counter or change direction. Both events are enabled
- * for the same state. The state number can be retrieved by calling the function
- * SCTIMER_GetCurrentStateNumber().
- * The counter is set to operate as one 32-bit counter (unify bit is set to 1).
- * The counter operates in bi-directional mode when generating a center-aligned PWM.
- *
- * @note When setting PWM output from multiple output pins, they all should use the same PWM mode
- * i.e all PWM's should be either edge-aligned or center-aligned.
- * When using this API, the PWM signal frequency of all the initialized channels must be the same.
- * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the 
- * API's pwmFreq_Hz.
- *
- * @param base        SCTimer peripheral base address
- * @param pwmParams   PWM parameters to configure the output
- * @param mode        PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
- * @param pwmFreq_Hz  PWM signal frequency in Hz
- * @param srcClock_Hz SCTimer counter clock in Hz
- * @param event       Pointer to a variable where the PWM period event number is stored
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If we have hit the limit in terms of number of events created or if
- *                      an incorrect PWM dutycylce is passed in.
- */
-status_t SCTIMER_SetupPwm(SCT_Type *base,
-                          const sctimer_pwm_signal_param_t *pwmParams,
-                          sctimer_pwm_mode_t mode,
-                          uint32_t pwmFreq_Hz,
-                          uint32_t srcClock_Hz,
-                          uint32_t *event);
-
-/*!
- * @brief Updates the duty cycle of an active PWM signal.
- *
- * @param base              SCTimer peripheral base address
- * @param output            The output to configure
- * @param dutyCyclePercent  New PWM pulse width; the value should be between 1 to 100
- * @param event             Event number associated with this PWM signal. This was returned to the user by the
- *                          function SCTIMER_SetupPwm().
- */
-void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event);
-
-/*!
- * @name Interrupt Interface
- * @{
- */
-
-/*!
- * @brief Enables the selected SCTimer interrupts.
- *
- * @param base SCTimer peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::sctimer_interrupt_enable_t
- */
-static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask)
-{
-    base->EVEN |= mask;
-}
-
-/*!
- * @brief Disables the selected SCTimer interrupts.
- *
- * @param base SCTimer peripheral base address
- * @param mask The interrupts to enable. This is a logical OR of members of the
- *             enumeration ::sctimer_interrupt_enable_t
- */
-static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask)
-{
-    base->EVEN &= ~mask;
-}
-
-/*!
- * @brief Gets the enabled SCTimer interrupts.
- *
- * @param base SCTimer peripheral base address
- *
- * @return The enabled interrupts. This is the logical OR of members of the
- *         enumeration ::sctimer_interrupt_enable_t
- */
-static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base)
-{
-    return (base->EVEN & 0xFFFFU);
-}
-
-/*! @}*/
-
-/*!
- * @name Status Interface
- * @{
- */
-
-/*!
- * @brief Gets the SCTimer status flags.
- *
- * @param base SCTimer peripheral base address
- *
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::sctimer_status_flags_t
- */
-static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base)
-{
-    uint32_t statusFlags = 0;
-
-    /* Add the recorded events */
-    statusFlags = (base->EVFLAG & 0xFFFFU);
-
-    /* Add bus error flags */
-    statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
-
-    return statusFlags;
-}
-
-/*!
- * @brief Clears the SCTimer status flags.
- *
- * @param base SCTimer peripheral base address
- * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::sctimer_status_flags_t
- */
-static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask)
-{
-    /* Write to the flag registers */
-    base->EVFLAG = (mask & 0xFFFFU);
-    base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
-}
-
-/*! @}*/
-
-/*!
- * @name Counter Start and Stop
- * @{
- */
-
-/*!
- * @brief Starts the SCTimer counter.
- *
- * @param base           SCTimer peripheral base address
- * @param countertoStart SCTimer counter to start; if unify mode is set then function always
- *                       writes to HALT_L bit
- */
-static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart)
-{
-    /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L))
-    {
-        base->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
-    }
-    else
-    {
-        /* Start H counter */
-        base->CTRL &= ~(SCT_CTRL_HALT_H_MASK);
-    }
-}
-
-/*!
- * @brief Halts the SCTimer counter.
- *
- * @param base          SCTimer peripheral base address
- * @param countertoStop SCTimer counter to stop; if unify mode is set then function always
- *                      writes to HALT_L bit
- */
-static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop)
-{
-    /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L))
-    {
-        base->CTRL |= (SCT_CTRL_HALT_L_MASK);
-    }
-    else
-    {
-        /* Stop H counter */
-        base->CTRL |= (SCT_CTRL_HALT_H_MASK);
-    }
-}
-
-/*! @}*/
-
-/*!
- * @name Functions to create a new event and manage the state logic
- * @{
- */
-
-/*!
- * @brief Create an event that is triggered on a match or IO and schedule in current state.
- *
- * This function will configure an event using the options provided by the user. If the event type uses
- * the counter match, then the function will set the user provided match value into a match register
- * and put this match register number into the event control register.
- * The event is enabled for the current state and the event number is increased by one at the end.
- * The function returns the event number; this event number can be used to configure actions to be
- * done when this event is triggered.
- *
- * @param base         SCTimer peripheral base address
- * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
- * @param matchValue   The match value that will be programmed to a match register
- * @param whichIO      The input or output that will be involved in event triggering. This field
- *                     is ignored if the event type is "match only"
- * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                     field has no meaning as we have only 1 unified counter; hence ignored.
- * @param event        Pointer to a variable where the new event number is stored
- *
- * @return kStatus_Success on success
- *         kStatus_Error if we have hit the limit in terms of number of events created or
-                         if we have reached the limit in terms of number of match registers
- */
-status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
-                                        sctimer_event_t howToMonitor,
-                                        uint32_t matchValue,
-                                        uint32_t whichIO,
-                                        sctimer_counter_t whichCounter,
-                                        uint32_t *event);
-
-/*!
- * @brief Enable an event in the current state.
- *
- * This function will allow the event passed in to trigger in the current state. The event must
- * be created earlier by either calling the function SCTIMER_SetupPwm() or function
- * SCTIMER_CreateAndScheduleEvent() .
- *
- * @param base  SCTimer peripheral base address
- * @param event Event number to enable in the current state
- *
- */
-void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event);
-
-/*!
- * @brief Increase the state by 1
- *
- * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
- * state.
- *
- * @param base  SCTimer peripheral base address
- *
- * @return kStatus_Success on success
- *         kStatus_Error if we have hit the limit in terms of states used
-
- */
-status_t SCTIMER_IncreaseState(SCT_Type *base);
-
-/*!
- * @brief Provides the current state
- *
- * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
- *
- * @param base SCTimer peripheral base address
- *
- * @return The current state
- */
-uint32_t SCTIMER_GetCurrentState(SCT_Type *base);
-
-/*! @}*/
-
-/*!
- * @name Actions to take in response to an event
- * @{
- */
-
-/*!
- * @brief Setup capture of the counter value on trigger of a selected event
- *
- * @param base            SCTimer peripheral base address
- * @param whichCounter    SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                        field has no meaning as only the Counter_L bits are used.
- * @param captureRegister Pointer to a variable where the capture register number will be returned. User
- *                        can read the captured value from this register when the specified event is triggered.
- * @param event           Event number that will trigger the capture
- *
- * @return kStatus_Success on success
- *         kStatus_Error if we have hit the limit in terms of number of match/capture registers available
- */
-status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
-                                    sctimer_counter_t whichCounter,
-                                    uint32_t *captureRegister,
-                                    uint32_t event);
-
-/*!
- * @brief Receive noticification when the event trigger an interrupt.
- *
- * If the interrupt for the event is enabled by the user, then a callback can be registered
- * which will be invoked when the event is triggered
- *
- * @param base     SCTimer peripheral base address
- * @param event    Event number that will trigger the interrupt
- * @param callback Function to invoke when the event is triggered
- */
-
-void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event);
-
-/*!
- * @brief Transition to the specified state.
- *
- * This transition will be triggered by the event number that is passed in by the user.
- *
- * @param base      SCTimer peripheral base address
- * @param nextState The next state SCTimer will transition to
- * @param event     Event number that will trigger the state transition
- */
-static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event)
-{
-    uint32_t reg = base->EVENT[event].CTRL;
-
-    reg &= ~(SCT_EVENT_CTRL_STATEV_MASK);
-    /* Load the STATEV value when the event occurs to be the next state */
-    reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK;
-
-    base->EVENT[event].CTRL = reg;
-}
-
-/*!
- * @brief Set the Output.
- *
- * This output will be set when the event number that is passed in by the user is triggered.
- *
- * @param base    SCTimer peripheral base address
- * @param whichIO The output to set
- * @param event   Event number that will trigger the output change
- */
-static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
-{
-    base->OUT[whichIO].SET |= (1U << event);
-}
-
-/*!
- * @brief Clear the Output.
- *
- * This output will be cleared when the event number that is passed in by the user is triggered.
- *
- * @param base    SCTimer peripheral base address
- * @param whichIO The output to clear
- * @param event   Event number that will trigger the output change
- */
-static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
-{
-    base->OUT[whichIO].CLR |= (1U << event);
-}
-
-/*!
- * @brief Toggle the output level.
- *
- * This change in the output level is triggered by the event number that is passed in by the user.
- *
- * @param base    SCTimer peripheral base address
- * @param whichIO The output to toggle
- * @param event   Event number that will trigger the output change
- */
-void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event);
-
-/*!
- * @brief Limit the running counter.
- *
- * The counter is limited when the event number that is passed in by the user is triggered.
- *
- * @param base         SCTimer peripheral base address
- * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                     field has no meaning as only the Counter_L bits are used.
- * @param event        Event number that will trigger the counter to be limited
- */
-static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
-{
-    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-    {
-        base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event);
-    }
-    else
-    {
-        base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event);
-    }
-}
-
-/*!
- * @brief Stop the running counter.
- *
- * The counter is stopped when the event number that is passed in by the user is triggered.
- *
- * @param base         SCTimer peripheral base address
- * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                     field has no meaning as only the Counter_L bits are used.
- * @param event        Event number that will trigger the counter to be stopped
- */
-static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
-{
-    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-    {
-        base->STOP |= SCT_STOP_STOPMSK_L(1U << event);
-    }
-    else
-    {
-        base->STOP |= SCT_STOP_STOPMSK_H(1U << event);
-    }
-}
-
-/*!
- * @brief Re-start the stopped counter.
- *
- * The counter will re-start when the event number that is passed in by the user is triggered.
- *
- * @param base         SCTimer peripheral base address
- * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                     field has no meaning as only the Counter_L bits are used.
- * @param event        Event number that will trigger the counter to re-start
- */
-static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
-{
-    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-    {
-        base->START |= SCT_START_STARTMSK_L(1U << event);
-    }
-    else
-    {
-        base->START |= SCT_START_STARTMSK_H(1U << event);
-    }
-}
-
-/*!
- * @brief Halt the running counter.
- *
- * The counter is disabled (halted) when the event number that is passed in by the user is
- * triggered. When the counter is halted, all further events are disabled. The HALT condition
- * can only be removed by calling the SCTIMER_StartTimer() function.
- *
- * @param base         SCTimer peripheral base address
- * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
- *                     field has no meaning as only the Counter_L bits are used.
- * @param event        Event number that will trigger the counter to be halted
- */
-static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
-{
-    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
-    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
-    {
-        base->HALT |= SCT_HALT_HALTMSK_L(1U << event);
-    }
-    else
-    {
-        base->HALT |= SCT_HALT_HALTMSK_H(1U << event);
-    }
-}
-
-/*!
- * @brief Generate a DMA request.
- *
- * DMA request will be triggered by the event number that is passed in by the user.
- *
- * @param base      SCTimer peripheral base address
- * @param dmaNumber The DMA request to generate
- * @param event     Event number that will trigger the DMA request
- */
-static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event)
-{
-    if (dmaNumber == 0)
-    {
-        base->DMA0REQUEST |= (1U << event);
-    }
-    else
-    {
-        base->DMA1REQUEST |= (1U << event);
-    }
-}
-
-/*!
- * @brief SCTimer interrupt handler.
- *
- * @param base SCTimer peripheral base address.
- */
-void SCTIMER_EventHandleIRQ(SCT_Type *base);
-
-/*! @}*/
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_SCTIMER_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1293 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_sdif.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Typedef for interrupt handler. */
-typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle);
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Get the instance.
- *
- * @param base SDIF peripheral base address.
- * @return Instance number.
- */
-static uint32_t SDIF_GetInstance(SDIF_Type *base);
-
-/*
-* @brief config the SDIF interface before transfer between the card and host
-* @param SDIF base address
-* @param transfer config structure
-*/
-static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer);
-
-/*
-* @brief wait the command done function and check error status
-* @param SDIF base address
-* @param command config structure
-*/
-static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command);
-
-/*
-* @brief transfer data in a blocking way
-* @param SDIF base address
-* @param data config structure
-* @param indicate current transfer mode:DMA or polling
-*/
-static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA);
-
-/*
-* @brief read the command response
-* @param SDIF base address
-* @param sdif command pointer
-*/
-static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command);
-
-/*
-* @brief handle transfer command interrupt
-* @param SDIF base address
-* @param sdif handle
-* @param interrupt mask flags
-*/
-static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
-
-/*
-* @brief handle transfer data interrupt
-* @param SDIF base address
-* @param sdif handle
-* @param interrupt mask flags
-*/
-static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
-
-/*
-* @brief handle DMA transfer
-* @param SDIF base address
-* @param sdif handle
-* @param interrupt mask flag
-*/
-static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
-
-/*
-* @brief driver IRQ handler
-* @param SDIF base address
-* @param sdif handle
-*/
-static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle);
-
-/*
-* @brief read data port
-* @param SDIF base address
-* @param sdif data
-* @param the number of data been transferred
-*/
-static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
-
-/*
-* @brief write data port
-* @param SDIF base address
-* @param sdif data
-* @param the number of data been transferred
-*/
-static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
-
-/*
-* @brief read data by blocking way
-* @param SDIF base address
-* @param sdif data
-*/
-static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
-
-/*
-* @brief write data by blocking way
-* @param SDIF base address
-* @param sdif data
-*/
-static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
-
-/*
-* @brief handle sdio interrupt
-* This function will call the SDIO interrupt callback
-* @param SDIF handle
-*/
-static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief SDIF internal handle pointer array */
-static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT];
-
-/*! @brief SDIF base pointer array */
-static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS;
-
-/*! @brief SDIF IRQ name array */
-static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS;
-
-/* SDIF ISR for transactional APIs. */
-static sdif_isr_t s_sdifIsr;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t SDIF_GetInstance(SDIF_Type *base)
-{
-    uint8_t instance = 0U;
-
-    while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base))
-    {
-        instance++;
-    }
-
-    assert(instance < ARRAY_SIZE(s_sdifBase));
-
-    return instance;
-}
-
-static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer)
-{
-    sdif_command_t *command = transfer->command;
-    sdif_data_t *data = transfer->data;
-
-    if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK)))
-    {
-        return kStatue_SDIF_InvalidArgument;
-    }
-
-    if (data != NULL)
-    {
-        /* config the block size register ,the block size maybe smaller than FIFO
-         depth, will test on the board */
-        base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize);
-        /* config the byte count register */
-        base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount);
-
-        command->flags |= kSDIF_DataExpect; /* need transfer data flag */
-
-        if (data->txData != NULL)
-        {
-            command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */
-        }
-        else
-        {
-            /* config the card read threshold,enable the card read threshold */
-            if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t)))
-            {
-                base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize);
-            }
-            else
-            {
-                base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK;
-            }
-        }
-
-        if (data->streamTransfer)
-        {
-            command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer  */
-        }
-
-        if ((data->enableAutoCommand12) &&
-            (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */
-        {
-            command->flags |= kSDIF_DataTransferAutoStop;
-        }
-    }
-    /* R2 response length long */
-    if (command->responseType == kCARD_ResponseTypeR2)
-    {
-        command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect);
-    }
-    else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4))
-    {
-        command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */
-    }
-    else
-    {
-        if (command->responseType != kCARD_ResponseTypeNone)
-        {
-            command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect);
-        }
-    }
-
-    if (command->type == kCARD_CommandTypeAbort)
-    {
-        command->flags |= kSDIF_TransferStopAbort;
-    }
-
-    /* wait pre-transfer complete */
-    command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg;
-
-    return kStatus_Success;
-}
-
-static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command)
-{
-    /* check if command exsit,if not, do not read the response */
-    if (NULL != command)
-    {
-        /* read reponse */
-        command->response[0U] = base->RESP[0U];
-        if (command->responseType == kCARD_ResponseTypeR2)
-        {
-            command->response[1U] = base->RESP[1U];
-            command->response[2U] = base->RESP[2U];
-            command->response[3U] = base->RESP[3U];
-        }
-
-        if ((command->responseErrorFlags != 0U) &&
-            ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
-             (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5)))
-        {
-            if (((command->responseErrorFlags) & (command->response[0U])) != 0U)
-            {
-                return kStatus_SDIF_ResponseError;
-            }
-        }
-    }
-
-    return kStatus_Success;
-}
-
-static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command)
-{
-    uint32_t status = 0U;
-
-    do
-    {
-        status = SDIF_GetInterruptStatus(base);
-        if ((status &
-             (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u)
-        {
-            SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError |
-                                                      kSDIF_ResponseTimeout | kSDIF_HardwareLockError));
-            return kStatus_SDIF_SendCmdFail;
-        }
-    } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone);
-
-    /* clear the command done bit */
-    SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone);
-
-    return SDIF_ReadCommandResponse(base, command);
-}
-
-status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig)
-{
-    assert(NULL != dmaConfig);
-    assert(NULL != dmaConfig->dmaDesBufferStartAddr);
-
-    sdif_dma_descriptor_t *dmaDesAddr;
-    uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr;
-    uint32_t dmaDesBufferSize = 0U;
-
-    dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
-
-    /* chain descriptor mode */
-    if (dmaConfig->mode == kSDIF_ChainDMAMode)
-    {
-        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorDataBufferEnd) != kSDIF_DMADescriptorDataBufferEnd) &&
-               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
-        {
-            /* set the OWN bit */
-            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
-            dmaDesAddr++;
-            dmaDesBufferSize += sizeof(sdif_dma_descriptor_t);
-        }
-        /* if access dma des address overflow, return fail */
-        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
-        {
-            return kStatus_Fail;
-        }
-        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
-    }
-    /* dual descriptor mode */
-    else
-    {
-        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorEnd) != kSDIF_DMADescriptorEnd) &&
-               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
-        {
-            dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
-            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
-            tempDMADesBuffer += dmaConfig->dmaDesSkipLen;
-        }
-        /* if access dma des address overflow, return fail */
-        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
-        {
-            return kStatus_Fail;
-        }
-        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
-    }
-    /* reload DMA descriptor */
-    base->PLDMND = SDIF_POLL_DEMAND_VALUE;
-
-    return kStatus_Success;
-}
-
-static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
-{
-    uint32_t i;
-    uint32_t totalWords;
-    uint32_t wordsCanBeRead; /* The words can be read at this time. */
-    uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT);
-
-    if (data->blockSize % sizeof(uint32_t) != 0U)
-    {
-        data->blockSize +=
-            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
-    }
-
-    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
-
-    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
-    if (readWatermark >= totalWords)
-    {
-        wordsCanBeRead = totalWords;
-    }
-    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark,
-    transfers watermark level words. */
-    else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark))
-    {
-        wordsCanBeRead = readWatermark;
-    }
-    /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left
-    words. */
-    else
-    {
-        wordsCanBeRead = (totalWords - transferredWords);
-    }
-
-    i = 0U;
-    while (i < wordsCanBeRead)
-    {
-        data->rxData[transferredWords++] = base->FIFO[i];
-        i++;
-    }
-
-    return transferredWords;
-}
-
-static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
-{
-    uint32_t i;
-    uint32_t totalWords;
-    uint32_t wordsCanBeWrite; /* The words can be read at this time. */
-    uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT);
-
-    if (data->blockSize % sizeof(uint32_t) != 0U)
-    {
-        data->blockSize +=
-            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
-    }
-
-    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
-
-    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
-    if (writeWatermark >= totalWords)
-    {
-        wordsCanBeWrite = totalWords;
-    }
-    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark,
-    transfers watermark level words. */
-    else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark))
-    {
-        wordsCanBeWrite = writeWatermark;
-    }
-    /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers left
-    words. */
-    else
-    {
-        wordsCanBeWrite = (totalWords - transferredWords);
-    }
-
-    i = 0U;
-    while (i < wordsCanBeWrite)
-    {
-        base->FIFO[i] = data->txData[transferredWords++];
-        i++;
-    }
-
-    return transferredWords;
-}
-
-static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
-{
-    uint32_t totalWords;
-    uint32_t transferredWords = 0U;
-    status_t error = kStatus_Success;
-    uint32_t status;
-    bool transferOver = false;
-
-    if (data->blockSize % sizeof(uint32_t) != 0U)
-    {
-        data->blockSize +=
-            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
-    }
-
-    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
-
-    while ((transferredWords < totalWords) && (error == kStatus_Success))
-    {
-        /* wait data transfer complete or reach RX watermark */
-        do
-        {
-            status = SDIF_GetInterruptStatus(base);
-            if (status & kSDIF_DataTransferError)
-            {
-                if (!(data->enableIgnoreError))
-                {
-                    error = kStatus_Fail;
-                }
-            }
-        } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver));
-
-        if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver)
-        {
-            transferOver = true;
-        }
-
-        if (error == kStatus_Success)
-        {
-            transferredWords = SDIF_ReadDataPort(base, data, transferredWords);
-        }
-
-        /* clear interrupt status */
-        SDIF_ClearInterruptStatus(base, status);
-    }
-
-    return error;
-}
-
-static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
-{
-    uint32_t totalWords;
-    uint32_t transferredWords = 0U;
-    status_t error = kStatus_Success;
-    uint32_t status;
-
-    if (data->blockSize % sizeof(uint32_t) != 0U)
-    {
-        data->blockSize +=
-            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
-    }
-
-    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
-
-    while ((transferredWords < totalWords) && (error == kStatus_Success))
-    {
-        /* wait data transfer complete or reach RX watermark */
-        do
-        {
-            status = SDIF_GetInterruptStatus(base);
-            if (status & kSDIF_DataTransferError)
-            {
-                if (!(data->enableIgnoreError))
-                {
-                    error = kStatus_Fail;
-                }
-            }
-        } while ((status & kSDIF_WriteFIFORequest) == 0U);
-
-        if (error == kStatus_Success)
-        {
-            transferredWords = SDIF_WriteDataPort(base, data, transferredWords);
-        }
-
-        /* clear interrupt status */
-        SDIF_ClearInterruptStatus(base, status);
-    }
-
-    while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver)
-    {
-    }
-
-    if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError)
-    {
-        if (!(data->enableIgnoreError))
-        {
-            error = kStatus_Fail;
-        }
-    }
-    SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError));
-
-    return error;
-}
-
-bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout)
-{
-    base->CTRL |= mask;
-
-    /* check software DMA reset here for DMA reset also need to check this bit */
-    while ((base->CTRL & mask) != 0U)
-    {
-        if (!timeout)
-        {
-            break;
-        }
-        timeout--;
-    }
-
-    return timeout ? true : false;
-}
-
-static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA)
-{
-    assert(NULL != data);
-
-    uint32_t dmaStatus = 0U;
-    status_t error = kStatus_Success;
-
-    /* in DMA mode, only need to wait the complete flag and check error */
-    if (isDMA)
-    {
-        do
-        {
-            dmaStatus = SDIF_GetInternalDMAStatus(base);
-            if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError)
-            {
-                SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary);
-                error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */
-            }
-            /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */
-            if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary)
-            {
-                SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary);
-                if (!(data->enableIgnoreError))
-                {
-                    error = kStatus_SDIF_DataTransferFail;
-                }
-
-                /* if error occur, then return */
-                break;
-            }
-        } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U);
-
-        /* clear the corresponding status bit */
-        SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor |
-                                           kSDIF_NormalInterruptSummary));
-
-        SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base));
-    }
-    else
-    {
-        if (data->rxData != NULL)
-        {
-            error = SDIF_ReadDataPortBlocking(base, data);
-        }
-        else
-        {
-            error = SDIF_WriteDataPortBlocking(base, data);
-        }
-    }
-
-    return error;
-}
-
-status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout)
-{
-    assert(NULL != cmd);
-
-    base->CMDARG = cmd->argument;
-    base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK));
-
-    /* wait start_cmd bit auto clear within timeout */
-    while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK)
-    {
-        if (!timeout)
-        {
-            break;
-        }
-
-        --timeout;
-    }
-
-    return timeout ? kStatus_Success : kStatus_Fail;
-}
-
-bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout)
-{
-    bool enINT = false;
-    sdif_command_t command;
-
-    memset(&command, 0U, sizeof(sdif_command_t));
-
-    /* add for confict with interrupt mode,close the interrupt temporary */
-    if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK)
-    {
-        enINT = true;
-        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
-    }
-
-    command.flags = SDIF_CMD_SEND_INITIALIZATION_MASK;
-
-    if (SDIF_SendCommand(base, &command, timeout) == kStatus_Fail)
-    {
-        return false;
-    }
-
-    /* wait command done */
-    while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone)
-    {
-    }
-
-    /* clear status */
-    SDIF_ClearInterruptStatus(base, kSDIF_CommandDone);
-
-    /* add for confict with interrupt mode */
-    if (enINT)
-    {
-        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
-    }
-
-    return true;
-}
-
-void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider)
-{
-    /*config the clock delay and pharse shift
-     *should config the clk_in_drv,
-     *clk_in_sample to meet the min hold and
-     *setup time
-     */
-    if (target_HZ <= kSDIF_Freq400KHZ)
-    {
-        /*min hold time:5ns
-        * min setup time: 5ns
-        * delay = (x+1)*250ps
-        */
-        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY);
-    }
-    else if (target_HZ >= kSDIF_Freq50MHZ)
-    {
-        /*
-        * user need to pay attention to this parameter
-        * can be change the setting for you card and board
-        * min hold time:2ns
-        * min setup time: 6ns
-        * delay = (x+1)*250ps
-        */
-        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY);
-        /* means the input clock = 2 * card clock,
-        * can use clock pharse shift tech
-        */
-        if (divider == 1U)
-        {
-            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
-                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
-                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180);
-        }
-    }
-    else
-    {
-        /*
-        * user need to pay attention to this parameter
-        * can be change the setting for you card and board
-        * min hold time:5ns
-        * min setup time: 5ns
-        * delay = (x+1)*250ps
-        */
-        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
-                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY);
-        /* means the input clock = 2 * card clock,
-        * can use clock pharse shift tech
-        */
-        if (divider == 1U)
-        {
-            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
-                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
-                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90);
-        }
-    }
-}
-
-uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ)
-{
-    assert(srcClock_Hz <= FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK);
-
-    sdif_command_t cmd = {0U};
-    uint32_t divider = 0U, targetFreq = target_HZ;
-
-    /* if target freq bigger than the source clk, set the target_HZ to
-     src clk, this interface can run up to 52MHZ with card */
-    if (srcClock_Hz < targetFreq)
-    {
-        targetFreq = srcClock_Hz;
-    }
-
-    /* disable the clock first,need sync to CIU*/
-    SDIF_EnableCardClock(base, false);
-
-    /* update the clock register and wait the pre-transfer complete */
-    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
-    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
-
-    /*calucate the divider*/
-    if (targetFreq != srcClock_Hz)
-    {
-        divider = (srcClock_Hz / targetFreq + 1U) / 2U;
-    }
-    /* load the clock divider */
-    base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider);
-
-    /* update the divider to CIU */
-    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
-    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
-
-    /* enable the card clock and sync to CIU */
-    SDIF_EnableCardClock(base, true);
-    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
-
-    /* config the clock delay to meet the hold time and setup time */
-    SDIF_ConfigClockDelay(target_HZ, divider);
-
-    /* return the actual card clock freq */
-
-    return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz;
-}
-
-bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout)
-{
-    /* assert this bit to reset the data machine to abort the read data */
-    base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK;
-    /* polling the bit self clear */
-    while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK)
-    {
-        if (!timeout)
-        {
-            break;
-        }
-        timeout--;
-    }
-
-    return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true;
-}
-
-status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize)
-{
-    assert(NULL != config);
-    assert(NULL != data);
-
-    uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U;
-    uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr;
-    const uint32_t *dataBuffer = data;
-    sdif_dma_descriptor_t *descriptorPoniter = NULL;
-    uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode);
-
-    /* check the dma descriptor buffer length , it is user's responsibility to make sure the DMA descriptor table
-    size is bigger enough to hold the transfer descriptor */
-    if (config->dmaDesBufferLen * sizeof(uint32_t) < sizeof(sdif_dma_descriptor_t))
-    {
-        return kStatus_SDIF_DescriptorBufferLenError;
-    }
-
-    /* check the read/write data size,must be a multiple of 4 */
-    if (dataSize % sizeof(uint32_t) != 0U)
-    {
-        dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t));
-    }
-
-    /*config the bus mode*/
-    if (config->enableFixBurstLen)
-    {
-        base->BMOD |= SDIF_BMOD_FB_MASK;
-    }
-
-    /* calucate the dma descriptor entry due to DMA buffer size limit */
-    /* if datasize smaller than one descriptor buffer size */
-    if (dataSize > maxDMABuffer)
-    {
-        dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U);
-    }
-    else /* need one dma descriptor */
-    {
-        dmaEntry = 1U;
-    }
-
-    /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor
-    table
-    size is bigger enough to hold the transfer descriptor */
-    if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen))
-    {
-        return kStatus_SDIF_DescriptorBufferLenError;
-    }
-
-    switch (config->mode)
-    {
-        case kSDIF_DualDMAMode:
-            base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */
-            for (i = 0U; i < dmaEntry; i++)
-            {
-                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
-                {
-                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
-                    dataSize -= dmaBufferSize;
-                    dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ?
-                                         FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE :
-                                         dataSize;
-                    dataSize -= dmaBuffer1Size;
-                }
-                else
-                {
-                    dmaBufferSize = dataSize;
-                    dmaBuffer1Size = 0U;
-                }
-
-                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
-                if (i == 0U)
-                {
-                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
-                }
-                descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA | kSDIF_DisableCompleteInterrupt;
-                descriptorPoniter->dmaDataBufferSize =
-                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size);
-
-                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
-                descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t);
-                dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t);
-
-                /* descriptor skip length */
-                tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t);
-            }
-            /* enable the completion interrupt when reach the last descriptor */
-            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
-            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd | kSDIF_DMADescriptorEnd;
-            break;
-
-        case kSDIF_ChainDMAMode:
-            for (i = 0U; i < dmaEntry; i++)
-            {
-                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
-                {
-                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
-                    dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
-                }
-                else
-                {
-                    dmaBufferSize = dataSize;
-                }
-
-                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
-                if (i == 0U)
-                {
-                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
-                }
-                descriptorPoniter->dmaDesAttribute |=
-                    kSDIF_DMADescriptorOwnByDMA | kSDIF_DMASecondAddrChained | kSDIF_DisableCompleteInterrupt;
-                descriptorPoniter->dmaDataBufferSize =
-                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/
-                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
-                dataBuffer += dmaBufferSize / sizeof(uint32_t);
-                tempDMADesBuffer +=
-                    sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calucate the next descriptor address */
-                /* this descriptor buffer2 pointer to the next descriptor address */
-                descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer;
-            }
-            /* enable the completion interrupt when reach the last descriptor */
-            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
-            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd;
-            break;
-
-        default:
-            break;
-    }
-
-    /* use internal DMA interface */
-    base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK;
-    /* enable the internal SD/MMC DMA */
-    base->BMOD |= SDIF_BMOD_DE_MASK;
-    /* enable DMA status check */
-    base->IDINTEN |= kSDIF_DMAAllStatus;
-    /* clear write/read FIFO request interrupt in DMA mode, DMA will handle the data transfer*/
-    SDIF_DisableInterrupt(base, kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | kSDIF_DataTransferOver);
-    /* load DMA descriptor buffer address */
-    base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr;
-
-    return kStatus_Success;
-}
-
-void SDIF_Init(SDIF_Type *base, sdif_config_t *config)
-{
-    assert(NULL != config);
-
-    uint32_t timeout;
-
-    /* enable SDIF clock */
-    CLOCK_EnableClock(kCLOCK_Sdio);
-
-    /* do software reset */
-    base->BMOD |= SDIF_BMOD_SWR_MASK;
-
-    /* reset all */
-    SDIF_Reset(base, kSDIF_ResetAll, SDIF_TIMEOUT_VALUE);
-
-    /*config timeout register */
-    timeout = base->TMOUT;
-    timeout &= ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK);
-    timeout |= SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout);
-
-    base->TMOUT = timeout;
-
-    /* config the card detect debounce clock count */
-    base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock);
-
-    /*config the watermark/burst transfer value */
-    base->FIFOTH =
-        SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U);
-
-    /* enable the interrupt status  */
-    SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus);
-
-    /* clear all interrupt/DMA status */
-    SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus);
-    SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus);
-}
-
-status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer)
-{
-    assert(NULL != transfer);
-
-    bool isDMA = false;
-    sdif_data_t *data = transfer->data;
-
-    /* config the transfer parameter */
-    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
-    {
-        return kStatue_SDIF_InvalidArgument;
-    }
-
-    /* if need transfer data in dma mode, config the DMA descriptor first */
-    if ((data != NULL) && (dmaConfig != NULL))
-    {
-        /* use internal DMA mode to transfer between the card and host*/
-        isDMA = true;
-
-        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
-                                   data->blockSize * data->blockCount) != kStatus_Success)
-        {
-            return kStatus_SDIF_DescriptorBufferLenError;
-        }
-    }
-
-    /* send command first */
-    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
-    {
-        return kStatus_SDIF_SyncCmdTimeout;
-    }
-
-    /* wait the command transfer done and check if error occurs */
-    if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success)
-    {
-        return kStatus_SDIF_SendCmdFail;
-    }
-
-    /* if use DMA transfer mode ,check the corresponding status bit */
-    if (data != NULL)
-    {
-        /* check the if has DMA descriptor featch error */
-        if (isDMA &&
-            ((SDIF_GetInternalDMAStatus(base) & kSDIF_DMADescriptorUnavailable) == kSDIF_DMADescriptorUnavailable))
-        {
-            SDIF_ClearInternalDMAStatus(base, kSDIF_DMADescriptorUnavailable | kSDIF_AbnormalInterruptSummary);
-
-            /* release the DMA descriptor to DMA */
-            SDIF_ReleaseDMADescriptor(base, dmaConfig);
-        }
-        /* handle data transfer */
-        if (SDIF_TransferDataBlocking(base, data, isDMA) != kStatus_Success)
-        {
-            return kStatus_SDIF_DataTransferFail;
-        }
-    }
-
-    return kStatus_Success;
-}
-
-status_t SDIF_TransferNonBlocking(SDIF_Type *base,
-                                  sdif_handle_t *handle,
-                                  sdif_dma_config_t *dmaConfig,
-                                  sdif_transfer_t *transfer)
-{
-    assert(NULL != transfer);
-
-    sdif_data_t *data = transfer->data;
-
-    /* save the data and command before transfer */
-    handle->data = transfer->data;
-    handle->command = transfer->command;
-    handle->transferredWords = 0U;
-    handle->interruptFlags = 0U;
-    handle->dmaInterruptFlags = 0U;
-
-    /* config the transfer parameter */
-    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
-    {
-        return kStatue_SDIF_InvalidArgument;
-    }
-
-    if ((data != NULL) && (dmaConfig != NULL))
-    {
-        /* use internal DMA mode to transfer between the card and host*/
-        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
-                                   data->blockSize * data->blockCount) != kStatus_Success)
-        {
-            return kStatus_SDIF_DescriptorBufferLenError;
-        }
-    }
-
-    /* send command first */
-    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
-    {
-        return kStatus_SDIF_SyncCmdTimeout;
-    }
-
-    return kStatus_Success;
-}
-
-void SDIF_TransferCreateHandle(SDIF_Type *base,
-                               sdif_handle_t *handle,
-                               sdif_transfer_callback_t *callback,
-                               void *userData)
-{
-    assert(handle);
-    assert(callback);
-
-    /* reset the handle. */
-    memset(handle, 0U, sizeof(*handle));
-
-    /* Set the callback. */
-    handle->callback.SDIOInterrupt = callback->SDIOInterrupt;
-    handle->callback.DMADesUnavailable = callback->DMADesUnavailable;
-    handle->callback.CommandReload = callback->CommandReload;
-    handle->callback.TransferComplete = callback->TransferComplete;
-
-    handle->userData = userData;
-
-    /* Save the handle in global variables to support the double weak mechanism. */
-    s_sdifHandle[SDIF_GetInstance(base)] = handle;
-
-    /* save IRQ handler */
-    s_sdifIsr = SDIF_TransferHandleIRQ;
-
-    /* enable the global interrupt */
-    SDIF_EnableGlobalInterrupt(base, true);
-
-    EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]);
-}
-
-void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability)
-{
-    assert(NULL != capability);
-
-    capability->sdVersion = SDIF_SUPPORT_SD_VERSION;
-    capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION;
-    capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK;
-    /* set the max block count = max byte conut / max block size */
-    capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK;
-    capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag |
-                        kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag;
-}
-
-static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
-{
-    assert(handle->command);
-
-    /* transfer error */
-    if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout))
-    {
-        handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData);
-    }
-    /* cmd buffer full, in this condition user need re-send the command */
-    else if (interruptFlags & kSDIF_HardwareLockError)
-    {
-        if (handle->callback.CommandReload)
-        {
-            handle->callback.CommandReload();
-        }
-    }
-    /* transfer command success */
-    else
-    {
-        SDIF_ReadCommandResponse(base, handle->command);
-        if (((handle->data) == NULL) && (handle->callback.TransferComplete))
-        {
-            handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
-        }
-    }
-}
-
-static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
-{
-    assert(handle->data);
-
-    /* data starvation by host time out, software should read/write FIFO*/
-    if (interruptFlags & kSDIF_DataStarvationByHostTimeout)
-    {
-        if (handle->data->rxData != NULL)
-        {
-            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
-        }
-        else if (handle->data->txData != NULL)
-        {
-            handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
-        }
-        else
-        {
-            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
-        }
-    }
-    /* data transfer fail */
-    else if (interruptFlags & kSDIF_DataTransferError)
-    {
-        if (!handle->data->enableIgnoreError)
-        {
-            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
-        }
-    }
-    /* need fill data to FIFO */
-    else if (interruptFlags & kSDIF_WriteFIFORequest)
-    {
-        handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
-    }
-    /* need read data from FIFO */
-    else if (interruptFlags & kSDIF_ReadFIFORequest)
-    {
-        handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
-    }
-    else
-    {
-    }
-
-    /* data transfer over */
-    if (interruptFlags & kSDIF_DataTransferOver)
-    {
-        while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U))
-        {
-            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
-        }
-        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
-    }
-}
-
-static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
-{
-    if (interruptFlags & kSDIF_DMAFatalBusError)
-    {
-        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData);
-    }
-    else if (interruptFlags & kSDIF_DMADescriptorUnavailable)
-    {
-        if (handle->callback.DMADesUnavailable)
-        {
-            handle->callback.DMADesUnavailable();
-        }
-    }
-    else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) &&
-             (!handle->data->enableIgnoreError))
-    {
-        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
-    }
-    /* card normal summary */
-    else
-    {
-        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
-    }
-}
-
-static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle)
-{
-    if (handle->callback.SDIOInterrupt != NULL)
-    {
-        handle->callback.SDIOInterrupt();
-    }
-}
-
-static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle)
-{
-    assert(handle);
-
-    uint32_t interruptFlags, dmaInterruptFlags;
-
-    interruptFlags = SDIF_GetInterruptStatus(base);
-    dmaInterruptFlags = SDIF_GetInternalDMAStatus(base);
-
-    handle->interruptFlags = interruptFlags;
-    handle->dmaInterruptFlags = dmaInterruptFlags;
-
-    if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U)
-    {
-        SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus));
-    }
-    if ((interruptFlags & kSDIF_DataTransferStatus) != 0U)
-    {
-        SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus));
-    }
-    if (interruptFlags & kSDIF_SDIOInterrupt)
-    {
-        SDIF_TransferHandleSDIOInterrupt(handle);
-    }
-    if (dmaInterruptFlags & kSDIF_DMAAllStatus)
-    {
-        SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags);
-    }
-
-    SDIF_ClearInterruptStatus(base, interruptFlags);
-    SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags);
-}
-
-void SDIF_Deinit(SDIF_Type *base)
-{
-    /* disable clock here*/
-    CLOCK_DisableClock(kCLOCK_Sdio);
-    /* disable the SDIOCLKCTRL */
-    SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
-                             SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK);
-    RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn);
-}
-
-#if defined(SDIF)
-void SDIF_DriverIRQHandler(void)
-{
-    assert(s_sdifHandle[0]);
-
-    s_sdifIsr(SDIF, s_sdifHandle[0]);
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,824 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SDIF_H_
-#define _FSL_SDIF_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup sdif
- * @{
- */
-
-/******************************************************************************
- * Definitions.
- *****************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Driver version 2.0.1. */
-#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
-/*@}*/
-
-#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */
-
-#define SDIF_SUPPORT_SD_VERSION (0x20)  /*!< define the controller support sd/sdio card version 2.0 */
-#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */
-
-#define SDIF_TIMEOUT_VALUE (65535U)    /*!< define the timeout counter */
-#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */
-
-#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU)          /*!< DMA descriptor buffer1 size */
-#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!<DMA descriptor buffer2 size */
-#define SDIF_RX_WATERMARK (15U)                                    /*!<RX water mark value */
-#define SDIF_TX_WATERMARK (16U)                                    /*!<TX water mark value */
-
-/*! @brief  SDIOCLKCTRL setting
-* below clock delay setting should meet you board layout
-* user can change it when you meet timing mismatch issue
-* such as: response error/CRC error and so on
-*/
-#define SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY (0X17U)
-#define SDIF_INDENTIFICATION_MODE_DRV_DELAY (0X17U)
-#define SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY (0x10U)
-#define SDIF_HIGHSPEED_25MHZ_DRV_DELAY (0x10U)
-#define SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY (0x1FU)
-#define SDIF_HIGHSPEED_50MHZ_DRV_DELAY (0x1FU)
-
-/*! @brief SDIF status */
-enum _sdif_status
-{
-    kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */
-    kStatue_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U),          /*!< invalid argument status */
-    kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */
-    kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U),    /* send command to card fail */
-    kStatus_SDIF_SendCmdErrorBufferFull =
-        MAKE_STATUS(kStatusGroup_SDIF, 4U), /* send command to card fail, due to command buffer full
-                                     user need to resend this command */
-    kStatus_SDIF_DMATransferFailWithFBE =
-        MAKE_STATUS(kStatusGroup_SDIF, 5U), /* DMA transfer data fail with fatal bus error ,
-                                     to do with this error :issue a hard reset/controller reset*/
-    kStatus_SDIF_DMATransferDescriptorUnavaliable = MAKE_STATUS(kStatusGroup_SDIF, 6U), /* DMA descriptor unavalible */
-    kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U),                 /* transfer data fail */
-    kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U),
-};
-
-/*! @brief Host controller capabilities flag mask */
-enum _sdif_capability_flag
-{
-    kSDIF_SupportHighSpeedFlag = 0x1U,     /*!< Support high-speed */
-    kSDIF_SupportDmaFlag = 0x2U,           /*!< Support DMA */
-    kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */
-    kSDIF_SupportV330Flag = 0x8U,          /*!< Support voltage 3.3V */
-    kSDIF_Support4BitFlag = 0x10U,         /*!< Support 4 bit mode */
-    kSDIF_Support8BitFlag = 0x20U,         /*!< Support 8 bit mode */
-};
-
-/*! @brief define the reset type */
-enum _sdif_reset_type
-{
-    kSDIF_ResetController =
-        SDIF_CTRL_CONTROLLER_RESET_MASK,                /*!< reset controller,will reset: BIU/CIU interface
-                                                          CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE
-                                                          and READ_WAIT bits of control register,START_CMD bit of the
-                                                          command register*/
-    kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK,        /*!< reset data FIFO*/
-    kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */
-
-    kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/
-                     kSDIF_ResetDMAInterface,
-};
-
-/*! @brief define the card bus width type */
-typedef enum _sdif_bus_width
-{
-    kSDIF_Bus1BitWidth = 0U,                          /*!< 1bit bus width, 1bit mode and 4bit mode
-                                                      share one register bit */
-    kSDIF_Bus4BitWidth = SDIF_CTYPE_CARD_WIDTH0_MASK, /*!< 4bit mode mask */
-    kSDIF_Bus8BitWidth = SDIF_CTYPE_CARD_WIDTH1_MASK, /*!< support 8 bit mode */
-} sdif_bus_width_t;
-
-/*! @brief define the command flags */
-enum _sdif_command_flags
-{
-    kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK,      /*!< command request response*/
-    kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK,  /*!< command response length long */
-    kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/
-    kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK,               /*!< request data transfer,ethier read/write*/
-    kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK,             /*!< data transfer direction */
-    kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK,    /*!< data transfer mode :stream/block transfer command */
-    kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */
-    kSDIF_WaitPreTransferComplete =
-        SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd  */
-    kSDIF_TransferStopAbort =
-        SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer
-                                       ,this bit should set so that cmd/data state-machines of CIU can return
-                                       to idle correctly*/
-    kSDIF_SendInitialization =
-        SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initaliztion  80 clocks for SD card after power on  */
-    kSDIF_CmdUpdateClockRegisterOnly =
-        SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK,                /*!< send cmd update the CIU clock register only */
-    kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */
-    kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK,         /*!< command expect command completion signal signal */
-    kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK,        /*!< this bit should only be set for mandatory boot mode */
-    kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */
-    kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK,      /*!< when software set this bit along with START_CMD, CIU
-                                                                terminates the boot operation*/
-    kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK,       /*!< select boot mode ,alternate or mandatory*/
-    kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK,      /*!< this bit set for CMD11 only */
-    kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK,    /*!< cmd and data send to card through the HOLD register*/
-};
-
-/*! @brief The command type */
-enum _sdif_command_type
-{
-    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
-    kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
-    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
-    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
-};
-
-/*!
- * @brief The command response type.
- *
- * Define the command response type from card to host controller.
- */
-enum _sdif_response_type
-{
-    kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
-    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
-    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
-    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
-    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
-    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
-    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
-    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
-    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
-    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
-};
-
-/*! @brief define the interrupt mask flags */
-enum _sdif_interrupt_mask
-{
-    kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK,                 /*!< mask for card detect */
-    kSDIF_ResponseError = SDIF_INTMASK_RE_MASK,                /*!< command response error */
-    kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK,               /*!< command transfer over*/
-    kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK,            /*!< data transfer over flag*/
-    kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK,           /*!< write FIFO request */
-    kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK,            /*!< read FIFO request */
-    kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK,           /*!< reponse CRC error */
-    kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK,               /*!< data CRC error */
-    kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK,             /*!< response timeout */
-    kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK,            /*!< read data timeout */
-    kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */
-    kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK,                  /*!< indicate the FIFO underrun or overrun error */
-    kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK,           /*!< hardware lock write error */
-    kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK,           /*!< start bit error */
-    kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK,                 /*!< indicate the auto command done */
-    kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK,             /*!< end bit error */
-    kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK,     /*!< interrupt from the SDIO card */
-
-    kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError |
-                                  kSDIF_ResponseTimeout |
-                                  kSDIF_HardwareLockError, /*!< command transfer status collection*/
-    kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest |
-                               kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout |
-                               kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError |
-                               kSDIF_AutoCmdDone, /*!< data transfer status collection */
-    kSDIF_DataTransferError =
-        kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout,
-    kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */
-
-};
-
-/*! @brief define the internal DMA status flags */
-enum _sdif_dma_status
-{
-    kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */
-    kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK,  /*!< DMA revieve finished for one DMA descriptor */
-    kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK,           /*!< DMA fatal bus error */
-    kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK,    /*!< DMA descriptor unavailable */
-    kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK,        /*!< card error summary */
-    kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK,     /*!< normal interrupt summary */
-    kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK,   /*!< abnormal interrupt summary*/
-
-    kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError |
-                         kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary |
-                         kSDIF_AbnormalInterruptSummary,
-
-};
-
-/*! @brief define the internal DMA descriptor flag */
-enum _sdif_dma_descriptor_flag
-{
-    kSDIF_DisableCompleteInterrupt = 0x2U,     /*!< disable the complete interrupt flag for the ends
-                                                in the buffer pointed to by this descriptor*/
-    kSDIF_DMADescriptorDataBufferEnd = 0x4U,   /*!< indicate this descriptor contain the last data buffer of data */
-    kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer
-                                                 of data,if first buffer size is 0,next descriptor contain
-                                                 the begaining of the data*/
-    kSDIF_DMASecondAddrChained = 0x10U,        /*!< indicate that the second addr in the descriptor is the
-                                               next descriptor addr not the data buffer */
-    kSDIF_DMADescriptorEnd = 0x20U,            /*!< indicate that the descriptor list reached its final descriptor*/
-    kSDIF_DMADescriptorOwnByDMA = 0x80000000U, /*!< indicate the descriptor is own by SD/MMC DMA */
-};
-
-/*! @brief define the internal DMA mode */
-typedef enum _sdif_dma_mode
-{
-    kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */
-    kSDIF_DualDMAMode = 0x02U,  /* dual mode is one descriptor with two buffer */
-} sdif_dma_mode_t;
-
-/*! @brief define the card work freq mode */
-enum _sdif_card_freq
-{
-    kSDIF_Freq50MHZ = 50000000U, /*!< 50MHZ mode*/
-    kSDIF_Freq400KHZ = 400000U,  /*!< identificatioin mode*/
-};
-
-/*! @brief define the clock pharse shift */
-enum _sdif_clock_pharse_shift
-{
-    kSDIF_ClcokPharseShift0,   /*!< clock pharse shift 0*/
-    kSDIF_ClcokPharseShift90,  /*!< clock pharse shift 90*/
-    kSDIF_ClcokPharseShift180, /*!< clock pharse shift 180*/
-    kSDIF_ClcokPharseShift270, /*!< clock pharse shift 270*/
-};
-
-/*! @brief define the internal DMA descriptor */
-typedef struct _sdif_dma_descriptor
-{
-    uint32_t dmaDesAttribute;           /*!< internal DMA attribute control and status */
-    uint32_t dmaDataBufferSize;         /*!< internal DMA transfer buffer size control */
-    const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */
-    const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */
-
-} sdif_dma_descriptor_t;
-
-/*! @brief Defines the internal DMA config structure. */
-typedef struct _sdif_dma_config
-{
-    bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will
-                             use only SINGLE, INCR4, INCR8 or INCR16 during start of
-                             normal burst transfers. When reset, the AHB will use SINGLE
-                             and INCR burst transfer operations */
-
-    sdif_dma_mode_t mode; /*!< define the DMA mode */
-
-    uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor
-                               this field is special for dual DMA mode */
-
-    uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/
-    uint32_t dmaDesBufferLen;        /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the
-                                        dma descriptor buffer length if it is bigger enough for your transfer */
-
-} sdif_dma_config_t;
-
-/*!
- * @brief Card data descriptor
- */
-typedef struct _sdif_data
-{
-    bool streamTransfer;      /*!< indicate this is a stream data transfer command */
-    bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */
-    bool enableIgnoreError;   /*!< indicate if enable ignore error when transfer data */
-
-    size_t blockSize;       /*!< Block size, take care when config this parameter */
-    uint32_t blockCount;    /*!< Block count */
-    uint32_t *rxData;       /*!< data buffer to recieve */
-    const uint32_t *txData; /*!< data buffer to transfer */
-} sdif_data_t;
-
-/*!
- * @brief Card command descriptor
- *
- * Define card command-related attribute.
- */
-typedef struct _sdif_command
-{
-    uint32_t index;              /*!< Command index */
-    uint32_t argument;           /*!< Command argument */
-    uint32_t response[4U];       /*!< Response for this command */
-    uint32_t type;               /*!< define the command type */
-    uint32_t responseType;       /*!< Command response type */
-    uint32_t flags;              /*!< Cmd flags */
-    uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when
-                                    recieve the cmd response */
-} sdif_command_t;
-
-/*! @brief Transfer state */
-typedef struct _sdif_transfer
-{
-    sdif_data_t *data;       /*!< Data to transfer */
-    sdif_command_t *command; /*!< Command to send */
-} sdif_transfer_t;
-
-/*! @brief Data structure to initialize the sdif */
-typedef struct _sdif_config
-{
-    uint8_t responseTimeout;        /*!< command reponse timeout value */
-    uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in
-                                        card detect logic,typical value is 5-25ms */
-    uint32_t endianMode;            /*!< define endian mode ,this field is not used in this
-                                    module actually, keep for compatible with middleware*/
-    uint32_t dataTimeout;           /*!< data timeout value  */
-} sdif_config_t;
-
-/*!
- * @brief SDIF capability information.
- * Defines a structure to get the capability information of SDIF.
- */
-typedef struct _sdif_capability
-{
-    uint32_t sdVersion;      /*!< support SD card/sdio version */
-    uint32_t mmcVersion;     /*!< support emmc card version */
-    uint32_t maxBlockLength; /*!< Maximum block length united as byte */
-    uint32_t maxBlockCount;  /*!< Maximum byte count can be transfered */
-    uint32_t flags;          /*!< Capability flags to indicate the support information */
-} sdif_capability_t;
-
-/*! @brief sdif callback functions. */
-typedef struct _sdif_transfer_callback
-{
-    void (*SDIOInterrupt)(void);     /*!< SDIO card interrupt occurs */
-    void (*DMADesUnavailable)(void); /*!< DMA descriptor unavailable */
-    void (*CommandReload)(void);     /*!< command buffer full,need re-load */
-    void (*TransferComplete)(SDIF_Type *base,
-                             void *handle,
-                             status_t status,
-                             void *userData); /*!< Transfer complete callback */
-} sdif_transfer_callback_t;
-
-/*!
- * @brief sdif handle
- *
- * Defines the structure to save the sdif state information and callback function. The detail interrupt status when
- * send command or transfer data can be obtained from interruptFlags field by using mask defined in
- * sdif_interrupt_flag_t;
- * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
- */
-typedef struct _sdif_handle
-{
-    /* Transfer parameter */
-    sdif_data_t *volatile data;       /*!< Data to transfer */
-    sdif_command_t *volatile command; /*!< Command to send */
-
-    /* Transfer status */
-    volatile uint32_t interruptFlags;    /*!< Interrupt flags of last transaction */
-    volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/
-    volatile uint32_t transferredWords;  /*!< Words transferred by polling way */
-
-    /* Callback functions */
-    sdif_transfer_callback_t callback; /*!< Callback function */
-    void *userData;                    /*!< Parameter for transfer complete callback */
-} sdif_handle_t;
-
-/*! @brief sdif transfer function. */
-typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content);
-
-/*! @brief sdif host descriptor */
-typedef struct _sdif_host
-{
-    SDIF_Type *base;                   /*!< sdif peripheral base address */
-    uint32_t sourceClock_Hz;           /*!< sdif source clock frequency united in Hz */
-    sdif_config_t config;              /*!< sdif configuration */
-    sdif_transfer_function_t transfer; /*!< sdif transfer function */
-    sdif_capability_t capability;      /*!< sdif capability information */
-} sdif_host_t;
-
-/*************************************************************************************************
- * API
- ************************************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief SDIF module initialization function.
- *
- * Configures the SDIF according to the user configuration.
- * @param base SDIF peripheral base address.
- * @param config SDIF configuration information.
- */
-void SDIF_Init(SDIF_Type *base, sdif_config_t *config);
-
-/*!
- * @brief SDIF module deinit function.
- * user should call this function follow with IP reset
- * @param base SDIF peripheral base address.
- */
-void SDIF_Deinit(SDIF_Type *base);
-
-/*!
- * @brief SDIF send initialize 80 clocks for SD card after initilize
- * @param base SDIF peripheral base address.
- * @param timeout value
- */
-bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout);
-
-/*!
- * @brief SDIF module detect card insert status function.
- * @param base SDIF peripheral base address.
- * @param data3 indicate use data3 as card insert detect pin
- * will return the data3 PIN status in this condition
- */
-static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
-{
-    if (data3)
-    {
-        return base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK;
-    }
-    else
-    {
-        return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK;
-    }
-}
-
-/*!
- * @brief SDIF module enable/disable card clock.
- * @param base SDIF peripheral base address.
- * @param enable/disable flag
- */
-static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK;
-    }
-    else
-    {
-        base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK;
-    }
-}
-
-/*!
- * @brief SDIF module enable/disable module disable the card clock
- * to enter low power mode when card is idle,for SDIF cards, if
- * interrupts must be detected, clock should not be stopped
- * @param base SDIF peripheral base address.
- * @param enable/disable flag
- */
-static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK;
-    }
-    else
-    {
-        base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK;
-    }
-}
-
-/*!
- * @brief Sets the card bus clock frequency.
- *
- * @param base SDIF peripheral base address.
- * @param srcClock_Hz SDIF source clock frequency united in Hz.
- * @param target_HZ card bus clock frequency united in Hz.
- * @return The nearest frequency of busClock_Hz configured to SD bus.
- */
-uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ);
-
-/*!
- * @brief reset the different block of the interface.
- * @param base SDIF peripheral base address.
- * @param mask indicate which block to reset.
- * @param timeout value,set to wait the bit self clear
- * @return reset result.
- */
-bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout);
-
-/*!
- * @brief enable/disable the card power.
- * once turn power on, software should wait for regulator/switch
- * ramp-up time before trying to initialize card.
- * @param base SDIF peripheral base address.
- * @param enable/disable flag.
- */
-static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK;
-    }
-    else
-    {
-        base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK;
-    }
-}
-
-/*!
- * @brief get the card write protect status
- * @param base SDIF peripheral base address.
- */
-static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base)
-{
-    return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK;
-}
-
-/*!
- * @brief set card data bus width
- * @param base SDIF peripheral base address.
- * @param data bus width type
- */
-static inline void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type)
-{
-    base->CTYPE = type;
-}
-
-/*!
- * @brief toggle state on hardware reset PIN
- * This is used which card has a reset PIN typically.
- * @param base SDIF peripheral base address.
- */
-static inline void SDIF_AssertHardwareReset(SDIF_Type *base)
-{
-    base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK;
-}
-
-/*!
- * @brief send command to the card
- * @param base SDIF peripheral base address.
- * @param command configuration collection
- * @param timeout value
- * @return command excute status
- */
-status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout);
-
-/*!
- * @brief SDIF enable/disable global interrupt
- * @param base SDIF peripheral base address.
- * @param enable/disable flag
- */
-static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
-    }
-    else
-    {
-        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
-    }
-}
-
-/*!
- * @brief SDIF enable interrupt
- * @param base SDIF peripheral base address.
- * @param interrupt mask
- */
-static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask)
-{
-    base->INTMASK |= mask;
-}
-
-/*!
- * @brief SDIF disable interrupt
- * @param base SDIF peripheral base address.
- * @param interrupt mask
- */
-static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask)
-{
-    base->INTMASK &= ~mask;
-}
-
-/*!
- * @brief SDIF get interrupt status
- * @param base SDIF peripheral base address.
- */
-static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base)
-{
-    return base->MINTSTS;
-}
-
-/*!
- * @brief SDIF clear interrupt status
- * @param base SDIF peripheral base address.
- * @param status mask to clear
- */
-static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask)
-{
-    base->RINTSTS &= mask;
-}
-
-/*!
- * @brief Creates the SDIF handle.
- * register call back function for interrupt and enable the interrupt
- * @param base SDIF peripheral base address.
- * @param handle SDIF handle pointer.
- * @param callback Structure pointer to contain all callback functions.
- * @param userData Callback function parameter.
- */
-void SDIF_TransferCreateHandle(SDIF_Type *base,
-                               sdif_handle_t *handle,
-                               sdif_transfer_callback_t *callback,
-                               void *userData);
-
-/*!
- * @brief SDIF enable DMA interrupt
- * @param base SDIF peripheral base address.
- * @param interrupt mask to set
- */
-static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask)
-{
-    base->IDINTEN |= mask;
-}
-
-/*!
- * @brief SDIF disable DMA interrupt
- * @param base SDIF peripheral base address.
- * @param interrupt mask to clear
- */
-static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask)
-{
-    base->IDINTEN &= ~mask;
-}
-
-/*!
- * @brief SDIF get internal DMA status
- * @param base SDIF peripheral base address.
- * @return the internal DMA status register
- */
-static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base)
-{
-    return base->IDSTS;
-}
-
-/*!
- * @brief SDIF clear internal DMA status
- * @param base SDIF peripheral base address.
- * @param status mask to clear
- */
-static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask)
-{
-    base->IDSTS &= mask;
-}
-
-/*!
- * @brief SDIF internal DMA config function
- * @param base SDIF peripheral base address.
- * @param internal DMA configuration collection
- * @param data buffer pointer
- * @param data buffer size
- */
-status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize);
-
-/*!
- * @brief SDIF send read wait to SDIF card function
- * @param base SDIF peripheral base address.
- */
-static inline void SDIF_SendReadWait(SDIF_Type *base)
-{
-    base->CTRL |= SDIF_CTRL_READ_WAIT_MASK;
-}
-
-/*!
- * @brief SDIF abort the read data when SDIF card is in suspend state
- * Once assert this bit,data state machine will be reset which is waiting for the
- * next blocking data,used in SDIO card suspend sequence,should call after suspend
- * cmd send
- * @param base SDIF peripheral base address.
- * @param timeout value to wait this bit self clear which indicate the data machine
- * reset to idle
- */
-bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout);
-
-/*!
- * @brief SDIF enable/disable CE-ATA card interrupt
- * this bit should set together with the card register
- * @param base SDIF peripheral base address.
- * @param enable/disable flag
- */
-static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
-    }
-    else
-    {
-        base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
-    }
-}
-
-/*!
- * @brief SDIF transfer function data/cmd in a non-blocking way
- * this API should be use in interrupt mode, when use this API user
- * must call SDIF_TransferCreateHandle first, all status check through
- * interrupt
- * @param base SDIF peripheral base address.
- * @param sdif handle
- * @param DMA config structure
- *  This parameter can be config as:
- *      1. NULL
-            In this condition, polling transfer mode is selected
-        2. avaliable DMA config
-            In this condition, DMA transfer mode is selected
- * @param sdif transfer configuration collection
- */
-status_t SDIF_TransferNonBlocking(SDIF_Type *base,
-                                  sdif_handle_t *handle,
-                                  sdif_dma_config_t *dmaConfig,
-                                  sdif_transfer_t *transfer);
-
-/*!
- * @brief SDIF transfer function data/cmd in a blocking way
- * @param base SDIF peripheral base address.
- * @param DMA config structure
- *       1. NULL
- *           In this condition, polling transfer mode is selected
- *       2. avaliable DMA config
- *           In this condition, DMA transfer mode is selected
- * @param sdif transfer configuration collection
- */
-status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer);
-
-/*!
- * @brief SDIF release the DMA descriptor to DMA engine
- * this function should be called when DMA descriptor unavailable status occurs
- * @param base SDIF peripheral base address.
- * @param sdif DMA config pointer
- */
-status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig);
-
-/*!
- * @brief SDIF return the controller capability
- * @param base SDIF peripheral base address.
- * @param sdif capability pointer
- */
-void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability);
-
-/*!
- * @brief SDIF return the controller status
- * @param base SDIF peripheral base address.
- */
-static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base)
-{
-    return base->STATUS;
-}
-
-/*!
- * @brief SDIF send command  complete signal disable to CE-ATA card
- * @param base SDIF peripheral base address.
- * @param send auto stop flag
- */
-static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop)
-{
-    if (withAutoStop)
-    {
-        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK;
-    }
-    else
-    {
-        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK;
-    }
-}
-
-/*!
- * @brief SDIF config the clock delay
- * This function is used to config the cclk_in delay to
- * sample and drvive the data ,should meet the min setup
- * time and hold time, and user need to config this paramter
- * according to your board setting
- * @param target freq work mode
- * @param clock divider which is used to decide if use pharse shift for delay
- */
-void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-/*! @} */
-
-#endif /* _FSL_sdif_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,712 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_spi.h"
-#include "fsl_flexcomm.h"
-
-/*******************************************************************************
- * Definitons
- ******************************************************************************/
-/* Note:  FIFOCFG[SIZE] has always value 1 = 8 items depth */
-#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3)
-
-/* Convert transfer count to transfer bytes. dataWidth is a
- * range <0,15>. Range <8,15> represents 2B transfer */
-#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U))
-#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U))
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief internal SPI config array */
-static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0};
-
-/*! @brief Array to map SPI instance number to base address. */
-static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS;
-
-/*! @brief IRQ name array */
-static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* Get the index corresponding to the FLEXCOMM */
-uint32_t SPI_GetInstance(SPI_Type *base)
-{
-    int i;
-
-    for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++)
-    {
-        if ((uint32_t)base == s_spiBaseAddrs[i])
-        {
-            return i;
-        }
-    }
-
-    assert(false);
-    return 0;
-}
-
-void *SPI_GetConfig(SPI_Type *base)
-{
-    int32_t instance;
-    instance = SPI_GetInstance(base);
-    if (instance < 0)
-    {
-        return NULL;
-    }
-    return &g_configs[instance];
-}
-
-void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
-{
-    assert(NULL != config);
-
-    config->enableLoopback = false;
-    config->enableMaster = true;
-    config->polarity = kSPI_ClockPolarityActiveHigh;
-    config->phase = kSPI_ClockPhaseFirstEdge;
-    config->direction = kSPI_MsbFirst;
-    config->baudRate_Bps = 500000U;
-    config->dataWidth = kSPI_Data8Bits;
-    config->sselNum = kSPI_Ssel0;
-    config->txWatermark = kSPI_TxFifo0;
-    config->rxWatermark = kSPI_RxFifo1;
-}
-
-status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
-{
-    int32_t result = 0, instance = 0;
-    uint32_t tmp;
-
-    /* assert params */
-    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
-    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* initialize flexcomm to SPI mode */
-    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
-    assert(kStatus_Success == result);
-    if (kStatus_Success != result)
-    {
-        return result;
-    }
-
-    /* set divider */
-    result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz);
-    if (kStatus_Success != result)
-    {
-        return result;
-    }
-    /* get instance number */
-    instance = SPI_GetInstance(base);
-    assert(instance >= 0);
-
-    /* configure SPI mode */
-    tmp = base->CFG;
-    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK);
-    /* phase */
-    tmp |= SPI_CFG_CPHA(config->phase);
-    /* polarity */
-    tmp |= SPI_CFG_CPOL(config->polarity);
-    /* direction */
-    tmp |= SPI_CFG_LSBF(config->direction);
-    /* master mode */
-    tmp |= SPI_CFG_MASTER(1);
-    /* loopback */
-    tmp |= SPI_CFG_LOOP(config->enableLoopback);
-    base->CFG = tmp;
-
-    /* store configuration */
-    g_configs[instance].dataWidth = config->dataWidth;
-    g_configs[instance].sselNum = config->sselNum;
-    /* enable FIFOs */
-    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
-    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
-    /* trigger level - empty txFIFO, one item in rxFIFO */
-    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
-    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
-    /* enable generating interrupts for FIFOTRIG levels */
-    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
-    /* set FIFOTRIG */
-    base->FIFOTRIG = tmp;
-
-    SPI_Enable(base, config->enableMaster);
-    return kStatus_Success;
-}
-
-void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
-{
-    assert(NULL != config);
-
-    config->enableSlave = true;
-    config->polarity = kSPI_ClockPolarityActiveHigh;
-    config->phase = kSPI_ClockPhaseFirstEdge;
-    config->direction = kSPI_MsbFirst;
-    config->dataWidth = kSPI_Data8Bits;
-    config->txWatermark = kSPI_TxFifo0;
-    config->rxWatermark = kSPI_RxFifo1;
-}
-
-status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
-{
-    int32_t result = 0, instance;
-    uint32_t tmp;
-
-    /* assert params */
-    assert(!((NULL == base) || (NULL == config)));
-    if ((NULL == base) || (NULL == config))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* configure flexcomm to SPI, enable clock gate */
-    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
-    assert(kStatus_Success == result);
-    if (kStatus_Success != result)
-    {
-        return result;
-    }
-
-    instance = SPI_GetInstance(base);
-
-    /* configure SPI mode */
-    tmp = base->CFG;
-    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK);
-    /* phase */
-    tmp |= SPI_CFG_CPHA(config->phase);
-    /* polarity */
-    tmp |= SPI_CFG_CPOL(config->polarity);
-    /* direction */
-    tmp |= SPI_CFG_LSBF(config->direction);
-    base->CFG = tmp;
-
-    /* store configuration */
-    g_configs[instance].dataWidth = config->dataWidth;
-    /* empty and enable FIFOs */
-    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
-    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
-    /* trigger level - empty txFIFO, one item in rxFIFO */
-    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
-    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
-    /* enable generating interrupts for FIFOTRIG levels */
-    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
-    /* set FIFOTRIG */
-    base->FIFOTRIG = tmp;
-
-    SPI_Enable(base, config->enableSlave);
-    return kStatus_Success;
-}
-
-void SPI_Deinit(SPI_Type *base)
-{
-    /* Assert arguments */
-    assert(NULL != base);
-    /* Disable interrupts, disable dma requests, disable peripheral */
-    base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK |
-                         SPI_FIFOINTENCLR_RXLVL_MASK;
-    base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK);
-    base->CFG &= ~(SPI_CFG_ENABLE_MASK);
-}
-
-void SPI_EnableTxDMA(SPI_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK;
-    }
-}
-
-void SPI_EnableRxDMA(SPI_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK;
-    }
-}
-
-status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
-{
-    uint32_t tmp;
-
-    /* assert params */
-    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
-    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* calculate baudrate */
-    tmp = (srcClock_Hz / baudrate_Bps) - 1;
-    if (tmp > 0xFFFF)
-    {
-        return kStatus_SPI_BaudrateNotSupport;
-    }
-    base->DIV &= ~SPI_DIV_DIVVAL_MASK;
-    base->DIV |= SPI_DIV_DIVVAL(tmp);
-    return kStatus_Success;
-}
-
-void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags)
-{
-    uint32_t control = 0;
-    int32_t instance;
-
-    /* check params */
-    assert(NULL != base);
-    /* get and check instance */
-    instance = SPI_GetInstance(base);
-    assert(!(instance < 0));
-    if (instance < 0)
-    {
-        return;
-    }
-
-    /* set data width */
-    control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth);
-    /* set sssel */
-    control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
-    /* mask configFlags */
-    control |= (configFlags & SPI_FIFOWR_FLAGS_MASK);
-    /* control should not affect lower 16 bits */
-    assert(!(control & 0xFFFF));
-    base->FIFOWR = data | control;
-}
-
-status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
-                                        spi_master_handle_t *handle,
-                                        spi_master_callback_t callback,
-                                        void *userData)
-{
-    int32_t instance = 0;
-
-    /* check 'base' */
-    assert(!(NULL == base));
-    if (NULL == base)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* check 'handle' */
-    assert(!(NULL == handle));
-    if (NULL == handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* get flexcomm instance by 'base' param */
-    instance = SPI_GetInstance(base);
-    assert(!(instance < 0));
-    if (instance < 0)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    memset(handle, 0, sizeof(*handle));
-    /* Initialize the handle */
-    if (base->CFG & SPI_CFG_MASTER_MASK)
-    {
-        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle);
-    }
-    else
-    {
-        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle);
-    }
-
-    handle->dataWidth = g_configs[instance].dataWidth;
-    /* in slave mode, the sselNum is not important */
-    handle->sselNum = g_configs[instance].sselNum;
-    handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base);
-    handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base);
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* Enable SPI NVIC */
-    EnableIRQ(s_spiIRQ[instance]);
-
-    return kStatus_Success;
-}
-
-status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
-{
-    int32_t instance;
-    uint32_t tx_ctrl = 0, last_ctrl = 0;
-    uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth;
-    uint32_t toReceiveCount = 0;
-    uint8_t *txData, *rxData;
-    uint32_t fifoDepth;
-
-    /* check params */
-    assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
-    if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    fifoDepth = SPI_FIFO_DEPTH(base);
-    txData = xfer->txData;
-    rxData = xfer->rxData;
-    txRemainingBytes = txData ? xfer->dataSize : 0;
-    rxRemainingBytes = rxData ? xfer->dataSize : 0;
-
-    instance = SPI_GetInstance(base);
-    assert(instance >= 0);
-    dataWidth = g_configs[instance].dataWidth;
-
-    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
-    assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
-    if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* clear tx/rx errors and empty FIFOs */
-    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
-    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
-    /* select slave to talk with */
-    tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
-    /* set width of data - range asserted at entry */
-    tx_ctrl |= SPI_FIFOWR_LEN(dataWidth);
-    /* end of transfer */
-    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
-    /* delay end of transfer */
-    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
-    /* last index of loop */
-    while (txRemainingBytes || rxRemainingBytes || toReceiveCount)
-    {
-        /* if rxFIFO is not empty */
-        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
-        {
-            tmp32 = base->FIFORD;
-            /* rxBuffer is not empty */
-            if (rxRemainingBytes)
-            {
-                *(rxData++) = tmp32;
-                rxRemainingBytes--;
-                /* read 16 bits at once */
-                if (dataWidth > 8)
-                {
-                    *(rxData++) = tmp32 >> 8;
-                    rxRemainingBytes--;
-                }
-            }
-            /* decrease number of data expected to receive */
-            toReceiveCount -= 1;
-        }
-        /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */
-        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) &&
-            ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))))
-        {
-            /* txBuffer is not empty */
-            if (txRemainingBytes)
-            {
-                tmp32 = *(txData++);
-                txRemainingBytes--;
-                /* write 16 bit at once */
-                if (dataWidth > 8)
-                {
-                    tmp32 |= ((uint32_t)(*(txData++))) << 8U;
-                    txRemainingBytes--;
-                }
-                if (!txRemainingBytes)
-                {
-                    tx_ctrl |= last_ctrl;
-                }
-            }
-            else
-            {
-                tmp32 = SPI_DUMMYDATA;
-                /* last transfer */
-                if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))
-                {
-                    tx_ctrl |= last_ctrl;
-                }
-            }
-            /* send data */
-            tmp32 = tx_ctrl | tmp32;
-            base->FIFOWR = tmp32;
-            toReceiveCount += 1;
-        }
-    }
-    /* wait if TX FIFO of previous transfer is not empty */
-    while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK))
-    {
-    }
-    return kStatus_Success;
-}
-
-status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
-{
-    /* check params */
-    assert(
-        !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
-    if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
-    assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
-    if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Check if SPI is busy */
-    if (handle->state == kStatus_SPI_Busy)
-    {
-        return kStatus_SPI_Busy;
-    }
-
-    /* Set the handle information */
-    handle->txData = xfer->txData;
-    handle->rxData = xfer->rxData;
-    /* set count */
-    handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0;
-    handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0;
-    handle->totalByteCount = xfer->dataSize;
-    /* other options */
-    handle->toReceiveCount = 0;
-    handle->configFlags = xfer->configFlags;
-    /* Set the SPI state to busy */
-    handle->state = kStatus_SPI_Busy;
-    /* clear FIFOs when transfer starts */
-    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
-    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
-    /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */
-    base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK;
-    return kStatus_Success;
-}
-
-status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
-{
-    assert(NULL != handle);
-
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Catch when there is not an active transfer. */
-    if (handle->state != kStatus_SPI_Busy)
-    {
-        *count = 0;
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->totalByteCount - handle->rxRemainingBytes;
-    return kStatus_Success;
-}
-
-void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    /* Disable interrupt requests*/
-    base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK);
-    /* Empty FIFOs */
-    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
-
-    handle->state = kStatus_SPI_Idle;
-    handle->txRemainingBytes = 0;
-    handle->rxRemainingBytes = 0;
-}
-
-static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle)
-{
-    uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32;
-    bool loopContinue;
-    uint32_t fifoDepth;
-
-    /* check params */
-    assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData)));
-
-    fifoDepth = SPI_FIFO_DEPTH(base);
-    /* select slave to talk with */
-    tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum));
-    /* set width of data */
-    tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth);
-    /* end of transfer */
-    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
-    /* delay end of transfer */
-    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
-    do
-    {
-        loopContinue = false;
-
-        /* rxFIFO is not empty */
-        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
-        {
-            tmp32 = base->FIFORD;
-            /* rxBuffer is not empty */
-            if (handle->rxRemainingBytes)
-            {
-                /* low byte must go first */
-                *(handle->rxData++) = tmp32;
-                handle->rxRemainingBytes--;
-                /* read 16 bits at once */
-                if (handle->dataWidth > kSPI_Data8Bits)
-                {
-                    *(handle->rxData++) = tmp32 >> 8;
-                    handle->rxRemainingBytes--;
-                }
-            }
-            /* decrease number of data expected to receive */
-            handle->toReceiveCount -= 1;
-            loopContinue = true;
-        }
-
-        /* - txFIFO is not full
-         * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO
-         * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer
-         */
-        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) &&
-            ((handle->txRemainingBytes) ||
-             (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))))
-        {
-            /* txBuffer is not empty */
-            if (handle->txRemainingBytes)
-            {
-                /* low byte must go first */
-                tmp32 = *(handle->txData++);
-                handle->txRemainingBytes--;
-                /* write 16 bit at once */
-                if (handle->dataWidth > kSPI_Data8Bits)
-                {
-                    tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U;
-                    handle->txRemainingBytes--;
-                }
-                /* last transfer */
-                if (!handle->txRemainingBytes)
-                {
-                    tx_ctrl |= last_ctrl;
-                }
-            }
-            else
-            {
-                tmp32 = SPI_DUMMYDATA;
-                /* last transfer */
-                if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))
-                {
-                    tx_ctrl |= last_ctrl;
-                }
-            }
-            /* send data */
-            tmp32 = tx_ctrl | tmp32;
-            base->FIFOWR = tmp32;
-            /* increase number of expected data to receive */
-            handle->toReceiveCount += 1;
-            loopContinue = true;
-        }
-    } while (loopContinue);
-}
-
-void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
-{
-    assert((NULL != base) && (NULL != handle));
-
-    /* IRQ behaviour:
-     * - first interrupt is triggered by empty txFIFO. The transfer function
-     *   then tries empty rxFIFO and fill txFIFO interleaved that results to
-     *   strategy to process as many items as possible.
-     * - the next IRQs can be:
-     *      rxIRQ from nonempty rxFIFO which requires to empty rxFIFO.
-     *      txIRQ from empty txFIFO which requires to refill txFIFO.
-     * - last interrupt is triggered by empty txFIFO. The last state is
-     *   known by empty rxBuffer and txBuffer. If there is nothing to receive
-     *   or send - both operations have been finished and interrupts can be
-     *   disabled.
-     */
-
-    /* Data to send or read or expected to receive */
-    if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount))
-    {
-        /* Transmit or receive data */
-        SPI_TransferHandleIRQInternal(base, handle);
-        /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and
-         * enable txIRQ to confirm when txFIFO becomes empty */
-        if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount))
-        {
-            base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK);
-            base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK;
-        }
-        else
-        {
-            uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes);
-            /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data,
-             * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */
-            if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount))
-            {
-                base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK;
-            }
-            /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel.
-             * Cannot clear rxFIFO, txFIFO might be still active */
-            if (rxRemainingCount == 0)
-            {
-                if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) &&
-                    (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1))
-                {
-                    base->FIFOTRIG =
-                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1);
-                }
-            }
-            /* Expected to receive less data than rxLevel value, we have to update rxLevel */
-            else
-            {
-                if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1))
-                {
-                    base->FIFOTRIG =
-                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1);
-                }
-            }
-        }
-    }
-    else
-    {
-        /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */
-        base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK;
-        base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) |
-                         SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark);
-        /* set idle state and call user callback */
-        handle->state = kStatus_SPI_Idle;
-        if (handle->callback)
-        {
-            (handle->callback)(base, handle, handle->state, handle->userData);
-        }
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,629 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SPI_H_
-#define _FSL_SPI_H_
-
-#include "fsl_common.h"
-#include "fsl_flexcomm.h"
-
-/*!
- * @addtogroup spi_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief USART driver version 2.0.0. */
-#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-#define SPI_DUMMYDATA (0xFFFF)
-#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
-#define SPI_CTRLMASK (0xFFFF0000)
-
-#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
-#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
-#define SPI_DEASSERT_ALL (0xF0000)
-
-#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
-
-#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
-#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
-
-/*! @brief SPI transfer option.*/
-typedef enum _spi_xfer_option {
-    kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK),  /*!< Delay chip select */
-    kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
-} spi_xfer_option_t;
-
-/*! @brief SPI data shifter direction options.*/
-typedef enum _spi_shift_direction {
-    kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
-    kSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit. */
-} spi_shift_direction_t;
-
-/*! @brief SPI clock polarity configuration.*/
-typedef enum _spi_clock_polarity {
-    kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
-    kSPI_ClockPolarityActiveLow          /*!< Active-low SPI clock (idles high). */
-} spi_clock_polarity_t;
-
-/*! @brief SPI clock phase configuration.*/
-typedef enum _spi_clock_phase {
-    kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
-                                         *   cycle of a data transfer. */
-    kSPI_ClockPhaseSecondEdge        /*!< First edge on SCK occurs at the start of the
-                                         *   first cycle of a data transfer. */
-} spi_clock_phase_t;
-
-/*! @brief txFIFO watermark values */
-typedef enum _spi_txfifo_watermark {
-    kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
-    kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
-    kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
-    kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
-    kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
-    kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
-    kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
-    kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
-} spi_txfifo_watermark_t;
-
-/*! @brief rxFIFO watermark values */
-typedef enum _spi_rxfifo_watermark {
-    kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
-    kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
-    kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
-    kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
-    kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
-    kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
-    kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
-    kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
-} spi_rxfifo_watermark_t;
-
-/*! @brief Transfer data width */
-typedef enum _spi_data_width {
-    kSPI_Data4Bits = 3,   /*!< 4 bits data width */
-    kSPI_Data5Bits = 4,   /*!< 5 bits data width */
-    kSPI_Data6Bits = 5,   /*!< 6 bits data width */
-    kSPI_Data7Bits = 6,   /*!< 7 bits data width */
-    kSPI_Data8Bits = 7,   /*!< 8 bits data width */
-    kSPI_Data9Bits = 8,   /*!< 9 bits data width */
-    kSPI_Data10Bits = 9,  /*!< 10 bits data width */
-    kSPI_Data11Bits = 10, /*!< 11 bits data width */
-    kSPI_Data12Bits = 11, /*!< 12 bits data width */
-    kSPI_Data13Bits = 12, /*!< 13 bits data width */
-    kSPI_Data14Bits = 13, /*!< 14 bits data width */
-    kSPI_Data15Bits = 14, /*!< 15 bits data width */
-    kSPI_Data16Bits = 15, /*!< 16 bits data width */
-} spi_data_width_t;
-
-/*! @brief Slave select */
-typedef enum _spi_ssel {
-    kSPI_Ssel0 = 0, /*!< Slave select 0 */
-    kSPI_Ssel1 = 1, /*!< Slave select 1 */
-    kSPI_Ssel2 = 2, /*!< Slave select 2 */
-    kSPI_Ssel3 = 3, /*!< Slave select 3 */
-} spi_ssel_t;
-
-/*! @brief SPI master user configure structure.*/
-typedef struct _spi_master_config
-{
-    bool enableLoopback;                /*!< Enable loopback for test purpose */
-    bool enableMaster;                  /*!< Enable SPI at initialization time */
-    spi_clock_polarity_t polarity;      /*!< Clock polarity */
-    spi_clock_phase_t phase;            /*!< Clock phase */
-    spi_shift_direction_t direction;    /*!< MSB or LSB */
-    uint32_t baudRate_Bps;              /*!< Baud Rate for SPI in Hz */
-    spi_data_width_t dataWidth;         /*!< Width of the data */
-    spi_ssel_t sselNum;                 /*!< Slave select number */
-    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
-    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
-} spi_master_config_t;
-
-/*! @brief SPI slave user configure structure.*/
-typedef struct _spi_slave_config
-{
-    bool enableSlave;                   /*!< Enable SPI at initialization time */
-    spi_clock_polarity_t polarity;      /*!< Clock polarity */
-    spi_clock_phase_t phase;            /*!< Clock phase */
-    spi_shift_direction_t direction;    /*!< MSB or LSB */
-    spi_data_width_t dataWidth;         /*!< Width of the data */
-    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
-    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
-} spi_slave_config_t;
-
-/*! @brief SPI transfer status.*/
-enum _spi_status
-{
-    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0),  /*!< SPI bus is busy */
-    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1),  /*!< SPI is idle */
-    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI  error */
-    kStatus_SPI_BaudrateNotSupport =
-        MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
-};
-
-/*! @brief SPI interrupt sources.*/
-enum _spi_interrupt_enable
-{
-    kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
-    kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
-};
-
-/*! @brief SPI status flags.*/
-enum _spi_statusflags
-{
-    kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK,       /*!< txFifo is empty */
-    kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK,   /*!< txFifo is not full */
-    kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
-    kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK,         /*!< rxFIFO is full */
-};
-
-/*! @brief SPI transfer structure */
-typedef struct _spi_transfer
-{
-    uint8_t *txData;      /*!< Send buffer */
-    uint8_t *rxData;      /*!< Receive buffer */
-    uint32_t configFlags; /*!< Additional option to control transfer */
-    size_t dataSize;      /*!< Transfer bytes */
-} spi_transfer_t;
-
-/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
-typedef struct _spi_config
-{
-    spi_data_width_t dataWidth;
-    spi_ssel_t sselNum;
-} spi_config_t;
-
-/*! @brief  Master handle type */
-typedef struct _spi_master_handle spi_master_handle_t;
-
-/*! @brief  Slave handle type */
-typedef spi_master_handle_t spi_slave_handle_t;
-
-/*! @brief SPI master callback for finished transmit */
-typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
-
-/*! @brief SPI slave callback for finished transmit */
-typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
-
-/*! @brief SPI transfer handle structure */
-struct _spi_master_handle
-{
-    uint8_t *volatile txData;         /*!< Transfer buffer */
-    uint8_t *volatile rxData;         /*!< Receive buffer */
-    volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
-    volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
-    volatile size_t toReceiveCount;   /*!< Receive data remaining in bytes */
-    size_t totalByteCount;            /*!< A number of transfer bytes */
-    volatile uint32_t state;          /*!< SPI internal state */
-    spi_master_callback_t callback;   /*!< SPI callback */
-    void *userData;                   /*!< Callback parameter */
-    uint8_t dataWidth;                /*!< Width of the data [Valid values: 1 to 16] */
-    uint8_t sselNum;      /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
-    uint32_t configFlags; /*!< Additional option to control transfer */
-    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
-    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
-};
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-/*! @brief Returns instance number for SPI peripheral base address. */
-uint32_t SPI_GetInstance(SPI_Type *base);
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief  Sets the SPI master configuration structure to default values.
- *
- * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
- * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
- * some fields of the structure before calling SPI_MasterInit(). After calling this API,
- * the master is ready to transfer.
- * Example:
-   @code
-   spi_master_config_t config;
-   SPI_MasterGetDefaultConfig(&config);
-   @endcode
- *
- * @param config pointer to master config structure
- */
-void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
-
-/*!
- * @brief Initializes the SPI with master configuration.
- *
- * The configuration structure can be filled by user from scratch, or be set with default
- * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
- * Example
-   @code
-   spi_master_config_t config = {
-   .baudRate_Bps = 400000,
-   ...
-   };
-   SPI_MasterInit(SPI0, &config);
-   @endcode
- *
- * @param base SPI base pointer
- * @param config pointer to master configuration structure
- * @param srcClock_Hz Source clock frequency.
- */
-status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
-
-/*!
- * @brief  Sets the SPI slave configuration structure to default values.
- *
- * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
- * Modify some fields of the structure before calling SPI_SlaveInit().
- * Example:
-   @code
-   spi_slave_config_t config;
-   SPI_SlaveGetDefaultConfig(&config);
-   @endcode
- *
- * @param config pointer to slave configuration structure
- */
-void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
-
-/*!
- * @brief Initializes the SPI with slave configuration.
- *
- * The configuration structure can be filled by user from scratch or be set with
- * default values by SPI_SlaveGetDefaultConfig().
- * After calling this API, the slave is ready to transfer.
- * Example
-   @code
-    spi_slave_config_t config = {
-    .polarity = flexSPIClockPolarity_ActiveHigh;
-    .phase = flexSPIClockPhase_FirstEdge;
-    .direction = flexSPIMsbFirst;
-    ...
-    };
-    SPI_SlaveInit(SPI0, &config);
-   @endcode
- *
- * @param base SPI base pointer
- * @param config pointer to slave configuration structure
- */
-status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
-
-/*!
- * @brief De-initializes the SPI.
- *
- * Calling this API resets the SPI module, gates the SPI clock.
- * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
- *
- * @param base SPI base pointer
- */
-void SPI_Deinit(SPI_Type *base);
-
-/*!
- * @brief Enable or disable the SPI Master or Slave
- * @param base SPI base pointer
- * @param enable or disable ( true = enable, false = disable)
- */
-static inline void SPI_Enable(SPI_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CFG |= SPI_CFG_ENABLE_MASK;
-    }
-    else
-    {
-        base->CFG &= ~SPI_CFG_ENABLE_MASK;
-    }
-}
-
-/*! @} */
-
-/*!
- * @name Status
- * @{
- */
-
-/*!
- * @brief Gets the status flag.
- *
- * @param base SPI base pointer
- * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
- */
-static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
-{
-    assert(NULL != base);
-    return base->FIFOSTAT;
-}
-
-/*! @} */
-
-/*!
- * @name Interrupts
- * @{
- */
-
-/*!
- * @brief Enables the interrupt for the SPI.
- *
- * @param base SPI base pointer
- * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
- *        @arg kSPI_RxLvlIrq
- *        @arg kSPI_TxLvlIrq
- */
-static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
-{
-    assert(NULL != base);
-    base->FIFOINTENSET = irqs;
-}
-
-/*!
- * @brief Disables the interrupt for the SPI.
- *
- * @param base SPI base pointer
- * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
- *        @arg kSPI_RxLvlIrq
- *        @arg kSPI_TxLvlIrq
- */
-static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
-{
-    assert(NULL != base);
-    base->FIFOINTENCLR = irqs;
-}
-
-/*! @} */
-
-/*!
- * @name DMA Control
- * @{
- */
-
-/*!
- * @brief Enables the DMA request from SPI txFIFO.
- *
- * @param base SPI base pointer
- * @param enable True means enable DMA, false means disable DMA
- */
-void SPI_EnableTxDMA(SPI_Type *base, bool enable);
-
-/*!
- * @brief Enables the DMA request from SPI rxFIFO.
- *
- * @param base SPI base pointer
- * @param enable True means enable DMA, false means disable DMA
- */
-void SPI_EnableRxDMA(SPI_Type *base, bool enable);
-
-/*! @} */
-
-/*!
- * @name Bus Operations
- * @{
- */
-
-/*!
- * @brief Sets the baud rate for SPI transfer. This is only used in master.
- *
- * @param base SPI base pointer
- * @param baudrate_Bps baud rate needed in Hz.
- * @param srcClock_Hz SPI source clock frequency in Hz.
- */
-status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
-
-/*!
- * @brief Writes a data into the SPI data register.
- *
- * @param base SPI base pointer
- * @param data needs to be write.
- * @param configFlags transfer configuration options @ref spi_xfer_option_t
- */
-void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
-
-/*!
- * @brief Gets a data from the SPI data register.
- *
- * @param base SPI base pointer
- * @return Data in the register.
- */
-static inline uint32_t SPI_ReadData(SPI_Type *base)
-{
-    assert(NULL != base);
-    return base->FIFORD;
-}
-
-/*! @} */
-
-/*!
- * @name Transactional
- * @{
- */
-
-/*!
- * @brief Initializes the SPI master handle.
- *
- * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
- * for a specified SPI instance, call this API once to get the initialized handle.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI handle pointer.
- * @param callback Callback function.
- * @param userData User data.
- */
-status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
-                                        spi_master_handle_t *handle,
-                                        spi_master_callback_t callback,
-                                        void *userData);
-
-/*!
- * @brief Transfers a block of data using a polling method.
- *
- * @param base SPI base pointer
- * @param xfer pointer to spi_xfer_config_t structure
- * @retval kStatus_Success Successfully start a transfer.
- * @retval kStatus_InvalidArgument Input argument is invalid.
- */
-status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
-
-/*!
- * @brief Performs a non-blocking SPI interrupt transfer.
- *
- * @param base SPI peripheral base address.
- * @param handle pointer to spi_master_handle_t structure which stores the transfer state
- * @param xfer pointer to spi_xfer_config_t structure
- * @retval kStatus_Success Successfully start a transfer.
- * @retval kStatus_InvalidArgument Input argument is invalid.
- * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
- */
-status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
-
-/*!
- * @brief Gets the master transfer count.
- *
- * This function gets the master transfer count.
- *
- * @param base SPI peripheral base address.
- * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
- * @param count The number of bytes transferred by using the non-blocking transaction.
- * @return status of status_t.
- */
-status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
-
-/*!
- * @brief SPI master aborts a transfer using an interrupt.
- *
- * This function aborts a transfer using an interrupt.
- *
- * @param base SPI peripheral base address.
- * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
- */
-void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
-
-/*!
- * @brief Interrupts the handler for the SPI.
- *
- * @param base SPI peripheral base address.
- * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
- */
-void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
-
-/*!
- * @brief Initializes the SPI slave handle.
- *
- * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
- * for a specified SPI instance, call this API once to get the initialized handle.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI handle pointer.
- * @param callback Callback function.
- * @param userData User data.
- */
-static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
-                                                     spi_slave_handle_t *handle,
-                                                     spi_slave_callback_t callback,
-                                                     void *userData)
-{
-    return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
-}
-
-/*!
- * @brief Performs a non-blocking SPI slave interrupt transfer.
- *
- * @note The API returns immediately after the transfer initialization is finished.
- *
- * @param base SPI peripheral base address.
- * @param handle pointer to spi_master_handle_t structure which stores the transfer state
- * @param xfer pointer to spi_xfer_config_t structure
- * @retval kStatus_Success Successfully start a transfer.
- * @retval kStatus_InvalidArgument Input argument is invalid.
- * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
- */
-static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
-{
-    return SPI_MasterTransferNonBlocking(base, handle, xfer);
-}
-
-/*!
- * @brief Gets the slave transfer count.
- *
- * This function gets the slave transfer count.
- *
- * @param base SPI peripheral base address.
- * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
- * @param count The number of bytes transferred by using the non-blocking transaction.
- * @return status of status_t.
- */
-static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
-{
-    return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count);
-}
-
-/*!
- * @brief SPI slave aborts a transfer using an interrupt.
- *
- * This function aborts a transfer using an interrupt.
- *
- * @param base SPI peripheral base address.
- * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
- */
-static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
-{
-    SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle);
-}
-
-/*!
- * @brief Interrupts a handler for the SPI slave.
- *
- * @param base SPI peripheral base address.
- * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
- */
-static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
-{
-    SPI_MasterTransferHandleIRQ(base, handle);
-}
-
-/*! @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @} */
-
-#endif /* _FSL_SPI_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,411 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_spi_dma.h"
-
-/*******************************************************************************
- * Definitons
- ******************************************************************************/
-/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
-typedef struct _spi_dma_private_handle
-{
-    SPI_Type *base;
-    spi_dma_handle_t *handle;
-} spi_dma_private_handle_t;
-
-/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
-enum _spi_dma_states_t
-{
-    kSPI_Idle = 0x0, /*!< SPI is idle state */
-    kSPI_Busy        /*!< SPI is busy tranferring data. */
-};
-
-typedef struct _spi_dma_txdummy
-{
-    uint32_t lastWord;
-    uint32_t word;
-} spi_dma_txdummy_t;
-
-/*<! Private handle only used for internally. */
-static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
-* @brief SPI private function to return SPI configuration
-*
-* @param base SPI base address.
-*/
-void *SPI_GetConfig(SPI_Type *base);
-
-/*!
- * @brief DMA callback function for SPI send transfer.
- *
- * @param handle DMA handle pointer.
- * @param userData User data for DMA callback function.
- */
-static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
-
-/*!
- * @brief DMA callback function for SPI receive transfer.
- *
- * @param handle DMA handle pointer.
- * @param userData User data for DMA callback function.
- */
-static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-#if defined(__ICCARM__)
-#pragma data_alignment = 4
-static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#elif defined(__CC_ARM)
-__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#elif defined(__GNUC__)
-__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#endif
-
-#if defined(__ICCARM__)
-#pragma data_alignment = 4
-static uint16_t s_rxDummy;
-#elif defined(__CC_ARM)
-__attribute__((aligned(4))) static uint16_t s_rxDummy;
-#elif defined(__GNUC__)
-__attribute__((aligned(4))) static uint16_t s_rxDummy;
-#endif
-
-#if defined(__ICCARM__)
-#pragma data_alignment = 16
-static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#elif defined(__CC_ARM)
-__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#elif defined(__GNUC__)
-__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
-#endif
-
-/*******************************************************************************
-* Code
-******************************************************************************/
-
-static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
-{
-    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0;
-    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0;
-}
-
-static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
-{
-    *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum)));
-    /* set width of data - range asserted at entry */
-    *fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
-}
-
-static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl)
-{
-    assert(!(fifo == NULL));
-    if (fifo == NULL)
-    {
-        return;
-    }
-    /* CS deassert and CS delay are relevant only for last word */
-    uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK));
-    uint32_t i = 0;
-    for (; i + 1 < count; i++)
-    {
-        fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U);
-    }
-    if (i < count)
-    {
-        fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U);
-    }
-}
-
-static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
-{
-    *dummy = SPI_DUMMYDATA;
-    XferToFifoWR(xfer, dummy);
-    SpiConfigToFifoWR(spi_config_p, dummy);
-}
-
-status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
-                                           spi_dma_handle_t *handle,
-                                           spi_dma_callback_t callback,
-                                           void *userData,
-                                           dma_handle_t *txHandle,
-                                           dma_handle_t *rxHandle)
-{
-    int32_t instance = 0;
-
-    /* check 'base' */
-    assert(!(NULL == base));
-    if (NULL == base)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* check 'handle' */
-    assert(!(NULL == handle));
-    if (NULL == handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    instance = SPI_GetInstance(base);
-
-    memset(handle, 0, sizeof(*handle));
-    /* Set spi base to handle */
-    handle->txHandle = txHandle;
-    handle->rxHandle = rxHandle;
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* Set SPI state to idle */
-    handle->state = kSPI_Idle;
-
-    /* Set handle to global state */
-    s_dmaPrivateHandle[instance].base = base;
-    s_dmaPrivateHandle[instance].handle = handle;
-
-    /* Install callback for Tx dma channel */
-    DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
-    DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
-
-    return kStatus_Success;
-}
-
-status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
-{
-    int32_t instance;
-    status_t result = kStatus_Success;
-    spi_config_t *spi_config_p;
-
-    assert(!((NULL == handle) || (NULL == xfer)));
-    if ((NULL == handle) || (NULL == xfer))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* txData set and not aligned to sizeof(uint32_t) */
-    assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))));
-    if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* rxData set and not aligned to sizeof(uint32_t) */
-    assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))));
-    if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* byte size is zero or not aligned to sizeof(uint32_t) */
-    assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))));
-    if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* cannot get instance from base address */
-    instance = SPI_GetInstance(base);
-    assert(!(instance < 0));
-    if (instance < 0)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Check if the device is busy */
-    if (handle->state == kSPI_Busy)
-    {
-        return kStatus_SPI_Busy;
-    }
-    else
-    {
-        uint32_t tmp;
-        dma_transfer_config_t xferConfig = {0};
-        spi_config_p = (spi_config_t *)SPI_GetConfig(base);
-
-        handle->state = kStatus_SPI_Busy;
-        handle->transferSize = xfer->dataSize;
-
-        /* receive */
-        SPI_EnableRxDMA(base, true);
-        if (xfer->rxData)
-        {
-            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize,
-                                kDMA_PeripheralToMemory, NULL);
-        }
-        else
-        {
-            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize,
-                                kDMA_StaticToStatic, NULL);
-        }
-        DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
-        handle->rxInProgress = true;
-        DMA_StartTransfer(handle->rxHandle);
-
-        /* transmit */
-        SPI_EnableTxDMA(base, true);
-        if (xfer->txData)
-        {
-            tmp = 0;
-            XferToFifoWR(xfer, &tmp);
-            SpiConfigToFifoWR(spi_config_p, &tmp);
-            PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp);
-            DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize,
-                                kDMA_MemoryToPeripheral, NULL);
-            DMA_SubmitTransfer(handle->txHandle, &xferConfig);
-        }
-        else
-        {
-            if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t)))
-            {
-                dma_xfercfg_t tmp_xfercfg = { 0 };
-                tmp_xfercfg.valid = true;
-                tmp_xfercfg.swtrig = true;
-                tmp_xfercfg.intA = true;
-                tmp_xfercfg.byteWidth = sizeof(uint32_t);
-                tmp_xfercfg.srcInc = 0;
-                tmp_xfercfg.dstInc = 0;
-                tmp_xfercfg.transferCount = 1;
-                /* create chained descriptor to transmit last word */
-                SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p);
-                DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
-                                     (uint32_t *)&base->FIFOWR, NULL);
-                /* use common API to setup first descriptor */
-                SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p);
-                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
-                                    xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic,
-                                    &s_spi_descriptor_table[instance]);
-                /* disable interrupts for first descriptor
-                 * to avoid calling callback twice */
-                xferConfig.xfercfg.intA = false;
-                xferConfig.xfercfg.intB = false;
-                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
-                if (result != kStatus_Success)
-                {
-                    return result;
-                }
-            }
-            else
-            {
-                SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p);
-                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
-                                    xfer->dataSize, kDMA_StaticToStatic, NULL);
-                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
-                if (result != kStatus_Success)
-                {
-                    return result;
-                }
-            }
-        }
-        handle->txInProgress = true;
-        DMA_StartTransfer(handle->txHandle);
-    }
-
-    return result;
-}
-
-static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
-{
-    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
-    spi_dma_handle_t *spiHandle = privHandle->handle;
-    SPI_Type *base = privHandle->base;
-
-    /* change the state */
-    spiHandle->rxInProgress = false;
-
-    /* All finished, call the callback */
-    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
-    {
-        spiHandle->state = kSPI_Idle;
-        if (spiHandle->callback)
-        {
-            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
-        }
-    }
-}
-
-static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
-{
-    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
-    spi_dma_handle_t *spiHandle = privHandle->handle;
-    SPI_Type *base = privHandle->base;
-
-    /* change the state */
-    spiHandle->txInProgress = false;
-
-    /* All finished, call the callback */
-    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
-    {
-        spiHandle->state = kSPI_Idle;
-        if (spiHandle->callback)
-        {
-            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
-        }
-    }
-}
-
-void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    /* Stop tx transfer first */
-    DMA_AbortTransfer(handle->txHandle);
-    /* Then rx transfer */
-    DMA_AbortTransfer(handle->rxHandle);
-
-    /* Set the handle state */
-    handle->txInProgress = false;
-    handle->rxInProgress = false;
-    handle->state = kSPI_Idle;
-}
-
-status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Catch when there is not an active transfer. */
-    if (handle->state != kSPI_Busy)
-    {
-        *count = 0;
-        return kStatus_NoTransferInProgress;
-    }
-
-    size_t bytes;
-
-    bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
-
-    *count = handle->transferSize - bytes;
-
-    return kStatus_Success;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,209 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SPI_DMA_H_
-#define _FSL_SPI_DMA_H_
-
-#include "fsl_dma.h"
-#include "fsl_spi.h"
-
-/*!
- * @addtogroup spi_dma_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-typedef struct _spi_dma_handle spi_dma_handle_t;
-
-/*! @brief SPI DMA callback called at the end of transfer. */
-typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
-
-/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
-struct _spi_dma_handle
-{
-    volatile bool txInProgress;  /*!< Send transfer finished */
-    volatile bool rxInProgress;  /*!< Receive transfer finished */
-    dma_handle_t *txHandle;      /*!< DMA handler for SPI send */
-    dma_handle_t *rxHandle;      /*!< DMA handler for SPI receive */
-    uint8_t bytesPerFrame;       /*!< Bytes in a frame for SPI tranfer */
-    spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
-    void *userData;              /*!< User Data for SPI DMA callback */
-    uint32_t state;              /*!< Internal state of SPI DMA transfer */
-    size_t transferSize;         /*!< Bytes need to be transfer */
-};
-
-/*******************************************************************************
- * APIs
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name DMA Transactional
- * @{
- */
-
-/*!
- * @brief Initialize the SPI master DMA handle.
- *
- * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
- * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI handle pointer.
- * @param callback User callback function called at the end of a transfer.
- * @param userData User data for callback.
- * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
- * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
- */
-status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
-                                           spi_dma_handle_t *handle,
-                                           spi_dma_callback_t callback,
-                                           void *userData,
-                                           dma_handle_t *txHandle,
-                                           dma_handle_t *rxHandle);
-
-/*!
- * @brief Perform a non-blocking SPI transfer using DMA.
- *
- * @note This interface returned immediately after transfer initiates, users should call
- * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI DMA handle pointer.
- * @param xfer Pointer to dma transfer structure.
- * @retval kStatus_Success Successfully start a transfer.
- * @retval kStatus_InvalidArgument Input argument is invalid.
- * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
- */
-status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
-
-/*!
- * @brief Initialize the SPI slave DMA handle.
- *
- * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
- * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI handle pointer.
- * @param callback User callback function called at the end of a transfer.
- * @param userData User data for callback.
- * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
- * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
- */
-static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
-                                                        spi_dma_handle_t *handle,
-                                                        spi_dma_callback_t callback,
-                                                        void *userData,
-                                                        dma_handle_t *txHandle,
-                                                        dma_handle_t *rxHandle)
-{
-    return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
-}
-
-/*!
- * @brief Perform a non-blocking SPI transfer using DMA.
- *
- * @note This interface returned immediately after transfer initiates, users should call
- * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI DMA handle pointer.
- * @param xfer Pointer to dma transfer structure.
- * @retval kStatus_Success Successfully start a transfer.
- * @retval kStatus_InvalidArgument Input argument is invalid.
- * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
- */
-static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
-{
-    return SPI_MasterTransferDMA(base, handle, xfer);
-}
-
-/*!
- * @brief Abort a SPI transfer using DMA.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI DMA handle pointer.
- */
-void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
-
-/*!
- * @brief Gets the master DMA transfer remaining bytes.
- *
- * This function gets the master DMA transfer remaining bytes.
- *
- * @param base SPI peripheral base address.
- * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
- * @param count A number of bytes transferred by the non-blocking transaction.
- * @return status of status_t.
- */
-status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
-
-/*!
- * @brief Abort a SPI transfer using DMA.
- *
- * @param base SPI peripheral base address.
- * @param handle SPI DMA handle pointer.
- */
-static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
-{
-    SPI_MasterTransferAbortDMA(base, handle);
-}
-
-/*!
- * @brief Gets the slave DMA transfer remaining bytes.
- *
- * This function gets the slave DMA transfer remaining bytes.
- *
- * @param base SPI peripheral base address.
- * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
- * @param count A number of bytes transferred by the non-blocking transaction.
- * @return status of status_t.
- */
-static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
-{
-    return SPI_MasterTransferGetCountDMA(base, handle, count);
-}
-
-/*! @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @} */
-
-#endif /* _FSL_SPI_DMA_H_*/

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_spifi.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Get the SPIFI instance from peripheral base address.
- *
- * @param base SPIFI peripheral base address.
- * @return SPIFI instance.
- */
-uint32_t SPIFI_GetInstance(SPIFI_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/* Array of SPIFI peripheral base address. */
-static SPIFI_Type *const s_spifiBases[] = SPIFI_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/* Array of SPIFI clock name. */
-static const clock_ip_name_t s_spifiClock[] = SPIFI_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-uint32_t SPIFI_GetInstance(SPIFI_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_spifiBases); instance++)
-    {
-        if (s_spifiBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_spifiBases));
-
-    return instance;
-}
-
-void SPIFI_GetDefaultConfig(spifi_config_t *config)
-{
-    config->timeout = 0xFFFFU;
-    config->csHighTime = 0xFU;
-    config->disablePrefetch = false;
-    config->disableCachePrefech = false;
-    config->isFeedbackClock = true;
-    config->spiMode = kSPIFI_SPISckLow;
-    config->isReadFullClockCycle = false;
-    config->dualMode = kSPIFI_QuadMode;
-}
-
-void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config)
-{
-    assert(config);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the SAI clock */
-    CLOCK_EnableClock(s_spifiClock[SPIFI_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the Command register */
-    SPIFI_ResetCommand(base);
-
-    /* Set time delay parameter */
-    base->CTRL = SPIFI_CTRL_TIMEOUT(config->timeout) | SPIFI_CTRL_CSHIGH(config->csHighTime) |
-                 SPIFI_CTRL_D_PRFTCH_DIS(config->disablePrefetch) | SPIFI_CTRL_MODE3(config->spiMode) |
-                 SPIFI_CTRL_PRFTCH_DIS(config->disableCachePrefech) | SPIFI_CTRL_DUAL(config->dualMode) |
-                 SPIFI_CTRL_RFCLK(config->isReadFullClockCycle) | SPIFI_CTRL_FBCLK(config->isFeedbackClock);
-}
-
-void SPIFI_Deinit(SPIFI_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the SAI clock */
-    CLOCK_DisableClock(s_spifiClock[SPIFI_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd)
-{
-    /* Wait for the CMD and MCINT flag all be 0 */
-    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
-    {
-    }
-    base->CMD = SPIFI_CMD_DATALEN(cmd->dataLen) | SPIFI_CMD_POLL(cmd->isPollMode) | SPIFI_CMD_DOUT(cmd->direction) |
-                SPIFI_CMD_INTLEN(cmd->intermediateBytes) | SPIFI_CMD_FIELDFORM(cmd->format) |
-                SPIFI_CMD_FRAMEFORM(cmd->type) | SPIFI_CMD_OPCODE(cmd->opcode);
-
-    /* Wait for the command written */
-    while ((base->STAT & SPIFI_STAT_CMD_MASK) == 0U)
-    {
-    }
-}
-
-void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd)
-{
-    /* Wait for the CMD and MCINT flag all be 0 */
-    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
-    {
-    }
-
-    base->MCMD = SPIFI_MCMD_POLL(0U) | SPIFI_MCMD_DOUT(0U) | SPIFI_MCMD_INTLEN(cmd->intermediateBytes) |
-                 SPIFI_MCMD_FIELDFORM(cmd->format) | SPIFI_MCMD_FRAMEFORM(cmd->type) | SPIFI_MCMD_OPCODE(cmd->opcode);
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,379 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SPIFI_H_
-#define _FSL_SPIFI_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup spifi
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief SPIFI driver version 2.0.0. */
-#define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief Status structure of SPIFI.*/
-enum _status_t
-{
-    kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0),  /*!< SPIFI is in idle state  */
-    kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1),  /*!< SPIFI is busy */
-    kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */
-};
-
-/*! @brief SPIFI interrupt source */
-typedef enum _spifi_interrupt_enable
-{
-    kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */
-} spifi_interrupt_enable_t;
-
-/*! @brief SPIFI SPI mode select */
-typedef enum _spifi_spi_mode
-{
-    kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */
-    kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */
-} spifi_spi_mode_t;
-
-/*! @brief SPIFI dual mode select */
-typedef enum _spifi_dual_mode
-{
-    kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */
-    kSPIFI_DualMode = 0x1U  /*!< SPIFI uses IO1:0 */
-} spifi_dual_mode_t;
-
-/*! @brief SPIFI data direction */
-typedef enum _spifi_data_direction
-{
-    kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
-    kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
-} spifi_data_direction_t;
-
-/*! @brief SPIFI command opcode format */
-typedef enum _spifi_command_format
-{
-    kSPIFI_CommandAllSerial = 0x0,     /*!< All fields of command are serial. */
-    kSPIFI_CommandDataQuad = 0x1U,     /*!< Only data field is dual/quad, others are serial. */
-    kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
-    kSPIFI_CommandAllQuad = 0x3U       /*!< All fields of command are dual/quad mode. */
-} spifi_command_format_t;
-
-/*! @brief SPIFI command type */
-typedef enum _spifi_command_type
-{
-    kSPIFI_CommandOpcodeOnly = 0x1U,             /*!< Command only have opcode, no address field */
-    kSPIFI_CommandOpcodeAddrOneByte = 0x2U,      /*!< Command have opcode and also one byte address field */
-    kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U,     /*!< Command have opcode and also two bytes address field */
-    kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U,   /*!< Command have opcode and also three bytes address field. */
-    kSPIFI_CommandOpcodeAddrFourBytes = 0x5U,    /*!< Command have opcode and also four bytes address field */
-    kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
-    kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U   /*!< Command have no opcode and four bytes address field */
-} spifi_command_type_t;
-
-/*! @brief SPIFI status flags */
-enum _spifi_status_flags
-{
-    kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */
-    kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK,          /*!< Command write finished */
-    kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */
-};
-
-/*! @brief SPIFI command structure */
-typedef struct _spifi_command
-{
-    uint16_t dataLen;                 /*!< How many data bytes are needed in this command. */
-    bool isPollMode;                  /*!< For command need to read data from serial flash */
-    spifi_data_direction_t direction; /*!< Data direction of this command. */
-    uint8_t intermediateBytes;        /*!< How many intermediate bytes needed */
-    spifi_command_format_t format;    /*!< Command format */
-    spifi_command_type_t type;        /*!< Command type */
-    uint8_t opcode;                   /*!< Command opcode value */
-} spifi_command_t;
-
-/*!
- * @brief SPIFI region configuration structure.
- */
-typedef struct _spifi_config
-{
-    uint16_t timeout;           /*!< SPI transfer timeout, the unit is SCK cycles */
-    uint8_t csHighTime;         /*!< CS high time cycles */
-    bool disablePrefetch;       /*!< True means SPIFI will not attempt a speculative prefetch. */
-    bool disableCachePrefech;   /*!< Disable prefetch of cache line */
-    bool isFeedbackClock;       /*!< Is data sample uses feedback clock. */
-    spifi_spi_mode_t spiMode;   /*!< SPIFI spi mode select */
-    bool isReadFullClockCycle;  /*!< If enable read full clock cycle. */
-    spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */
-} spifi_config_t;
-
-/*! @brief Transfer structure for SPIFI */
-typedef struct _spifi_transfer
-{
-    uint8_t *data;   /*!< Pointer to data to transmit */
-    size_t dataSize; /*!< Bytes to be transmit */
-} spifi_transfer_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes the SPIFI with the user configuration structure.
- *
- * This function configures the SPIFI module with the user-defined configuration.
- *
- * @param base     SPIFI peripheral base address.
- * @param config   The pointer to the configuration structure.
- */
-void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config);
-
-/*!
- * @brief Get SPIFI default configure settings.
- *
- * @param config  SPIFI config structure pointer.
- */
-void SPIFI_GetDefaultConfig(spifi_config_t *config);
-
-/*!
- * @brief Deinitializes the SPIFI regions.
- *
- * @param base     SPIFI peripheral base address.
- */
-void SPIFI_Deinit(SPIFI_Type *base);
-
-/* @}*/
-
-/*!
- * @name Basic Control Operations
- * @{
- */
-
-/*!
- * @brief Set SPIFI flash command.
- *
- * @param base     SPIFI peripheral base address.
- * @param cmd      SPIFI command structure pointer.
- */
-void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd);
-
-/*!
- * @brief Set SPIFI command address.
- *
- * @param base     SPIFI peripheral base address.
- * @param addr     Address value for the command.
- */
-static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr)
-{
-    base->ADDR = addr;
-}
-
-/*!
- * @brief Set SPIFI intermediate data.
- *
- * Before writing a command wihch needs specific intermediate value, users shall call this function to write it.
- * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As
- * dummy cycle do not care about the value, no need to call this function.
- *
- * @param base     SPIFI peripheral base address.
- * @param val      Intermediate data.
- */
-static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val)
-{
-    base->IDATA = val;
-}
-
-/*!
- * @brief Set SPIFI Cache limit value.
- *
- * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this
- * function, to prevent such caching at and above the address.
- *
- * @param base     SPIFI peripheral base address.
- * @param val     Zero-based upper limit of cacheable memory.
- */
-static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val)
-{
-    base->CLIMIT = val;
-}
-
-/*!
- * @brief Reset the command field of SPIFI.
- *
- * This function is used to abort the current command or memory mode.
- *
- * @param base     SPIFI peripheral base address.
- */
-static inline void SPIFI_ResetCommand(SPIFI_Type *base)
-{
-    base->STAT = SPIFI_STAT_RESET_MASK;
-    /* Wait for the RESET flag cleared by HW */
-    while (base->STAT & SPIFI_STAT_RESET_MASK)
-    {
-    }
-}
-
-/*!
- * @brief Set SPIFI flash AHB read command.
- *
- * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall
- * be called.
- *
- * @param base     SPIFI peripheral base address.
- * @param cmd      SPIFI command structure pointer.
- */
-void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd);
-
-/*!
- * @brief Enable SPIFI interrupt.
- *
- * The interrupt is triggered only in command mode, and it means the command now is finished.
- *
- * @param base     SPIFI peripheral base address.
- * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
- *                 enumeration :: spifi_interrupt_enable_t
- */
-static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask)
-{
-    base->CTRL |= mask;
-}
-
-/*!
- * @brief Disable SPIFI interrupt.
- *
- * The interrupt is triggered only in command mode, and it means the command now is finished.
- *
- * @param base     SPIFI peripheral base address.
- * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
- *                 enumeration :: spifi_interrupt_enable_t
- */
-static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask)
-{
-    base->CTRL &= ~mask;
-}
-
-/*!
- * @name Status
- * @{
- */
-
-/*!
- * @brief Get the status of all interrupt flags for SPIFI.
- *
- * @param base     SPIFI peripheral base address.
- * @return SPIFI flag status
- */
-static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base)
-{
-    return base->STAT;
-}
-
-/* @}*/
-
-/*!
- * @brief Enable or disable DMA request for SPIFI.
- *
- * @param base     SPIFI peripheral base address.
- * @param enable   True means enable DMA and false means disable DMA.
- */
-static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CTRL |= SPIFI_CTRL_DMAEN_MASK;
-    }
-    else
-    {
-        base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK;
-    }
-}
-
-/*!
- * @brief  Gets the SPIFI data register address.
- *
- * This API is used to provide a transfer address for the SPIFI DMA transfer configuration.
- *
- * @param base SPIFI base pointer
- * @return data register address
- */
-static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base)
-{
-    return (uint32_t)(&(base->DATA));
-}
-
-/*!
- * @brief Write a word data in address of SPIFI.
- *
- * Users can write a page or at least a word data into SPIFI address.
- *
- * @param base     SPIFI peripheral base address.
- * @param data     Data need be write.
- */
-static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data)
-{
-    base->DATA = data;
-}
-
-/*!
- * @brief Read data from serial flash.
- *
- * Users should notice before call this function, the data length field in command register shall larger
- * than 4, otherwise a hardfault will happen.
- *
- * @param base     SPIFI peripheral base address.
- * @return Data input from flash.
- */
-static inline uint32_t SPIFI_ReadData(SPIFI_Type *base)
-{
-    return base->DATA;
-}
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_SPIFI_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,313 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_spifi_dma.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*<! Structure definition for spifi_dma_private_handle_t. The structure is private. */
-typedef struct _spifi_dma_private_handle
-{
-    SPIFI_Type *base;
-    spifi_dma_handle_t *handle;
-} spifi_dma_private_handle_t;
-
-/* SPIFI DMA transfer handle. */
-enum _spifi_dma_tansfer_states
-{
-    kSPIFI_Idle,   /* TX idle. */
-    kSPIFI_BusBusy /* RX busy. */
-};
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*<! Private handle only used for internally. */
-static spifi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPIFI_COUNT][2];
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief SPIFI DMA send finished callback function.
- *
- * This function is called when SPIFI DMA send finished. It disables the SPIFI
- * TX DMA request and sends @ref kStatus_SPIFI_TxIdle to SPIFI callback.
- *
- * @param handle The DMA handle.
- * @param param Callback function parameter.
- */
-static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
-
-/*!
- * @brief SPIFI DMA receive finished callback function.
- *
- * This function is called when SPIFI DMA receive finished. It disables the SPIFI
- * RX DMA request and sends @ref kStatus_SPIFI_RxIdle to SPIFI callback.
- *
- * @param handle The DMA handle.
- * @param param Callback function parameter.
- */
-static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
-
-/*!
- * @brief Get the SPIFI instance from peripheral base address.
- *
- * @param base SPIFI peripheral base address.
- * @return SPIFI instance.
- */
-extern uint32_t SPIFI_GetInstance(SPIFI_Type *base);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
-{
-    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
-
-    /* Avoid the warning for unused variables. */
-    handle = handle;
-    intmode = intmode;
-
-    if (transferDone)
-    {
-        SPIFI_TransferAbortSendDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
-
-        if (spifiPrivateHandle->handle->callback)
-        {
-            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
-                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
-        }
-    }
-}
-
-static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
-{
-    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
-
-    /* Avoid warning for unused parameters. */
-    handle = handle;
-    intmode = intmode;
-
-    if (transferDone)
-    {
-        /* Disable transfer. */
-        SPIFI_TransferAbortReceiveDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
-
-        if (spifiPrivateHandle->handle->callback)
-        {
-            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
-                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
-        }
-    }
-}
-
-void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
-                                     spifi_dma_handle_t *handle,
-                                     spifi_dma_callback_t callback,
-                                     void *userData,
-                                     dma_handle_t *dmaHandle)
-{
-    assert(handle);
-
-    uint32_t instance = SPIFI_GetInstance(base);
-
-    s_dmaPrivateHandle[instance][0].base = base;
-    s_dmaPrivateHandle[instance][0].handle = handle;
-
-    memset(handle, 0, sizeof(*handle));
-
-    handle->state = kSPIFI_Idle;
-    handle->dmaHandle = dmaHandle;
-
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* Configure TX dma callback */
-    DMA_SetCallback(handle->dmaHandle, SPIFI_SendDMACallback, &s_dmaPrivateHandle[instance][0]);
-}
-
-void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
-                                     spifi_dma_handle_t *handle,
-                                     spifi_dma_callback_t callback,
-                                     void *userData,
-                                     dma_handle_t *dmaHandle)
-{
-    assert(handle);
-
-    uint32_t instance = SPIFI_GetInstance(base);
-
-    s_dmaPrivateHandle[instance][1].base = base;
-    s_dmaPrivateHandle[instance][1].handle = handle;
-
-    memset(handle, 0, sizeof(*handle));
-
-    handle->state = kSPIFI_Idle;
-    handle->dmaHandle = dmaHandle;
-
-    handle->callback = callback;
-    handle->userData = userData;
-
-    /* Configure RX dma callback */
-    DMA_SetCallback(handle->dmaHandle, SPIFI_ReceiveDMACallback, &s_dmaPrivateHandle[instance][1]);
-}
-
-status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
-{
-    assert(handle && (handle->dmaHandle));
-
-    dma_transfer_config_t xferConfig;
-    status_t status;
-
-    /* If previous TX not finished. */
-    if (kSPIFI_BusBusy == handle->state)
-    {
-        status = kStatus_SPIFI_Busy;
-    }
-    else
-    {
-        handle->state = kSPIFI_BusBusy;
-
-        /* Prepare transfer. */
-        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)SPIFI_GetDataRegisterAddress(base), sizeof(uint32_t),
-                            xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
-
-        /* Submit transfer. */
-        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-        DMA_StartTransfer(handle->dmaHandle);
-
-        /* Enable SPIFI TX DMA. */
-        SPIFI_EnableDMA(base, true);
-
-        status = kStatus_Success;
-    }
-
-    return status;
-}
-
-status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
-{
-    assert(handle && (handle->dmaHandle));
-
-    dma_transfer_config_t xferConfig;
-    status_t status;
-
-    /* If previous TX not finished. */
-    if (kSPIFI_BusBusy == handle->state)
-    {
-        status = kStatus_SPIFI_Busy;
-    }
-    else
-    {
-        handle->state = kSPIFI_BusBusy;
-
-        /* Prepare transfer. */
-        DMA_PrepareTransfer(&xferConfig, (void *)SPIFI_GetDataRegisterAddress(base), xfer->data, sizeof(uint32_t),
-                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
-
-        /* Submit transfer. */
-        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-        DMA_StartTransfer(handle->dmaHandle);
-
-        /* Enable SPIFI TX DMA. */
-        SPIFI_EnableDMA(base, true);
-
-        status = kStatus_Success;
-    }
-
-    return status;
-}
-
-void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
-{
-    assert(handle && (handle->dmaHandle));
-
-    /* Disable SPIFI TX DMA. */
-    SPIFI_EnableDMA(base, false);
-
-    /* Stop transfer. */
-    DMA_AbortTransfer(handle->dmaHandle);
-
-    handle->state = kSPIFI_Idle;
-}
-
-void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
-{
-    assert(handle && (handle->dmaHandle));
-
-    /* Disable SPIFI RX DMA. */
-    SPIFI_EnableDMA(base, false);
-
-    /* Stop transfer. */
-    DMA_AbortTransfer(handle->dmaHandle);
-
-    handle->state = kSPIFI_Idle;
-}
-
-status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    status_t status = kStatus_Success;
-
-    if (handle->state != kSPIFI_BusBusy)
-    {
-        status = kStatus_NoTransferInProgress;
-    }
-    else
-    {
-        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
-    }
-
-    return status;
-}
-
-status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
-{
-    assert(handle);
-
-    status_t status = kStatus_Success;
-
-    if (handle->state != kSPIFI_BusBusy)
-    {
-        status = kStatus_NoTransferInProgress;
-    }
-    else
-    {
-        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
-    }
-
-    return status;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,172 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_SPIFI_DMA_H_
-#define _FSL_SPIFI_DMA_H_
-
-#include "fsl_dma.h"
-#include "fsl_spifi.h"
-
-/*!
- * @addtogroup spifi
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-typedef struct _spifi_dma_handle spifi_dma_handle_t;
-
-/*! @brief SPIFI DMA transfer callback function for finish and error */
-typedef void (*spifi_dma_callback_t)(SPIFI_Type *base, spifi_dma_handle_t *handle, status_t status, void *userData);
-
-/*! @brief SPIFI DMA transfer handle, users should not touch the content of the handle.*/
-struct _spifi_dma_handle
-{
-    dma_handle_t *dmaHandle;       /*!< DMA handler for SPIFI send */
-    size_t transferSize;           /*!< Bytes need to transfer. */
-    uint32_t state;                /*!< Internal state for SPIFI DMA transfer */
-    spifi_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
-    void *userData;                /*!< User callback parameter */
-};
-
-/*******************************************************************************
- * APIs
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @name DMA Transactional
- * @{
- */
-
-/*!
- * @brief Initializes the SPIFI handle for send which is used in transactional functions and set the callback.
- *
- * @param base SPIFI peripheral base address
- * @param handle Pointer to spifi_dma_handle_t structure
- * @param callback SPIFI callback, NULL means no callback.
- * @param userData User callback function data.
- * @param rxDmaHandle User requested DMA handle for DMA transfer
- */
-void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
-                                     spifi_dma_handle_t *handle,
-                                     spifi_dma_callback_t callback,
-                                     void *userData,
-                                     dma_handle_t *dmaHandle);
-
-/*!
- * @brief Initializes the SPIFI handle for receive which is used in transactional functions and set the callback.
- *
- * @param base SPIFI peripheral base address
- * @param handle Pointer to spifi_dma_handle_t structure
- * @param callback SPIFI callback, NULL means no callback.
- * @param userData User callback function data.
- * @param rxDmaHandle User requested DMA handle for DMA transfer
- */
-void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
-                                     spifi_dma_handle_t *handle,
-                                     spifi_dma_callback_t callback,
-                                     void *userData,
-                                     dma_handle_t *dmaHandle);
-
-/*!
- * @brief Transfers SPIFI data using an DMA non-blocking method.
- *
- * This function writes data to the SPIFI transmit FIFO. This function is non-blocking.
- * @param base Pointer to QuadSPI Type.
- * @param handle Pointer to spifi_dma_handle_t structure
- * @param xfer SPIFI transfer structure.
- */
-status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
-
-/*!
- * @brief Receives data using an DMA non-blocking method.
- *
- * This function receive data from the SPIFI receive buffer/FIFO. This function is non-blocking.
- * @param base Pointer to QuadSPI Type.
- * @param handle Pointer to spifi_dma_handle_t structure
- * @param xfer SPIFI transfer structure.
- */
-status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
-
-/*!
- * @brief Aborts the sent data using DMA.
- *
- * This function aborts the sent data using DMA.
- *
- * @param base SPIFI peripheral base address.
- * @param handle Pointer to spifi_dma_handle_t structure
- */
-void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
-
-/*!
- * @brief Aborts the receive data using DMA.
- *
- * This function abort receive data which using DMA.
- *
- * @param base SPIFI peripheral base address.
- * @param handle Pointer to spifi_dma_handle_t structure
- */
-void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
-
-/*!
- * @brief Gets the transferred counts of send.
- *
- * @param base Pointer to QuadSPI Type.
- * @param handle Pointer to spifi_dma_handle_t structure.
- * @param count Bytes sent.
- * @retval kStatus_Success Succeed get the transfer count.
- * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
- */
-status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
-
-/*!
- * @brief Gets the status of the receive transfer.
- *
- * @param base Pointer to QuadSPI Type.
- * @param handle Pointer to spifi_dma_handle_t structure
- * @param count Bytes received.
- * @retval kStatus_Success Succeed get the transfer count.
- * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
- */
-status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/* @} */
-
-#endif /* _FSL_SPIFI_DMA_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,708 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_usart.h"
-#include "fsl_device_registers.h"
-#include "fsl_flexcomm.h"
-
-enum _usart_transfer_states
-{
-    kUSART_TxIdle, /* TX idle. */
-    kUSART_TxBusy, /* TX busy. */
-    kUSART_RxIdle, /* RX idle. */
-    kUSART_RxBusy  /* RX busy. */
-};
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-/*! @brief IRQ name array */
-static const IRQn_Type s_usartIRQ[] = USART_IRQS;
-
-/*! @brief Array to map USART instance number to base address. */
-static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/* Get the index corresponding to the USART */
-uint32_t USART_GetInstance(USART_Type *base)
-{
-    int i;
-
-    for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)
-    {
-        if ((uint32_t)base == s_usartBaseAddrs[i])
-        {
-            return i;
-        }
-    }
-
-    assert(false);
-    return 0;
-}
-
-static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
-{
-    size_t size;
-
-    /* Check arguments */
-    assert(NULL != handle);
-
-    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
-    {
-        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
-    }
-    else
-    {
-        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
-    }
-    return size;
-}
-
-static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
-{
-    bool full;
-
-    /* Check arguments */
-    assert(NULL != handle);
-
-    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
-    {
-        full = true;
-    }
-    else
-    {
-        full = false;
-    }
-    return full;
-}
-
-void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
-{
-    /* Check arguments */
-    assert(NULL != base);
-    assert(NULL != handle);
-    assert(NULL != ringBuffer);
-
-    /* Setup the ringbuffer address */
-    handle->rxRingBuffer = ringBuffer;
-    handle->rxRingBufferSize = ringBufferSize;
-    handle->rxRingBufferHead = 0U;
-    handle->rxRingBufferTail = 0U;
-    /* ring buffer is ready we can start receiving data */
-    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
-}
-
-void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
-{
-    /* Check arguments */
-    assert(NULL != base);
-    assert(NULL != handle);
-
-    if (handle->rxState == kUSART_RxIdle)
-    {
-        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
-    }
-    handle->rxRingBuffer = NULL;
-    handle->rxRingBufferSize = 0U;
-    handle->rxRingBufferHead = 0U;
-    handle->rxRingBufferTail = 0U;
-}
-
-status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
-{
-    int result;
-
-    /* check arguments */
-    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
-    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* initialize flexcomm to USART mode */
-    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
-    if (kStatus_Success != result)
-    {
-        return result;
-    }
-
-    /* setup baudrate */
-    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
-    if (kStatus_Success != result)
-    {
-        return result;
-    }
-
-    if (config->enableTx)
-    {
-        /* empty and enable txFIFO */
-        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
-        /* setup trigger level */
-        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
-        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
-        /* enable trigger interrupt */
-        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
-    }
-
-    /* empty and enable rxFIFO */
-    if (config->enableRx)
-    {
-        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
-        /* setup trigger level */
-        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
-        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
-        /* enable trigger interrupt */
-        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
-    }
-    /* setup configuration and enable USART */
-    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
-                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;
-    return kStatus_Success;
-}
-
-void USART_Deinit(USART_Type *base)
-{
-    /* Check arguments */
-    assert(NULL != base);
-    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
-    {
-    }
-    /* Disable interrupts, disable dma requests, disable peripheral */
-    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
-                         USART_FIFOINTENCLR_RXLVL_MASK;
-    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
-    base->CFG &= ~(USART_CFG_ENABLE_MASK);
-}
-
-void USART_GetDefaultConfig(usart_config_t *config)
-{
-    /* Check arguments */
-    assert(NULL != config);
-
-    /* Set always all members ! */
-    config->baudRate_Bps = 115200U;
-    config->parityMode = kUSART_ParityDisabled;
-    config->stopBitCount = kUSART_OneStopBit;
-    config->bitCountPerChar = kUSART_8BitsPerChar;
-    config->loopback = false;
-    config->enableRx = false;
-    config->enableTx = false;
-    config->txWatermark = kUSART_TxFifo0;
-    config->rxWatermark = kUSART_RxFifo1;
-}
-
-status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
-{
-    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
-    uint32_t osrval, brgval, diff, baudrate;
-
-    /* check arguments */
-    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
-    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /*
-     * Smaller values of OSR can make the sampling position within a data bit less accurate and may
-     * potentially cause more noise errors or incorrect data.
-     */
-    for (osrval = best_osrval; osrval >= 8; osrval--)
-    {
-        brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;
-        if (brgval > 0xFFFF)
-        {
-            continue;
-        }
-        baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));
-        diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
-        if (diff < best_diff)
-        {
-            best_diff = diff;
-            best_osrval = osrval;
-            best_brgval = brgval;
-        }
-    }
-
-    /* value over range */
-    if (best_brgval > 0xFFFF)
-    {
-        return kStatus_USART_BaudrateNotSupport;
-    }
-
-    base->OSR = best_osrval;
-    base->BRG = best_brgval;
-    return kStatus_Success;
-}
-
-void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
-{
-    /* Check arguments */
-    assert(!((NULL == base) || (NULL == data)));
-    if ((NULL == base) || (NULL == data))
-    {
-        return;
-    }
-    /* Check whether txFIFO is enabled */
-    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
-    {
-        return;
-    }
-    for (; length > 0; length--)
-    {
-        /* Loop until txFIFO get some space for new data */
-        while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
-        {
-        }
-        base->FIFOWR = *data;
-        data++;
-    }
-    /* Wait to finish transfer */
-    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
-    {
-    }
-}
-
-status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
-{
-    uint32_t status;
-
-    /* check arguments */
-    assert(!((NULL == base) || (NULL == data)));
-    if ((NULL == base) || (NULL == data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Check whether rxFIFO is enabled */
-    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))
-    {
-        return kStatus_Fail;
-    }
-    for (; length > 0; length--)
-    {
-        /* loop until rxFIFO have some data to read */
-        while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
-        {
-        }
-        /* check receive status */
-        status = base->STAT;
-        if (status & USART_STAT_FRAMERRINT_MASK)
-        {
-            base->STAT |= USART_STAT_FRAMERRINT_MASK;
-            return kStatus_USART_FramingError;
-        }
-        if (status & USART_STAT_PARITYERRINT_MASK)
-        {
-            base->STAT |= USART_STAT_PARITYERRINT_MASK;
-            return kStatus_USART_ParityError;
-        }
-        if (status & USART_STAT_RXNOISEINT_MASK)
-        {
-            base->STAT |= USART_STAT_RXNOISEINT_MASK;
-            return kStatus_USART_NoiseError;
-        }
-        /* check rxFIFO status */
-        if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
-        {
-            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
-            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
-            return kStatus_USART_RxError;
-        }
-
-        *data = base->FIFORD;
-        data++;
-    }
-    return kStatus_Success;
-}
-
-status_t USART_TransferCreateHandle(USART_Type *base,
-                                    usart_handle_t *handle,
-                                    usart_transfer_callback_t callback,
-                                    void *userData)
-{
-    int32_t instance = 0;
-
-    /* Check 'base' */
-    assert(!((NULL == base) || (NULL == handle)));
-    if ((NULL == base) || (NULL == handle))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    instance = USART_GetInstance(base);
-
-    memset(handle, 0, sizeof(*handle));
-    /* Set the TX/RX state. */
-    handle->rxState = kUSART_RxIdle;
-    handle->txState = kUSART_TxIdle;
-    /* Set the callback and user data. */
-    handle->callback = callback;
-    handle->userData = userData;
-    handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);
-    handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);
-
-    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle);
-
-    /* Enable interrupt in NVIC. */
-    EnableIRQ(s_usartIRQ[instance]);
-
-    return kStatus_Success;
-}
-
-status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
-{
-    /* Check arguments */
-    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
-    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* Check xfer members */
-    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
-    if ((0 == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* Return error if current TX busy. */
-    if (kUSART_TxBusy == handle->txState)
-    {
-        return kStatus_USART_TxBusy;
-    }
-    else
-    {
-        handle->txData = xfer->data;
-        handle->txDataSize = xfer->dataSize;
-        handle->txDataSizeAll = xfer->dataSize;
-        handle->txState = kUSART_TxBusy;
-        /* Enable transmiter interrupt. */
-        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
-    }
-    return kStatus_Success;
-}
-
-void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    /* Disable interrupts */
-    base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK;
-    /* Empty txFIFO */
-    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
-
-    handle->txDataSize = 0;
-    handle->txState = kUSART_TxIdle;
-}
-
-status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
-{
-    assert(NULL != handle);
-    assert(NULL != count);
-
-    if (kUSART_TxIdle == handle->txState)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->txDataSizeAll - handle->txDataSize;
-
-    return kStatus_Success;
-}
-
-status_t USART_TransferReceiveNonBlocking(USART_Type *base,
-                                          usart_handle_t *handle,
-                                          usart_transfer_t *xfer,
-                                          size_t *receivedBytes)
-{
-    uint32_t i;
-    /* How many bytes to copy from ring buffer to user memory. */
-    size_t bytesToCopy = 0U;
-    /* How many bytes to receive. */
-    size_t bytesToReceive;
-    /* How many bytes currently have received. */
-    size_t bytesCurrentReceived;
-    uint32_t regPrimask = 0U;
-
-    /* Check arguments */
-    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
-    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* Check xfer members */
-    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
-    if ((0 == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    /* How to get data:
-       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
-          to uart handle, enable interrupt to store received data to xfer->data. When
-          all data received, trigger callback.
-       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
-          If there are enough data in ring buffer, copy them to xfer->data and return.
-          If there are not enough data in ring buffer, copy all of them to xfer->data,
-          save the xfer->data remained empty space to uart handle, receive data
-          to this empty space and trigger callback when finished. */
-    if (kUSART_RxBusy == handle->rxState)
-    {
-        return kStatus_USART_RxBusy;
-    }
-    else
-    {
-        bytesToReceive = xfer->dataSize;
-        bytesCurrentReceived = 0U;
-        /* If RX ring buffer is used. */
-        if (handle->rxRingBuffer)
-        {
-            /* Disable IRQ, protect ring buffer. */
-            regPrimask = DisableGlobalIRQ();
-            /* How many bytes in RX ring buffer currently. */
-            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
-            if (bytesToCopy)
-            {
-                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
-                bytesToReceive -= bytesToCopy;
-                /* Copy data from ring buffer to user memory. */
-                for (i = 0U; i < bytesToCopy; i++)
-                {
-                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
-                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
-                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
-                    {
-                        handle->rxRingBufferTail = 0U;
-                    }
-                    else
-                    {
-                        handle->rxRingBufferTail++;
-                    }
-                }
-            }
-            /* If ring buffer does not have enough data, still need to read more data. */
-            if (bytesToReceive)
-            {
-                /* No data in ring buffer, save the request to UART handle. */
-                handle->rxData = xfer->data + bytesCurrentReceived;
-                handle->rxDataSize = bytesToReceive;
-                handle->rxDataSizeAll = bytesToReceive;
-                handle->rxState = kUSART_RxBusy;
-            }
-            /* Enable IRQ if previously enabled. */
-            EnableGlobalIRQ(regPrimask);
-            /* Call user callback since all data are received. */
-            if (0 == bytesToReceive)
-            {
-                if (handle->callback)
-                {
-                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
-                }
-            }
-        }
-        /* Ring buffer not used. */
-        else
-        {
-            handle->rxData = xfer->data + bytesCurrentReceived;
-            handle->rxDataSize = bytesToReceive;
-            handle->rxDataSizeAll = bytesToReceive;
-            handle->rxState = kUSART_RxBusy;
-
-            /* Enable RX interrupt. */
-            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
-        }
-        /* Return the how many bytes have read. */
-        if (receivedBytes)
-        {
-            *receivedBytes = bytesCurrentReceived;
-        }
-    }
-    return kStatus_Success;
-}
-
-void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
-{
-    assert(NULL != handle);
-
-    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
-    if (!handle->rxRingBuffer)
-    {
-        /* Disable interrupts */
-        base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK;
-        /* Empty rxFIFO */
-        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
-    }
-
-    handle->rxDataSize = 0U;
-    handle->rxState = kUSART_RxIdle;
-}
-
-status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
-{
-    assert(NULL != handle);
-    assert(NULL != count);
-
-    if (kUSART_RxIdle == handle->rxState)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->rxDataSizeAll - handle->rxDataSize;
-
-    return kStatus_Success;
-}
-
-void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
-{
-    /* Check arguments */
-    assert((NULL != base) && (NULL != handle));
-
-    bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);
-    bool sendEnabled = handle->txDataSize;
-
-    /* If RX overrun. */
-    if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
-    {
-        /* Clear rx error state. */
-        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
-        /* clear rxFIFO */
-        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
-        /* Trigger callback. */
-        if (handle->callback)
-        {
-            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
-        }
-    }
-    while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
-           (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
-    {
-        /* Receive data */
-        if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
-        {
-            /* Receive to app bufffer if app buffer is present */
-            if (handle->rxDataSize)
-            {
-                *handle->rxData = base->FIFORD;
-                handle->rxDataSize--;
-                handle->rxData++;
-                receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));
-                if (!handle->rxDataSize)
-                {
-                    if (!handle->rxRingBuffer)
-                    {
-                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
-                    }
-                    handle->rxState = kUSART_RxIdle;
-                    if (handle->callback)
-                    {
-                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
-                    }
-                }
-            }
-            /* Otherwise receive to ring buffer if ring buffer is present */
-            else
-            {
-                if (handle->rxRingBuffer)
-                {
-                    /* If RX ring buffer is full, trigger callback to notify over run. */
-                    if (USART_TransferIsRxRingBufferFull(handle))
-                    {
-                        if (handle->callback)
-                        {
-                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
-                        }
-                    }
-                    /* If ring buffer is still full after callback function, the oldest data is overrided. */
-                    if (USART_TransferIsRxRingBufferFull(handle))
-                    {
-                        /* Increase handle->rxRingBufferTail to make room for new data. */
-                        if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
-                        {
-                            handle->rxRingBufferTail = 0U;
-                        }
-                        else
-                        {
-                            handle->rxRingBufferTail++;
-                        }
-                    }
-                    /* Read data. */
-                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;
-                    /* Increase handle->rxRingBufferHead. */
-                    if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
-                    {
-                        handle->rxRingBufferHead = 0U;
-                    }
-                    else
-                    {
-                        handle->rxRingBufferHead++;
-                    }
-                }
-            }
-        }
-        /* Send data */
-        if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
-        {
-            base->FIFOWR = *handle->txData;
-            handle->txDataSize--;
-            handle->txData++;
-            sendEnabled = handle->txDataSize != 0;
-            if (!sendEnabled)
-            {
-                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
-                handle->txState = kUSART_TxIdle;
-                if (handle->callback)
-                {
-                    handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
-                }
-            }
-        }
-    }
-
-    /* ring buffer is not used */
-    if (NULL == handle->rxRingBuffer)
-    {
-        /* restore if rx transfer ends and rxLevel is different from default value */
-        if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
-        {
-            base->FIFOTRIG =
-                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
-        }
-        /* decrease level if rx transfer is bellow */
-        if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))
-        {
-            base->FIFOTRIG =
-                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));
-        }
-    }
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_USART_H_
-#define _FSL_USART_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup usart_driver
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief USART driver version 2.0.0. */
-#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
-#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
-
-/*! @brief Error codes for the USART driver. */
-enum _usart_status
-{
-    kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0),              /*!< Transmitter is busy. */
-    kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1),              /*!< Receiver is busy. */
-    kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2),              /*!< USART transmitter is idle. */
-    kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3),              /*!< USART receiver is idle. */
-    kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7),             /*!< Error happens on txFIFO. */
-    kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9),             /*!< Error happens on rxFIFO. */
-    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
-    kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10),         /*!< USART noise error. */
-    kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11),       /*!< USART framing error. */
-    kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12),        /*!< USART parity error. */
-    kStatus_USART_BaudrateNotSupport =
-        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
-};
-
-/*! @brief USART parity mode. */
-typedef enum _usart_parity_mode
-{
-    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
-    kUSART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
-    kUSART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
-} usart_parity_mode_t;
-
-/*! @brief USART stop bit count. */
-typedef enum _usart_stop_bit_count
-{
-    kUSART_OneStopBit = 0U, /*!< One stop bit */
-    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
-} usart_stop_bit_count_t;
-
-/*! @brief USART data size. */
-typedef enum _usart_data_len
-{
-    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
-    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
-} usart_data_len_t;
-
-/*! @brief txFIFO watermark values */
-typedef enum _usart_txfifo_watermark
-{
-    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
-    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
-    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
-    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
-    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
-    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
-    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
-    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
-} usart_txfifo_watermark_t;
-
-/*! @brief rxFIFO watermark values */
-typedef enum _usart_rxfifo_watermark
-{
-    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
-    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
-    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
-    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
-    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
-    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
-    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
-    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
-} usart_rxfifo_watermark_t;
-
-/*!
- * @brief USART interrupt configuration structure, default settings all disabled.
- */
-enum _usart_interrupt_enable
-{
-    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
-    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
-    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
-    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
-};
-
-/*!
- * @brief USART status flags.
- *
- * This provides constants for the USART status flags for use in the USART functions.
- */
-enum _usart_flags
-{
-    kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK),                 /*!< TEERR bit, sets if TX buffer is error */
-    kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK),                 /*!< RXERR bit, sets if RX buffer is error */
-    kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK),       /*!< TXEMPTY bit, sets if TX buffer is empty */
-    kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXNOTFULL bit, sets if TX buffer is not full */
-    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
-    kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK),         /*!< RXFULL bit, sets if RX buffer is full */
-};
-
-/*! @brief USART configuration structure. */
-typedef struct _usart_config
-{
-    uint32_t baudRate_Bps;                /*!< USART baud rate  */
-    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
-    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
-    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
-    bool loopback;                        /*!< Enable peripheral loopback */
-    bool enableRx;                        /*!< Enable RX */
-    bool enableTx;                        /*!< Enable TX */
-    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
-    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
-} usart_config_t;
-
-/*! @brief USART transfer structure. */
-typedef struct _usart_transfer
-{
-    uint8_t *data;   /*!< The buffer of data to be transfer.*/
-    size_t dataSize; /*!< The byte count to be transfer. */
-} usart_transfer_t;
-
-/* Forward declaration of the handle typedef. */
-typedef struct _usart_handle usart_handle_t;
-
-/*! @brief USART transfer callback function. */
-typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
-
-/*! @brief USART handle structure. */
-struct _usart_handle
-{
-    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
-    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
-    size_t txDataSizeAll;       /*!< Size of the data to send out. */
-    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
-    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
-    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
-
-    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
-    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
-    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
-    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
-
-    usart_transfer_callback_t callback; /*!< Callback function. */
-    void *userData;                     /*!< USART callback function parameter.*/
-
-    volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state */
-
-    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
-    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*! @brief Returns instance number for USART peripheral base address. */
-uint32_t USART_GetInstance(USART_Type *base);
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes a USART instance with user configuration structure and peripheral clock.
- *
- * This function configures the USART module with the user-defined settings. The user can configure the configuration
- * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
- * Example below shows how to use this API to configure USART.
- * @code
- *  usart_config_t usartConfig;
- *  usartConfig.baudRate_Bps = 115200U;
- *  usartConfig.parityMode = kUSART_ParityDisabled;
- *  usartConfig.stopBitCount = kUSART_OneStopBit;
- *  USART_Init(USART1, &usartConfig, 20000000U);
- * @endcode
- *
- * @param base USART peripheral base address.
- * @param config Pointer to user-defined configuration structure.
- * @param srcClock_Hz USART clock source frequency in HZ.
- * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
- * @retval kStatus_InvalidArgument USART base address is not valid
- * @retval kStatus_Success Status USART initialize succeed
- */
-status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
-
-/*!
- * @brief Deinitializes a USART instance.
- *
- * This function waits for TX complete, disables TX and RX, and disables the USART clock.
- *
- * @param base USART peripheral base address.
- */
-void USART_Deinit(USART_Type *base);
-
-/*!
- * @brief Gets the default configuration structure.
- *
- * This function initializes the USART configuration structure to a default value. The default
- * values are:
- *   usartConfig->baudRate_Bps = 115200U;
- *   usartConfig->parityMode = kUSART_ParityDisabled;
- *   usartConfig->stopBitCount = kUSART_OneStopBit;
- *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
- *   usartConfig->loopback = false;
- *   usartConfig->enableTx = false;
- *   usartConfig->enableRx = false;
- *
- * @param config Pointer to configuration structure.
- */
-void USART_GetDefaultConfig(usart_config_t *config);
-
-/*!
- * @brief Sets the USART instance baud rate.
- *
- * This function configures the USART module baud rate. This function is used to update
- * the USART module baud rate after the USART module is initialized by the USART_Init.
- * @code
- *  USART_SetBaudRate(USART1, 115200U, 20000000U);
- * @endcode
- *
- * @param base USART peripheral base address.
- * @param baudrate_Bps USART baudrate to be set.
- * @param srcClock_Hz USART clock source freqency in HZ.
- * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
- * @retval kStatus_Success Set baudrate succeed.
- * @retval kStatus_InvalidArgument One or more arguments are invalid.
- */
-status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
-
-/* @} */
-
-/*!
- * @name Status
- * @{
- */
-
-/*!
- * @brief Get USART status flags.
- *
- * This function get all USART status flags, the flags are returned as the logical
- * OR value of the enumerators @ref _usart_flags. To check a specific status,
- * compare the return value with enumerators in @ref _usart_flags.
- * For example, to check whether the TX is empty:
- * @code
- *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
- *     {
- *         ...
- *     }
- * @endcode
- *
- * @param base USART peripheral base address.
- * @return USART status flags which are ORed by the enumerators in the _usart_flags.
- */
-static inline uint32_t USART_GetStatusFlags(USART_Type *base)
-{
-    return base->FIFOSTAT;
-}
-
-/*!
- * @brief Clear USART status flags.
- *
- * This function clear supported USART status flags
- * Flags that can be cleared or set are:
- *      kUSART_TxError
- *      kUSART_RxError
- * For example:
- * @code
- *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
- * @endcode
- *
- * @param base USART peripheral base address.
- * @param mask status flags to be cleared.
- */
-static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
-{
-    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
-    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
-}
-
-/* @} */
-
-/*!
- * @name Interrupts
- * @{
- */
-
-/*!
- * @brief Enables USART interrupts according to the provided mask.
- *
- * This function enables the USART interrupts according to the provided mask. The mask
- * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
- * For example, to enable TX empty interrupt and RX full interrupt:
- * @code
- *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
- * @endcode
- *
- * @param base USART peripheral base address.
- * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
- */
-static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
-{
-    base->FIFOINTENSET = mask & 0xF;
-}
-
-/*!
- * @brief Disables USART interrupts according to a provided mask.
- *
- * This function disables the USART interrupts according to a provided mask. The mask
- * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
- * This example shows how to disable the TX empty interrupt and RX full interrupt:
- * @code
- *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
- * @endcode
- *
- * @param base USART peripheral base address.
- * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
- */
-static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
-{
-    base->FIFOINTENSET = ~(mask & 0xF);
-}
-
-/*!
-* @brief Enable DMA for Tx
-*/
-static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
-    }
-}
-
-/*!
-* @brief Enable DMA for Rx
-*/
-static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
-    }
-    else
-    {
-        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
-    }
-}
-
-/* @} */
-
-/*!
- * @name Bus Operations
- * @{
- */
-
-/*!
- * @brief Writes to the FIFOWR register.
- *
- * This function writes data to the txFIFO directly. The upper layer must ensure
- * that txFIFO has space for data to write before calling this function.
- *
- * @param base USART peripheral base address.
- * @param data The byte to write.
- */
-static inline void USART_WriteByte(USART_Type *base, uint8_t data)
-{
-    base->FIFOWR = data;
-}
-
-/*!
- * @brief Reads the FIFORD register directly.
- *
- * This function reads data from the rxFIFO directly. The upper layer must
- * ensure that the rxFIFO is not empty before calling this function.
- *
- * @param base USART peripheral base address.
- * @return The byte read from USART data register.
- */
-static inline uint8_t USART_ReadByte(USART_Type *base)
-{
-    return base->FIFORD;
-}
-
-/*!
- * @brief Writes to the TX register using a blocking method.
- *
- * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
- * to have room and writes data to the TX buffer.
- *
- * @param base USART peripheral base address.
- * @param data Start address of the data to write.
- * @param length Size of the data to write.
- */
-void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
-
-/*!
- * @brief Read RX data register using a blocking method.
- *
- * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
- * have data and read data from the TX register.
- *
- * @param base USART peripheral base address.
- * @param data Start address of the buffer to store the received data.
- * @param length Size of the buffer.
- * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
- * @retval kStatus_USART_ParityError Noise error happened while receiving data.
- * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
- * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
- * @retval kStatus_Success Successfully received all data.
- */
-status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
-
-/* @} */
-
-/*!
- * @name Transactional
- * @{
- */
-
-/*!
- * @brief Initializes the USART handle.
- *
- * This function initializes the USART handle which can be used for other USART
- * transactional APIs. Usually, for a specified USART instance,
- * call this API once to get the initialized handle.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param callback The callback function.
- * @param userData The parameter of the callback function.
- */
-status_t USART_TransferCreateHandle(USART_Type *base,
-                                    usart_handle_t *handle,
-                                    usart_transfer_callback_t callback,
-                                    void *userData);
-
-/*!
- * @brief Transmits a buffer of data using the interrupt method.
- *
- * This function sends data using an interrupt method. This is a non-blocking function, which
- * returns directly without waiting for all data to be written to the TX register. When
- * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
- * function and passes the @ref kStatus_USART_TxIdle as status parameter.
- *
- * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
- * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
- * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param xfer USART transfer structure. See  #usart_transfer_t.
- * @retval kStatus_Success Successfully start the data transmission.
- * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
- * @retval kStatus_InvalidArgument Invalid argument.
- */
-status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
-
-/*!
- * @brief Sets up the RX ring buffer.
- *
- * This function sets up the RX ring buffer to a specific USART handle.
- *
- * When the RX ring buffer is used, data received are stored into the ring buffer even when the
- * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
- * in the ring buffer, the user can get the received data from the ring buffer directly.
- *
- * @note When using the RX ring buffer, one byte is reserved for internal use. In other
- * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
- * @param ringBufferSize size of the ring buffer.
- */
-void USART_TransferStartRingBuffer(USART_Type *base,
-                                   usart_handle_t *handle,
-                                   uint8_t *ringBuffer,
-                                   size_t ringBufferSize);
-
-/*!
- * @brief Aborts the background transfer and uninstalls the ring buffer.
- *
- * This function aborts the background transfer and uninstalls the ring buffer.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- */
-void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
-
-/*!
- * @brief Aborts the interrupt-driven data transmit.
- *
- * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
- * how many bytes are still not sent out.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- */
-void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
-
-/*!
- * @brief Get the number of bytes that have been written to USART TX register.
- *
- * This function gets the number of bytes that have been written to USART TX
- * register by interrupt method.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param count Send bytes count.
- * @retval kStatus_NoTransferInProgress No send in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
- * @retval kStatus_Success Get successfully through the parameter \p count;
- */
-status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
-
-/*!
- * @brief Receives a buffer of data using an interrupt method.
- *
- * This function receives data using an interrupt method. This is a non-blocking function, which
- *  returns without waiting for all data to be received.
- * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
- * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
- * After copying, if the data in the ring buffer is not enough to read, the receive
- * request is saved by the USART driver. When the new data arrives, the receive request
- * is serviced first. When all data is received, the USART driver notifies the upper layer
- * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
- * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
- * The 5 bytes are copied to the xfer->data and this function returns with the
- * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
- * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
- * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
- * to receive data to the xfer->data. When all data is received, the upper layer is notified.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param xfer USART transfer structure, see #usart_transfer_t.
- * @param receivedBytes Bytes received from the ring buffer directly.
- * @retval kStatus_Success Successfully queue the transfer into transmit queue.
- * @retval kStatus_USART_RxBusy Previous receive request is not finished.
- * @retval kStatus_InvalidArgument Invalid argument.
- */
-status_t USART_TransferReceiveNonBlocking(USART_Type *base,
-                                          usart_handle_t *handle,
-                                          usart_transfer_t *xfer,
-                                          size_t *receivedBytes);
-
-/*!
- * @brief Aborts the interrupt-driven data receiving.
- *
- * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
- * how many bytes not received yet.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- */
-void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
-
-/*!
- * @brief Get the number of bytes that have been received.
- *
- * This function gets the number of bytes that have been received.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param count Receive bytes count.
- * @retval kStatus_NoTransferInProgress No receive in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
- * @retval kStatus_Success Get successfully through the parameter \p count;
- */
-status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
-
-/*!
- * @brief USART IRQ handle function.
- *
- * This function handles the USART transmit and receive IRQ request.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- */
-void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_USART_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,261 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_usart.h"
-#include "fsl_device_registers.h"
-#include "fsl_dma.h"
-#include "fsl_flexcomm.h"
-#include "fsl_usart_dma.h"
-
-/*<! Structure definition for uart_dma_handle_t. The structure is private. */
-typedef struct _usart_dma_private_handle
-{
-    USART_Type *base;
-    usart_dma_handle_t *handle;
-} usart_dma_private_handle_t;
-
-enum _usart_transfer_states
-{
-    kUSART_TxIdle, /* TX idle. */
-    kUSART_TxBusy, /* TX busy. */
-    kUSART_RxIdle, /* RX idle. */
-    kUSART_RxBusy  /* RX busy. */
-};
-
-/*<! Private handle only used for internally. */
-static usart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_USART_COUNT];
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
-{
-    assert(handle);
-    assert(param);
-
-    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
-
-    /* Disable UART TX DMA. */
-    USART_EnableTxDMA(usartPrivateHandle->base, false);
-
-    usartPrivateHandle->handle->txState = kUSART_TxIdle;
-
-    if (usartPrivateHandle->handle->callback)
-    {
-        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
-                                             usartPrivateHandle->handle->userData);
-    }
-}
-
-static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
-{
-    assert(handle);
-    assert(param);
-
-    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
-
-    /* Disable UART RX DMA. */
-    USART_EnableRxDMA(usartPrivateHandle->base, false);
-
-    usartPrivateHandle->handle->rxState = kUSART_RxIdle;
-
-    if (usartPrivateHandle->handle->callback)
-    {
-        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
-                                             usartPrivateHandle->handle->userData);
-    }
-}
-
-status_t USART_TransferCreateHandleDMA(USART_Type *base,
-                                       usart_dma_handle_t *handle,
-                                       usart_dma_transfer_callback_t callback,
-                                       void *userData,
-                                       dma_handle_t *txDmaHandle,
-                                       dma_handle_t *rxDmaHandle)
-{
-    int32_t instance = 0;
-
-    /* check 'base' */
-    assert(!(NULL == base));
-    if (NULL == base)
-    {
-        return kStatus_InvalidArgument;
-    }
-    /* check 'handle' */
-    assert(!(NULL == handle));
-    if (NULL == handle)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    instance = USART_GetInstance(base);
-
-    memset(handle, 0, sizeof(*handle));
-    /* assign 'base' and 'handle' */
-    s_dmaPrivateHandle[instance].base = base;
-    s_dmaPrivateHandle[instance].handle = handle;
-
-    /* set tx/rx 'idle' state */
-    handle->rxState = kUSART_RxIdle;
-    handle->txState = kUSART_TxIdle;
-
-    handle->callback = callback;
-    handle->userData = userData;
-
-    handle->rxDmaHandle = rxDmaHandle;
-    handle->txDmaHandle = txDmaHandle;
-
-    /* Configure TX. */
-    if (txDmaHandle)
-    {
-        DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
-    }
-
-    /* Configure RX. */
-    if (rxDmaHandle)
-    {
-        DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
-    }
-
-    return kStatus_Success;
-}
-
-status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
-{
-    assert(handle);
-    assert(handle->txDmaHandle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
-
-    dma_transfer_config_t xferConfig;
-    status_t status;
-
-    /* If previous TX not finished. */
-    if (kUSART_TxBusy == handle->txState)
-    {
-        status = kStatus_USART_TxBusy;
-    }
-    else
-    {
-        handle->txState = kUSART_TxBusy;
-        handle->txDataSizeAll = xfer->dataSize;
-
-        /* Enable DMA request from txFIFO */
-        USART_EnableTxDMA(base, true);
-
-        /* Prepare transfer. */
-        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize,
-                            kDMA_MemoryToPeripheral, NULL);
-
-        /* Submit transfer. */
-        DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
-        DMA_StartTransfer(handle->txDmaHandle);
-
-        status = kStatus_Success;
-    }
-
-    return status;
-}
-
-status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
-{
-    assert(handle);
-    assert(handle->rxDmaHandle);
-    assert(xfer);
-    assert(xfer->data);
-    assert(xfer->dataSize);
-
-    dma_transfer_config_t xferConfig;
-    status_t status;
-
-    /* If previous RX not finished. */
-    if (kUSART_RxBusy == handle->rxState)
-    {
-        status = kStatus_USART_RxBusy;
-    }
-    else
-    {
-        handle->rxState = kUSART_RxBusy;
-        handle->rxDataSizeAll = xfer->dataSize;
-
-        /* Enable DMA request from rxFIFO */
-        USART_EnableRxDMA(base, true);
-
-        /* Prepare transfer. */
-        DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize,
-                            kDMA_PeripheralToMemory, NULL);
-
-        /* Submit transfer. */
-        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
-        DMA_StartTransfer(handle->rxDmaHandle);
-
-        status = kStatus_Success;
-    }
-
-    return status;
-}
-
-void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
-{
-    assert(NULL != handle);
-    assert(NULL != handle->txDmaHandle);
-
-    /* Stop transfer. */
-    DMA_AbortTransfer(handle->txDmaHandle);
-    handle->txState = kUSART_TxIdle;
-}
-
-void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
-{
-    assert(NULL != handle);
-    assert(NULL != handle->rxDmaHandle);
-
-    /* Stop transfer. */
-    DMA_AbortTransfer(handle->rxDmaHandle);
-    handle->rxState = kUSART_RxIdle;
-}
-
-status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
-{
-    assert(handle);
-    assert(handle->rxDmaHandle);
-    assert(count);
-
-    if (kUSART_RxIdle == handle->rxState)
-    {
-        return kStatus_NoTransferInProgress;
-    }
-
-    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
-
-    return kStatus_Success;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_USART_DMA_H_
-#define _FSL_USART_DMA_H_
-
-#include "fsl_common.h"
-#include "fsl_dma.h"
-#include "fsl_usart.h"
-
-/*!
- * @addtogroup usart_dma_driver
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Forward declaration of the handle typedef. */
-typedef struct _usart_dma_handle usart_dma_handle_t;
-
-/*! @brief UART transfer callback function. */
-typedef void (*usart_dma_transfer_callback_t)(USART_Type *base,
-                                              usart_dma_handle_t *handle,
-                                              status_t status,
-                                              void *userData);
-
-/*!
-* @brief UART DMA handle
-*/
-struct _usart_dma_handle
-{
-    USART_Type *base; /*!< UART peripheral base address. */
-
-    usart_dma_transfer_callback_t callback; /*!< Callback function. */
-    void *userData;                         /*!< UART callback function parameter.*/
-    size_t rxDataSizeAll;                   /*!< Size of the data to receive. */
-    size_t txDataSizeAll;                   /*!< Size of the data to send out. */
-
-    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
-    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
-
-    volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state */
-};
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name DMA transactional
- * @{
- */
-
-/*!
- * @brief Initializes the USART handle which is used in transactional functions.
- * @param base USART peripheral base address.
- * @param handle Pointer to usart_dma_handle_t structure.
- * @param callback Callback function.
- * @param userData User data.
- * @param txDmaHandle User-requested DMA handle for TX DMA transfer.
- * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
- */
-status_t USART_TransferCreateHandleDMA(USART_Type *base,
-                                       usart_dma_handle_t *handle,
-                                       usart_dma_transfer_callback_t callback,
-                                       void *userData,
-                                       dma_handle_t *txDmaHandle,
-                                       dma_handle_t *rxDmaHandle);
-
-/*!
- * @brief Sends data using DMA.
- *
- * This function sends data using DMA. This is a non-blocking function, which returns
- * right away. When all data is sent, the send callback function is called.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param xfer USART DMA transfer structure. See #usart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_USART_TxBusy Previous transfer on going.
- * @retval kStatus_InvalidArgument Invalid argument.
- */
-status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
-
-/*!
- * @brief Receives data using DMA.
- *
- * This function receives data using DMA. This is a non-blocking function, which returns
- * right away. When all data is received, the receive callback function is called.
- *
- * @param base USART peripheral base address.
- * @param handle Pointer to usart_dma_handle_t structure.
- * @param xfer USART DMA transfer structure. See #usart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_USART_RxBusy Previous transfer on going.
- * @retval kStatus_InvalidArgument Invalid argument.
- */
-status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
-
-/*!
- * @brief Aborts the sent data using DMA.
- *
- * This function aborts send data using DMA.
- *
- * @param base USART peripheral base address
- * @param handle Pointer to usart_dma_handle_t structure
- */
-void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle);
-
-/*!
- * @brief Aborts the received data using DMA.
- *
- * This function aborts the received data using DMA.
- *
- * @param base USART peripheral base address
- * @param handle Pointer to usart_dma_handle_t structure
- */
-void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle);
-
-/*!
- * @brief Get the number of bytes that have been received.
- *
- * This function gets the number of bytes that have been received.
- *
- * @param base USART peripheral base address.
- * @param handle USART handle pointer.
- * @param count Receive bytes count.
- * @retval kStatus_NoTransferInProgress No receive in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
- * @retval kStatus_Success Get successfully through the parameter \p count;
- */
-status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_USART_DMA_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_utick.h"
-#include "fsl_power.h"
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Typedef for interrupt handler. */
-typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb);
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Gets the instance from the base address
- *
- * @param base UTICK peripheral base address
- *
- * @return The UTICK instance
- */
-static uint32_t UTICK_GetInstance(UTICK_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* Array of UTICK handle. */
-static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT];
-/* Array of UTICK peripheral base address. */
-static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS;
-/* Array of UTICK IRQ number. */
-static const IRQn_Type s_utickIRQ[] = UTICK_IRQS;
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/* Array of UTICK clock name. */
-static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-/* UTICK ISR for transactional APIs. */
-static utick_isr_t s_utickIsr;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t UTICK_GetInstance(UTICK_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++)
-    {
-        if (s_utickBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_utickBases));
-
-    return instance;
-}
-
-void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)
-{
-    uint32_t instance;
-
-    /* Get instance from peripheral base address. */
-    instance = UTICK_GetInstance(base);
-
-    /* Save the handle in global variables to support the double weak mechanism. */
-    s_utickHandle[instance] = cb;
-    EnableDeepSleepIRQ(s_utickIRQ[instance]);
-    base->CTRL = count | UTICK_CTRL_REPEAT(mode);
-}
-
-void UTICK_Init(UTICK_Type *base)
-{
-    /* Enable utick clock */
-    CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]);
-    /* Power up Watchdog oscillator*/
-    POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
-    s_utickIsr = UTICK_HandleIRQ;
-}
-
-void UTICK_Deinit(UTICK_Type *base)
-{
-    /* Turn off utick */
-    base->CTRL = 0;
-    /* Disable utick clock */
-    CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]);
-}
-
-uint32_t UTICK_GetStatusFlags(UTICK_Type *base)
-{
-    return (base->STAT);
-}
-
-void UTICK_ClearStatusFlags(UTICK_Type *base)
-{
-    base->STAT = UTICK_STAT_INTR_MASK;
-}
-
-void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)
-{
-    UTICK_ClearStatusFlags(base);
-    if (cb)
-    {
-        cb();
-    }
-}
-
-#if defined(UTICK0)
-void UTICK0_DriverIRQHandler(void)
-{
-    s_utickIsr(UTICK0, s_utickHandle[0]);
-}
-#endif
-#if defined(UTICK1)
-void UTICK1_DriverIRQHandler(void)
-{
-    s_utickIsr(UTICK1, s_utickHandle[1]);
-}
-#endif
-#if defined(UTICK2)
-void UTICK2_DriverIRQHandler(void)
-{
-    s_utickIsr(UTICK2, s_utickHandle[2]);
-}
-#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_UTICK_H_
-#define _FSL_UTICK_H_
-
-#include "fsl_common.h"
-/*!
- * @addtogroup utick
- * @{
- */
-
-/*! @file*/
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief UTICK driver version 2.0.0. */
-#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief UTICK timer operational mode. */
-typedef enum _utick_mode
-{
-    kUTICK_Onetime = 0x0U, /*!< Trigger once*/
-    kUTICK_Repeat = 0x1U,  /*!< Trigger repeatedly */
-} utick_mode_t;
-
-/*! @brief UTICK callback function. */
-typedef void (*utick_callback_t)(void);
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
-* @brief Initializes an UTICK by turning its bus clock on
-*
-*/
-void UTICK_Init(UTICK_Type *base);
-
-/*!
- * @brief Deinitializes a UTICK instance.
- *
- * This function shuts down Utick bus clock
- *
- * @param base UTICK peripheral base address.
- */
-void UTICK_Deinit(UTICK_Type *base);
-/*!
- * @brief Get Status Flags.
- *
- * This returns the status flag
- *
- * @param base UTICK peripheral base address.
- * @return status register value
- */
-uint32_t UTICK_GetStatusFlags(UTICK_Type *base);
-/*!
- * @brief Clear Status Interrupt Flags.
- *
- * This clears intr status flag
- *
- * @param base UTICK peripheral base address.
- * @return none
- */
-void UTICK_ClearStatusFlags(UTICK_Type *base);
-
-/*!
- * @brief Starts UTICK.
- *
- * This function starts a repeat/onetime countdown with an optional callback
- *
- * @param base   UTICK peripheral base address.
- * @param mode  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
- * @param count  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
- * @param cb  UTICK callback (can be left as NULL if none, otherwise should be a void func(void))
- * @return none
- */
-void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb);
-/*!
- * @brief UTICK Interrupt Service Handler.
- *
- * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
- * in UTICK_SetTick()).
- * if no user callback is scheduled, the interrupt will simply be cleared.
- *
- * @param base   UTICK peripheral base address.
- * @param cb  callback scheduled for this instance of UTICK
- * @return none
- */
-void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_UTICK_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_wwdt.h"
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*!
- * @brief Gets the instance from the base address
- *
- * @param base WWDT peripheral base address
- *
- * @return The WWDT instance
- */
-static uint32_t WWDT_GetInstance(WWDT_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to WWDT bases for each instance. */
-static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to WWDT clocks for each instance. */
-static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to WWDT resets for each instance. */
-static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t WWDT_GetInstance(WWDT_Type *base)
-{
-    uint32_t instance;
-    uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0]));
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < wwdtArrayCount; instance++)
-    {
-        if (s_wwdtBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < wwdtArrayCount);
-
-    return instance;
-}
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-void WWDT_GetDefaultConfig(wwdt_config_t *config)
-{
-    assert(config);
-
-    /* Enable the watch dog */
-    config->enableWwdt = true;
-    /* Disable the watchdog timeout reset */
-    config->enableWatchdogReset = false;
-    /* Disable the watchdog protection for updating the timeout value */
-    config->enableWatchdogProtect = false;
-    /* Do not lock the watchdog oscillator */
-    config->enableLockOscillator = false;
-    /* Windowing is not in effect */
-    config->windowValue = 0xFFFFFFU;
-    /* Set the timeout value to the max */
-    config->timeoutValue = 0xFFFFFFU;
-    /* No warning is provided */
-    config->warningValue = 0;
-}
-
-void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
-{
-    assert(config);
-
-    uint32_t value = 0U;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the WWDT clock */
-    CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* Reset the WWDT module */
-    RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]);
-
-    value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
-            WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator);
-    /* Set configruation */
-    base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);
-    base->TC = WWDT_TC_COUNT(config->timeoutValue);
-    base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue);
-    base->MOD = value;
-}
-
-void WWDT_Deinit(WWDT_Type *base)
-{
-    WWDT_Disable(base);
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the WWDT clock */
-    CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-void WWDT_Refresh(WWDT_Type *base)
-{
-    uint32_t primaskValue = 0U;
-
-    /* Disable the global interrupt to protect refresh sequence */
-    primaskValue = DisableGlobalIRQ();
-    base->FEED = WWDT_FIRST_WORD_OF_REFRESH;
-    base->FEED = WWDT_SECOND_WORD_OF_REFRESH;
-    EnableGlobalIRQ(primaskValue);
-}
-
-void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)
-{
-    /* Clear the WDINT bit so that we don't accidentally clear it */
-    uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK));
-
-    /* Clear timeout by writing a zero */
-    if (mask & kWWDT_TimeoutFlag)
-    {
-        reg &= ~WWDT_MOD_WDTOF_MASK;
-    }
-
-    /* Clear warning interrupt flag by writing a one */
-    if (mask & kWWDT_WarningFlag)
-    {
-        reg |= WWDT_MOD_WDINT_MASK;
-    }
-
-    base->MOD = reg;
-}

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_WWDT_H_
-#define _FSL_WWDT_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup wwdt
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- *******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief Defines WWDT driver version 2.0.0. */
-#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @name Refresh sequence */
-/*@{*/
-#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU)  /*!< First word of refresh sequence */
-#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
-/*@}*/
-
-/*! @brief Describes WWDT configuration structure. */
-typedef struct _wwdt_config
-{
-    bool enableWwdt;            /*!< Enables or disables WWDT */
-    bool enableWatchdogReset;   /*!< true: Watchdog timeout will cause a chip reset
-                                     false: Watchdog timeout will not cause a chip reset */
-    bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be
-                                           changed after counter is below warning & window values
-                                     false: Disable watchdog protect; timeout value can be changed
-                                            at any time */
-    bool enableLockOscillator;  /*!< true: Disabling or powering down the watchdog oscillator is prevented
-                                           Once set, this bit can only be cleared by a reset
-                                     false: Do not lock oscillator */
-    uint32_t windowValue;       /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
-    uint32_t timeoutValue;      /*!< Timeout value */
-    uint32_t warningValue;      /*!< Watchdog time counter value that will generate a
-                                     warning interrupt. Set this to 0 for no warning */
-
-} wwdt_config_t;
-
-/*!
- * @brief WWDT status flags.
- *
- * This structure contains the WWDT status flags for use in the WWDT functions.
- */
-enum _wwdt_status_flags_t
-{
-    kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */
-    kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK  /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */
-};
-
-/*******************************************************************************
- * API
- *******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*!
- * @name WWDT Initialization and De-initialization
- * @{
- */
-
-/*!
- * @brief Initializes WWDT configure sturcture.
- *
- * This function initializes the WWDT configure structure to default value. The default
- * value are:
- * @code
- *  config->enableWwdt = true;
- *  config->enableWatchdogReset = false;
- *  config->enableWatchdogProtect = false;
- *  config->enableLockOscillator = false;
- *  config->windowValue = 0xFFFFFFU;
- *  config->timeoutValue = 0xFFFFFFU;
- *  config->warningValue = 0;
- * @endcode
- *
- * @param config Pointer to WWDT config structure.
- * @see wwdt_config_t
- */
-void WWDT_GetDefaultConfig(wwdt_config_t *config);
-
-/*!
- * @brief Initializes the WWDT.
- *
- * This function initializes the WWDT. When called, the WWDT runs according to the configuration.
- *
- * Example:
- * @code
- *   wwdt_config_t config;
- *   WWDT_GetDefaultConfig(&config);
- *   config.timeoutValue = 0x7ffU;
- *   WWDT_Init(wwdt_base,&config);
- * @endcode
- *
- * @param base   WWDT peripheral base address
- * @param config The configuration of WWDT
- */
-void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
-
-/*!
- * @brief Shuts down the WWDT.
- *
- * This function shuts down the WWDT.
- *
- * @param base WWDT peripheral base address
- */
-void WWDT_Deinit(WWDT_Type *base);
-
-/* @} */
-
-/*!
- * @name WWDT Functional Operation
- * @{
- */
-
-/*!
- * @brief Enables the WWDT module.
- *
- * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit;
- * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run
- * permanently.
- *
- * @param base WWDT peripheral base address
- */
-static inline void WWDT_Enable(WWDT_Type *base)
-{
-    base->MOD |= WWDT_MOD_WDEN_MASK;
-}
-
-/*!
- * @brief Disables the WWDT module.
- *
- * This function write value into WWDT_MOD register to disable the WWDT.
- *
- * @param base WWDT peripheral base address
- */
-static inline void WWDT_Disable(WWDT_Type *base)
-{
-    base->MOD &= ~WWDT_MOD_WDEN_MASK;
-}
-
-/*!
- * @brief Gets all WWDT status flags.
- *
- * This function gets all status flags.
- *
- * Example for getting Timeout Flag:
- * @code
- *   uint32_t status;
- *   status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;
- * @endcode
- * @param base        WWDT peripheral base address
- * @return The status flags. This is the logical OR of members of the
- *         enumeration ::_wwdt_status_flags_t
- */
-static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)
-{
-    return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK));
-}
-
-/*!
- * @brief Clear WWDT flag.
- *
- * This function clears WWDT status flag.
- *
- * Example for clearing warning flag:
- * @code
- *   WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);
- * @endcode
- * @param base WWDT peripheral base address
- * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::_wwdt_status_flags_t
- */
-void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask);
-
-/*!
- * @brief Set the WWDT warning value.
- *
- * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog
- * interrupt. When the watchdog timer counter is no longer greater than the value defined by
- * WARNINT, an interrupt will be generated after the subsequent WDCLK.
- *
- * @param base         WWDT peripheral base address
- * @param warningValue WWDT warning value.
- */
-static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)
-{
-    base->WARNINT = WWDT_WARNINT_WARNINT(warningValue);
-}
-
-/*!
- * @brief Set the WWDT timeout value.
- *
- * This function sets the timeout value. Every time a feed sequence occurs the value in the TC
- * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be
- * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4.
- * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change
- * the timeout value before the watchdog counter is below the warning and window values
- * will cause a watchdog reset and set the WDTOF flag.
- *
- * @param base WWDT peripheral base address
- * @param timeoutCount WWDT timeout value, count of WWDT clock tick.
- */
-static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)
-{
-    base->TC = WWDT_TC_COUNT(timeoutCount);
-}
-
-/*!
- * @brief Sets the WWDT window value.
- *
- * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed.
- * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog
- * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer
- * value) so windowing is not in effect.
- *
- * @param base        WWDT peripheral base address
- * @param windowValue WWDT window value.
- */
-static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
-{
-    base->WINDOW = WWDT_WINDOW_WINDOW(windowValue);
-}
-
-/*!
- * @brief Refreshes the WWDT timer.
- *
- * This function feeds the WWDT.
- * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.
- *
- * @param base WWDT peripheral base address
- */
-void WWDT_Refresh(WWDT_Type *base);
-
-/*@}*/
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-/*! @}*/
-
-#endif /* _FSL_WWDT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,112 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = Flexcomm0,
+    UART_1 = Flexcomm4
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = Flexcomm1,
+    I2C_1 = Flexcomm2
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT           8
+#define ADC_B_CHANNEL_SHIFT        5
+
+typedef enum {
+    ADC0_SE0  = 0,
+    ADC0_SE1  = 1,
+    ADC0_SE2  = 2,
+    ADC0_SE3  = 3,
+    ADC0_SE4  = 4,
+    ADC0_SE5  = 5,
+    ADC0_SE6  = 6,
+    ADC0_SE7  = 7,
+    ADC0_SE8  = 8,
+    ADC0_SE9  = 9,
+    ADC0_SE10 = 10,
+    ADC0_SE11 = 11,
+} ADCName;
+
+typedef enum {
+    CAN_0 = 0,
+    CAN_1 = 1
+} CANName;
+
+typedef enum {
+    SPI_0 = Flexcomm3,
+    SPI_1 = Flexcomm9
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_16, ADC0_SE4,  0},
+    {P0_31, ADC0_SE5,  0},
+    {P1_0,  ADC0_SE6,  0},
+    {P2_0,  ADC0_SE7,  0},
+    {NC   , NC      ,  0}
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_TD[] = {
+    {P3_18, CAN_0,  4},
+    {P1_17, CAN_1,  5},
+    {NC   , NC   ,  0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {P3_19, CAN_0,  4},
+    {P1_18, CAN_1,  5},
+    {NC   , NC   ,  0}
+};
+
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {NC      , NC   , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_13, I2C_0, 1},
+    {P3_23, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_14, I2C_0, 1},
+    {P3_24, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_30, UART_0, 1},
+    {P3_27, UART_1, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_29, UART_0, 1},
+    {P3_26, UART_1, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {P3_28, UART_1, 1},
+    {NC   , NC    , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {P3_29, UART_1, 1},
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_0,  SPI_0, 2},
+    {P3_20, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_3,  SPI_0, 1},
+    {P3_21, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_2,  SPI_0, 1},
+    {P3_22, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_1,  SPI_0, 2},
+    {P3_30, SPI_1, 1},
+    {P4_6,  SPI_1, 2},
+    {NC  ,  NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {NC   , NC    , 0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    P0_0 = (0 << PORT_SHIFT | 0),
+    P0_1 = (0 << PORT_SHIFT | 1),
+    P0_2 = (0 << PORT_SHIFT | 2),
+    P0_3 = (0 << PORT_SHIFT | 3),
+    P0_4 = (0 << PORT_SHIFT | 4),
+    P0_5 = (0 << PORT_SHIFT | 5),
+    P0_6 = (0 << PORT_SHIFT | 6),
+    P0_7 = (0 << PORT_SHIFT | 7),
+    P0_8 = (0 << PORT_SHIFT | 8),
+    P0_9 = (0 << PORT_SHIFT | 9),
+    P0_10 = (0 << PORT_SHIFT | 10),
+    P0_11 = (0 << PORT_SHIFT | 11),
+    P0_12 = (0 << PORT_SHIFT | 12),
+    P0_13 = (0 << PORT_SHIFT | 13),
+    P0_14 = (0 << PORT_SHIFT | 14),
+    P0_15 = (0 << PORT_SHIFT | 15),
+    P0_16 = (0 << PORT_SHIFT | 16),
+    P0_17 = (0 << PORT_SHIFT | 17),
+    P0_18 = (0 << PORT_SHIFT | 18),
+    P0_19 = (0 << PORT_SHIFT | 19),
+    P0_20 = (0 << PORT_SHIFT | 20),
+    P0_21 = (0 << PORT_SHIFT | 21),
+    P0_22 = (0 << PORT_SHIFT | 22),
+    P0_23 = (0 << PORT_SHIFT | 23),
+    P0_24 = (0 << PORT_SHIFT | 24),
+    P0_25 = (0 << PORT_SHIFT | 25),
+    P0_26 = (0 << PORT_SHIFT | 26),
+    P0_27 = (0 << PORT_SHIFT | 27),
+    P0_28 = (0 << PORT_SHIFT | 28),
+    P0_29 = (0 << PORT_SHIFT | 29),
+    P0_30 = (0 << PORT_SHIFT | 30),
+    P0_31 = (0 << PORT_SHIFT | 31),
+
+    P1_0 = (1 << PORT_SHIFT | 0),
+    P1_1 = (1 << PORT_SHIFT | 1),
+    P1_2 = (1 << PORT_SHIFT | 2),
+    P1_3 = (1 << PORT_SHIFT | 3),
+    P1_4 = (1 << PORT_SHIFT | 4),
+    P1_5 = (1 << PORT_SHIFT | 5),
+    P1_6 = (1 << PORT_SHIFT | 6),
+    P1_7 = (1 << PORT_SHIFT | 7),
+    P1_8 = (1 << PORT_SHIFT | 8),
+    P1_9 = (1 << PORT_SHIFT | 9),
+    P1_10 = (1 << PORT_SHIFT | 10),
+    P1_11 = (1 << PORT_SHIFT | 11),
+    P1_12 = (1 << PORT_SHIFT | 12),
+    P1_13 = (1 << PORT_SHIFT | 13),
+    P1_14 = (1 << PORT_SHIFT | 14),
+    P1_15 = (1 << PORT_SHIFT | 15),
+    P1_16 = (1 << PORT_SHIFT | 16),
+    P1_17 = (1 << PORT_SHIFT | 17),
+    P1_18 = (1 << PORT_SHIFT | 18),
+    P1_19 = (1 << PORT_SHIFT | 19),
+    P1_20 = (1 << PORT_SHIFT | 20),
+    P1_21 = (1 << PORT_SHIFT | 21),
+    P1_22 = (1 << PORT_SHIFT | 22),
+    P1_23 = (1 << PORT_SHIFT | 23),
+    P1_24 = (1 << PORT_SHIFT | 24),
+    P1_25 = (1 << PORT_SHIFT | 25),
+    P1_26 = (1 << PORT_SHIFT | 26),
+    P1_27 = (1 << PORT_SHIFT | 27),
+    P1_28 = (1 << PORT_SHIFT | 28),
+    P1_29 = (1 << PORT_SHIFT | 29),
+    P1_30 = (1 << PORT_SHIFT | 30),
+    P1_31 = (1 << PORT_SHIFT | 31),
+
+    P2_0 = (2 <<  PORT_SHIFT | 0),
+    P2_1 = (2 <<  PORT_SHIFT | 1),
+    P2_2 = (2 <<  PORT_SHIFT | 2),
+    P2_3 = (2 <<  PORT_SHIFT | 3),
+    P2_4 = (2 <<  PORT_SHIFT | 4),
+    P2_5 = (2 <<  PORT_SHIFT | 5),
+    P2_6 = (2 <<  PORT_SHIFT | 6),
+    P2_7 = (2 <<  PORT_SHIFT | 7),
+    P2_8 = (2 <<  PORT_SHIFT | 8),
+    P2_9 = (2 <<  PORT_SHIFT | 9),
+    P2_10 = (2 <<  PORT_SHIFT | 10),
+    P2_11 = (2 <<  PORT_SHIFT | 11),
+    P2_12 = (2 <<  PORT_SHIFT | 12),
+    P2_13 = (2 <<  PORT_SHIFT | 13),
+    P2_14 = (2 <<  PORT_SHIFT | 14),
+    P2_15 = (2 <<  PORT_SHIFT | 15),
+    P2_16 = (2 <<  PORT_SHIFT | 16),
+    P2_17 = (2 <<  PORT_SHIFT | 17),
+    P2_18 = (2 <<  PORT_SHIFT | 18),
+    P2_19 = (2 <<  PORT_SHIFT | 19),
+    P2_20 = (2 <<  PORT_SHIFT | 20),
+    P2_21 = (2 <<  PORT_SHIFT | 21),
+    P2_22 = (2 <<  PORT_SHIFT | 22),
+    P2_23 = (2 <<  PORT_SHIFT | 23),
+    P2_24 = (2 <<  PORT_SHIFT | 24),
+    P2_25 = (2 <<  PORT_SHIFT | 25),
+    P2_26 = (2 <<  PORT_SHIFT | 26),
+    P2_27 = (2 <<  PORT_SHIFT | 27),
+    P2_28 = (2 <<  PORT_SHIFT | 28),
+    P2_29 = (2 <<  PORT_SHIFT | 29),
+    P2_30 = (2 <<  PORT_SHIFT | 30),
+    P2_31 = (2 <<  PORT_SHIFT | 31),
+
+    P3_0 = (3 <<  PORT_SHIFT | 0),
+    P3_1 = (3 <<  PORT_SHIFT | 1),
+    P3_2 = (3 <<  PORT_SHIFT | 2),
+    P3_3 = (3 <<  PORT_SHIFT | 3),
+    P3_4 = (3 <<  PORT_SHIFT | 4),
+    P3_5 = (3 <<  PORT_SHIFT | 5),
+    P3_6 = (3 <<  PORT_SHIFT | 6),
+    P3_7 = (3 <<  PORT_SHIFT | 7),
+    P3_8 = (3 <<  PORT_SHIFT | 8),
+    P3_9 = (3 <<  PORT_SHIFT | 9),
+    P3_10 = (3 <<  PORT_SHIFT | 10),
+    P3_11 = (3 <<  PORT_SHIFT | 11),
+    P3_12 = (3 <<  PORT_SHIFT | 12),
+    P3_13 = (3 <<  PORT_SHIFT | 13),
+    P3_14 = (3 <<  PORT_SHIFT | 14),
+    P3_15 = (3 <<  PORT_SHIFT | 15),
+    P3_16 = (3 <<  PORT_SHIFT | 16),
+    P3_17 = (3 <<  PORT_SHIFT | 17),
+    P3_18 = (3 <<  PORT_SHIFT | 18),
+    P3_19 = (3 <<  PORT_SHIFT | 19),
+    P3_20 = (3 <<  PORT_SHIFT | 20),
+    P3_21 = (3 <<  PORT_SHIFT | 21),
+    P3_22 = (3 <<  PORT_SHIFT | 22),
+    P3_23 = (3 <<  PORT_SHIFT | 23),
+    P3_24 = (3 <<  PORT_SHIFT | 24),
+    P3_25 = (3 <<  PORT_SHIFT | 25),
+    P3_26 = (3 <<  PORT_SHIFT | 26),
+    P3_27 = (3 <<  PORT_SHIFT | 27),
+    P3_28 = (3 <<  PORT_SHIFT | 28),
+    P3_29 = (3 <<  PORT_SHIFT | 29),
+    P3_30 = (3 <<  PORT_SHIFT | 30),
+    P3_31 = (3 <<  PORT_SHIFT | 31),
+
+    P4_0 = (4 <<  PORT_SHIFT | 0),
+    P4_1 = (4 <<  PORT_SHIFT | 1),
+    P4_2 = (4 <<  PORT_SHIFT | 2),
+    P4_3 = (4 <<  PORT_SHIFT | 3),
+    P4_4 = (4 <<  PORT_SHIFT | 4),
+    P4_5 = (4 <<  PORT_SHIFT | 5),
+    P4_6 = (4 <<  PORT_SHIFT | 6),
+    P4_7 = (4 <<  PORT_SHIFT | 7),
+    P4_8 = (4 <<  PORT_SHIFT | 8),
+    P4_9 = (4 <<  PORT_SHIFT | 9),
+    P4_10 = (4 <<  PORT_SHIFT | 10),
+    P4_11 = (4 <<  PORT_SHIFT | 11),
+    P4_12 = (4 <<  PORT_SHIFT | 12),
+    P4_13 = (4 <<  PORT_SHIFT | 13),
+    P4_14 = (4 <<  PORT_SHIFT | 14),
+    P4_15 = (4 <<  PORT_SHIFT | 15),
+    P4_16 = (4 <<  PORT_SHIFT | 16),
+
+    LED_RED   = P2_2,
+
+    // mbed original LED naming
+    LED1 = P3_14,
+    LED2 = P3_3,
+    LED3 = LED_RED,
+    LED4 = LED_RED,
+
+    //Push buttons
+    SW2 = P0_6,
+    SW3 = P0_5,
+    SW4 = P0_4,
+    SW5 = P1_1,
+
+    // USB Pins
+    USBTX = P0_30,
+    USBRX = P0_29,
+
+    // Arduino Headers
+    D0 = P3_26,
+    D1 = P3_27,
+    D2 = P3_2,
+    D3 = P4_5,
+    D4 = P3_10,
+    D5 = P3_14,
+    D6 = P3_1,
+    D7 = P1_22,
+    D8 = P4_7,
+    D9 = P2_1,
+    D10 = P3_30,
+    D11 = P3_21,
+    D12 = P3_22,
+    D13 = P3_20,
+    D14 = P3_23,
+    D15 = P3_24,
+
+    I2C_SCL = D15,
+    I2C_SDA = D14,
+
+    A0 = P0_16,
+    A1 = P0_31,
+    A2 = P1_0,
+    A3 = P2_0,
+    A4 = P3_4,
+    A5 = P1_1,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: LPC54618J512
+package_id: LPC54618J512ET180
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+board: LPCXpresso54618
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+settings:
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up SYS PLL */
+    const pll_setup_t pllSetup = {
+        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+        .pllRate = 180000000U,
+        .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+    CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */
+    CLOCK_SetPLLFreq(&pllSetup);          /*!< Configure PLL to the desired value */
+    POWER_SetVoltageForFreq(
+        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
+    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK);         /*!< Switch System clock to SYS PLL 180MHz */
+
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
+
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK   12000000U    /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK   48000000U    /*!< Core clock frequency:48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK   96000000U    /*!< Core clock frequency:96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#define BOARD_BootClockPLL180M_CORE_CLOCK   180000000U    /*!< Core clock frequency:180000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL180M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+#endif /* _CLOCK_CONFIG_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,39 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define NUMBER_OF_GPIO_INTS    8
+
+#define APP_EXCLUDE_FROM_DEEPSLEEP                                                                        \
+    (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK |  SYSCON_PDRUNCFG_PDEN_SRAMX_MASK |                               \
+     SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+
+/* Defines used by the sleep code */
+#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M
+#define LPC_CLOCK_RUN          BOARD_BootClockFROHF48M
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "clock_config.h"
+#include "fsl_emc.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* The SDRAM timing. */
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (18u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (67u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (6u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+
+// called before main
+void mbed_sdk_init()
+{
+    BOARD_BootClockFROHF48M();
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+//  be used as a low power mode wakeup.  The application will
+//  need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+    //gpio_t gpio;
+    //gpio_init_in(&gpio, PTA4);
+}
+
+// Enable the RTC oscillator if available on the board
+void rtc_setup_oscillator(void)
+{
+    /* Enable the RTC 32K Oscillator */
+    SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
+}
+
+void ADC_ClockPower_Configuration(void)
+{
+    /* SYSCON power. */
+    POWER_DisablePD(kPDRUNCFG_PD_VDDA);    /* Power on VDDA. */
+    POWER_DisablePD(kPDRUNCFG_PD_ADC0);    /* Power on the ADC converter. */
+    POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */
+    POWER_DisablePD(kPDRUNCFG_PD_VREFP);   /* Power on the reference voltage source. */
+    POWER_DisablePD(kPDRUNCFG_PD_TS);      /* Power on the temperature sensor. */
+
+    /* Enable the clock. */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+    /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
+    /* Sync clock source is not used. Using sync clock source and would be divided by 2.
+     * The divider would be set when configuring the converter.
+     */
+    CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */
+}
+
+/* Initialize the external memory. */
+void BOARD_InitSDRAM(void)
+{
+    emc_basic_config_t basicConfig;
+    emc_dynamic_timing_config_t dynTiming;
+    emc_dynamic_chip_config_t dynChipConfig;
+
+    /* Basic configuration. */
+    basicConfig.endian = kEMC_LittleEndian;
+    basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
+    /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
+     * If you change the divide to 0 and EMC clock is larger than 100M
+     * please take refer to emc.dox to adjust EMC clock delay.
+     */
+    basicConfig.emcClkDiv = 1;
+    /* Dynamic memory timing configuration. */
+    dynTiming.readConfig = kEMC_Cmddelay;
+    dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
+    dynTiming.tRp_Ns = SDRAM_TRP_NS;
+    dynTiming.tRas_Ns = SDRAM_TRAS_NS;
+    dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
+    dynTiming.tApr_Ns = SDRAM_TAPR_NS;
+    dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
+    dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
+    dynTiming.tRc_Ns = SDRAM_TRC_NS;
+    dynTiming.tRfc_Ns = SDRAM_RFC_NS;
+    dynTiming.tXsr_Ns = SDRAM_XSR_NS;
+    dynTiming.tRrd_Ns = SDRAM_RRD_NS;
+    dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
+    /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
+    dynChipConfig.chipIndex = 0;
+    dynChipConfig.dynamicDevice = kEMC_Sdram;
+    dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
+    dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
+    dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
+    dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
+    /* EMC Basic configuration. */
+    EMC_Init(EMC, &basicConfig);
+    /* EMC Dynamc memory configuration. */
+    EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,12410 @@
+/*
+** ###################################################################
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170214
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54618
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54618.h
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief CMSIS Peripheral Access Layer for LPC54618
+ *
+ * CMSIS Peripheral Access Layer for LPC54618
+ */
+
+#ifndef _LPC54618_H_
+#define _LPC54618_H_                             /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  EEPROM_IRQn                  = 52,               /**< EEPROM interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56                /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54618.h"           /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+
+/*! @name STARTUP - ADC Startup register. */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+
+/*! @name CALIB - ADC Calibration register. */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DBTP;                              /**< Data Bit Timing Prescaler Register, offset: 0xC */
+  __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
+  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
+  __IO uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
+  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
+  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
+       uint8_t RESERVED_2[16];
+  __I  uint32_t ECR;                               /**< Error Counter Register, offset: 0x40 */
+  __I  uint32_t PSR;                               /**< Protocol Status Register, offset: 0x44 */
+  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator Register, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x50 */
+  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
+  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
+  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
+       uint8_t RESERVED_4[32];
+  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
+  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
+  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
+  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
+  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
+  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
+  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+  __IO uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
+  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
+  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
+  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
+  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
+  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+  __IO uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
+  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
+  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+  __IO uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+  __IO uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+       uint8_t RESERVED_6[8];
+  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
+  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
+  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+       uint8_t RESERVED_7[260];
+  __IO uint32_t MRBA;                              /**< CAN Message RAM Base Address, offset: 0x200 */
+       uint8_t RESERVED_8[508];
+  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
+       uint8_t RESERVED_9[508];
+  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+#define CAN_DBTP_DSJW_MASK                       (0xFU)
+#define CAN_DBTP_DSJW_SHIFT                      (0U)
+#define CAN_DBTP_DSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK                     (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT                    (4U)
+#define CAN_DBTP_DTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK                     (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT                    (8U)
+#define CAN_DBTP_DTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK                       (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT                      (16U)
+#define CAN_DBTP_DBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK                        (0x800000U)
+#define CAN_DBTP_TDC_SHIFT                       (23U)
+#define CAN_DBTP_TDC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+
+/*! @name TEST - Test Register */
+#define CAN_TEST_LBCK_MASK                       (0x10U)
+#define CAN_TEST_LBCK_SHIFT                      (4U)
+#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK                         (0x60U)
+#define CAN_TEST_TX_SHIFT                        (5U)
+#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK                         (0x80U)
+#define CAN_TEST_RX_SHIFT                        (7U)
+#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+
+/*! @name CCCR - CC Control Register */
+#define CAN_CCCR_INIT_MASK                       (0x1U)
+#define CAN_CCCR_INIT_SHIFT                      (0U)
+#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK                        (0x2U)
+#define CAN_CCCR_CCE_SHIFT                       (1U)
+#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK                        (0x4U)
+#define CAN_CCCR_ASM_SHIFT                       (2U)
+#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK                        (0x8U)
+#define CAN_CCCR_CSA_SHIFT                       (3U)
+#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK                        (0x10U)
+#define CAN_CCCR_CSR_SHIFT                       (4U)
+#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK                        (0x20U)
+#define CAN_CCCR_MON_SHIFT                       (5U)
+#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK                        (0x40U)
+#define CAN_CCCR_DAR_SHIFT                       (6U)
+#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK                       (0x80U)
+#define CAN_CCCR_TEST_SHIFT                      (7U)
+#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK                       (0x100U)
+#define CAN_CCCR_FDOE_SHIFT                      (8U)
+#define CAN_CCCR_FDOE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK                       (0x200U)
+#define CAN_CCCR_BRSE_SHIFT                      (9U)
+#define CAN_CCCR_BRSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
+#define CAN_CCCR_PXHD_MASK                       (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT                      (12U)
+#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK                       (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT                      (13U)
+#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK                        (0x4000U)
+#define CAN_CCCR_TXP_SHIFT                       (14U)
+#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK                       (0x8000U)
+#define CAN_CCCR_NISO_SHIFT                      (15U)
+#define CAN_CCCR_NISO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
+#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
+#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT                      (16U)
+#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT                      (25U)
+#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+
+/*! @name TSCC - Timestamp Counter Configuration */
+#define CAN_TSCC_TSS_MASK                        (0x3U)
+#define CAN_TSCC_TSS_SHIFT                       (0U)
+#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK                        (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT                       (16U)
+#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+
+/*! @name TSCV - Timestamp Counter Value */
+#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT                       (0U)
+#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+
+/*! @name TOCC - Timeout Counter Configuration */
+#define CAN_TOCC_ETOC_MASK                       (0x1U)
+#define CAN_TOCC_ETOC_SHIFT                      (0U)
+#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK                        (0x6U)
+#define CAN_TOCC_TOS_SHIFT                       (1U)
+#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT                       (16U)
+#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+
+/*! @name TOCV - Timeout Counter Value */
+#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT                       (0U)
+#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+
+/*! @name ECR - Error Counter Register */
+#define CAN_ECR_TEC_MASK                         (0xFFU)
+#define CAN_ECR_TEC_SHIFT                        (0U)
+#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK                         (0x7F00U)
+#define CAN_ECR_REC_SHIFT                        (8U)
+#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK                          (0x8000U)
+#define CAN_ECR_RP_SHIFT                         (15U)
+#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK                         (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT                        (16U)
+#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+
+/*! @name PSR - Protocol Status Register */
+#define CAN_PSR_LEC_MASK                         (0x7U)
+#define CAN_PSR_LEC_SHIFT                        (0U)
+#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK                         (0x18U)
+#define CAN_PSR_ACT_SHIFT                        (3U)
+#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK                          (0x20U)
+#define CAN_PSR_EP_SHIFT                         (5U)
+#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK                          (0x40U)
+#define CAN_PSR_EW_SHIFT                         (6U)
+#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK                          (0x80U)
+#define CAN_PSR_BO_SHIFT                         (7U)
+#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK                        (0x700U)
+#define CAN_PSR_DLEC_SHIFT                       (8U)
+#define CAN_PSR_DLEC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK                        (0x800U)
+#define CAN_PSR_RESI_SHIFT                       (11U)
+#define CAN_PSR_RESI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK                        (0x1000U)
+#define CAN_PSR_RBRS_SHIFT                       (12U)
+#define CAN_PSR_RBRS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK                        (0x2000U)
+#define CAN_PSR_RFDF_SHIFT                       (13U)
+#define CAN_PSR_RFDF(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
+#define CAN_PSR_PXE_MASK                         (0x4000U)
+#define CAN_PSR_PXE_SHIFT                        (14U)
+#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT                       (16U)
+#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+#define CAN_TDCR_TDCF_MASK                       (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT                      (0U)
+#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT                      (8U)
+#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+
+/*! @name IR - Interrupt Register */
+#define CAN_IR_RF0N_MASK                         (0x1U)
+#define CAN_IR_RF0N_SHIFT                        (0U)
+#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK                         (0x2U)
+#define CAN_IR_RF0W_SHIFT                        (1U)
+#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK                         (0x4U)
+#define CAN_IR_RF0F_SHIFT                        (2U)
+#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK                         (0x8U)
+#define CAN_IR_RF0L_SHIFT                        (3U)
+#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK                         (0x10U)
+#define CAN_IR_RF1N_SHIFT                        (4U)
+#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK                         (0x20U)
+#define CAN_IR_RF1W_SHIFT                        (5U)
+#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK                         (0x40U)
+#define CAN_IR_RF1F_SHIFT                        (6U)
+#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK                         (0x80U)
+#define CAN_IR_RF1L_SHIFT                        (7U)
+#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK                          (0x100U)
+#define CAN_IR_HPM_SHIFT                         (8U)
+#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK                           (0x200U)
+#define CAN_IR_TC_SHIFT                          (9U)
+#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK                          (0x400U)
+#define CAN_IR_TCF_SHIFT                         (10U)
+#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK                          (0x800U)
+#define CAN_IR_TFE_SHIFT                         (11U)
+#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK                         (0x1000U)
+#define CAN_IR_TEFN_SHIFT                        (12U)
+#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK                         (0x2000U)
+#define CAN_IR_TEFW_SHIFT                        (13U)
+#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK                         (0x4000U)
+#define CAN_IR_TEFF_SHIFT                        (14U)
+#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK                         (0x8000U)
+#define CAN_IR_TEFL_SHIFT                        (15U)
+#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK                          (0x10000U)
+#define CAN_IR_TSW_SHIFT                         (16U)
+#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK                         (0x20000U)
+#define CAN_IR_MRAF_SHIFT                        (17U)
+#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK                          (0x40000U)
+#define CAN_IR_TOO_SHIFT                         (18U)
+#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK                          (0x80000U)
+#define CAN_IR_DRX_SHIFT                         (19U)
+#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK                          (0x100000U)
+#define CAN_IR_BEC_SHIFT                         (20U)
+#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK                          (0x200000U)
+#define CAN_IR_BEU_SHIFT                         (21U)
+#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK                          (0x400000U)
+#define CAN_IR_ELO_SHIFT                         (22U)
+#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK                           (0x800000U)
+#define CAN_IR_EP_SHIFT                          (23U)
+#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK                           (0x1000000U)
+#define CAN_IR_EW_SHIFT                          (24U)
+#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK                           (0x2000000U)
+#define CAN_IR_BO_SHIFT                          (25U)
+#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK                          (0x4000000U)
+#define CAN_IR_WDI_SHIFT                         (26U)
+#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK                          (0x8000000U)
+#define CAN_IR_PEA_SHIFT                         (27U)
+#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK                          (0x10000000U)
+#define CAN_IR_PED_SHIFT                         (28U)
+#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK                          (0x20000000U)
+#define CAN_IR_ARA_SHIFT                         (29U)
+#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+
+/*! @name IE - Interrupt Enable */
+#define CAN_IE_RF0NE_MASK                        (0x1U)
+#define CAN_IE_RF0NE_SHIFT                       (0U)
+#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK                        (0x2U)
+#define CAN_IE_RF0WE_SHIFT                       (1U)
+#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK                        (0x4U)
+#define CAN_IE_RF0FE_SHIFT                       (2U)
+#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK                        (0x8U)
+#define CAN_IE_RF0LE_SHIFT                       (3U)
+#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK                        (0x10U)
+#define CAN_IE_RF1NE_SHIFT                       (4U)
+#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK                        (0x20U)
+#define CAN_IE_RF1WE_SHIFT                       (5U)
+#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK                        (0x40U)
+#define CAN_IE_RF1FE_SHIFT                       (6U)
+#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK                        (0x80U)
+#define CAN_IE_RF1LE_SHIFT                       (7U)
+#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK                         (0x100U)
+#define CAN_IE_HPME_SHIFT                        (8U)
+#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK                          (0x200U)
+#define CAN_IE_TCE_SHIFT                         (9U)
+#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK                         (0x400U)
+#define CAN_IE_TCFE_SHIFT                        (10U)
+#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK                         (0x800U)
+#define CAN_IE_TFEE_SHIFT                        (11U)
+#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK                        (0x1000U)
+#define CAN_IE_TEFNE_SHIFT                       (12U)
+#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK                        (0x2000U)
+#define CAN_IE_TEFWE_SHIFT                       (13U)
+#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK                        (0x4000U)
+#define CAN_IE_TEFFE_SHIFT                       (14U)
+#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK                        (0x8000U)
+#define CAN_IE_TEFLE_SHIFT                       (15U)
+#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK                         (0x10000U)
+#define CAN_IE_TSWE_SHIFT                        (16U)
+#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK                        (0x20000U)
+#define CAN_IE_MRAFE_SHIFT                       (17U)
+#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK                         (0x40000U)
+#define CAN_IE_TOOE_SHIFT                        (18U)
+#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK                         (0x80000U)
+#define CAN_IE_DRXE_SHIFT                        (19U)
+#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK                         (0x100000U)
+#define CAN_IE_BECE_SHIFT                        (20U)
+#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK                         (0x200000U)
+#define CAN_IE_BEUE_SHIFT                        (21U)
+#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK                         (0x400000U)
+#define CAN_IE_ELOE_SHIFT                        (22U)
+#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK                          (0x800000U)
+#define CAN_IE_EPE_SHIFT                         (23U)
+#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK                          (0x1000000U)
+#define CAN_IE_EWE_SHIFT                         (24U)
+#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK                          (0x2000000U)
+#define CAN_IE_BOE_SHIFT                         (25U)
+#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK                         (0x4000000U)
+#define CAN_IE_WDIE_SHIFT                        (26U)
+#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK                         (0x8000000U)
+#define CAN_IE_PEAE_SHIFT                        (27U)
+#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK                         (0x10000000U)
+#define CAN_IE_PEDE_SHIFT                        (28U)
+#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK                         (0x20000000U)
+#define CAN_IE_ARAE_SHIFT                        (29U)
+#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+
+/*! @name ILS - Interrupt Line Select */
+#define CAN_ILS_RF0NL_MASK                       (0x1U)
+#define CAN_ILS_RF0NL_SHIFT                      (0U)
+#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK                       (0x2U)
+#define CAN_ILS_RF0WL_SHIFT                      (1U)
+#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK                       (0x4U)
+#define CAN_ILS_RF0FL_SHIFT                      (2U)
+#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK                       (0x8U)
+#define CAN_ILS_RF0LL_SHIFT                      (3U)
+#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK                       (0x10U)
+#define CAN_ILS_RF1NL_SHIFT                      (4U)
+#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK                       (0x20U)
+#define CAN_ILS_RF1WL_SHIFT                      (5U)
+#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK                       (0x40U)
+#define CAN_ILS_RF1FL_SHIFT                      (6U)
+#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK                       (0x80U)
+#define CAN_ILS_RF1LL_SHIFT                      (7U)
+#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK                        (0x100U)
+#define CAN_ILS_HPML_SHIFT                       (8U)
+#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK                         (0x200U)
+#define CAN_ILS_TCL_SHIFT                        (9U)
+#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK                        (0x400U)
+#define CAN_ILS_TCFL_SHIFT                       (10U)
+#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK                        (0x800U)
+#define CAN_ILS_TFEL_SHIFT                       (11U)
+#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK                       (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT                      (12U)
+#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK                       (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT                      (13U)
+#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK                       (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT                      (14U)
+#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK                       (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT                      (15U)
+#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK                        (0x10000U)
+#define CAN_ILS_TSWL_SHIFT                       (16U)
+#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK                       (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT                      (17U)
+#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK                        (0x40000U)
+#define CAN_ILS_TOOL_SHIFT                       (18U)
+#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK                        (0x80000U)
+#define CAN_ILS_DRXL_SHIFT                       (19U)
+#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK                        (0x100000U)
+#define CAN_ILS_BECL_SHIFT                       (20U)
+#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK                        (0x200000U)
+#define CAN_ILS_BEUL_SHIFT                       (21U)
+#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK                        (0x400000U)
+#define CAN_ILS_ELOL_SHIFT                       (22U)
+#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK                         (0x800000U)
+#define CAN_ILS_EPL_SHIFT                        (23U)
+#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK                         (0x1000000U)
+#define CAN_ILS_EWL_SHIFT                        (24U)
+#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK                         (0x2000000U)
+#define CAN_ILS_BOL_SHIFT                        (25U)
+#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK                        (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT                       (26U)
+#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK                        (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT                       (27U)
+#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK                        (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT                       (28U)
+#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK                        (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT                       (29U)
+#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+
+/*! @name ILE - Interrupt Line Enable */
+#define CAN_ILE_EINT0_MASK                       (0x1U)
+#define CAN_ILE_EINT0_SHIFT                      (0U)
+#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK                       (0x2U)
+#define CAN_ILE_EINT1_SHIFT                      (1U)
+#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+
+/*! @name GFC - Global Filter Configuration */
+#define CAN_GFC_RRFE_MASK                        (0x1U)
+#define CAN_GFC_RRFE_SHIFT                       (0U)
+#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK                        (0x2U)
+#define CAN_GFC_RRFS_SHIFT                       (1U)
+#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK                        (0xCU)
+#define CAN_GFC_ANFE_SHIFT                       (2U)
+#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK                        (0x30U)
+#define CAN_GFC_ANFS_SHIFT                       (4U)
+#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
+#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT                      (16U)
+#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT                    (2U)
+#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT                      (16U)
+#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+
+/*! @name XIDAM - Extended ID AND Mask */
+#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT                     (0U)
+#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+
+/*! @name HPMS - High Priority Message Status */
+#define CAN_HPMS_BIDX_MASK                       (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT                      (0U)
+#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK                        (0xC0U)
+#define CAN_HPMS_MSI_SHIFT                       (6U)
+#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT                      (8U)
+#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK                       (0x8000U)
+#define CAN_HPMS_FLST_SHIFT                      (15U)
+#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+
+/*! @name NDAT1 - New Data 1 */
+#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT                       (0U)
+#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+
+/*! @name NDAT2 - New Data 2 */
+#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT                       (0U)
+#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT                     (2U)
+#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT                      (16U)
+#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT                     (24U)
+#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT                     (31U)
+#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT                     (0U)
+#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT                     (8U)
+#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT                     (16U)
+#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT                      (24U)
+#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT                     (25U)
+#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT                     (0U)
+#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+
+/*! @name RXBC - Rx Buffer Configuration */
+#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT                      (2U)
+#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT                     (2U)
+#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT                      (16U)
+#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT                     (24U)
+#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT                     (31U)
+#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT                     (0U)
+#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT                     (8U)
+#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT                     (16U)
+#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT                      (24U)
+#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT                     (25U)
+#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT                     (0U)
+#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+#define CAN_RXESC_F0DS_MASK                      (0x7U)
+#define CAN_RXESC_F0DS_SHIFT                     (0U)
+#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK                      (0x70U)
+#define CAN_RXESC_F1DS_SHIFT                     (4U)
+#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK                      (0x700U)
+#define CAN_RXESC_RBDS_SHIFT                     (8U)
+#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+
+/*! @name TXBC - Tx Buffer Configuration */
+#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT                      (2U)
+#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT                      (16U)
+#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT                      (24U)
+#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT                      (30U)
+#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT                     (8U)
+#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
+#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT                     (21U)
+#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+#define CAN_TXESC_TBDS_MASK                      (0x7U)
+#define CAN_TXESC_TBDS_SHIFT                     (0U)
+#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT                      (0U)
+#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+
+/*! @name TXBAR - Tx Buffer Add Request */
+#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT                       (0U)
+#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT                       (0U)
+#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT                       (0U)
+#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT                       (0U)
+#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT                     (0U)
+#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
+#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT                     (2U)
+#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT                      (16U)
+#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT                     (24U)
+#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+
+/*! @name TXEFS - Tx Event FIFO Status */
+#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT                     (0U)
+#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT                     (8U)
+#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT                     (16U)
+#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT                      (24U)
+#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT                     (25U)
+#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT                     (0U)
+#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+
+/*! @name MRBA - CAN Message RAM Base Address */
+#define CAN_MRBA_BA_MASK                         (0xFFFFFFFFU)
+#define CAN_MRBA_BA_SHIFT                        (0U)
+#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT                     (0U)
+#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT                     (31U)
+#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+
+/*! @name ETSCV - External Timestamp Counter Value */
+#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT                     (0U)
+#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+
+/*! @name SEED - CRC seed register */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+
+/*! @name SUM - CRC checksum register */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+
+/*! @name WR_DATA - CRC data register */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+/*! @name TC - Timer Counter */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+
+/*! @name PR - Prescale Register */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+
+/*! @name PC - Prescale Counter */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+
+/*! @name MCR - Match Control Register */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+
+/*! @name MSR - Match Shadow Register */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[30];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+
+/*! @name INTSTAT - Interrupt status. */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (30U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (30U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (30U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+
+/*! @name IOCFG - I/O Configuration register */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+
+/*! @name USE2FS - Use 2FS register */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+
+/*! @name HWVADST10 - HWVAD control register */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+
+/*! @name ID - Module Identification register */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EEPROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
+ * @{
+ */
+
+/** EEPROM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CMD;                               /**< EEPROM command register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RWSTATE;                           /**< EEPROM read wait state register, offset: 0x8 */
+  __IO uint32_t AUTOPROG;                          /**< EEPROM auto programming register, offset: 0xC */
+  __IO uint32_t WSTATE;                            /**< EEPROM wait state register, offset: 0x10 */
+  __IO uint32_t CLKDIV;                            /**< EEPROM clock divider register, offset: 0x14 */
+  __IO uint32_t PWRDWN;                            /**< EEPROM power-down register, offset: 0x18 */
+       uint8_t RESERVED_1[4028];
+  __O  uint32_t INTENCLR;                          /**< EEPROM interrupt enable clear, offset: 0xFD8 */
+  __O  uint32_t INTENSET;                          /**< EEPROM interrupt enable set, offset: 0xFDC */
+  __I  uint32_t INTSTAT;                           /**< EEPROM interrupt status, offset: 0xFE0 */
+  __I  uint32_t INTEN;                             /**< EEPROM interrupt enable, offset: 0xFE4 */
+  __O  uint32_t INTSTATCLR;                        /**< EEPROM interrupt status clear, offset: 0xFE8 */
+  __O  uint32_t INTSTATSET;                        /**< EEPROM interrupt status set, offset: 0xFEC */
+} EEPROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EEPROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
+ * @{
+ */
+
+/*! @name CMD - EEPROM command register */
+#define EEPROM_CMD_CMD_MASK                      (0x7U)
+#define EEPROM_CMD_CMD_SHIFT                     (0U)
+#define EEPROM_CMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
+
+/*! @name RWSTATE - EEPROM read wait state register */
+#define EEPROM_RWSTATE_RPHASE2_MASK              (0xFFU)
+#define EEPROM_RWSTATE_RPHASE2_SHIFT             (0U)
+#define EEPROM_RWSTATE_RPHASE2(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
+#define EEPROM_RWSTATE_RPHASE1_MASK              (0xFF00U)
+#define EEPROM_RWSTATE_RPHASE1_SHIFT             (8U)
+#define EEPROM_RWSTATE_RPHASE1(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
+
+/*! @name AUTOPROG - EEPROM auto programming register */
+#define EEPROM_AUTOPROG_AUTOPROG_MASK            (0x3U)
+#define EEPROM_AUTOPROG_AUTOPROG_SHIFT           (0U)
+#define EEPROM_AUTOPROG_AUTOPROG(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
+
+/*! @name WSTATE - EEPROM wait state register */
+#define EEPROM_WSTATE_PHASE3_MASK                (0xFFU)
+#define EEPROM_WSTATE_PHASE3_SHIFT               (0U)
+#define EEPROM_WSTATE_PHASE3(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
+#define EEPROM_WSTATE_PHASE2_MASK                (0xFF00U)
+#define EEPROM_WSTATE_PHASE2_SHIFT               (8U)
+#define EEPROM_WSTATE_PHASE2(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
+#define EEPROM_WSTATE_PHASE1_MASK                (0xFF0000U)
+#define EEPROM_WSTATE_PHASE1_SHIFT               (16U)
+#define EEPROM_WSTATE_PHASE1(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
+#define EEPROM_WSTATE_LCK_PARWEP_MASK            (0x80000000U)
+#define EEPROM_WSTATE_LCK_PARWEP_SHIFT           (31U)
+#define EEPROM_WSTATE_LCK_PARWEP(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
+
+/*! @name CLKDIV - EEPROM clock divider register */
+#define EEPROM_CLKDIV_CLKDIV_MASK                (0xFFFFU)
+#define EEPROM_CLKDIV_CLKDIV_SHIFT               (0U)
+#define EEPROM_CLKDIV_CLKDIV(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
+
+/*! @name PWRDWN - EEPROM power-down register */
+#define EEPROM_PWRDWN_PWRDWN_MASK                (0x1U)
+#define EEPROM_PWRDWN_PWRDWN_SHIFT               (0U)
+#define EEPROM_PWRDWN_PWRDWN(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
+
+/*! @name INTENCLR - EEPROM interrupt enable clear */
+#define EEPROM_INTENCLR_PROG_CLR_EN_MASK         (0x4U)
+#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT        (2U)
+#define EEPROM_INTENCLR_PROG_CLR_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
+
+/*! @name INTENSET - EEPROM interrupt enable set */
+#define EEPROM_INTENSET_PROG_SET_EN_MASK         (0x4U)
+#define EEPROM_INTENSET_PROG_SET_EN_SHIFT        (2U)
+#define EEPROM_INTENSET_PROG_SET_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
+
+/*! @name INTSTAT - EEPROM interrupt status */
+#define EEPROM_INTSTAT_END_OF_PROG_MASK          (0x4U)
+#define EEPROM_INTSTAT_END_OF_PROG_SHIFT         (2U)
+#define EEPROM_INTSTAT_END_OF_PROG(x)            (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
+
+/*! @name INTEN - EEPROM interrupt enable */
+#define EEPROM_INTEN_EE_PROG_DONE_MASK           (0x4U)
+#define EEPROM_INTEN_EE_PROG_DONE_SHIFT          (2U)
+#define EEPROM_INTEN_EE_PROG_DONE(x)             (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
+
+/*! @name INTSTATCLR - EEPROM interrupt status clear */
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK       (0x4U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT      (2U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
+
+/*! @name INTSTATSET - EEPROM interrupt status set */
+#define EEPROM_INTSTATSET_PROG_SET_ST_MASK       (0x4U)
+#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT      (2U)
+#define EEPROM_INTSTATSET_PROG_SET_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Register_Masks */
+
+
+/* EEPROM - Peripheral instance base addresses */
+/** Peripheral EEPROM base address */
+#define EEPROM_BASE                              (0x40014000u)
+/** Peripheral EEPROM base pointer */
+#define EEPROM                                   ((EEPROM_Type *)EEPROM_BASE)
+/** Array initializer of EEPROM peripheral base addresses */
+#define EEPROM_BASE_ADDRS                        { EEPROM_BASE }
+/** Array initializer of EEPROM peripheral base pointers */
+#define EEPROM_BASE_PTRS                         { EEPROM }
+/** Interrupt vectors for the EEPROM peripheral type */
+#define EEPROM_IRQS                              { EEPROM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
+  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
+  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
+  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
+  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
+  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
+  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
+  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
+  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
+  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
+  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
+  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
+  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
+  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
+       uint8_t RESERVED_3[124];
+  struct {                                         /* offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+         uint8_t RESERVED_0[24];
+  } DYNAMIC[4];
+       uint8_t RESERVED_4[128];
+  struct {                                         /* offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+         uint8_t RESERVED_0[4];
+  } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+#define EMC_CONTROL_E_MASK                       (0x1U)
+#define EMC_CONTROL_E_SHIFT                      (0U)
+#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK                       (0x2U)
+#define EMC_CONTROL_M_SHIFT                      (1U)
+#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK                       (0x4U)
+#define EMC_CONTROL_L_SHIFT                      (2U)
+#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+
+/*! @name STATUS - Provides EMC status information */
+#define EMC_STATUS_B_MASK                        (0x1U)
+#define EMC_STATUS_B_SHIFT                       (0U)
+#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK                        (0x2U)
+#define EMC_STATUS_S_SHIFT                       (1U)
+#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK                       (0x4U)
+#define EMC_STATUS_SA_SHIFT                      (2U)
+#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+
+/*! @name CONFIG - Configures operation of the memory controller */
+#define EMC_CONFIG_EM_MASK                       (0x1U)
+#define EMC_CONFIG_EM_SHIFT                      (0U)
+#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK                     (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT                    (8U)
+#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
+#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
+#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
+#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
+#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
+#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
+#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
+#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+
+/*! @name DYNAMICRP - Precharge command period */
+#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
+#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
+#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
+#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
+#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
+#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+
+/*! @name DYNAMICWR - Write recovery time */
+#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
+#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
+#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
+#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
+#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
+#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
+#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
+#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
+#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
+#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
+#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
+#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
+#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
+#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
+#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
+#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE                                 (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC                                      ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS                           { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS                            { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MAC_CONFIG;                        /**< MAC configuration register, offset: 0x0 */
+  __IO uint32_t MAC_EXT_CONFIG;                    /**< , offset: 0x4 */
+  __IO uint32_t MAC_FRAME_FILTER;                  /**< MAC frame filter register, offset: 0x8 */
+  __IO uint32_t MAC_WD_TIMEROUT;                   /**< MAC watchdog Timeout register, offset: 0xC */
+       uint8_t RESERVED_0[64];
+  __IO uint32_t MAC_VLAN_TAG;                      /**< MAC vlan tag register, offset: 0x50 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t MAC_TX_FLOW_CTRL_Q[2];             /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< Receive flow control register, offset: 0x90 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MAC_TXQ_PRIO_MAP;                  /**< , offset: 0x98 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MAC_RXQ_CTRL[3];                   /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[4];
+  __I  uint32_t MAC_INTR_STAT;                     /**< Interrupt status register 0x0000, offset: 0xB0 */
+  __IO uint32_t MAC_INTR_EN;                       /**< Interrupt enable register 0x0000, offset: 0xB4 */
+  __I  uint32_t MAC_RXTX_STAT;                     /**< Receive Transmit Status register, offset: 0xB8 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t MAC_PMT_CRTL_STAT;                 /**< , offset: 0xC0 */
+  __IO uint32_t MAC_RWAKE_FRFLT;                   /**< Remote wake-up frame filter, offset: 0xC4 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t MAC_LPI_CTRL_STAT;                 /**< LPI Control and Status Register, offset: 0xD0 */
+  __IO uint32_t MAC_LPI_TIMER_CTRL;                /**< LPI Timers Control register, offset: 0xD4 */
+  __IO uint32_t MAC_LPI_ENTR_TIMR;                 /**< LPI entry Timer register, offset: 0xD8 */
+  __IO uint32_t MAC_1US_TIC_COUNTR;                /**< , offset: 0xDC */
+       uint8_t RESERVED_8[48];
+  __IO uint32_t MAC_VERSION;                       /**< MAC version register, offset: 0x110 */
+  __I  uint32_t MAC_DBG;                           /**< MAC debug register, offset: 0x114 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t MAC_HW_FEAT[3];                    /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
+       uint8_t RESERVED_10[216];
+  __IO uint32_t MAC_MDIO_ADDR;                     /**< MIDO address Register, offset: 0x200 */
+  __IO uint32_t MAC_MDIO_DATA;                     /**< MDIO Data register, offset: 0x204 */
+       uint8_t RESERVED_11[248];
+  __IO uint32_t MAC_ADDR_HIGH;                     /**< MAC address0 high register, offset: 0x300 */
+  __IO uint32_t MAC_ADDR_LOW;                      /**< MAC address0 low register, offset: 0x304 */
+       uint8_t RESERVED_12[2040];
+  __IO uint32_t MAC_TIMESTAMP_CTRL;                /**< Time stamp control register, offset: 0xB00 */
+  __IO uint32_t MAC_SUB_SCND_INCR;                 /**< Sub-second increment register, offset: 0xB04 */
+  __I  uint32_t MAC_SYS_TIME_SCND;                 /**< System time seconds register, offset: 0xB08 */
+  __I  uint32_t MAC_SYS_TIME_NSCND;                /**< System time nanoseconds register, offset: 0xB0C */
+  __IO uint32_t MAC_SYS_TIME_SCND_UPD;             /**< , offset: 0xB10 */
+  __IO uint32_t MAC_SYS_TIME_NSCND_UPD;            /**< , offset: 0xB14 */
+  __IO uint32_t MAC_SYS_TIMESTMP_ADDEND;           /**< Time stamp addend register, offset: 0xB18 */
+  __IO uint32_t MAC_SYS_TIME_HWORD_SCND;           /**< , offset: 0xB1C */
+  __I  uint32_t MAC_SYS_TIMESTMP_STAT;             /**< Time stamp status register, offset: 0xB20 */
+       uint8_t RESERVED_13[12];
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Tx timestamp status seconds, offset: 0xB34 */
+       uint8_t RESERVED_14[32];
+  __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
+  __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
+       uint8_t RESERVED_15[160];
+  __IO uint32_t MTL_OP_MODE;                       /**< MTL Operation Mode Register, offset: 0xC00 */
+       uint8_t RESERVED_16[28];
+  __I  uint32_t MTL_INTR_STAT;                     /**< MTL Interrupt Status register, offset: 0xC20 */
+       uint8_t RESERVED_17[12];
+  __IO uint32_t MTL_RXQ_DMA_MAP;                   /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
+       uint8_t RESERVED_18[204];
+  struct {                                         /* offset: 0xD00, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_OP_MODE;                  /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_DBG;                      /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
+         uint8_t RESERVED_0[4];
+    __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_ETS_STAT;                 /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< , array offset: 0xD18, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< , array offset: 0xD2C, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_OP_MODE;                  /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_DBG;                      /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_CTRL;                     /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
+  } MTL_QUEUE[2];
+       uint8_t RESERVED_19[640];
+  __IO uint32_t DMA_MODE;                          /**< DMA mode register, offset: 0x1000 */
+  __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus mode, offset: 0x1004 */
+  __IO uint32_t DMA_INTR_STAT;                     /**< DMA Interrupt status, offset: 0x1008 */
+  __IO uint32_t DMA_DBG_STAT;                      /**< DMA Debug Status, offset: 0x100C */
+       uint8_t RESERVED_20[240];
+  struct {                                         /* offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< , array offset: 0x1114, array step: 0x80 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< , array offset: 0x111C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< , array offset: 0x1120, array step: 0x80 */
+         uint8_t RESERVED_2[4];
+    __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< , array offset: 0x1128, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< , array offset: 0x112C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
+    __IO uint32_t DMA_CHX_INT_EN;                    /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
+    __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
+         uint8_t RESERVED_3[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
+         uint8_t RESERVED_4[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< , array offset: 0x114C, array step: 0x80 */
+         uint8_t RESERVED_5[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< , array offset: 0x1154, array step: 0x80 */
+         uint8_t RESERVED_6[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_STAT;                      /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
+         uint8_t RESERVED_7[28];
+  } DMA_CH[2];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name MAC_CONFIG - MAC configuration register */
+#define ENET_MAC_CONFIG_RE_MASK                  (0x1U)
+#define ENET_MAC_CONFIG_RE_SHIFT                 (0U)
+#define ENET_MAC_CONFIG_RE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
+#define ENET_MAC_CONFIG_TE_MASK                  (0x2U)
+#define ENET_MAC_CONFIG_TE_SHIFT                 (1U)
+#define ENET_MAC_CONFIG_TE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
+#define ENET_MAC_CONFIG_PRELEN_MASK              (0xCU)
+#define ENET_MAC_CONFIG_PRELEN_SHIFT             (2U)
+#define ENET_MAC_CONFIG_PRELEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
+#define ENET_MAC_CONFIG_DC_MASK                  (0x10U)
+#define ENET_MAC_CONFIG_DC_SHIFT                 (4U)
+#define ENET_MAC_CONFIG_DC(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
+#define ENET_MAC_CONFIG_BL_MASK                  (0x60U)
+#define ENET_MAC_CONFIG_BL_SHIFT                 (5U)
+#define ENET_MAC_CONFIG_BL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
+#define ENET_MAC_CONFIG_DR_MASK                  (0x100U)
+#define ENET_MAC_CONFIG_DR_SHIFT                 (8U)
+#define ENET_MAC_CONFIG_DR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
+#define ENET_MAC_CONFIG_DCRS_MASK                (0x200U)
+#define ENET_MAC_CONFIG_DCRS_SHIFT               (9U)
+#define ENET_MAC_CONFIG_DCRS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
+#define ENET_MAC_CONFIG_DO_MASK                  (0x400U)
+#define ENET_MAC_CONFIG_DO_SHIFT                 (10U)
+#define ENET_MAC_CONFIG_DO(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
+#define ENET_MAC_CONFIG_ECRSFD_MASK              (0x800U)
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT             (11U)
+#define ENET_MAC_CONFIG_ECRSFD(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
+#define ENET_MAC_CONFIG_LM_MASK                  (0x1000U)
+#define ENET_MAC_CONFIG_LM_SHIFT                 (12U)
+#define ENET_MAC_CONFIG_LM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
+#define ENET_MAC_CONFIG_DM_MASK                  (0x2000U)
+#define ENET_MAC_CONFIG_DM_SHIFT                 (13U)
+#define ENET_MAC_CONFIG_DM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
+#define ENET_MAC_CONFIG_FES_MASK                 (0x4000U)
+#define ENET_MAC_CONFIG_FES_SHIFT                (14U)
+#define ENET_MAC_CONFIG_FES(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
+#define ENET_MAC_CONFIG_PS_MASK                  (0x8000U)
+#define ENET_MAC_CONFIG_PS_SHIFT                 (15U)
+#define ENET_MAC_CONFIG_PS(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
+#define ENET_MAC_CONFIG_JE_MASK                  (0x10000U)
+#define ENET_MAC_CONFIG_JE_SHIFT                 (16U)
+#define ENET_MAC_CONFIG_JE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
+#define ENET_MAC_CONFIG_JD_MASK                  (0x20000U)
+#define ENET_MAC_CONFIG_JD_SHIFT                 (17U)
+#define ENET_MAC_CONFIG_JD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
+#define ENET_MAC_CONFIG_BE_MASK                  (0x40000U)
+#define ENET_MAC_CONFIG_BE_SHIFT                 (18U)
+#define ENET_MAC_CONFIG_BE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
+#define ENET_MAC_CONFIG_WD_MASK                  (0x80000U)
+#define ENET_MAC_CONFIG_WD_SHIFT                 (19U)
+#define ENET_MAC_CONFIG_WD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
+#define ENET_MAC_CONFIG_ACS_MASK                 (0x100000U)
+#define ENET_MAC_CONFIG_ACS_SHIFT                (20U)
+#define ENET_MAC_CONFIG_ACS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
+#define ENET_MAC_CONFIG_CST_MASK                 (0x200000U)
+#define ENET_MAC_CONFIG_CST_SHIFT                (21U)
+#define ENET_MAC_CONFIG_CST(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
+#define ENET_MAC_CONFIG_S2KP_MASK                (0x400000U)
+#define ENET_MAC_CONFIG_S2KP_SHIFT               (22U)
+#define ENET_MAC_CONFIG_S2KP(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
+#define ENET_MAC_CONFIG_GPSLCE_MASK              (0x800000U)
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT             (23U)
+#define ENET_MAC_CONFIG_GPSLCE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
+#define ENET_MAC_CONFIG_IPG_MASK                 (0x7000000U)
+#define ENET_MAC_CONFIG_IPG_SHIFT                (24U)
+#define ENET_MAC_CONFIG_IPG(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
+#define ENET_MAC_CONFIG_IPC_MASK                 (0x8000000U)
+#define ENET_MAC_CONFIG_IPC_SHIFT                (27U)
+#define ENET_MAC_CONFIG_IPC(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
+
+/*! @name MAC_EXT_CONFIG -  */
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK            (0x3FFFU)
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT           (0U)
+#define ENET_MAC_EXT_CONFIG_GPSL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK           (0x10000U)
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT          (16U)
+#define ENET_MAC_EXT_CONFIG_DCRCC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK            (0x20000U)
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT           (17U)
+#define ENET_MAC_EXT_CONFIG_SPEN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
+#define ENET_MAC_EXT_CONFIG_USP_MASK             (0x40000U)
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT            (18U)
+#define ENET_MAC_EXT_CONFIG_USP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
+
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */
+#define ENET_MAC_FRAME_FILTER_PR_MASK            (0x1U)
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT           (0U)
+#define ENET_MAC_FRAME_FILTER_PR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK          (0x8U)
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT         (3U)
+#define ENET_MAC_FRAME_FILTER_DAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_PM_MASK            (0x10U)
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT           (4U)
+#define ENET_MAC_FRAME_FILTER_PM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
+#define ENET_MAC_FRAME_FILTER_DBF_MASK           (0x20U)
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT          (5U)
+#define ENET_MAC_FRAME_FILTER_DBF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
+#define ENET_MAC_FRAME_FILTER_PCF_MASK           (0xC0U)
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT          (6U)
+#define ENET_MAC_FRAME_FILTER_PCF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK          (0x100U)
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT         (8U)
+#define ENET_MAC_FRAME_FILTER_SAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAF_MASK           (0x200U)
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT          (9U)
+#define ENET_MAC_FRAME_FILTER_SAF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
+#define ENET_MAC_FRAME_FILTER_RA_MASK            (0x80000000U)
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT           (31U)
+#define ENET_MAC_FRAME_FILTER_RA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
+
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK            (0xFU)
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT           (0U)
+#define ENET_MAC_WD_TIMEROUT_WTO(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK            (0x100U)
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT           (8U)
+#define ENET_MAC_WD_TIMEROUT_PWE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
+
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */
+#define ENET_MAC_VLAN_TAG_VL_MASK                (0xFFFFU)
+#define ENET_MAC_VLAN_TAG_VL_SHIFT               (0U)
+#define ENET_MAC_VLAN_TAG_VL(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
+#define ENET_MAC_VLAN_TAG_ETV_MASK               (0x10000U)
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT              (16U)
+#define ENET_MAC_VLAN_TAG_ETV(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
+#define ENET_MAC_VLAN_TAG_VTIM_MASK              (0x20000U)
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT             (17U)
+#define ENET_MAC_VLAN_TAG_VTIM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
+#define ENET_MAC_VLAN_TAG_ESVL_MASK              (0x40000U)
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT             (18U)
+#define ENET_MAC_VLAN_TAG_ESVL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK            (0x80000U)
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT           (19U)
+#define ENET_MAC_VLAN_TAG_ERSVLM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK            (0x100000U)
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT           (20U)
+#define ENET_MAC_VLAN_TAG_DOVLTC(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
+#define ENET_MAC_VLAN_TAG_EVLS_MASK              (0x600000U)
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT             (21U)
+#define ENET_MAC_VLAN_TAG_EVLS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK            (0x1000000U)
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT           (24U)
+#define ENET_MAC_VLAN_TAG_EVLRXS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
+#define ENET_MAC_VLAN_TAG_VTHM_MASK              (0x2000000U)
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT             (25U)
+#define ENET_MAC_VLAN_TAG_VTHM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK             (0x4000000U)
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT            (26U)
+#define ENET_MAC_VLAN_TAG_EDVLP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK            (0x8000000U)
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT           (27U)
+#define ENET_MAC_VLAN_TAG_ERIVLT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK             (0x30000000U)
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT            (28U)
+#define ENET_MAC_VLAN_TAG_EIVLS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK           (0x80000000U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT          (31U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
+
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK         (0x1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT        (0U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK         (0x2U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT        (1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK         (0x70U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT        (4U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK        (0x80U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT       (7U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK          (0xFFFF0000U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT         (16U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
+
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT            (2U)
+
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK           (0x1U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT          (0U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK            (0x2U)
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT           (1U)
+#define ENET_MAC_RX_FLOW_CTRL_UP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
+
+/*! @name MAC_TXQ_PRIO_MAP -  */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK         (0xFFU)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT        (0U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK         (0xFF00U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT        (8U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
+
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK            (0x3U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT           (0U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK             (0xFFU)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT            (0U)
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK             (0x7U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT            (0U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK            (0xCU)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT           (2U)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK            (0x70U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT           (4U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK             (0xFF00U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT            (8U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK               (0x7000U)
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT              (12U)
+#define ENET_MAC_RXQ_CTRL_UPQ(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK             (0xFF0000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT            (16U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK             (0x70000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT            (16U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK           (0x100000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT          (20U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK             (0xFF000000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT            (24U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
+
+/* The count of ENET_MAC_RXQ_CTRL */
+#define ENET_MAC_RXQ_CTRL_COUNT                  (3U)
+
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
+#define ENET_MAC_INTR_STAT_PHYIS_MASK            (0x8U)
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT           (3U)
+#define ENET_MAC_INTR_STAT_PHYIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
+#define ENET_MAC_INTR_STAT_PMTIS_MASK            (0x10U)
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT           (4U)
+#define ENET_MAC_INTR_STAT_PMTIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
+#define ENET_MAC_INTR_STAT_LPIIS_MASK            (0x20U)
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT           (5U)
+#define ENET_MAC_INTR_STAT_LPIIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
+#define ENET_MAC_INTR_STAT_TSIS_MASK             (0x1000U)
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT            (12U)
+#define ENET_MAC_INTR_STAT_TSIS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK          (0x2000U)
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT         (13U)
+#define ENET_MAC_INTR_STAT_TXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK          (0x4000U)
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT         (14U)
+#define ENET_MAC_INTR_STAT_RXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
+
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
+#define ENET_MAC_INTR_EN_PHYIE_MASK              (0x8U)
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT             (3U)
+#define ENET_MAC_INTR_EN_PHYIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
+#define ENET_MAC_INTR_EN_PMTIE_MASK              (0x10U)
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT             (4U)
+#define ENET_MAC_INTR_EN_PMTIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
+#define ENET_MAC_INTR_EN_LPIIE_MASK              (0x20U)
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT             (5U)
+#define ENET_MAC_INTR_EN_LPIIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
+#define ENET_MAC_INTR_EN_TSIE_MASK               (0x1000U)
+#define ENET_MAC_INTR_EN_TSIE_SHIFT              (12U)
+#define ENET_MAC_INTR_EN_TSIE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK            (0x2000U)
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT           (13U)
+#define ENET_MAC_INTR_EN_TXSTSIE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK            (0x4000U)
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT           (14U)
+#define ENET_MAC_INTR_EN_RXSTSIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
+
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
+#define ENET_MAC_RXTX_STAT_TJT_MASK              (0x1U)
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT             (0U)
+#define ENET_MAC_RXTX_STAT_TJT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
+#define ENET_MAC_RXTX_STAT_NCARR_MASK            (0x2U)
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT           (1U)
+#define ENET_MAC_RXTX_STAT_NCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
+#define ENET_MAC_RXTX_STAT_LCARR_MASK            (0x4U)
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT           (2U)
+#define ENET_MAC_RXTX_STAT_LCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK            (0x8U)
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT           (3U)
+#define ENET_MAC_RXTX_STAT_EXDEF(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
+#define ENET_MAC_RXTX_STAT_LCOL_MASK             (0x10U)
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT            (4U)
+#define ENET_MAC_RXTX_STAT_LCOL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK            (0x20U)
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT           (5U)
+#define ENET_MAC_RXTX_STAT_EXCOL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
+#define ENET_MAC_RXTX_STAT_RWT_MASK              (0x100U)
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT             (8U)
+#define ENET_MAC_RXTX_STAT_RWT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
+
+/*! @name MAC_PMT_CRTL_STAT -  */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK       (0x1U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT      (0U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK     (0x2U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT    (1U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK     (0x4U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT    (2U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK     (0x20U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT    (5U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK     (0x40U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT    (6U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK    (0x200U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT   (9U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK       (0x400U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT      (10U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK       (0x1F000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT      (24U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK   (0x80000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT  (31U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
+
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK           (0xFFFFFFFFU)
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT          (0U)
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
+
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK       (0x1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT      (0U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK       (0x2U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT      (1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK       (0x4U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT      (2U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK       (0x8U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT      (3U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK       (0x100U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT      (8U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK       (0x200U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT      (9U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK        (0x10000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT       (16U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK          (0x20000U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT         (17U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK       (0x80000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT      (19U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK       (0x100000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT      (20U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK      (0x200000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT     (21U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
+
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK         (0xFFFFU)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT        (0U)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK         (0x3FF0000U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT        (16U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
+
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK        (0xFFFF8U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT       (3U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
+
+/*! @name MAC_1US_TIC_COUNTR -  */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
+
+/*! @name MAC_VERSION - MAC version register */
+#define ENET_MAC_VERSION_SNPVER_MASK             (0xFFU)
+#define ENET_MAC_VERSION_SNPVER_SHIFT            (0U)
+#define ENET_MAC_VERSION_SNPVER(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
+#define ENET_MAC_VERSION_USERVER_MASK            (0xFF00U)
+#define ENET_MAC_VERSION_USERVER_SHIFT           (8U)
+#define ENET_MAC_VERSION_USERVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
+
+/*! @name MAC_DBG - MAC debug register */
+#define ENET_MAC_DBG_REPESTS_MASK                (0x1U)
+#define ENET_MAC_DBG_REPESTS_SHIFT               (0U)
+#define ENET_MAC_DBG_REPESTS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
+#define ENET_MAC_DBG_RFCFCSTS_MASK               (0x6U)
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT              (1U)
+#define ENET_MAC_DBG_RFCFCSTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
+#define ENET_MAC_DBG_TPESTS_MASK                 (0x10000U)
+#define ENET_MAC_DBG_TPESTS_SHIFT                (16U)
+#define ENET_MAC_DBG_TPESTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
+#define ENET_MAC_DBG_TFCSTS_MASK                 (0x60000U)
+#define ENET_MAC_DBG_TFCSTS_SHIFT                (17U)
+#define ENET_MAC_DBG_TFCSTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
+
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK         (0x1FU)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT        (0U)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK             (0xFU)
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT            (0U)
+#define ENET_MAC_HW_FEAT_RXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_MIISEL_MASK             (0x1U)
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT            (0U)
+#define ENET_MAC_HW_FEAT_MIISEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
+#define ENET_MAC_HW_FEAT_HDSEL_MASK              (0x4U)
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT             (2U)
+#define ENET_MAC_HW_FEAT_HDSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
+#define ENET_MAC_HW_FEAT_VLHASH_MASK             (0x10U)
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT            (4U)
+#define ENET_MAC_HW_FEAT_VLHASH(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
+#define ENET_MAC_HW_FEAT_SMASEL_MASK             (0x20U)
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT            (5U)
+#define ENET_MAC_HW_FEAT_SMASEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK             (0x3C0U)
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT            (6U)
+#define ENET_MAC_HW_FEAT_TXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK             (0x40U)
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT            (6U)
+#define ENET_MAC_HW_FEAT_RWKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK         (0x7C0U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT        (6U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK             (0x80U)
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT            (7U)
+#define ENET_MAC_HW_FEAT_MGKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK             (0x100U)
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT            (8U)
+#define ENET_MAC_HW_FEAT_MMCSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK          (0x200U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT         (9U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
+#define ENET_MAC_HW_FEAT_OSTEN_MASK              (0x800U)
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT             (11U)
+#define ENET_MAC_HW_FEAT_OSTEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK            (0xF000U)
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT           (12U)
+#define ENET_MAC_HW_FEAT_RXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSSEL_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT             (12U)
+#define ENET_MAC_HW_FEAT_TSSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
+#define ENET_MAC_HW_FEAT_PTOEN_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT             (12U)
+#define ENET_MAC_HW_FEAT_PTOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
+#define ENET_MAC_HW_FEAT_EEESEL_MASK             (0x2000U)
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT            (13U)
+#define ENET_MAC_HW_FEAT_EEESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK          (0x2000U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT         (13U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
+#define ENET_MAC_HW_FEAT_ADDR64_MASK             (0xC000U)
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT            (14U)
+#define ENET_MAC_HW_FEAT_ADDR64(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK           (0x4000U)
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT          (14U)
+#define ENET_MAC_HW_FEAT_TXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_DCBEN_MASK              (0x10000U)
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT             (16U)
+#define ENET_MAC_HW_FEAT_DCBEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK           (0x10000U)
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT          (16U)
+#define ENET_MAC_HW_FEAT_RXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_SPEN_MASK               (0x20000U)
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT              (17U)
+#define ENET_MAC_HW_FEAT_SPEN(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK            (0x3C0000U)
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT           (18U)
+#define ENET_MAC_HW_FEAT_TXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSOEN_MASK              (0x40000U)
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT             (18U)
+#define ENET_MAC_HW_FEAT_TSOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK            (0x80000U)
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT           (19U)
+#define ENET_MAC_HW_FEAT_DBGMEMA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
+#define ENET_MAC_HW_FEAT_AVSEL_MASK              (0x100000U)
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT             (20U)
+#define ENET_MAC_HW_FEAT_AVSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK           (0x800000U)
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT          (23U)
+#define ENET_MAC_HW_FEAT_LPMODEEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK          (0x7000000U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT         (24U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK          (0x3000000U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT         (24U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK           (0x6000000U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT          (25U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK       (0x78000000U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT      (27U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK         (0x70000000U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT        (28U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK          (0x70000000U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT         (28U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
+
+/* The count of ENET_MAC_HW_FEAT */
+#define ENET_MAC_HW_FEAT_COUNT                   (3U)
+
+/*! @name MAC_MDIO_ADDR - MIDO address Register */
+#define ENET_MAC_MDIO_ADDR_MB_MASK               (0x1U)
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT              (0U)
+#define ENET_MAC_MDIO_ADDR_MB(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
+#define ENET_MAC_MDIO_ADDR_MOC_MASK              (0xCU)
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT             (2U)
+#define ENET_MAC_MDIO_ADDR_MOC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
+#define ENET_MAC_MDIO_ADDR_CR_MASK               (0xF00U)
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT              (8U)
+#define ENET_MAC_MDIO_ADDR_CR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
+#define ENET_MAC_MDIO_ADDR_NTC_MASK              (0x7000U)
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT             (12U)
+#define ENET_MAC_MDIO_ADDR_NTC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
+#define ENET_MAC_MDIO_ADDR_RDA_MASK              (0x1F0000U)
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT             (16U)
+#define ENET_MAC_MDIO_ADDR_RDA(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
+#define ENET_MAC_MDIO_ADDR_PA_MASK               (0x3E00000U)
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT              (21U)
+#define ENET_MAC_MDIO_ADDR_PA(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
+#define ENET_MAC_MDIO_ADDR_BTB_MASK              (0x4000000U)
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT             (26U)
+#define ENET_MAC_MDIO_ADDR_BTB(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
+#define ENET_MAC_MDIO_ADDR_PSE_MASK              (0x8000000U)
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT             (27U)
+#define ENET_MAC_MDIO_ADDR_PSE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
+
+/*! @name MAC_MDIO_DATA - MDIO Data register */
+#define ENET_MAC_MDIO_DATA_MD_MASK               (0xFFFFU)
+#define ENET_MAC_MDIO_DATA_MD_SHIFT              (0U)
+#define ENET_MAC_MDIO_DATA_MD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
+
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK           (0xFFFFU)
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT          (0U)
+#define ENET_MAC_ADDR_HIGH_A47_32(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
+#define ENET_MAC_ADDR_HIGH_DCS_MASK              (0x10000U)
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT             (16U)
+#define ENET_MAC_ADDR_HIGH_DCS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
+#define ENET_MAC_ADDR_HIGH_AE_MASK               (0x80000000U)
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT              (31U)
+#define ENET_MAC_ADDR_HIGH_AE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
+
+/*! @name MAC_ADDR_LOW - MAC address0 low register */
+#define ENET_MAC_ADDR_LOW_A31_0_MASK             (0xFFFFFFFFU)
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT            (0U)
+#define ENET_MAC_ADDR_LOW_A31_0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
+
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK       (0x1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT      (0U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK    (0x2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT   (1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK      (0x4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT     (2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK      (0x8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT     (3U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK      (0x10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT     (4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK     (0x20U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT    (5U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK     (0x100U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT    (8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK   (0x200U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT  (9U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK   (0x400U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT  (10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK     (0x800U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT    (11U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK   (0x1000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT  (12U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK   (0x2000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT  (13U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK    (0x4000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT   (14U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK   (0x8000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT  (15U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK  (0x30000U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK   (0x1000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT  (24U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
+
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK        (0xFF0000U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT       (16U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
+
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK          (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT         (0U)
+#define ENET_MAC_SYS_TIME_SCND_TSS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK        (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT       (0U)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
+
+/*! @name MAC_SYS_TIME_SCND_UPD -  */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK      (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT     (0U)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND_UPD -  */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK    (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT   (0U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK  (0x80000000U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK   (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT  (0U)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
+
+/*! @name MAC_SYS_TIME_HWORD_SCND -  */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK  (0xFFFFU)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK   (0x1U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT  (0U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
+
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */
+#define ENET_MTL_OP_MODE_DTXSTS_MASK             (0x2U)
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT            (1U)
+#define ENET_MTL_OP_MODE_DTXSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
+#define ENET_MTL_OP_MODE_RAA_MASK                (0x4U)
+#define ENET_MTL_OP_MODE_RAA_SHIFT               (2U)
+#define ENET_MTL_OP_MODE_RAA(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
+#define ENET_MTL_OP_MODE_SCHALG_MASK             (0x60U)
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT            (5U)
+#define ENET_MTL_OP_MODE_SCHALG(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
+#define ENET_MTL_OP_MODE_CNTPRST_MASK            (0x100U)
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT           (8U)
+#define ENET_MTL_OP_MODE_CNTPRST(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
+#define ENET_MTL_OP_MODE_CNTCLR_MASK             (0x200U)
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT            (9U)
+#define ENET_MTL_OP_MODE_CNTCLR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
+
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
+#define ENET_MTL_INTR_STAT_Q0IS_MASK             (0x1U)
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT            (0U)
+#define ENET_MTL_INTR_STAT_Q0IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
+#define ENET_MTL_INTR_STAT_Q1IS_MASK             (0x2U)
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT            (1U)
+#define ENET_MTL_INTR_STAT_Q1IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
+
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK       (0x1U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT      (0U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK       (0x10U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT      (4U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK       (0x100U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT      (8U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK       (0x1000U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT      (12U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
+
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK  (0x6U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK  (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK  (0x10U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK    (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT   (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT        (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT   (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT   (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT -  */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT  (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK  (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK  (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT -  */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK  (0x1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK  (0x6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK  (0x30U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK    (0x3FFF0000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT   (16U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT        (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT       (2U)
+
+/*! @name DMA_MODE - DMA mode register */
+#define ENET_DMA_MODE_SWR_MASK                   (0x1U)
+#define ENET_DMA_MODE_SWR_SHIFT                  (0U)
+#define ENET_DMA_MODE_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
+#define ENET_DMA_MODE_DA_MASK                    (0x2U)
+#define ENET_DMA_MODE_DA_SHIFT                   (1U)
+#define ENET_DMA_MODE_DA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
+#define ENET_DMA_MODE_TAA_MASK                   (0x1CU)
+#define ENET_DMA_MODE_TAA_SHIFT                  (2U)
+#define ENET_DMA_MODE_TAA(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
+#define ENET_DMA_MODE_TXPR_MASK                  (0x800U)
+#define ENET_DMA_MODE_TXPR_SHIFT                 (11U)
+#define ENET_DMA_MODE_TXPR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
+#define ENET_DMA_MODE_PR_MASK                    (0x7000U)
+#define ENET_DMA_MODE_PR_SHIFT                   (12U)
+#define ENET_DMA_MODE_PR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
+
+/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
+#define ENET_DMA_SYSBUS_MODE_FB_MASK             (0x1U)
+#define ENET_DMA_SYSBUS_MODE_FB_SHIFT            (0U)
+#define ENET_DMA_SYSBUS_MODE_FB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
+#define ENET_DMA_SYSBUS_MODE_AAL_MASK            (0x1000U)
+#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT           (12U)
+#define ENET_DMA_SYSBUS_MODE_AAL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
+#define ENET_DMA_SYSBUS_MODE_MB_MASK             (0x4000U)
+#define ENET_DMA_SYSBUS_MODE_MB_SHIFT            (14U)
+#define ENET_DMA_SYSBUS_MODE_MB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
+#define ENET_DMA_SYSBUS_MODE_RB_MASK             (0x8000U)
+#define ENET_DMA_SYSBUS_MODE_RB_SHIFT            (15U)
+#define ENET_DMA_SYSBUS_MODE_RB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
+
+/*! @name DMA_INTR_STAT - DMA Interrupt status */
+#define ENET_DMA_INTR_STAT_DC0IS_MASK            (0x1U)
+#define ENET_DMA_INTR_STAT_DC0IS_SHIFT           (0U)
+#define ENET_DMA_INTR_STAT_DC0IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
+#define ENET_DMA_INTR_STAT_DC1IS_MASK            (0x2U)
+#define ENET_DMA_INTR_STAT_DC1IS_SHIFT           (1U)
+#define ENET_DMA_INTR_STAT_DC1IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
+#define ENET_DMA_INTR_STAT_MTLIS_MASK            (0x10000U)
+#define ENET_DMA_INTR_STAT_MTLIS_SHIFT           (16U)
+#define ENET_DMA_INTR_STAT_MTLIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
+#define ENET_DMA_INTR_STAT_MACIS_MASK            (0x20000U)
+#define ENET_DMA_INTR_STAT_MACIS_SHIFT           (17U)
+#define ENET_DMA_INTR_STAT_MACIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
+
+/*! @name DMA_DBG_STAT - DMA Debug Status */
+#define ENET_DMA_DBG_STAT_AHSTS_MASK             (0x1U)
+#define ENET_DMA_DBG_STAT_AHSTS_SHIFT            (0U)
+#define ENET_DMA_DBG_STAT_AHSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
+#define ENET_DMA_DBG_STAT_RPS0_MASK              (0xF00U)
+#define ENET_DMA_DBG_STAT_RPS0_SHIFT             (8U)
+#define ENET_DMA_DBG_STAT_RPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
+#define ENET_DMA_DBG_STAT_TPS0_MASK              (0xF000U)
+#define ENET_DMA_DBG_STAT_TPS0_SHIFT             (12U)
+#define ENET_DMA_DBG_STAT_TPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
+#define ENET_DMA_DBG_STAT_RPS1_MASK              (0xF0000U)
+#define ENET_DMA_DBG_STAT_RPS1_SHIFT             (16U)
+#define ENET_DMA_DBG_STAT_RPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
+#define ENET_DMA_DBG_STAT_TPS1_MASK              (0xF00000U)
+#define ENET_DMA_DBG_STAT_TPS1_SHIFT             (20U)
+#define ENET_DMA_DBG_STAT_TPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
+
+/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK      (0x10000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT     (16U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK        (0x1C0000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT       (18U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT           (2U)
+
+/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK     (0xEU)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT    (1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK     (0x10U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT    (4U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK   (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT  (16U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT        (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK    (0x7FF8U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT   (3U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK   (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT  (16U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK     (0x80000000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT    (31U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT        (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR -  */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR -  */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK      (0x2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT     (1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK     (0x4U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT    (2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK      (0x40U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT     (6U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK     (0x80U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT    (7U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK      (0x100U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT     (8U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK     (0x200U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT    (9U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK     (0x400U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT    (10U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK     (0x800U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT    (11U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK     (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT    (12U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK      (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT     (14U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK      (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT     (15U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT         (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC -  */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF -  */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT  (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT  (2U)
+
+/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK         (0x1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT        (0U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK        (0x2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT       (1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK        (0x4U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT       (2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK         (0x40U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT        (6U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK        (0x80U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT       (7U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK        (0x100U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT       (8U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK        (0x200U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT       (9U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK        (0x400U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT       (10U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK        (0x800U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT       (11U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK        (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT       (12U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK        (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT       (14U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK        (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT       (15U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK         (0x70000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT        (16U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_STAT */
+#define ENET_DMA_CH_DMA_CHX_STAT_COUNT           (2U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x40092000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_IRQS                                { ETHERNET_IRQn }
+#define ENET_PMT_IRQS                            { ETHERNET_PMT_IRQn }
+#define ENET_MACLP_IRQS                          { ETHERNET_MACLP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+  __IO uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+
+/*! @name PID - Peripheral identification register. */
+#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
+#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
+#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE                           (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE                           (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE                           (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE                           (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE                           (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE                           (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE                           (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE                           (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE                           (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE                           (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t FCTR;                              /**< Control register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t FBWST;                             /**< Wait state register, offset: 0x10 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t FMSSTART;                          /**< Signature start address register, offset: 0x20 */
+  __IO uint32_t FMSSTOP;                           /**< Signature stop-address register, offset: 0x24 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t FMSW[4];                           /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */
+       uint8_t RESERVED_3[4004];
+  __I  uint32_t FMSTAT;                            /**< Signature generation status register, offset: 0xFE0 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FMSTATCLR;                         /**< Signature generation status clear register, offset: 0xFE8 */
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name FCTR - Control register */
+#define FMC_FCTR_FS_RD0_MASK                     (0x8U)
+#define FMC_FCTR_FS_RD0_SHIFT                    (3U)
+#define FMC_FCTR_FS_RD0(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)
+#define FMC_FCTR_FS_RD1_MASK                     (0x10U)
+#define FMC_FCTR_FS_RD1_SHIFT                    (4U)
+#define FMC_FCTR_FS_RD1(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)
+
+/*! @name FBWST - Wait state register */
+#define FMC_FBWST_WAITSTATES_MASK                (0xFFU)
+#define FMC_FBWST_WAITSTATES_SHIFT               (0U)
+#define FMC_FBWST_WAITSTATES(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)
+
+/*! @name FMSSTART - Signature start address register */
+#define FMC_FMSSTART_START_MASK                  (0x1FFFFU)
+#define FMC_FMSSTART_START_SHIFT                 (0U)
+#define FMC_FMSSTART_START(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)
+
+/*! @name FMSSTOP - Signature stop-address register */
+#define FMC_FMSSTOP_STOP_MASK                    (0x1FFFFU)
+#define FMC_FMSSTOP_STOP_SHIFT                   (0U)
+#define FMC_FMSSTOP_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)
+#define FMC_FMSSTOP_SIG_START_MASK               (0x20000U)
+#define FMC_FMSSTOP_SIG_START_SHIFT              (17U)
+#define FMC_FMSSTOP_SIG_START(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)
+
+/*! @name FMSW - Words of 128-bit signature word */
+#define FMC_FMSW_SW_MASK                         (0xFFFFFFFFU)
+#define FMC_FMSW_SW_SHIFT                        (0U)
+#define FMC_FMSW_SW(x)                           (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)
+
+/* The count of FMC_FMSW */
+#define FMC_FMSW_COUNT                           (4U)
+
+/*! @name FMSTAT - Signature generation status register */
+#define FMC_FMSTAT_SIG_DONE_MASK                 (0x4U)
+#define FMC_FMSTAT_SIG_DONE_SHIFT                (2U)
+#define FMC_FMSTAT_SIG_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)
+
+/*! @name FMSTATCLR - Signature generation status clear register */
+#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK          (0x4U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT         (2U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR(x)            (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x40034000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+#define GINT_CTRL_INT_MASK                       (0x1U)
+#define GINT_CTRL_INT_SHIFT                      (0U)
+#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK                      (0x2U)
+#define GINT_CTRL_COMB_SHIFT                     (1U)
+#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK                      (0x4U)
+#define GINT_CTRL_TRIG_SHIFT                     (2U)
+#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT                  (0U)
+#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT                      (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
+#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE                               (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0                                    ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE                               (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1                                    ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS                           { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[6][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+       uint8_t RESERVED_0[3904];
+  __IO uint32_t W[6][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+       uint8_t RESERVED_1[3328];
+  __IO uint32_t DIR[6];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+       uint8_t RESERVED_2[104];
+  __IO uint32_t MASK[6];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
+       uint8_t RESERVED_3[104];
+  __IO uint32_t PIN[6];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+       uint8_t RESERVED_4[104];
+  __IO uint32_t MPIN[6];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+       uint8_t RESERVED_5[104];
+  __IO uint32_t SET[6];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+       uint8_t RESERVED_6[104];
+  __O  uint32_t CLR[6];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
+       uint8_t RESERVED_7[104];
+  __O  uint32_t NOT[6];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+       uint8_t RESERVED_8[104];
+  __O  uint32_t DIRSET[6];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+       uint8_t RESERVED_9[104];
+  __O  uint32_t DIRCLR[6];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+       uint8_t RESERVED_10[104];
+  __O  uint32_t DIRNOT[6];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Direction registers */
+#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT                      (0U)
+#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (6U)
+
+/*! @name MASK - Mask register */
+#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT                    (0U)
+#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (6U)
+
+/*! @name PIN - Port pin register */
+#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT                      (0U)
+#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (6U)
+
+/*! @name MPIN - Masked port register */
+#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
+#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (6U)
+
+/*! @name CLR - Clear port */
+#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT                      (0U)
+#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (6U)
+
+/*! @name NOT - Toggle port */
+#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT                      (0U)
+#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
+#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
+#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE                                (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
+       uint8_t RESERVED_4[1912];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+
+/*! @name TIMEOUT - Time-out value register. */
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+
+/*! @name MSTCTL - Master control register. */
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+
+/*! @name MSTTIME - Master timing configuration. */
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT                    (0U)
+#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+
+/*! @name SLVCTL - Slave control register. */
+#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
+#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
+#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
+#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
+#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
+#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT                    (0U)
+#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+
+/*! @name SLVADR - Slave address register. */
+#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
+#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
+#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
+#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT                         (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
+#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
+#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
+#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
+#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
+#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
+#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define I2C_ID_APERTURE_MASK                     (0xFFU)
+#define I2C_ID_APERTURE_SHIFT                    (0U)
+#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT                   (8U)
+#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
+#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK                           (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT                          (16U)
+#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE                                (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE                                (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4                                     ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE                                (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5                                     ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE                                (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6                                     ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE                                (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7                                     ((I2C_Type *)I2C7_BASE)
+/** Peripheral I2C8 base address */
+#define I2C8_BASE                                (0x40099000u)
+/** Peripheral I2C8 base pointer */
+#define I2C8                                     ((I2C_Type *)I2C8_BASE)
+/** Peripheral I2C9 base address */
+#define I2C9_BASE                                (0x4009A000u)
+/** Peripheral I2C9 base pointer */
+#define I2C9                                     ((I2C_Type *)I2C9_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[32];
+  struct {                                         /* offset: 0x20, array step: 0x20 */
+    __IO uint32_t PCFG1;                             /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */
+    __IO uint32_t PCFG2;                             /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */
+    __IO uint32_t PSTAT;                             /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */
+         uint8_t RESERVED_0[20];
+  } SECCHANNEL[3];
+       uint8_t RESERVED_1[2944];
+  __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+  __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+  __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+       uint8_t RESERVED_3[480];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_5[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+  __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+       uint8_t RESERVED_6[8];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+  __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+       uint8_t RESERVED_7[8];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+       uint8_t RESERVED_8[4020];
+  __I  uint32_t ID;                                /**< I2S Module identification, offset: 0x1DFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
+#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
+#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
+#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
+#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
+#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
+#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
+#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK                       (0xC0U)
+#define I2S_CFG1_MODE_SHIFT                      (6U)
+#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
+#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
+#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
+#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
+#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
+#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT                    (13U)
+#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT                   (16U)
+#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
+#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT                  (16U)
+#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+
+/*! @name STAT - Status register for the primary channel pair. */
+#define I2S_STAT_BUSY_MASK                       (0x1U)
+#define I2S_STAT_BUSY_SHIFT                      (0U)
+#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
+#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK                         (0x4U)
+#define I2S_STAT_LR_SHIFT                        (2U)
+#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
+#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+#define I2S_DIV_DIV_MASK                         (0xFFFU)
+#define I2S_DIV_DIV_SHIFT                        (0U)
+#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
+#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
+#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
+#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
+#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
+#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
+#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
+#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
+#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
+#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
+#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
+#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
+#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+
+/*! @name ID - I2S Module identification */
+#define I2S_ID_Aperture_MASK                     (0xFFU)
+#define I2S_ID_Aperture_SHIFT                    (0U)
+#define I2S_ID_Aperture(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
+#define I2S_ID_Minor_Rev_MASK                    (0xF00U)
+#define I2S_ID_Minor_Rev_SHIFT                   (8U)
+#define I2S_ID_Minor_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
+#define I2S_ID_Major_Rev_MASK                    (0xF000U)
+#define I2S_ID_Major_Rev_SHIFT                   (12U)
+#define I2S_ID_Major_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
+#define I2S_ID_ID_MASK                           (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT                          (16U)
+#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE                                (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1                                     ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS                                 { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SCT0_INMUX[7];                     /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[164];
+  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+  __IO uint32_t DMA_ITRIG_INMUX[30];               /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DMA_OTRIG_INMUX[4];                /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
+  __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
+#define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+
+/* The count of INPUTMUX_SCT0_INMUX */
+#define INPUTMUX_SCT0_INMUX_COUNT                (7U)
+
+/*! @name PINTSEL - Pin interrupt select register */
+#define INPUTMUX_PINTSEL_INTPIN_MASK             (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
+#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT                   (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT           (30U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT           (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE                            (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PIO[6][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
+#define IOCON_PIO_FUNC_MASK                      (0xFU)
+#define IOCON_PIO_FUNC_SHIFT                     (0U)
+#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK                      (0x30U)
+#define IOCON_PIO_MODE_SHIFT                     (4U)
+#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK                   (0x40U)
+#define IOCON_PIO_I2CSLEW_SHIFT                  (6U)
+#define IOCON_PIO_I2CSLEW(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK                    (0x80U)
+#define IOCON_PIO_INVERT_SHIFT                   (7U)
+#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
+#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK                 (0x200U)
+#define IOCON_PIO_FILTEROFF_SHIFT                (9U)
+#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK                  (0x400U)
+#define IOCON_PIO_I2CDRIVE_SHIFT                 (10U)
+#define IOCON_PIO_I2CDRIVE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK                      (0x400U)
+#define IOCON_PIO_SLEW_SHIFT                     (10U)
+#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_OD_MASK                        (0x800U)
+#define IOCON_PIO_OD_SHIFT                       (11U)
+#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+#define IOCON_PIO_I2CFILTER_MASK                 (0x800U)
+#define IOCON_PIO_I2CFILTER_SHIFT                (11U)
+#define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT                          (6U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2                         (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE                               (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON                                    ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS                         { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS                          { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TIMH;                              /**< Horizontal Timing Control register, offset: 0x0 */
+  __IO uint32_t TIMV;                              /**< Vertical Timing Control register, offset: 0x4 */
+  __IO uint32_t POL;                               /**< Clock and Signal Polarity Control register, offset: 0x8 */
+  __IO uint32_t LE;                                /**< Line End Control register, offset: 0xC */
+  __IO uint32_t UPBASE;                            /**< Upper Panel Frame Base Address register, offset: 0x10 */
+  __IO uint32_t LPBASE;                            /**< Lower Panel Frame Base Address register, offset: 0x14 */
+  __IO uint32_t CTRL;                              /**< LCD Control register, offset: 0x18 */
+  __IO uint32_t INTMSK;                            /**< Interrupt Mask register, offset: 0x1C */
+  __I  uint32_t INTRAW;                            /**< Raw Interrupt Status register, offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Masked Interrupt Status register, offset: 0x24 */
+  __IO uint32_t INTCLR;                            /**< Interrupt Clear register, offset: 0x28 */
+  __I  uint32_t UPCURR;                            /**< Upper Panel Current Address Value register, offset: 0x2C */
+  __I  uint32_t LPCURR;                            /**< Lower Panel Current Address Value register, offset: 0x30 */
+       uint8_t RESERVED_0[460];
+  __IO uint32_t PAL[128];                          /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_1[1024];
+  __IO uint32_t CRSR_IMG[256];                     /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
+  __IO uint32_t CRSR_CTRL;                         /**< Cursor Control register, offset: 0xC00 */
+  __IO uint32_t CRSR_CFG;                          /**< Cursor Configuration register, offset: 0xC04 */
+  __IO uint32_t CRSR_PAL0;                         /**< Cursor Palette register 0, offset: 0xC08 */
+  __IO uint32_t CRSR_PAL1;                         /**< Cursor Palette register 1, offset: 0xC0C */
+  __IO uint32_t CRSR_XY;                           /**< Cursor XY Position register, offset: 0xC10 */
+  __IO uint32_t CRSR_CLIP;                         /**< Cursor Clip Position register, offset: 0xC14 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CRSR_INTMSK;                       /**< Cursor Interrupt Mask register, offset: 0xC20 */
+  __O  uint32_t CRSR_INTCLR;                       /**< Cursor Interrupt Clear register, offset: 0xC24 */
+  __I  uint32_t CRSR_INTRAW;                       /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
+  __I  uint32_t CRSR_INTSTAT;                      /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/*! @name TIMH - Horizontal Timing Control register */
+#define LCD_TIMH_PPL_MASK                        (0xFCU)
+#define LCD_TIMH_PPL_SHIFT                       (2U)
+#define LCD_TIMH_PPL(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
+#define LCD_TIMH_HSW_MASK                        (0xFF00U)
+#define LCD_TIMH_HSW_SHIFT                       (8U)
+#define LCD_TIMH_HSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
+#define LCD_TIMH_HFP_MASK                        (0xFF0000U)
+#define LCD_TIMH_HFP_SHIFT                       (16U)
+#define LCD_TIMH_HFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
+#define LCD_TIMH_HBP_MASK                        (0xFF000000U)
+#define LCD_TIMH_HBP_SHIFT                       (24U)
+#define LCD_TIMH_HBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
+
+/*! @name TIMV - Vertical Timing Control register */
+#define LCD_TIMV_LPP_MASK                        (0x3FFU)
+#define LCD_TIMV_LPP_SHIFT                       (0U)
+#define LCD_TIMV_LPP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
+#define LCD_TIMV_VSW_MASK                        (0xFC00U)
+#define LCD_TIMV_VSW_SHIFT                       (10U)
+#define LCD_TIMV_VSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
+#define LCD_TIMV_VFP_MASK                        (0xFF0000U)
+#define LCD_TIMV_VFP_SHIFT                       (16U)
+#define LCD_TIMV_VFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
+#define LCD_TIMV_VBP_MASK                        (0xFF000000U)
+#define LCD_TIMV_VBP_SHIFT                       (24U)
+#define LCD_TIMV_VBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
+
+/*! @name POL - Clock and Signal Polarity Control register */
+#define LCD_POL_PCD_LO_MASK                      (0x1FU)
+#define LCD_POL_PCD_LO_SHIFT                     (0U)
+#define LCD_POL_PCD_LO(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
+#define LCD_POL_ACB_MASK                         (0x7C0U)
+#define LCD_POL_ACB_SHIFT                        (6U)
+#define LCD_POL_ACB(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
+#define LCD_POL_IVS_MASK                         (0x800U)
+#define LCD_POL_IVS_SHIFT                        (11U)
+#define LCD_POL_IVS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
+#define LCD_POL_IHS_MASK                         (0x1000U)
+#define LCD_POL_IHS_SHIFT                        (12U)
+#define LCD_POL_IHS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
+#define LCD_POL_IPC_MASK                         (0x2000U)
+#define LCD_POL_IPC_SHIFT                        (13U)
+#define LCD_POL_IPC(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
+#define LCD_POL_IOE_MASK                         (0x4000U)
+#define LCD_POL_IOE_SHIFT                        (14U)
+#define LCD_POL_IOE(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
+#define LCD_POL_CPL_MASK                         (0x3FF0000U)
+#define LCD_POL_CPL_SHIFT                        (16U)
+#define LCD_POL_CPL(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
+#define LCD_POL_BCD_MASK                         (0x4000000U)
+#define LCD_POL_BCD_SHIFT                        (26U)
+#define LCD_POL_BCD(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
+#define LCD_POL_PCD_HI_MASK                      (0xF8000000U)
+#define LCD_POL_PCD_HI_SHIFT                     (27U)
+#define LCD_POL_PCD_HI(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
+
+/*! @name LE - Line End Control register */
+#define LCD_LE_LED_MASK                          (0x7FU)
+#define LCD_LE_LED_SHIFT                         (0U)
+#define LCD_LE_LED(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
+#define LCD_LE_LEE_MASK                          (0x10000U)
+#define LCD_LE_LEE_SHIFT                         (16U)
+#define LCD_LE_LEE(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
+
+/*! @name UPBASE - Upper Panel Frame Base Address register */
+#define LCD_UPBASE_LCDUPBASE_MASK                (0xFFFFFFF8U)
+#define LCD_UPBASE_LCDUPBASE_SHIFT               (3U)
+#define LCD_UPBASE_LCDUPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
+
+/*! @name LPBASE - Lower Panel Frame Base Address register */
+#define LCD_LPBASE_LCDLPBASE_MASK                (0xFFFFFFF8U)
+#define LCD_LPBASE_LCDLPBASE_SHIFT               (3U)
+#define LCD_LPBASE_LCDLPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
+
+/*! @name CTRL - LCD Control register */
+#define LCD_CTRL_LCDEN_MASK                      (0x1U)
+#define LCD_CTRL_LCDEN_SHIFT                     (0U)
+#define LCD_CTRL_LCDEN(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
+#define LCD_CTRL_LCDBPP_MASK                     (0xEU)
+#define LCD_CTRL_LCDBPP_SHIFT                    (1U)
+#define LCD_CTRL_LCDBPP(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
+#define LCD_CTRL_LCDBW_MASK                      (0x10U)
+#define LCD_CTRL_LCDBW_SHIFT                     (4U)
+#define LCD_CTRL_LCDBW(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
+#define LCD_CTRL_LCDTFT_MASK                     (0x20U)
+#define LCD_CTRL_LCDTFT_SHIFT                    (5U)
+#define LCD_CTRL_LCDTFT(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
+#define LCD_CTRL_LCDMONO8_MASK                   (0x40U)
+#define LCD_CTRL_LCDMONO8_SHIFT                  (6U)
+#define LCD_CTRL_LCDMONO8(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
+#define LCD_CTRL_LCDDUAL_MASK                    (0x80U)
+#define LCD_CTRL_LCDDUAL_SHIFT                   (7U)
+#define LCD_CTRL_LCDDUAL(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
+#define LCD_CTRL_BGR_MASK                        (0x100U)
+#define LCD_CTRL_BGR_SHIFT                       (8U)
+#define LCD_CTRL_BGR(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
+#define LCD_CTRL_BEBO_MASK                       (0x200U)
+#define LCD_CTRL_BEBO_SHIFT                      (9U)
+#define LCD_CTRL_BEBO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
+#define LCD_CTRL_BEPO_MASK                       (0x400U)
+#define LCD_CTRL_BEPO_SHIFT                      (10U)
+#define LCD_CTRL_BEPO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
+#define LCD_CTRL_LCDPWR_MASK                     (0x800U)
+#define LCD_CTRL_LCDPWR_SHIFT                    (11U)
+#define LCD_CTRL_LCDPWR(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
+#define LCD_CTRL_LCDVCOMP_MASK                   (0x3000U)
+#define LCD_CTRL_LCDVCOMP_SHIFT                  (12U)
+#define LCD_CTRL_LCDVCOMP(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
+#define LCD_CTRL_WATERMARK_MASK                  (0x10000U)
+#define LCD_CTRL_WATERMARK_SHIFT                 (16U)
+#define LCD_CTRL_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
+
+/*! @name INTMSK - Interrupt Mask register */
+#define LCD_INTMSK_FUFIM_MASK                    (0x2U)
+#define LCD_INTMSK_FUFIM_SHIFT                   (1U)
+#define LCD_INTMSK_FUFIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
+#define LCD_INTMSK_LNBUIM_MASK                   (0x4U)
+#define LCD_INTMSK_LNBUIM_SHIFT                  (2U)
+#define LCD_INTMSK_LNBUIM(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
+#define LCD_INTMSK_VCOMPIM_MASK                  (0x8U)
+#define LCD_INTMSK_VCOMPIM_SHIFT                 (3U)
+#define LCD_INTMSK_VCOMPIM(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
+#define LCD_INTMSK_BERIM_MASK                    (0x10U)
+#define LCD_INTMSK_BERIM_SHIFT                   (4U)
+#define LCD_INTMSK_BERIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
+
+/*! @name INTRAW - Raw Interrupt Status register */
+#define LCD_INTRAW_FUFRIS_MASK                   (0x2U)
+#define LCD_INTRAW_FUFRIS_SHIFT                  (1U)
+#define LCD_INTRAW_FUFRIS(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
+#define LCD_INTRAW_LNBURIS_MASK                  (0x4U)
+#define LCD_INTRAW_LNBURIS_SHIFT                 (2U)
+#define LCD_INTRAW_LNBURIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
+#define LCD_INTRAW_VCOMPRIS_MASK                 (0x8U)
+#define LCD_INTRAW_VCOMPRIS_SHIFT                (3U)
+#define LCD_INTRAW_VCOMPRIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
+#define LCD_INTRAW_BERRAW_MASK                   (0x10U)
+#define LCD_INTRAW_BERRAW_SHIFT                  (4U)
+#define LCD_INTRAW_BERRAW(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
+
+/*! @name INTSTAT - Masked Interrupt Status register */
+#define LCD_INTSTAT_FUFMIS_MASK                  (0x2U)
+#define LCD_INTSTAT_FUFMIS_SHIFT                 (1U)
+#define LCD_INTSTAT_FUFMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
+#define LCD_INTSTAT_LNBUMIS_MASK                 (0x4U)
+#define LCD_INTSTAT_LNBUMIS_SHIFT                (2U)
+#define LCD_INTSTAT_LNBUMIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
+#define LCD_INTSTAT_VCOMPMIS_MASK                (0x8U)
+#define LCD_INTSTAT_VCOMPMIS_SHIFT               (3U)
+#define LCD_INTSTAT_VCOMPMIS(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
+#define LCD_INTSTAT_BERMIS_MASK                  (0x10U)
+#define LCD_INTSTAT_BERMIS_SHIFT                 (4U)
+#define LCD_INTSTAT_BERMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
+
+/*! @name INTCLR - Interrupt Clear register */
+#define LCD_INTCLR_FUFIC_MASK                    (0x2U)
+#define LCD_INTCLR_FUFIC_SHIFT                   (1U)
+#define LCD_INTCLR_FUFIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
+#define LCD_INTCLR_LNBUIC_MASK                   (0x4U)
+#define LCD_INTCLR_LNBUIC_SHIFT                  (2U)
+#define LCD_INTCLR_LNBUIC(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
+#define LCD_INTCLR_VCOMPIC_MASK                  (0x8U)
+#define LCD_INTCLR_VCOMPIC_SHIFT                 (3U)
+#define LCD_INTCLR_VCOMPIC(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
+#define LCD_INTCLR_BERIC_MASK                    (0x10U)
+#define LCD_INTCLR_BERIC_SHIFT                   (4U)
+#define LCD_INTCLR_BERIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
+
+/*! @name UPCURR - Upper Panel Current Address Value register */
+#define LCD_UPCURR_LCDUPCURR_MASK                (0xFFFFFFFFU)
+#define LCD_UPCURR_LCDUPCURR_SHIFT               (0U)
+#define LCD_UPCURR_LCDUPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
+
+/*! @name LPCURR - Lower Panel Current Address Value register */
+#define LCD_LPCURR_LCDLPCURR_MASK                (0xFFFFFFFFU)
+#define LCD_LPCURR_LCDLPCURR_SHIFT               (0U)
+#define LCD_LPCURR_LCDLPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
+
+/*! @name PAL - 256x16-bit Color Palette registers */
+#define LCD_PAL_R04_0_MASK                       (0x1FU)
+#define LCD_PAL_R04_0_SHIFT                      (0U)
+#define LCD_PAL_R04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
+#define LCD_PAL_G04_0_MASK                       (0x3E0U)
+#define LCD_PAL_G04_0_SHIFT                      (5U)
+#define LCD_PAL_G04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
+#define LCD_PAL_B04_0_MASK                       (0x7C00U)
+#define LCD_PAL_B04_0_SHIFT                      (10U)
+#define LCD_PAL_B04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
+#define LCD_PAL_I0_MASK                          (0x8000U)
+#define LCD_PAL_I0_SHIFT                         (15U)
+#define LCD_PAL_I0(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
+#define LCD_PAL_R14_0_MASK                       (0x1F0000U)
+#define LCD_PAL_R14_0_SHIFT                      (16U)
+#define LCD_PAL_R14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
+#define LCD_PAL_G14_0_MASK                       (0x3E00000U)
+#define LCD_PAL_G14_0_SHIFT                      (21U)
+#define LCD_PAL_G14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
+#define LCD_PAL_B14_0_MASK                       (0x7C000000U)
+#define LCD_PAL_B14_0_SHIFT                      (26U)
+#define LCD_PAL_B14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
+#define LCD_PAL_I1_MASK                          (0x80000000U)
+#define LCD_PAL_I1_SHIFT                         (31U)
+#define LCD_PAL_I1(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
+
+/* The count of LCD_PAL */
+#define LCD_PAL_COUNT                            (128U)
+
+/*! @name CRSR_IMG - Cursor Image registers */
+#define LCD_CRSR_IMG_CRSR_IMG_MASK               (0xFFFFFFFFU)
+#define LCD_CRSR_IMG_CRSR_IMG_SHIFT              (0U)
+#define LCD_CRSR_IMG_CRSR_IMG(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
+
+/* The count of LCD_CRSR_IMG */
+#define LCD_CRSR_IMG_COUNT                       (256U)
+
+/*! @name CRSR_CTRL - Cursor Control register */
+#define LCD_CRSR_CTRL_CRSRON_MASK                (0x1U)
+#define LCD_CRSR_CTRL_CRSRON_SHIFT               (0U)
+#define LCD_CRSR_CTRL_CRSRON(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK            (0x30U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT           (4U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
+
+/*! @name CRSR_CFG - Cursor Configuration register */
+#define LCD_CRSR_CFG_CRSRSIZE_MASK               (0x1U)
+#define LCD_CRSR_CFG_CRSRSIZE_SHIFT              (0U)
+#define LCD_CRSR_CFG_CRSRSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
+#define LCD_CRSR_CFG_FRAMESYNC_MASK              (0x2U)
+#define LCD_CRSR_CFG_FRAMESYNC_SHIFT             (1U)
+#define LCD_CRSR_CFG_FRAMESYNC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
+
+/*! @name CRSR_PAL0 - Cursor Palette register 0 */
+#define LCD_CRSR_PAL0_RED_MASK                   (0xFFU)
+#define LCD_CRSR_PAL0_RED_SHIFT                  (0U)
+#define LCD_CRSR_PAL0_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
+#define LCD_CRSR_PAL0_GREEN_MASK                 (0xFF00U)
+#define LCD_CRSR_PAL0_GREEN_SHIFT                (8U)
+#define LCD_CRSR_PAL0_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
+#define LCD_CRSR_PAL0_BLUE_MASK                  (0xFF0000U)
+#define LCD_CRSR_PAL0_BLUE_SHIFT                 (16U)
+#define LCD_CRSR_PAL0_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
+
+/*! @name CRSR_PAL1 - Cursor Palette register 1 */
+#define LCD_CRSR_PAL1_RED_MASK                   (0xFFU)
+#define LCD_CRSR_PAL1_RED_SHIFT                  (0U)
+#define LCD_CRSR_PAL1_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
+#define LCD_CRSR_PAL1_GREEN_MASK                 (0xFF00U)
+#define LCD_CRSR_PAL1_GREEN_SHIFT                (8U)
+#define LCD_CRSR_PAL1_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
+#define LCD_CRSR_PAL1_BLUE_MASK                  (0xFF0000U)
+#define LCD_CRSR_PAL1_BLUE_SHIFT                 (16U)
+#define LCD_CRSR_PAL1_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
+
+/*! @name CRSR_XY - Cursor XY Position register */
+#define LCD_CRSR_XY_CRSRX_MASK                   (0x3FFU)
+#define LCD_CRSR_XY_CRSRX_SHIFT                  (0U)
+#define LCD_CRSR_XY_CRSRX(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
+#define LCD_CRSR_XY_CRSRY_MASK                   (0x3FF0000U)
+#define LCD_CRSR_XY_CRSRY_SHIFT                  (16U)
+#define LCD_CRSR_XY_CRSRY(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
+
+/*! @name CRSR_CLIP - Cursor Clip Position register */
+#define LCD_CRSR_CLIP_CRSRCLIPX_MASK             (0x3FU)
+#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT            (0U)
+#define LCD_CRSR_CLIP_CRSRCLIPX(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
+#define LCD_CRSR_CLIP_CRSRCLIPY_MASK             (0x3F00U)
+#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT            (8U)
+#define LCD_CRSR_CLIP_CRSRCLIPY(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
+
+/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
+#define LCD_CRSR_INTMSK_CRSRIM_MASK              (0x1U)
+#define LCD_CRSR_INTMSK_CRSRIM_SHIFT             (0U)
+#define LCD_CRSR_INTMSK_CRSRIM(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
+
+/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
+#define LCD_CRSR_INTCLR_CRSRIC_MASK              (0x1U)
+#define LCD_CRSR_INTCLR_CRSRIC_SHIFT             (0U)
+#define LCD_CRSR_INTCLR_CRSRIC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
+
+/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
+#define LCD_CRSR_INTRAW_CRSRRIS_MASK             (0x1U)
+#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT            (0U)
+#define LCD_CRSR_INTRAW_CRSRRIS(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
+
+/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
+#define LCD_CRSR_INTSTAT_CRSRMIS_MASK            (0x1U)
+#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT           (0U)
+#define LCD_CRSR_INTSTAT_CRSRMIS(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE                                 (0x40083000u)
+/** Peripheral LCD base pointer */
+#define LCD                                      ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS                           { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS                            { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_IRQS                                 { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MRT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+    __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+    __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+    __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+  } CHANNEL[4];
+       uint8_t RESERVED_0[176];
+  __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+  __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+  __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
+#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
+#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT                 (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
+#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT                  (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
+#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
+#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT                   (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
+#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
+#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
+#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT                   (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+#define MRT_MODCFG_NOC_MASK                      (0xFU)
+#define MRT_MODCFG_NOC_SHIFT                     (0U)
+#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT                     (4U)
+#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
+#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
+#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
+#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
+#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
+#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
+#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE                                (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0                                     ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS                           { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS                            { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS                                 { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
+ * @{
+ */
+
+/** OTPC - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __I  uint32_t AESKEY[8];                         /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
+  __I  uint32_t ECRP;                              /**< ECRP options., offset: 0x30 */
+       uint8_t RESERVED_1[4];
+  __I  uint32_t USER0;                             /**< User application specific options., offset: 0x38 */
+  __I  uint32_t USER1;                             /**< User application specific options., offset: 0x3C */
+} OTPC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks
+ * @{
+ */
+
+/*! @name AESKEY - Register for reading the AES key. */
+#define OTPC_AESKEY_KEY_MASK                     (0xFFFFFFFFU)
+#define OTPC_AESKEY_KEY_SHIFT                    (0U)
+#define OTPC_AESKEY_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
+
+/* The count of OTPC_AESKEY */
+#define OTPC_AESKEY_COUNT                        (8U)
+
+/*! @name ECRP - ECRP options. */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK    (0x10U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT   (4U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK     (0x20U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT    (5U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK       (0x40U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT      (6U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK       (0x80U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT      (7U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK            (0x200U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT           (9U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x)              (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
+#define OTPC_ECRP_JTAG_DISABLE_MASK              (0x80000000U)
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT             (31U)
+#define OTPC_ECRP_JTAG_DISABLE(x)                (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
+
+/*! @name USER0 - User application specific options. */
+#define OTPC_USER0_USER0_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER0_USER0_SHIFT                   (0U)
+#define OTPC_USER0_USER0(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
+
+/*! @name USER1 - User application specific options. */
+#define OTPC_USER1_USER1_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER1_USER1_SHIFT                   (0U)
+#define OTPC_USER1_USER1(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OTPC_Register_Masks */
+
+
+/* OTPC - Peripheral instance base addresses */
+/** Peripheral OTPC base address */
+#define OTPC_BASE                                (0x40015000u)
+/** Peripheral OTPC base pointer */
+#define OTPC                                     ((OTPC_Type *)OTPC_BASE)
+/** Array initializer of OTPC peripheral base addresses */
+#define OTPC_BASE_ADDRS                          { OTPC_BASE }
+/** Array initializer of OTPC peripheral base pointers */
+#define OTPC_BASE_PTRS                           { OTPC }
+
+/*!
+ * @}
+ */ /* end of group OTPC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
+  __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+  __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+  __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+  __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+  __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+  __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+  __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
+  __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
+  __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
+  __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
+  __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+  __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+#define PINT_ISEL_PMODE_MASK                     (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT                    (0U)
+#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+#define PINT_IENR_ENRL_MASK                      (0xFFU)
+#define PINT_IENR_ENRL_SHIFT                     (0U)
+#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT                 (0U)
+#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+#define PINT_CIENR_CENRL_MASK                    (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT                   (0U)
+#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+#define PINT_IENF_ENAF_MASK                      (0xFFU)
+#define PINT_IENF_ENAF_SHIFT                     (0U)
+#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT                 (0U)
+#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+#define PINT_CIENF_CENAF_MASK                    (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT                   (0U)
+#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+
+/*! @name RISE - Pin interrupt rising edge register */
+#define PINT_RISE_RDET_MASK                      (0xFFU)
+#define PINT_RISE_RDET_SHIFT                     (0U)
+#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+
+/*! @name FALL - Pin interrupt falling edge register */
+#define PINT_FALL_FDET_MASK                      (0xFFU)
+#define PINT_FALL_FDET_SHIFT                     (0U)
+#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+
+/*! @name IST - Pin interrupt status register */
+#define PINT_IST_PSTAT_MASK                      (0xFFU)
+#define PINT_IST_PSTAT_SHIFT                     (0U)
+#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
+#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
+#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
+#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+#define PINT_PMSRC_SRC0_MASK                     (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT                    (8U)
+#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT                    (11U)
+#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT                    (14U)
+#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT                    (17U)
+#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT                    (20U)
+#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT                    (23U)
+#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT                    (26U)
+#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT                    (29U)
+#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
+#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
+#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
+#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
+#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
+#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
+#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
+#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK                     (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT                    (8U)
+#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT                    (11U)
+#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT                    (14U)
+#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT                    (17U)
+#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT                    (20U)
+#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT                    (23U)
+#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT                    (26U)
+#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT                    (29U)
+#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE                                (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT                                     ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS                          { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS                           { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
+ * @{
+ */
+
+/** RIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t COMPVAL;                           /**< Compare value LSB register, offset: 0x0 */
+  __IO uint32_t MASK;                              /**< Mask LSB register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x8 */
+  __IO uint32_t COUNTER;                           /**< Counter LSB register, offset: 0xC */
+  __IO uint32_t COMPVAL_H;                         /**< Compare value MSB register, offset: 0x10 */
+  __IO uint32_t MASK_H;                            /**< Mask MSB register, offset: 0x14 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t COUNTER_H;                         /**< Counter MSB register, offset: 0x1C */
+} RIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Register_Masks RIT Register Masks
+ * @{
+ */
+
+/*! @name COMPVAL - Compare value LSB register */
+#define RIT_COMPVAL_RICOMP_MASK                  (0xFFFFFFFFU)
+#define RIT_COMPVAL_RICOMP_SHIFT                 (0U)
+#define RIT_COMPVAL_RICOMP(x)                    (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
+
+/*! @name MASK - Mask LSB register */
+#define RIT_MASK_RIMASK_MASK                     (0xFFFFFFFFU)
+#define RIT_MASK_RIMASK_SHIFT                    (0U)
+#define RIT_MASK_RIMASK(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
+
+/*! @name CTRL - Control register */
+#define RIT_CTRL_RITINT_MASK                     (0x1U)
+#define RIT_CTRL_RITINT_SHIFT                    (0U)
+#define RIT_CTRL_RITINT(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
+#define RIT_CTRL_RITENCLR_MASK                   (0x2U)
+#define RIT_CTRL_RITENCLR_SHIFT                  (1U)
+#define RIT_CTRL_RITENCLR(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
+#define RIT_CTRL_RITENBR_MASK                    (0x4U)
+#define RIT_CTRL_RITENBR_SHIFT                   (2U)
+#define RIT_CTRL_RITENBR(x)                      (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
+#define RIT_CTRL_RITEN_MASK                      (0x8U)
+#define RIT_CTRL_RITEN_SHIFT                     (3U)
+#define RIT_CTRL_RITEN(x)                        (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
+
+/*! @name COUNTER - Counter LSB register */
+#define RIT_COUNTER_RICOUNTER_MASK               (0xFFFFFFFFU)
+#define RIT_COUNTER_RICOUNTER_SHIFT              (0U)
+#define RIT_COUNTER_RICOUNTER(x)                 (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
+
+/*! @name COMPVAL_H - Compare value MSB register */
+#define RIT_COMPVAL_H_RICOMP_MASK                (0xFFFFU)
+#define RIT_COMPVAL_H_RICOMP_SHIFT               (0U)
+#define RIT_COMPVAL_H_RICOMP(x)                  (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
+
+/*! @name MASK_H - Mask MSB register */
+#define RIT_MASK_H_RIMASK_MASK                   (0xFFFFU)
+#define RIT_MASK_H_RIMASK_SHIFT                  (0U)
+#define RIT_MASK_H_RIMASK(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
+
+/*! @name COUNTER_H - Counter MSB register */
+#define RIT_COUNTER_H_RICOUNTER_MASK             (0xFFFFU)
+#define RIT_COUNTER_H_RICOUNTER_SHIFT            (0U)
+#define RIT_COUNTER_H_RICOUNTER(x)               (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RIT_Register_Masks */
+
+
+/* RIT - Peripheral instance base addresses */
+/** Peripheral RIT base address */
+#define RIT_BASE                                 (0x4002D000u)
+/** Peripheral RIT base pointer */
+#define RIT                                      ((RIT_Type *)RIT_BASE)
+/** Array initializer of RIT peripheral base addresses */
+#define RIT_BASE_ADDRS                           { RIT_BASE }
+/** Array initializer of RIT peripheral base pointers */
+#define RIT_BASE_PTRS                            { RIT }
+/** Interrupt vectors for the RIT peripheral type */
+#define RIT_IRQS                                 { RIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
+  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
+  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
+  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+#define RTC_CTRL_SWRESET_MASK                    (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT                   (0U)
+#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
+#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
+#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
+#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
+#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
+#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
+#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
+#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+
+/*! @name MATCH - RTC match register */
+#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT                   (0U)
+#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+
+/*! @name COUNT - RTC counter register */
+#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT                      (0U)
+#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT                       (0U)
+#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+
+/*! @name GPREG - General Purpose register */
+#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT                   (0U)
+#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
+  __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
+  __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
+  __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
+  __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
+  __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
+       uint8_t RESERVED_0[40];
+  __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
+  __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
+  __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
+  __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
+  __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
+  __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
+  __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
+  __IO uint32_t DMA0REQUEST;                       /**< SCT DMA request 0 register, offset: 0x5C */
+  __IO uint32_t DMA1REQUEST;                       /**< SCT DMA request 1 register, offset: 0x60 */
+       uint8_t RESERVED_1[140];
+  __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
+  __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
+  __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
+  __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
+  union {                                          /* offset: 0x100 */
+    __IO uint32_t SCTCAP[10];                        /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+    __IO uint32_t SCTMATCH[10];                      /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+  };
+       uint8_t RESERVED_2[216];
+  union {                                          /* offset: 0x200 */
+    __IO uint32_t SCTCAPCTRL[10];                    /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+    __IO uint32_t SCTMATCHREL[10];                   /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+  };
+       uint8_t RESERVED_3[216];
+  struct {                                         /* offset: 0x300, array step: 0x8 */
+    __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+    __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+  } EVENT[10];
+       uint8_t RESERVED_4[432];
+  struct {                                         /* offset: 0x500, array step: 0x8 */
+    __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+    __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+  } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
+#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
+#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
+#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELAOD_L_MASK               (0x80U)
+#define SCT_CONFIG_NORELAOD_L_SHIFT              (7U)
+#define SCT_CONFIG_NORELAOD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
+#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK                   (0x1E00U)
+#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
+#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
+#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
+#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+
+/*! @name CTRL - SCT control register */
+#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
+#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK                     (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT                    (1U)
+#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK                     (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT                    (2U)
+#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
+#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
+#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT                     (5U)
+#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
+#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT                    (17U)
+#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT                    (18U)
+#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
+#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
+#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT                     (21U)
+#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+
+/*! @name LIMIT - SCT limit event select register */
+#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
+#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
+#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+
+/*! @name HALT - SCT halt event select register */
+#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
+#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
+#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+
+/*! @name STOP - SCT stop event select register */
+#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
+#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
+#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+
+/*! @name START - SCT start event select register */
+#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT               (0U)
+#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT               (16U)
+#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+
+/*! @name COUNT - SCT counter register */
+#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT                    (0U)
+#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT                    (16U)
+#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+
+/*! @name STATE - SCT state register */
+#define SCT_STATE_STATE_L_MASK                   (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT                  (0U)
+#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT                  (16U)
+#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+
+/*! @name INPUT - SCT input register */
+#define SCT_INPUT_AIN0_MASK                      (0x1U)
+#define SCT_INPUT_AIN0_SHIFT                     (0U)
+#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK                      (0x2U)
+#define SCT_INPUT_AIN1_SHIFT                     (1U)
+#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK                      (0x4U)
+#define SCT_INPUT_AIN2_SHIFT                     (2U)
+#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK                      (0x8U)
+#define SCT_INPUT_AIN3_SHIFT                     (3U)
+#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK                      (0x10U)
+#define SCT_INPUT_AIN4_SHIFT                     (4U)
+#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK                      (0x20U)
+#define SCT_INPUT_AIN5_SHIFT                     (5U)
+#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK                      (0x40U)
+#define SCT_INPUT_AIN6_SHIFT                     (6U)
+#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK                      (0x80U)
+#define SCT_INPUT_AIN7_SHIFT                     (7U)
+#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK                      (0x100U)
+#define SCT_INPUT_AIN8_SHIFT                     (8U)
+#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK                      (0x200U)
+#define SCT_INPUT_AIN9_SHIFT                     (9U)
+#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK                     (0x400U)
+#define SCT_INPUT_AIN10_SHIFT                    (10U)
+#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK                     (0x800U)
+#define SCT_INPUT_AIN11_SHIFT                    (11U)
+#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK                     (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT                    (12U)
+#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK                     (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT                    (13U)
+#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK                     (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT                    (14U)
+#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK                     (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT                    (15U)
+#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK                      (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT                     (16U)
+#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK                      (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT                     (17U)
+#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK                      (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT                     (18U)
+#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK                      (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT                     (19U)
+#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK                      (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT                     (20U)
+#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK                      (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT                     (21U)
+#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK                      (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT                     (22U)
+#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK                      (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT                     (23U)
+#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT                     (24U)
+#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT                     (25U)
+#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT                    (26U)
+#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT                    (27U)
+#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT                    (28U)
+#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT                    (29U)
+#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT                    (30U)
+#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT                    (31U)
+#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+
+/*! @name REGMODE - SCT match/capture mode register */
+#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
+#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
+#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+
+/*! @name OUTPUT - SCT output register */
+#define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT                     (0U)
+#define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+
+/*! @name RES - SCT conflict resolution register */
+#define SCT_RES_O0RES_MASK                       (0x3U)
+#define SCT_RES_O0RES_SHIFT                      (0U)
+#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK                       (0xCU)
+#define SCT_RES_O1RES_SHIFT                      (2U)
+#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK                       (0x30U)
+#define SCT_RES_O2RES_SHIFT                      (4U)
+#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK                       (0xC0U)
+#define SCT_RES_O3RES_SHIFT                      (6U)
+#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK                       (0x300U)
+#define SCT_RES_O4RES_SHIFT                      (8U)
+#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK                       (0xC00U)
+#define SCT_RES_O5RES_SHIFT                      (10U)
+#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK                       (0x3000U)
+#define SCT_RES_O6RES_SHIFT                      (12U)
+#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK                       (0xC000U)
+#define SCT_RES_O7RES_SHIFT                      (14U)
+#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK                       (0x30000U)
+#define SCT_RES_O8RES_SHIFT                      (16U)
+#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK                       (0xC0000U)
+#define SCT_RES_O9RES_SHIFT                      (18U)
+#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK                      (0x300000U)
+#define SCT_RES_O10RES_SHIFT                     (20U)
+#define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK                      (0xC00000U)
+#define SCT_RES_O11RES_SHIFT                     (22U)
+#define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK                      (0x3000000U)
+#define SCT_RES_O12RES_SHIFT                     (24U)
+#define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK                      (0xC000000U)
+#define SCT_RES_O13RES_SHIFT                     (26U)
+#define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK                      (0x30000000U)
+#define SCT_RES_O14RES_SHIFT                     (28U)
+#define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK                      (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT                     (30U)
+#define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+
+/*! @name DMA0REQUEST - SCT DMA request 0 register */
+#define SCT_DMA0REQUEST_DEV_0_MASK               (0xFFFFU)
+#define SCT_DMA0REQUEST_DEV_0_SHIFT              (0U)
+#define SCT_DMA0REQUEST_DEV_0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
+#define SCT_DMA0REQUEST_DRL0_MASK                (0x40000000U)
+#define SCT_DMA0REQUEST_DRL0_SHIFT               (30U)
+#define SCT_DMA0REQUEST_DRL0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
+#define SCT_DMA0REQUEST_DRQ0_MASK                (0x80000000U)
+#define SCT_DMA0REQUEST_DRQ0_SHIFT               (31U)
+#define SCT_DMA0REQUEST_DRQ0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
+
+/*! @name DMA1REQUEST - SCT DMA request 1 register */
+#define SCT_DMA1REQUEST_DEV_1_MASK               (0xFFFFU)
+#define SCT_DMA1REQUEST_DEV_1_SHIFT              (0U)
+#define SCT_DMA1REQUEST_DEV_1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
+#define SCT_DMA1REQUEST_DRL1_MASK                (0x40000000U)
+#define SCT_DMA1REQUEST_DRL1_SHIFT               (30U)
+#define SCT_DMA1REQUEST_DRL1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
+#define SCT_DMA1REQUEST_DRQ1_MASK                (0x80000000U)
+#define SCT_DMA1REQUEST_DRQ1_SHIFT               (31U)
+#define SCT_DMA1REQUEST_DRQ1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
+
+/*! @name EVEN - SCT event interrupt enable register */
+#define SCT_EVEN_IEN_MASK                        (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT                       (0U)
+#define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+
+/*! @name EVFLAG - SCT event flag register */
+#define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT                    (0U)
+#define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+#define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT                     (0U)
+#define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+
+/*! @name CONFLAG - SCT conflict flag register */
+#define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
+#define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
+#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
+#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+
+/*! @name SCTCAP - SCT capture register of capture channel */
+#define SCT_SCTCAP_CAPn_L_MASK                   (0xFFFFU)
+#define SCT_SCTCAP_CAPn_L_SHIFT                  (0U)
+#define SCT_SCTCAP_CAPn_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
+#define SCT_SCTCAP_CAPn_H_MASK                   (0xFFFF0000U)
+#define SCT_SCTCAP_CAPn_H_SHIFT                  (16U)
+#define SCT_SCTCAP_CAPn_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
+
+/* The count of SCT_SCTCAP */
+#define SCT_SCTCAP_COUNT                         (10U)
+
+/*! @name SCTMATCH - SCT match value register of match channels */
+#define SCT_SCTMATCH_MATCHn_L_MASK               (0xFFFFU)
+#define SCT_SCTMATCH_MATCHn_L_SHIFT              (0U)
+#define SCT_SCTMATCH_MATCHn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
+#define SCT_SCTMATCH_MATCHn_H_MASK               (0xFFFF0000U)
+#define SCT_SCTMATCH_MATCHn_H_SHIFT              (16U)
+#define SCT_SCTMATCH_MATCHn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
+
+/* The count of SCT_SCTMATCH */
+#define SCT_SCTMATCH_COUNT                       (10U)
+
+/*! @name SCTCAPCTRL - SCT capture control register */
+#define SCT_SCTCAPCTRL_CAPCONn_L_MASK            (0xFFFFU)
+#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT           (0U)
+#define SCT_SCTCAPCTRL_CAPCONn_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
+#define SCT_SCTCAPCTRL_CAPCONn_H_MASK            (0xFFFF0000U)
+#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT           (16U)
+#define SCT_SCTCAPCTRL_CAPCONn_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
+
+/* The count of SCT_SCTCAPCTRL */
+#define SCT_SCTCAPCTRL_COUNT                     (10U)
+
+/*! @name SCTMATCHREL - SCT match reload value register */
+#define SCT_SCTMATCHREL_RELOADn_L_MASK           (0xFFFFU)
+#define SCT_SCTMATCHREL_RELOADn_L_SHIFT          (0U)
+#define SCT_SCTMATCHREL_RELOADn_L(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
+#define SCT_SCTMATCHREL_RELOADn_H_MASK           (0xFFFF0000U)
+#define SCT_SCTMATCHREL_RELOADn_H_SHIFT          (16U)
+#define SCT_SCTMATCHREL_RELOADn_H(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
+
+/* The count of SCT_SCTMATCHREL */
+#define SCT_SCTMATCHREL_COUNT                    (10U)
+
+/*! @name EVENT_STATE - SCT event state register 0 */
+#define SCT_EVENT_STATE_STATEMSKn_MASK           (0xFFFFU)
+#define SCT_EVENT_STATE_STATEMSKn_SHIFT          (0U)
+#define SCT_EVENT_STATE_STATEMSKn(x)             (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
+
+/* The count of SCT_EVENT_STATE */
+#define SCT_EVENT_STATE_COUNT                    (10U)
+
+/*! @name EVENT_CTRL - SCT event control register 0 */
+#define SCT_EVENT_CTRL_MATCHSEL_MASK             (0xFU)
+#define SCT_EVENT_CTRL_MATCHSEL_SHIFT            (0U)
+#define SCT_EVENT_CTRL_MATCHSEL(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
+#define SCT_EVENT_CTRL_HEVENT_MASK               (0x10U)
+#define SCT_EVENT_CTRL_HEVENT_SHIFT              (4U)
+#define SCT_EVENT_CTRL_HEVENT(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
+#define SCT_EVENT_CTRL_OUTSEL_MASK               (0x20U)
+#define SCT_EVENT_CTRL_OUTSEL_SHIFT              (5U)
+#define SCT_EVENT_CTRL_OUTSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
+#define SCT_EVENT_CTRL_IOSEL_MASK                (0x3C0U)
+#define SCT_EVENT_CTRL_IOSEL_SHIFT               (6U)
+#define SCT_EVENT_CTRL_IOSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
+#define SCT_EVENT_CTRL_IOCOND_MASK               (0xC00U)
+#define SCT_EVENT_CTRL_IOCOND_SHIFT              (10U)
+#define SCT_EVENT_CTRL_IOCOND(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
+#define SCT_EVENT_CTRL_COMBMODE_MASK             (0x3000U)
+#define SCT_EVENT_CTRL_COMBMODE_SHIFT            (12U)
+#define SCT_EVENT_CTRL_COMBMODE(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
+#define SCT_EVENT_CTRL_STATELD_MASK              (0x4000U)
+#define SCT_EVENT_CTRL_STATELD_SHIFT             (14U)
+#define SCT_EVENT_CTRL_STATELD(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
+#define SCT_EVENT_CTRL_STATEV_MASK               (0xF8000U)
+#define SCT_EVENT_CTRL_STATEV_SHIFT              (15U)
+#define SCT_EVENT_CTRL_STATEV(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
+#define SCT_EVENT_CTRL_MATCHMEM_MASK             (0x100000U)
+#define SCT_EVENT_CTRL_MATCHMEM_SHIFT            (20U)
+#define SCT_EVENT_CTRL_MATCHMEM(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
+#define SCT_EVENT_CTRL_DIRECTION_MASK            (0x600000U)
+#define SCT_EVENT_CTRL_DIRECTION_SHIFT           (21U)
+#define SCT_EVENT_CTRL_DIRECTION(x)              (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
+
+/* The count of SCT_EVENT_CTRL */
+#define SCT_EVENT_CTRL_COUNT                     (10U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT                    (0U)
+#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT                        (10U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
+#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT                        (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE                                (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0                                     ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS                           { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS                            { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS                                 { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
+ * @{
+ */
+
+/** SDIF - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
+  __IO uint32_t PWREN;                             /**< Power Enable register, offset: 0x4 */
+  __IO uint32_t CLKDIV;                            /**< Clock Divider register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLKENA;                            /**< Clock Enable register, offset: 0x10 */
+  __IO uint32_t TMOUT;                             /**< Time-out register, offset: 0x14 */
+  __IO uint32_t CTYPE;                             /**< Card Type register, offset: 0x18 */
+  __IO uint32_t BLKSIZ;                            /**< Block Size register, offset: 0x1C */
+  __IO uint32_t BYTCNT;                            /**< Byte Count register, offset: 0x20 */
+  __IO uint32_t INTMASK;                           /**< Interrupt Mask register, offset: 0x24 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x28 */
+  __IO uint32_t CMD;                               /**< Command register, offset: 0x2C */
+  __IO uint32_t RESP[4];                           /**< Response register, array offset: 0x30, array step: 0x4 */
+  __IO uint32_t MINTSTS;                           /**< Masked Interrupt Status register, offset: 0x40 */
+  __IO uint32_t RINTSTS;                           /**< Raw Interrupt Status register, offset: 0x44 */
+  __IO uint32_t STATUS;                            /**< Status register, offset: 0x48 */
+  __IO uint32_t FIFOTH;                            /**< FIFO Threshold Watermark register, offset: 0x4C */
+  __IO uint32_t CDETECT;                           /**< Card Detect register, offset: 0x50 */
+  __IO uint32_t WRTPRT;                            /**< Write Protect register, offset: 0x54 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t TCBCNT;                            /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+  __IO uint32_t TBBCNT;                            /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+  __IO uint32_t DEBNCE;                            /**< Debounce Count register, offset: 0x64 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t RST_N;                             /**< Hardware Reset, offset: 0x78 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t BMOD;                              /**< Bus Mode register, offset: 0x80 */
+  __IO uint32_t PLDMND;                            /**< Poll Demand register, offset: 0x84 */
+  __IO uint32_t DBADDR;                            /**< Descriptor List Base Address register, offset: 0x88 */
+  __IO uint32_t IDSTS;                             /**< Internal DMAC Status register, offset: 0x8C */
+  __IO uint32_t IDINTEN;                           /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+  __IO uint32_t DSCADDR;                           /**< Current Host Descriptor Address register, offset: 0x94 */
+  __IO uint32_t BUFADDR;                           /**< Current Buffer Descriptor Address register, offset: 0x98 */
+       uint8_t RESERVED_4[100];
+  __IO uint32_t CARDTHRCTL;                        /**< Card Threshold Control, offset: 0x100 */
+  __IO uint32_t BACKENDPWR;                        /**< Power control, offset: 0x104 */
+       uint8_t RESERVED_5[248];
+  __IO uint32_t FIFO[64];                          /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+} SDIF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
+#define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
+#define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
+#define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
+#define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
+#define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
+#define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
+#define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+
+/*! @name PWREN - Power Enable register */
+#define SDIF_PWREN_POWER_ENABLE_MASK             (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT            (0U)
+#define SDIF_PWREN_POWER_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+
+/*! @name CLKDIV - Clock Divider register */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
+#define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+
+/*! @name CLKENA - Clock Enable register */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK             (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT            (0U)
+#define SDIF_CLKENA_CCLK_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK          (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT         (16U)
+#define SDIF_CLKENA_CCLK_LOW_POWER(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+
+/*! @name TMOUT - Time-out register */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
+#define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+
+/*! @name CTYPE - Card Type register */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK              (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT             (0U)
+#define SDIF_CTYPE_CARD_WIDTH0(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK              (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT             (16U)
+#define SDIF_CTYPE_CARD_WIDTH1(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+
+/*! @name BLKSIZ - Block Size register */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
+#define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+
+/*! @name BYTCNT - Byte Count register */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
+#define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+
+/*! @name INTMASK - Interrupt Mask register */
+#define SDIF_INTMASK_CDET_MASK                   (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT                  (0U)
+#define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK                     (0x2U)
+#define SDIF_INTMASK_RE_SHIFT                    (1U)
+#define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK                  (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT                 (2U)
+#define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK                    (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT                   (3U)
+#define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK                   (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT                  (4U)
+#define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK                   (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT                  (5U)
+#define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK                   (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT                  (6U)
+#define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK                   (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT                  (7U)
+#define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK                    (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT                   (8U)
+#define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK                   (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT                  (9U)
+#define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK                    (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT                   (10U)
+#define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK                   (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT                  (11U)
+#define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK                    (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT                   (12U)
+#define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK                    (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT                   (13U)
+#define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK                    (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT                   (14U)
+#define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK                    (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT                   (15U)
+#define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
+#define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
+#define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+
+/*! @name CMD - Command register */
+#define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
+#define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
+#define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
+#define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
+#define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT                (10U)
+#define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
+#define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
+#define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
+#define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
+#define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
+#define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
+#define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
+#define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
+#define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
+#define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
+#define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
+#define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
+#define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT                 (31U)
+#define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+
+/*! @name RESP - Response register */
+#define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT                 (0U)
+#define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT                          (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+#define SDIF_MINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK                     (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT                    (1U)
+#define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK                    (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT                   (8U)
+#define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
+#define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+#define SDIF_RINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK                     (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT                    (1U)
+#define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
+#define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
+#define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name STATUS - Status register */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
+#define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
+#define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
+#define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
+#define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
+#define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
+#define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
+#define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
+#define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
+#define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+#define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
+#define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
+#define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
+#define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+
+/*! @name CDETECT - Card Detect register */
+#define SDIF_CDETECT_CARD_DETECT_MASK            (0x1U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT           (0U)
+#define SDIF_CDETECT_CARD_DETECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+
+/*! @name WRTPRT - Write Protect register */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
+#define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+
+/*! @name DEBNCE - Debounce Count register */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+
+/*! @name RST_N - Hardware Reset */
+#define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
+#define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+
+/*! @name BMOD - Bus Mode register */
+#define SDIF_BMOD_SWR_MASK                       (0x1U)
+#define SDIF_BMOD_SWR_SHIFT                      (0U)
+#define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK                        (0x2U)
+#define SDIF_BMOD_FB_SHIFT                       (1U)
+#define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK                       (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT                      (2U)
+#define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK                        (0x80U)
+#define SDIF_BMOD_DE_SHIFT                       (7U)
+#define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK                       (0x700U)
+#define SDIF_BMOD_PBL_SHIFT                      (8U)
+#define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+
+/*! @name PLDMND - Poll Demand register */
+#define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT                     (0U)
+#define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+
+/*! @name DBADDR - Descriptor List Base Address register */
+#define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT                    (0U)
+#define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+
+/*! @name IDSTS - Internal DMAC Status register */
+#define SDIF_IDSTS_TI_MASK                       (0x1U)
+#define SDIF_IDSTS_TI_SHIFT                      (0U)
+#define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK                       (0x2U)
+#define SDIF_IDSTS_RI_SHIFT                      (1U)
+#define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK                      (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT                     (2U)
+#define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK                       (0x10U)
+#define SDIF_IDSTS_DU_SHIFT                      (4U)
+#define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK                      (0x20U)
+#define SDIF_IDSTS_CES_SHIFT                     (5U)
+#define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK                      (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT                     (8U)
+#define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK                      (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT                     (9U)
+#define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK                       (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT                      (10U)
+#define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT                     (13U)
+#define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+#define SDIF_IDINTEN_TI_MASK                     (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT                    (0U)
+#define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK                     (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT                    (1U)
+#define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK                    (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT                   (2U)
+#define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK                     (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT                    (4U)
+#define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK                    (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT                   (5U)
+#define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK                    (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT                   (8U)
+#define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK                    (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT                   (9U)
+#define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+#define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT                   (0U)
+#define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+#define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT                   (0U)
+#define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+
+/*! @name BACKENDPWR - Power control */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
+#define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+
+/*! @name FIFO - SDIF FIFO */
+#define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT                     (0U)
+#define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT                          (64U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/* SDIF - Peripheral instance base addresses */
+/** Peripheral SDIF base address */
+#define SDIF_BASE                                (0x4009B000u)
+/** Peripheral SDIF base pointer */
+#define SDIF                                     ((SDIF_Type *)SDIF_BASE)
+/** Array initializer of SDIF peripheral base addresses */
+#define SDIF_BASE_ADDRS                          { SDIF_BASE }
+/** Array initializer of SDIF peripheral base pointers */
+#define SDIF_BASE_PTRS                           { SDIF }
+/** Interrupt vectors for the SDIF peripheral type */
+#define SDIF_IRQS                                { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTCARD - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t DLL;                               /**< Divisor Latch LSB, offset: 0x0 */
+    __I  uint32_t RBR;                               /**< Receiver Buffer Register, offset: 0x0 */
+    __O  uint32_t THR;                               /**< Transmit Holding Register, offset: 0x0 */
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t DLM;                               /**< Divisor Latch MSB, offset: 0x4 */
+    __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    __O  uint32_t FCR;                               /**< FIFO Control Register, offset: 0x8 */
+    __I  uint32_t IIR;                               /**< Interrupt ID Register, offset: 0x8 */
+  };
+  __IO uint32_t LCR;                               /**< Line Control Register, offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t LSR;                               /**< Line Status Register, offset: 0x14 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SCR;                               /**< Scratch Pad Register, offset: 0x1C */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t OSR;                               /**< Oversampling register, offset: 0x2C */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t SCICTRL;                           /**< Smart Card Interface control register, offset: 0x48 */
+} SMARTCARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch LSB */
+#define SMARTCARD_DLL_DLLSB_MASK                 (0xFFU)
+#define SMARTCARD_DLL_DLLSB_SHIFT                (0U)
+#define SMARTCARD_DLL_DLLSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
+
+/*! @name RBR - Receiver Buffer Register */
+#define SMARTCARD_RBR_RBR_MASK                   (0xFFU)
+#define SMARTCARD_RBR_RBR_SHIFT                  (0U)
+#define SMARTCARD_RBR_RBR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
+
+/*! @name THR - Transmit Holding Register */
+#define SMARTCARD_THR_THR_MASK                   (0xFFU)
+#define SMARTCARD_THR_THR_SHIFT                  (0U)
+#define SMARTCARD_THR_THR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
+
+/*! @name DLM - Divisor Latch MSB */
+#define SMARTCARD_DLM_DLMSB_MASK                 (0xFFU)
+#define SMARTCARD_DLM_DLMSB_SHIFT                (0U)
+#define SMARTCARD_DLM_DLMSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
+
+/*! @name IER - Interrupt Enable Register */
+#define SMARTCARD_IER_RBRIE_MASK                 (0x1U)
+#define SMARTCARD_IER_RBRIE_SHIFT                (0U)
+#define SMARTCARD_IER_RBRIE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
+#define SMARTCARD_IER_THREIE_MASK                (0x2U)
+#define SMARTCARD_IER_THREIE_SHIFT               (1U)
+#define SMARTCARD_IER_THREIE(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
+#define SMARTCARD_IER_RXIE_MASK                  (0x4U)
+#define SMARTCARD_IER_RXIE_SHIFT                 (2U)
+#define SMARTCARD_IER_RXIE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
+
+/*! @name FCR - FIFO Control Register */
+#define SMARTCARD_FCR_FIFOEN_MASK                (0x1U)
+#define SMARTCARD_FCR_FIFOEN_SHIFT               (0U)
+#define SMARTCARD_FCR_FIFOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
+#define SMARTCARD_FCR_RXFIFORES_MASK             (0x2U)
+#define SMARTCARD_FCR_RXFIFORES_SHIFT            (1U)
+#define SMARTCARD_FCR_RXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
+#define SMARTCARD_FCR_TXFIFORES_MASK             (0x4U)
+#define SMARTCARD_FCR_TXFIFORES_SHIFT            (2U)
+#define SMARTCARD_FCR_TXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
+#define SMARTCARD_FCR_DMAMODE_MASK               (0x8U)
+#define SMARTCARD_FCR_DMAMODE_SHIFT              (3U)
+#define SMARTCARD_FCR_DMAMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
+#define SMARTCARD_FCR_RXTRIGLVL_MASK             (0xC0U)
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT            (6U)
+#define SMARTCARD_FCR_RXTRIGLVL(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
+
+/*! @name IIR - Interrupt ID Register */
+#define SMARTCARD_IIR_INTSTATUS_MASK             (0x1U)
+#define SMARTCARD_IIR_INTSTATUS_SHIFT            (0U)
+#define SMARTCARD_IIR_INTSTATUS(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
+#define SMARTCARD_IIR_INTID_MASK                 (0xEU)
+#define SMARTCARD_IIR_INTID_SHIFT                (1U)
+#define SMARTCARD_IIR_INTID(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
+#define SMARTCARD_IIR_FIFOENABLE_MASK            (0xC0U)
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT           (6U)
+#define SMARTCARD_IIR_FIFOENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
+
+/*! @name LCR - Line Control Register */
+#define SMARTCARD_LCR_WLS_MASK                   (0x3U)
+#define SMARTCARD_LCR_WLS_SHIFT                  (0U)
+#define SMARTCARD_LCR_WLS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
+#define SMARTCARD_LCR_SBS_MASK                   (0x4U)
+#define SMARTCARD_LCR_SBS_SHIFT                  (2U)
+#define SMARTCARD_LCR_SBS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
+#define SMARTCARD_LCR_PE_MASK                    (0x8U)
+#define SMARTCARD_LCR_PE_SHIFT                   (3U)
+#define SMARTCARD_LCR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
+#define SMARTCARD_LCR_PS_MASK                    (0x30U)
+#define SMARTCARD_LCR_PS_SHIFT                   (4U)
+#define SMARTCARD_LCR_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
+#define SMARTCARD_LCR_DLAB_MASK                  (0x80U)
+#define SMARTCARD_LCR_DLAB_SHIFT                 (7U)
+#define SMARTCARD_LCR_DLAB(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
+
+/*! @name LSR - Line Status Register */
+#define SMARTCARD_LSR_RDR_MASK                   (0x1U)
+#define SMARTCARD_LSR_RDR_SHIFT                  (0U)
+#define SMARTCARD_LSR_RDR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
+#define SMARTCARD_LSR_OE_MASK                    (0x2U)
+#define SMARTCARD_LSR_OE_SHIFT                   (1U)
+#define SMARTCARD_LSR_OE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
+#define SMARTCARD_LSR_PE_MASK                    (0x4U)
+#define SMARTCARD_LSR_PE_SHIFT                   (2U)
+#define SMARTCARD_LSR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
+#define SMARTCARD_LSR_FE_MASK                    (0x8U)
+#define SMARTCARD_LSR_FE_SHIFT                   (3U)
+#define SMARTCARD_LSR_FE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
+#define SMARTCARD_LSR_THRE_MASK                  (0x20U)
+#define SMARTCARD_LSR_THRE_SHIFT                 (5U)
+#define SMARTCARD_LSR_THRE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
+#define SMARTCARD_LSR_TEMT_MASK                  (0x40U)
+#define SMARTCARD_LSR_TEMT_SHIFT                 (6U)
+#define SMARTCARD_LSR_TEMT(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
+#define SMARTCARD_LSR_RXFE_MASK                  (0x80U)
+#define SMARTCARD_LSR_RXFE_SHIFT                 (7U)
+#define SMARTCARD_LSR_RXFE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
+
+/*! @name SCR - Scratch Pad Register */
+#define SMARTCARD_SCR_PAD_MASK                   (0xFFU)
+#define SMARTCARD_SCR_PAD_SHIFT                  (0U)
+#define SMARTCARD_SCR_PAD(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
+
+/*! @name OSR - Oversampling register */
+#define SMARTCARD_OSR_OSFRAC_MASK                (0xEU)
+#define SMARTCARD_OSR_OSFRAC_SHIFT               (1U)
+#define SMARTCARD_OSR_OSFRAC(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
+#define SMARTCARD_OSR_OSINT_MASK                 (0xF0U)
+#define SMARTCARD_OSR_OSINT_SHIFT                (4U)
+#define SMARTCARD_OSR_OSINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
+#define SMARTCARD_OSR_FDINT_MASK                 (0x7F00U)
+#define SMARTCARD_OSR_FDINT_SHIFT                (8U)
+#define SMARTCARD_OSR_FDINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
+
+/*! @name SCICTRL - Smart Card Interface control register */
+#define SMARTCARD_SCICTRL_SCIEN_MASK             (0x1U)
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT            (0U)
+#define SMARTCARD_SCICTRL_SCIEN(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
+#define SMARTCARD_SCICTRL_NACKDIS_MASK           (0x2U)
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT          (1U)
+#define SMARTCARD_SCICTRL_NACKDIS(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
+#define SMARTCARD_SCICTRL_PROTSEL_MASK           (0x4U)
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT          (2U)
+#define SMARTCARD_SCICTRL_PROTSEL(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
+#define SMARTCARD_SCICTRL_TXRETRY_MASK           (0xE0U)
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT          (5U)
+#define SMARTCARD_SCICTRL_TXRETRY(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK         (0xFF00U)
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT        (8U)
+#define SMARTCARD_SCICTRL_GUARDTIME(x)           (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Register_Masks */
+
+
+/* SMARTCARD - Peripheral instance base addresses */
+/** Peripheral SMARTCARD0 base address */
+#define SMARTCARD0_BASE                          (0x40036000u)
+/** Peripheral SMARTCARD0 base pointer */
+#define SMARTCARD0                               ((SMARTCARD_Type *)SMARTCARD0_BASE)
+/** Peripheral SMARTCARD1 base address */
+#define SMARTCARD1_BASE                          (0x40037000u)
+/** Peripheral SMARTCARD1 base pointer */
+#define SMARTCARD1                               ((SMARTCARD_Type *)SMARTCARD1_BASE)
+/** Array initializer of SMARTCARD peripheral base addresses */
+#define SMARTCARD_BASE_ADDRS                     { SMARTCARD0_BASE, SMARTCARD1_BASE }
+/** Array initializer of SMARTCARD peripheral base pointers */
+#define SMARTCARD_BASE_PTRS                      { SMARTCARD0, SMARTCARD1 }
+/** Interrupt vectors for the SMARTCARD peripheral type */
+#define SMARTCARD_IRQS                           { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
+  __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
+  __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+  __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+  __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
+  __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
+       uint8_t RESERVED_2[2516];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_7[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+#define SPI_CFG_ENABLE_MASK                      (0x1U)
+#define SPI_CFG_ENABLE_SHIFT                     (0U)
+#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK                      (0x4U)
+#define SPI_CFG_MASTER_SHIFT                     (2U)
+#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK                        (0x8U)
+#define SPI_CFG_LSBF_SHIFT                       (3U)
+#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK                        (0x10U)
+#define SPI_CFG_CPHA_SHIFT                       (4U)
+#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK                        (0x20U)
+#define SPI_CFG_CPOL_SHIFT                       (5U)
+#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK                        (0x80U)
+#define SPI_CFG_LOOP_SHIFT                       (7U)
+#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK                       (0x100U)
+#define SPI_CFG_SPOL0_SHIFT                      (8U)
+#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK                       (0x200U)
+#define SPI_CFG_SPOL1_SHIFT                      (9U)
+#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK                       (0x400U)
+#define SPI_CFG_SPOL2_SHIFT                      (10U)
+#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK                       (0x800U)
+#define SPI_CFG_SPOL3_SHIFT                      (11U)
+#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+
+/*! @name DLY - SPI Delay register */
+#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
+#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
+#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
+#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
+#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+#define SPI_STAT_SSA_MASK                        (0x10U)
+#define SPI_STAT_SSA_SHIFT                       (4U)
+#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK                        (0x20U)
+#define SPI_STAT_SSD_SHIFT                       (5U)
+#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK                    (0x40U)
+#define SPI_STAT_STALLED_SHIFT                   (6U)
+#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
+#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
+#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
+#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
+#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
+#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
+#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
+#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
+#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+
+/*! @name DIV - SPI clock Divider */
+#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT                     (0U)
+#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - SPI Interrupt Status */
+#define SPI_INTSTAT_SSA_MASK                     (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT                    (4U)
+#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK                     (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT                    (5U)
+#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
+#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
+#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
+#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
+#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
+#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
+#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
+#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT                     (20U)
+#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT                     (21U)
+#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
+#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT                     (24U)
+#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
+#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK                      (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT                     (20U)
+#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
+#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define SPI_ID_APERTURE_MASK                     (0xFFU)
+#define SPI_ID_APERTURE_SHIFT                    (0U)
+#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT                   (8U)
+#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
+#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK                           (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT                          (16U)
+#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE                                (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3                                     ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE                                (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4                                     ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE                                (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5                                     ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE                                (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6                                     ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE                                (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7                                     ((SPI_Type *)SPI7_BASE)
+/** Peripheral SPI8 base address */
+#define SPI8_BASE                                (0x40099000u)
+/** Peripheral SPI8 base pointer */
+#define SPI8                                     ((SPI_Type *)SPI8_BASE)
+/** Peripheral SPI9 base address */
+#define SPI9_BASE                                (0x4009A000u)
+/** Peripheral SPI9 base pointer */
+#define SPI9                                     ((SPI_Type *)SPI9_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< SPIFI control register, offset: 0x0 */
+  __IO uint32_t CMD;                               /**< SPIFI command register, offset: 0x4 */
+  __IO uint32_t ADDR;                              /**< SPIFI address register, offset: 0x8 */
+  __IO uint32_t IDATA;                             /**< SPIFI intermediate data register, offset: 0xC */
+  __IO uint32_t CLIMIT;                            /**< SPIFI limit register, offset: 0x10 */
+  __IO uint32_t DATA;                              /**< SPIFI data register, offset: 0x14 */
+  __IO uint32_t MCMD;                              /**< SPIFI memory command register, offset: 0x18 */
+  __IO uint32_t STAT;                              /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+#define SPIFI_CTRL_TIMEOUT_MASK                  (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT                 (0U)
+#define SPIFI_CTRL_TIMEOUT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK                   (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT                  (16U)
+#define SPIFI_CTRL_CSHIGH(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK             (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT            (21U)
+#define SPIFI_CTRL_D_PRFTCH_DIS(x)               (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK                    (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT                   (22U)
+#define SPIFI_CTRL_INTEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK                    (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT                   (23U)
+#define SPIFI_CTRL_MODE3(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK               (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT              (27U)
+#define SPIFI_CTRL_PRFTCH_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK                     (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT                    (28U)
+#define SPIFI_CTRL_DUAL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK                    (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT                   (29U)
+#define SPIFI_CTRL_RFCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK                    (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT                   (30U)
+#define SPIFI_CTRL_FBCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK                    (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT                   (31U)
+#define SPIFI_CTRL_DMAEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+
+/*! @name CMD - SPIFI command register */
+#define SPIFI_CMD_DATALEN_MASK                   (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT                  (0U)
+#define SPIFI_CMD_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK                      (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT                     (14U)
+#define SPIFI_CMD_POLL(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK                      (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT                     (15U)
+#define SPIFI_CMD_DOUT(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK                    (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT                   (16U)
+#define SPIFI_CMD_INTLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK                 (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT                (19U)
+#define SPIFI_CMD_FIELDFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK                 (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT                (21U)
+#define SPIFI_CMD_FRAMEFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK                    (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT                   (24U)
+#define SPIFI_CMD_OPCODE(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+
+/*! @name ADDR - SPIFI address register */
+#define SPIFI_ADDR_ADDRESS_MASK                  (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT                 (0U)
+#define SPIFI_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+
+/*! @name IDATA - SPIFI intermediate data register */
+#define SPIFI_IDATA_IDATA_MASK                   (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT                  (0U)
+#define SPIFI_IDATA_IDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+
+/*! @name CLIMIT - SPIFI limit register */
+#define SPIFI_CLIMIT_CLIMIT_MASK                 (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT                (0U)
+#define SPIFI_CLIMIT_CLIMIT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+
+/*! @name DATA - SPIFI data register */
+#define SPIFI_DATA_DATA_MASK                     (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT                    (0U)
+#define SPIFI_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+
+/*! @name MCMD - SPIFI memory command register */
+#define SPIFI_MCMD_POLL_MASK                     (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT                    (14U)
+#define SPIFI_MCMD_POLL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK                     (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT                    (15U)
+#define SPIFI_MCMD_DOUT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK                   (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT                  (16U)
+#define SPIFI_MCMD_INTLEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK                (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT               (19U)
+#define SPIFI_MCMD_FIELDFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK                (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT               (21U)
+#define SPIFI_MCMD_FRAMEFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK                   (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT                  (24U)
+#define SPIFI_MCMD_OPCODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+
+/*! @name STAT - SPIFI status register */
+#define SPIFI_STAT_MCINIT_MASK                   (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT                  (0U)
+#define SPIFI_STAT_MCINIT(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK                      (0x2U)
+#define SPIFI_STAT_CMD_SHIFT                     (1U)
+#define SPIFI_STAT_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK                    (0x10U)
+#define SPIFI_STAT_RESET_SHIFT                   (4U)
+#define SPIFI_STAT_RESET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK                    (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT                   (5U)
+#define SPIFI_STAT_INTRQ(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE                              (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0                                   ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS                         { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS                          { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS                               { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t AHBMATPRIO;                        /**< AHB multilayer matrix priority control, offset: 0x10 */
+       uint8_t RESERVED_1[44];
+  __IO uint32_t SYSTCKCAL;                         /**< System tick counter calibration, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
+  __IO uint32_t ASYNCAPBCTRL;                      /**< Asynchronous APB Control, offset: 0x4C */
+       uint8_t RESERVED_3[112];
+  __I  uint32_t PIOPORCAP[2];                      /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t PIORESCAP[2];                      /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+       uint8_t RESERVED_5[40];
+  __IO uint32_t PRESETCTRL[3];                     /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_6[20];
+  __O  uint32_t PRESETCTRLSET[3];                  /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t PRESETCTRLCLR[3];                  /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+       uint8_t RESERVED_8[164];
+  __IO uint32_t SYSRSTSTAT;                        /**< System reset status register, offset: 0x1F0 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t AHBCLKCTRL[3];                     /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_10[20];
+  __O  uint32_t AHBCLKCTRLSET[3];                  /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+       uint8_t RESERVED_11[20];
+  __O  uint32_t AHBCLKCTRLCLR[3];                  /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+       uint8_t RESERVED_12[52];
+  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
+  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
+  __IO uint32_t CLKOUTSELA;                        /**< CLKOUT clock source select A, offset: 0x288 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t SYSPLLCLKSEL;                      /**< PLL clock source select, offset: 0x290 */
+       uint8_t RESERVED_14[4];
+  __IO uint32_t AUDPLLCLKSEL;                      /**< Audio PLL clock source select, offset: 0x298 */
+       uint8_t RESERVED_15[4];
+  __IO uint32_t SPIFICLKSEL;                       /**< SPIFI clock source select, offset: 0x2A0 */
+  __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
+  __IO uint32_t USB0CLKSEL;                        /**< USB0 clock source select, offset: 0x2A8 */
+  __IO uint32_t USB1CLKSEL;                        /**< USB1 clock source select, offset: 0x2AC */
+  __IO uint32_t FCLKSEL[10];                       /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
+       uint8_t RESERVED_16[8];
+  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
+       uint8_t RESERVED_17[4];
+  __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+  __IO uint32_t DMICCLKSEL;                        /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
+  __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+  __IO uint32_t LCDCLKSEL;                         /**< LCD clock source select, offset: 0x2F4 */
+  __IO uint32_t SDIOCLKSEL;                        /**< SDIO clock source select, offset: 0x2F8 */
+       uint8_t RESERVED_18[4];
+  __IO uint32_t SYSTICKCLKDIV;                     /**< SYSTICK clock divider, offset: 0x300 */
+  __IO uint32_t ARMTRACECLKDIV;                    /**< ARM Trace clock divider, offset: 0x304 */
+  __IO uint32_t CAN0CLKDIV;                        /**< MCAN0 clock divider, offset: 0x308 */
+  __IO uint32_t CAN1CLKDIV;                        /**< MCAN1 clock divider, offset: 0x30C */
+  __IO uint32_t SC0CLKDIV;                         /**< Smartcard0 clock divider, offset: 0x310 */
+  __IO uint32_t SC1CLKDIV;                         /**< Smartcard1 clock divider, offset: 0x314 */
+       uint8_t RESERVED_19[104];
+  __IO uint32_t AHBCLKDIV;                         /**< AHB clock divider, offset: 0x380 */
+  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
+  __IO uint32_t FROHFCLKDIV;                       /**< FROHF clock divider, offset: 0x388 */
+       uint8_t RESERVED_20[4];
+  __IO uint32_t SPIFICLKDIV;                       /**< SPIFI clock divider, offset: 0x390 */
+  __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
+  __IO uint32_t USB0CLKDIV;                        /**< USB0 clock divider, offset: 0x398 */
+  __IO uint32_t USB1CLKDIV;                        /**< USB1 clock divider, offset: 0x39C */
+  __IO uint32_t FRGCTRL;                           /**< Fractional rate divider, offset: 0x3A0 */
+       uint8_t RESERVED_21[4];
+  __IO uint32_t DMICCLKDIV;                        /**< DMIC clock divider, offset: 0x3A8 */
+  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
+  __IO uint32_t LCDCLKDIV;                         /**< LCD clock divider, offset: 0x3B0 */
+  __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
+  __IO uint32_t EMCCLKDIV;                         /**< EMC clock divider, offset: 0x3B8 */
+  __IO uint32_t SDIOCLKDIV;                        /**< SDIO clock divider, offset: 0x3BC */
+       uint8_t RESERVED_22[64];
+  __IO uint32_t FLASHCFG;                          /**< Flash wait states configuration, offset: 0x400 */
+       uint8_t RESERVED_23[8];
+  __IO uint32_t USB0CLKCTRL;                       /**< USB0 clock control, offset: 0x40C */
+  __IO uint32_t USB0CLKSTAT;                       /**< USB0 clock status, offset: 0x410 */
+       uint8_t RESERVED_24[4];
+  __IO uint32_t FREQMECTRL;                        /**< Frequency measure register, offset: 0x418 */
+       uint8_t RESERVED_25[4];
+  __IO uint32_t MCLKIO;                            /**< MCLK input/output control, offset: 0x420 */
+  __IO uint32_t USB1CLKCTRL;                       /**< USB1 clock control, offset: 0x424 */
+  __IO uint32_t USB1CLKSTAT;                       /**< USB1 clock status, offset: 0x428 */
+       uint8_t RESERVED_26[24];
+  __IO uint32_t EMCSYSCTRL;                        /**< EMC system control, offset: 0x444 */
+  __IO uint32_t EMCDLYCTRL;                        /**< EMC clock delay control, offset: 0x448 */
+  __IO uint32_t EMCDLYCAL;                         /**< EMC delay chain calibration control, offset: 0x44C */
+  __IO uint32_t ETHPHYSEL;                         /**< Ethernet PHY Selection, offset: 0x450 */
+  __IO uint32_t ETHSBDCTRL;                        /**< Ethernet SBD flow control, offset: 0x454 */
+       uint8_t RESERVED_27[8];
+  __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+       uint8_t RESERVED_28[156];
+  __IO uint32_t FROCTRL;                           /**< FRO oscillator control, offset: 0x500 */
+  __IO uint32_t SYSOSCCTRL;                        /**< System oscillator control, offset: 0x504 */
+  __IO uint32_t WDTOSCCTRL;                        /**< Watchdog oscillator control, offset: 0x508 */
+  __IO uint32_t RTCOSCCTRL;                        /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+       uint8_t RESERVED_29[12];
+  __IO uint32_t USBPLLCTRL;                        /**< USB PLL control, offset: 0x51C */
+  __IO uint32_t USBPLLSTAT;                        /**< USB PLL status, offset: 0x520 */
+       uint8_t RESERVED_30[92];
+  __IO uint32_t SYSPLLCTRL;                        /**< System PLL control, offset: 0x580 */
+  __IO uint32_t SYSPLLSTAT;                        /**< PLL status, offset: 0x584 */
+  __IO uint32_t SYSPLLNDEC;                        /**< PLL N divider, offset: 0x588 */
+  __IO uint32_t SYSPLLPDEC;                        /**< PLL P divider, offset: 0x58C */
+  __IO uint32_t SYSPLLMDEC;                        /**< System PLL M divider, offset: 0x590 */
+       uint8_t RESERVED_31[12];
+  __IO uint32_t AUDPLLCTRL;                        /**< Audio PLL control, offset: 0x5A0 */
+  __IO uint32_t AUDPLLSTAT;                        /**< Audio PLL status, offset: 0x5A4 */
+  __IO uint32_t AUDPLLNDEC;                        /**< Audio PLL N divider, offset: 0x5A8 */
+  __IO uint32_t AUDPLLPDEC;                        /**< Audio PLL P divider, offset: 0x5AC */
+  __IO uint32_t AUDPLLMDEC;                        /**< Audio PLL M divider, offset: 0x5B0 */
+  __IO uint32_t AUDPLLFRAC;                        /**< Audio PLL fractional divider control, offset: 0x5B4 */
+       uint8_t RESERVED_32[72];
+  __IO uint32_t PDSLEEPCFG[2];                     /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */
+       uint8_t RESERVED_33[8];
+  __IO uint32_t PDRUNCFG[2];                       /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */
+       uint8_t RESERVED_34[8];
+  __IO uint32_t PDRUNCFGSET[2];                    /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */
+       uint8_t RESERVED_35[8];
+  __IO uint32_t PDRUNCFGCLR[2];                    /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */
+       uint8_t RESERVED_36[72];
+  __IO uint32_t STARTER[2];                        /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_37[24];
+  __O  uint32_t STARTERSET[2];                     /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
+       uint8_t RESERVED_38[24];
+  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
+       uint8_t RESERVED_39[184];
+  __IO uint32_t HWWAKE;                            /**< Configures special cases of hardware wake-up, offset: 0x780 */
+       uint8_t RESERVED_40[1664];
+  __IO uint32_t AUTOCGOR;                          /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+       uint8_t RESERVED_41[492];
+  __I  uint32_t JTAGIDCODE;                        /**< JTAG ID code register, offset: 0xFF4 */
+  __I  uint32_t DEVICE_ID0;                        /**< Part ID register, offset: 0xFF8 */
+  __I  uint32_t DEVICE_ID1;                        /**< Boot ROM and die revision register, offset: 0xFFC */
+       uint8_t RESERVED_42[127044];
+  __IO uint32_t BODCTRL;                           /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK         (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT        (0U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK         (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT        (2U)
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK           (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT          (4U)
+#define SYSCON_AHBMATPRIO_PRI_SYS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK           (0x3C0U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT          (6U)
+#define SYSCON_AHBMATPRIO_PRI_DMA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK           (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT          (10U)
+#define SYSCON_AHBMATPRIO_PRI_ETH(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK           (0x3000U)
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT          (12U)
+#define SYSCON_AHBMATPRIO_PRI_LCD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK          (0xC000U)
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT         (14U)
+#define SYSCON_AHBMATPRIO_PRI_USB0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK          (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT         (16U)
+#define SYSCON_AHBMATPRIO_PRI_USB1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK          (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT         (18U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK         (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT        (20U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK         (0xC00000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT        (22U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SHA_MASK           (0x3000000U)
+#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT          (24U)
+#define SYSCON_AHBMATPRIO_PRI_SHA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+#define SYSCON_SYSTCKCAL_CAL_MASK                (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT               (0U)
+#define SYSCON_SYSTCKCAL_CAL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK               (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT              (24U)
+#define SYSCON_SYSTCKCAL_SKEW(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK              (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT             (25U)
+#define SYSCON_SYSTCKCAL_NOREF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+
+/*! @name NMISRC - NMI Source Select */
+#define SYSCON_NMISRC_IRQM4_MASK                 (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT                (0U)
+#define SYSCON_NMISRC_IRQM4(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK               (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT              (31U)
+#define SYSCON_NMISRC_NMIENM4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK          (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT         (0U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+
+/*! @name PIOPORCAP - POR captured value of port n */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT         (0U)
+#define SYSCON_PIOPORCAP_PIOPORCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT                   (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT         (0U)
+#define SYSCON_PIORESCAP_PIORESCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT                   (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+#define SYSCON_PRESETCTRL_MRT_RST_MASK           (0x1U)
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT          (0U)
+#define SYSCON_PRESETCTRL_MRT_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK          (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT         (2U)
+#define SYSCON_PRESETCTRL_SCT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_LCD_RST_MASK           (0x4U)
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT          (2U)
+#define SYSCON_PRESETCTRL_LCD_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK          (0x8U)
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT         (3U)
+#define SYSCON_PRESETCTRL_SDIO_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK         (0x10U)
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT        (4U)
+#define SYSCON_PRESETCTRL_USB1H_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK         (0x20U)
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT        (5U)
+#define SYSCON_PRESETCTRL_USB1D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK       (0x40U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT      (6U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_EMC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
+#define SYSCON_PRESETCTRL_FLASH_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_FLASH_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_MCAN0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
+#define SYSCON_PRESETCTRL_FMC_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_FMC_RST_SHIFT          (8U)
+#define SYSCON_PRESETCTRL_FMC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
+#define SYSCON_PRESETCTRL_ETH_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT          (8U)
+#define SYSCON_PRESETCTRL_ETH_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK         (0x100U)
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT        (8U)
+#define SYSCON_PRESETCTRL_MCAN1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK         (0x200U)
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT        (9U)
+#define SYSCON_PRESETCTRL_GPIO4_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
+#define SYSCON_PRESETCTRL_EEPROM_RST_MASK        (0x200U)
+#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT       (9U)
+#define SYSCON_PRESETCTRL_EEPROM_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_GPIO5_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_UTICK_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_SPIFI_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
+#define SYSCON_PRESETCTRL_AES_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_AES_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_AES_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_MUX_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_FC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_OTP_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT          (12U)
+#define SYSCON_PRESETCTRL_OTP_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT          (12U)
+#define SYSCON_PRESETCTRL_FC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK         (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT        (13U)
+#define SYSCON_PRESETCTRL_IOCON_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_RNG_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT          (13U)
+#define SYSCON_PRESETCTRL_RNG_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT          (13U)
+#define SYSCON_PRESETCTRL_FC2_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC8_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT          (14U)
+#define SYSCON_PRESETCTRL_FC8_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT          (14U)
+#define SYSCON_PRESETCTRL_FC3_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK         (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT        (14U)
+#define SYSCON_PRESETCTRL_GPIO0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK         (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT        (15U)
+#define SYSCON_PRESETCTRL_GPIO1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC9_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT          (15U)
+#define SYSCON_PRESETCTRL_FC9_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT          (15U)
+#define SYSCON_PRESETCTRL_FC4_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK       (0x10000U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT      (16U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK         (0x10000U)
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT        (16U)
+#define SYSCON_PRESETCTRL_GPIO2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK           (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT          (16U)
+#define SYSCON_PRESETCTRL_FC5_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK         (0x20000U)
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT        (17U)
+#define SYSCON_PRESETCTRL_GPIO3_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK           (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT          (17U)
+#define SYSCON_PRESETCTRL_FC6_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK       (0x20000U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT      (17U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT          (18U)
+#define SYSCON_PRESETCTRL_FC7_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_SHA_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT          (18U)
+#define SYSCON_PRESETCTRL_SHA_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK          (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT         (18U)
+#define SYSCON_PRESETCTRL_PINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT         (19U)
+#define SYSCON_PRESETCTRL_DMIC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
+#define SYSCON_PRESETCTRL_SC0_RST_MASK           (0x80000U)
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT          (19U)
+#define SYSCON_PRESETCTRL_SC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT         (19U)
+#define SYSCON_PRESETCTRL_GINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SC1_RST_MASK           (0x100000U)
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT          (20U)
+#define SYSCON_PRESETCTRL_SC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA0_RST_MASK          (0x100000U)
+#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT         (20U)
+#define SYSCON_PRESETCTRL_DMA0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK           (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT          (21U)
+#define SYSCON_PRESETCTRL_CRC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK       (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT      (22U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK          (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT         (22U)
+#define SYSCON_PRESETCTRL_WWDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK         (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT        (25U)
+#define SYSCON_PRESETCTRL_USB0D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK       (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT      (26U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK          (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT         (27U)
+#define SYSCON_PRESETCTRL_ADC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK       (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT      (27U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT                  (3U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT       (0U)
+#define SYSCON_PRESETCTRLSET_RST_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT               (3U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT       (0U)
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT               (3U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+#define SYSCON_SYSRSTSTAT_POR_MASK               (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT              (0U)
+#define SYSCON_SYSRSTSTAT_POR(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK            (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT           (1U)
+#define SYSCON_SYSRSTSTAT_EXTRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK               (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT              (2U)
+#define SYSCON_SYSRSTSTAT_WDT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK               (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT              (3U)
+#define SYSCON_SYSRSTSTAT_BOD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK            (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT           (4U)
+#define SYSCON_SYSRSTSTAT_SYSRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+#define SYSCON_AHBCLKCTRL_MRT_MASK               (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT              (0U)
+#define SYSCON_AHBCLKCTRL_MRT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
+#define SYSCON_AHBCLKCTRL_RIT_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT              (1U)
+#define SYSCON_AHBCLKCTRL_RIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT              (1U)
+#define SYSCON_AHBCLKCTRL_ROM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK              (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT             (2U)
+#define SYSCON_AHBCLKCTRL_SCT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_LCD_MASK               (0x4U)
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT              (2U)
+#define SYSCON_AHBCLKCTRL_LCD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK             (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT            (3U)
+#define SYSCON_AHBCLKCTRL_SRAM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SDIO_MASK              (0x8U)
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT             (3U)
+#define SYSCON_AHBCLKCTRL_SDIO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT            (4U)
+#define SYSCON_AHBCLKCTRL_SRAM2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_USB1H_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT            (4U)
+#define SYSCON_AHBCLKCTRL_USB1H(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT            (5U)
+#define SYSCON_AHBCLKCTRL_SRAM3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
+#define SYSCON_AHBCLKCTRL_USB1D_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT            (5U)
+#define SYSCON_AHBCLKCTRL_USB1D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK           (0x40U)
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT          (6U)
+#define SYSCON_AHBCLKCTRL_USB1RAM(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
+#define SYSCON_AHBCLKCTRL_FLASH_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_FLASH_SHIFT            (7U)
+#define SYSCON_AHBCLKCTRL_FLASH(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
+#define SYSCON_AHBCLKCTRL_EMC_MASK               (0x80U)
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT              (7U)
+#define SYSCON_AHBCLKCTRL_EMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT            (7U)
+#define SYSCON_AHBCLKCTRL_MCAN0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
+#define SYSCON_AHBCLKCTRL_FMC_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_FMC_SHIFT              (8U)
+#define SYSCON_AHBCLKCTRL_FMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
+#define SYSCON_AHBCLKCTRL_ETH_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT              (8U)
+#define SYSCON_AHBCLKCTRL_ETH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK             (0x100U)
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT            (8U)
+#define SYSCON_AHBCLKCTRL_MCAN1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
+#define SYSCON_AHBCLKCTRL_EEPROM_MASK            (0x200U)
+#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT           (9U)
+#define SYSCON_AHBCLKCTRL_EEPROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK             (0x200U)
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT            (9U)
+#define SYSCON_AHBCLKCTRL_GPIO4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_GPIO5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_UTICK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_SPIFI(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK          (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT         (11U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_AES_MASK               (0x800U)
+#define SYSCON_AHBCLKCTRL_AES_SHIFT              (11U)
+#define SYSCON_AHBCLKCTRL_AES(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK         (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT        (11U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_OTP_MASK               (0x1000U)
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT              (12U)
+#define SYSCON_AHBCLKCTRL_OTP(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK         (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT        (12U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_RNG_MASK               (0x2000U)
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT              (13U)
+#define SYSCON_AHBCLKCTRL_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK             (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT            (13U)
+#define SYSCON_AHBCLKCTRL_IOCON(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK         (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT        (13U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK             (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT            (14U)
+#define SYSCON_AHBCLKCTRL_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT        (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT        (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT        (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT        (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK             (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT            (15U)
+#define SYSCON_AHBCLKCTRL_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK             (0x10000U)
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT            (16U)
+#define SYSCON_AHBCLKCTRL_GPIO2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK           (0x10000U)
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT          (16U)
+#define SYSCON_AHBCLKCTRL_USB0HMR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK         (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT        (16U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK         (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT        (17U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK             (0x20000U)
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT            (17U)
+#define SYSCON_AHBCLKCTRL_GPIO3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK           (0x20000U)
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT          (17U)
+#define SYSCON_AHBCLKCTRL_USB0HSL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT             (18U)
+#define SYSCON_AHBCLKCTRL_PINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_SHA0_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_SHA0_SHIFT             (18U)
+#define SYSCON_AHBCLKCTRL_SHA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK         (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT        (18U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT             (19U)
+#define SYSCON_AHBCLKCTRL_DMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT             (19U)
+#define SYSCON_AHBCLKCTRL_GINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_SC0_MASK               (0x80000U)
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT              (19U)
+#define SYSCON_AHBCLKCTRL_SC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
+#define SYSCON_AHBCLKCTRL_SC1_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT              (20U)
+#define SYSCON_AHBCLKCTRL_SC1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
+#define SYSCON_AHBCLKCTRL_DMA_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT              (20U)
+#define SYSCON_AHBCLKCTRL_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK               (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT              (21U)
+#define SYSCON_AHBCLKCTRL_CRC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK              (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT             (22U)
+#define SYSCON_AHBCLKCTRL_WWDT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK           (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT          (22U)
+#define SYSCON_AHBCLKCTRL_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK               (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT              (23U)
+#define SYSCON_AHBCLKCTRL_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0D_MASK             (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT            (25U)
+#define SYSCON_AHBCLKCTRL_USB0D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK           (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT          (26U)
+#define SYSCON_AHBCLKCTRL_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK           (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT          (27U)
+#define SYSCON_AHBCLKCTRL_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK              (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT             (27U)
+#define SYSCON_AHBCLKCTRL_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT                  (3U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT               (3U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT               (3U)
+
+/*! @name MAINCLKSELA - Main clock source select A */
+#define SYSCON_MAINCLKSELA_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+
+/*! @name MAINCLKSELB - Main clock source select B */
+#define SYSCON_MAINCLKSELB_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+#define SYSCON_CLKOUTSELA_SEL_MASK               (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT              (0U)
+#define SYSCON_CLKOUTSELA_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT            (0U)
+#define SYSCON_SYSPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT            (0U)
+#define SYSCON_AUDPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+#define SYSCON_SPIFICLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT             (0U)
+#define SYSCON_SPIFICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+
+/*! @name ADCCLKSEL - ADC clock source select */
+#define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+
+/*! @name USB0CLKSEL - USB0 clock source select */
+#define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+
+/*! @name USB1CLKSEL - USB1 clock source select */
+#define SYSCON_USB1CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB1CLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_USB1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
+
+/*! @name FCLKSEL - Flexcomm 0 clock source select */
+#define SYSCON_FCLKSEL_SEL_MASK                  (0x7U)
+#define SYSCON_FCLKSEL_SEL_SHIFT                 (0U)
+#define SYSCON_FCLKSEL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
+
+/* The count of SYSCON_FCLKSEL */
+#define SYSCON_FCLKSEL_COUNT                     (10U)
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+#define SYSCON_FRGCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_FRGCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
+#define SYSCON_DMICCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_DMICCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
+#define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+
+/*! @name LCDCLKSEL - LCD clock source select */
+#define SYSCON_LCDCLKSEL_SEL_MASK                (0x3U)
+#define SYSCON_LCDCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_LCDCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
+
+/*! @name SDIOCLKSEL - SDIO clock source select */
+#define SYSCON_SDIOCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_SDIOCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
+#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
+#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
+#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK        (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT       (31U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
+
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK           (0xFFU)
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT          (0U)
+#define SYSCON_ARMTRACECLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK         (0x20000000U)
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT        (29U)
+#define SYSCON_ARMTRACECLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK          (0x40000000U)
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT         (30U)
+#define SYSCON_ARMTRACECLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK       (0x80000000U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT      (31U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
+
+/*! @name CAN0CLKDIV - MCAN0 clock divider */
+#define SYSCON_CAN0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_CAN0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
+#define SYSCON_CAN0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_CAN0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
+#define SYSCON_CAN0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_CAN0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_CAN0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
+
+/*! @name CAN1CLKDIV - MCAN1 clock divider */
+#define SYSCON_CAN1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_CAN1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
+#define SYSCON_CAN1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_CAN1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
+#define SYSCON_CAN1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_CAN1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_CAN1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
+
+/*! @name SC0CLKDIV - Smartcard0 clock divider */
+#define SYSCON_SC0CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC0CLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SC0CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
+#define SYSCON_SC0CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC0CLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SC0CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
+#define SYSCON_SC0CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC0CLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SC0CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SC0CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
+
+/*! @name SC1CLKDIV - Smartcard1 clock divider */
+#define SYSCON_SC1CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC1CLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SC1CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
+#define SYSCON_SC1CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC1CLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SC1CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
+#define SYSCON_SC1CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC1CLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SC1CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SC1CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
+
+/*! @name AHBCLKDIV - AHB clock divider */
+#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_AHBCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
+#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
+#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
+#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_CLKOUTDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+
+/*! @name FROHFCLKDIV - FROHF clock divider */
+#define SYSCON_FROHFCLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_FROHFCLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_FROHFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)
+#define SYSCON_FROHFCLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_FROHFCLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_FROHFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)
+#define SYSCON_FROHFCLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_FROHFCLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_FROHFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)
+#define SYSCON_FROHFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT         (31U)
+#define SYSCON_FROHFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+#define SYSCON_SPIFICLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_SPIFICLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_SPIFICLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_SPIFICLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK          (0x80000000U)
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT         (31U)
+#define SYSCON_SPIFICLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
+
+/*! @name ADCCLKDIV - ADC clock divider */
+#define SYSCON_ADCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_ADCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+
+/*! @name USB0CLKDIV - USB0 clock divider */
+#define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+#define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+#define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_USB0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+
+/*! @name USB1CLKDIV - USB1 clock divider */
+#define SYSCON_USB1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB1CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_USB1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
+#define SYSCON_USB1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB1CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_USB1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
+#define SYSCON_USB1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB1CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_USB1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_USB1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
+
+/*! @name FRGCTRL - Fractional rate divider */
+#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
+#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
+#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+#define SYSCON_DMICCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_DMICCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_DMICCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_DMICCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_DMICCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
+#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
+#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
+#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+#define SYSCON_MCLKDIV_REQFLAG_MASK              (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT             (31U)
+#define SYSCON_MCLKDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+
+/*! @name LCDCLKDIV - LCD clock divider */
+#define SYSCON_LCDCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_LCDCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_LCDCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
+#define SYSCON_LCDCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_LCDCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_LCDCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
+#define SYSCON_LCDCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_LCDCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_LCDCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_LCDCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
+
+/*! @name SCTCLKDIV - SCT/PWM clock divider */
+#define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+#define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+#define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SCTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+
+/*! @name EMCCLKDIV - EMC clock divider */
+#define SYSCON_EMCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_EMCCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_EMCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
+#define SYSCON_EMCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_EMCCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_EMCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
+#define SYSCON_EMCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_EMCCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_EMCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_EMCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
+
+/*! @name SDIOCLKDIV - SDIO clock divider */
+#define SYSCON_SDIOCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_SDIOCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+#define SYSCON_SDIOCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_SDIOCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+#define SYSCON_SDIOCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_SDIOCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_SDIOCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+
+/*! @name FLASHCFG - Flash wait states configuration */
+#define SYSCON_FLASHCFG_FETCHCFG_MASK            (0x3U)
+#define SYSCON_FLASHCFG_FETCHCFG_SHIFT           (0U)
+#define SYSCON_FLASHCFG_FETCHCFG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
+#define SYSCON_FLASHCFG_DATACFG_MASK             (0xCU)
+#define SYSCON_FLASHCFG_DATACFG_SHIFT            (2U)
+#define SYSCON_FLASHCFG_DATACFG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
+#define SYSCON_FLASHCFG_ACCEL_MASK               (0x10U)
+#define SYSCON_FLASHCFG_ACCEL_SHIFT              (4U)
+#define SYSCON_FLASHCFG_ACCEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
+#define SYSCON_FLASHCFG_PREFEN_MASK              (0x20U)
+#define SYSCON_FLASHCFG_PREFEN_SHIFT             (5U)
+#define SYSCON_FLASHCFG_PREFEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
+#define SYSCON_FLASHCFG_PREFOVR_MASK             (0x40U)
+#define SYSCON_FLASHCFG_PREFOVR_SHIFT            (6U)
+#define SYSCON_FLASHCFG_PREFOVR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
+#define SYSCON_FLASHCFG_FLASHTIM_MASK            (0xF000U)
+#define SYSCON_FLASHCFG_FLASHTIM_SHIFT           (12U)
+#define SYSCON_FLASHCFG_FLASHTIM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
+
+/*! @name USB0CLKCTRL - USB0 clock control */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK       (0x10U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT      (4U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
+
+/*! @name USB0CLKSTAT - USB0 clock status */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name FREQMECTRL - Frequency measure register */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK            (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT           (0U)
+#define SYSCON_FREQMECTRL_CAPVAL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK              (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT             (31U)
+#define SYSCON_FREQMECTRL_PROG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+
+/*! @name MCLKIO - MCLK input/output control */
+#define SYSCON_MCLKIO_DIR_MASK                   (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT                  (0U)
+#define SYSCON_MCLKIO_DIR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+
+/*! @name USB1CLKCTRL - USB1 clock control */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK  (0x10U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+
+/*! @name USB1CLKSTAT - USB1 clock status */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name EMCSYSCTRL - EMC system control */
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK             (0x1U)
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT            (0U)
+#define SYSCON_EMCSYSCTRL_EMCSC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK             (0x2U)
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT            (1U)
+#define SYSCON_EMCSYSCTRL_EMCRD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK             (0x4U)
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT            (2U)
+#define SYSCON_EMCSYSCTRL_EMCBC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK     (0x8U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT    (3U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
+
+/*! @name EMCDLYCTRL - EMC clock delay control */
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK         (0x1FU)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT        (0U)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK       (0x1F00U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT      (8U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)
+
+/*! @name EMCDLYCAL - EMC delay chain calibration control */
+#define SYSCON_EMCDLYCAL_CALVALUE_MASK           (0xFFU)
+#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT          (0U)
+#define SYSCON_EMCDLYCAL_CALVALUE(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)
+#define SYSCON_EMCDLYCAL_START_MASK              (0x4000U)
+#define SYSCON_EMCDLYCAL_START_SHIFT             (14U)
+#define SYSCON_EMCDLYCAL_START(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)
+#define SYSCON_EMCDLYCAL_DONE_MASK               (0x8000U)
+#define SYSCON_EMCDLYCAL_DONE_SHIFT              (15U)
+#define SYSCON_EMCDLYCAL_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)
+
+/*! @name ETHPHYSEL - Ethernet PHY Selection */
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK            (0x4U)
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT           (2U)
+#define SYSCON_ETHPHYSEL_PHY_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
+
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK          (0x3U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT         (0U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
+
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK   (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT  (0U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK     (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT    (7U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK   (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT  (16U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+
+/*! @name FROCTRL - FRO oscillator control */
+#define SYSCON_FROCTRL_TRIM_MASK                 (0x3FFFU)
+#define SYSCON_FROCTRL_TRIM_SHIFT                (0U)
+#define SYSCON_FROCTRL_TRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
+#define SYSCON_FROCTRL_SEL_MASK                  (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT                 (14U)
+#define SYSCON_FROCTRL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK             (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT            (16U)
+#define SYSCON_FROCTRL_FREQTRIM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK            (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT           (24U)
+#define SYSCON_FROCTRL_USBCLKADJ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK            (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT           (25U)
+#define SYSCON_FROCTRL_USBMODCHG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK              (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT             (30U)
+#define SYSCON_FROCTRL_HSPDCLK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+#define SYSCON_FROCTRL_WRTRIM_MASK               (0x80000000U)
+#define SYSCON_FROCTRL_WRTRIM_SHIFT              (31U)
+#define SYSCON_FROCTRL_WRTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
+
+/*! @name SYSOSCCTRL - System oscillator control */
+#define SYSCON_SYSOSCCTRL_BYPASS_MASK            (0x1U)
+#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT           (0U)
+#define SYSCON_SYSOSCCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK         (0x2U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT        (1U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK            (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT           (0U)
+#define SYSCON_WDTOSCCTRL_DIVSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK           (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT          (5U)
+#define SYSCON_WDTOSCCTRL_FREQSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+#define SYSCON_RTCOSCCTRL_EN_MASK                (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT               (0U)
+#define SYSCON_RTCOSCCTRL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+
+/*! @name USBPLLCTRL - USB PLL control */
+#define SYSCON_USBPLLCTRL_MSEL_MASK              (0xFFU)
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT             (0U)
+#define SYSCON_USBPLLCTRL_MSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
+#define SYSCON_USBPLLCTRL_PSEL_MASK              (0x300U)
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT             (8U)
+#define SYSCON_USBPLLCTRL_PSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
+#define SYSCON_USBPLLCTRL_NSEL_MASK              (0xC00U)
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT             (10U)
+#define SYSCON_USBPLLCTRL_NSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
+#define SYSCON_USBPLLCTRL_DIRECT_MASK            (0x1000U)
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT           (12U)
+#define SYSCON_USBPLLCTRL_DIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
+#define SYSCON_USBPLLCTRL_BYPASS_MASK            (0x2000U)
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT           (13U)
+#define SYSCON_USBPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
+#define SYSCON_USBPLLCTRL_FBSEL_MASK             (0x4000U)
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT            (14U)
+#define SYSCON_USBPLLCTRL_FBSEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
+
+/*! @name USBPLLSTAT - USB PLL status */
+#define SYSCON_USBPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_USBPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLCTRL - System PLL control */
+#define SYSCON_SYSPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT             (0U)
+#define SYSCON_SYSPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT             (4U)
+#define SYSCON_SYSPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT             (10U)
+#define SYSCON_SYSPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT           (15U)
+#define SYSCON_SYSPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT         (17U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT          (19U)
+#define SYSCON_SYSPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT          (20U)
+#define SYSCON_SYSPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+
+/*! @name SYSPLLSTAT - PLL status */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_SYSPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLNDEC - PLL N divider */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT             (10U)
+#define SYSCON_SYSPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+
+/*! @name SYSPLLPDEC - PLL P divider */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT             (7U)
+#define SYSCON_SYSPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+
+/*! @name SYSPLLMDEC - System PLL M divider */
+#define SYSCON_SYSPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
+#define SYSCON_SYSPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT             (17U)
+#define SYSCON_SYSPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLCTRL - Audio PLL control */
+#define SYSCON_AUDPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT             (0U)
+#define SYSCON_AUDPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
+#define SYSCON_AUDPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT             (4U)
+#define SYSCON_AUDPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
+#define SYSCON_AUDPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT             (10U)
+#define SYSCON_AUDPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT           (15U)
+#define SYSCON_AUDPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT         (17U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT          (19U)
+#define SYSCON_AUDPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT          (20U)
+#define SYSCON_AUDPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
+
+/*! @name AUDPLLSTAT - Audio PLL status */
+#define SYSCON_AUDPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_AUDPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
+
+/*! @name AUDPLLNDEC - Audio PLL N divider */
+#define SYSCON_AUDPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
+#define SYSCON_AUDPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT             (10U)
+#define SYSCON_AUDPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
+
+/*! @name AUDPLLPDEC - Audio PLL P divider */
+#define SYSCON_AUDPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
+#define SYSCON_AUDPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT             (7U)
+#define SYSCON_AUDPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
+
+/*! @name AUDPLLMDEC - Audio PLL M divider */
+#define SYSCON_AUDPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
+#define SYSCON_AUDPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT             (17U)
+#define SYSCON_AUDPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
+#define SYSCON_AUDPLLFRAC_CTRL_MASK              (0x3FFFFFU)
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT             (0U)
+#define SYSCON_AUDPLLFRAC_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
+#define SYSCON_AUDPLLFRAC_REQ_MASK               (0x400000U)
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT              (22U)
+#define SYSCON_AUDPLLFRAC_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK           (0x800000U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT          (23U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
+
+/*! @name PDSLEEPCFG - Power configuration register 0 */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK     (0x1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT    (0U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK     (0x2U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT    (1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK      (0x4U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT     (2U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK       (0x8U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT      (3U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK          (0x10U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT         (4U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK       (0x20U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT      (5U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK           (0x40U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT          (6U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK      (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT     (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK          (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT         (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK     (0x100U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT    (8U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK      (0x200U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT     (9U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK         (0x400U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT        (10U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK        (0x2000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT       (13U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK        (0x4000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT       (14U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK    (0x8000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT   (15U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK      (0x10000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT     (16U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK          (0x20000U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT         (17U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK         (0x80000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT        (19U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK      (0x100000U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT     (20U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK     (0x200000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT    (21U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK      (0x400000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT     (22U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK        (0x800000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT       (23U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK          (0x4000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT         (26U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK          (0x8000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT         (27U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK          (0x10000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT         (28U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK          (0x20000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT         (29U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT                  (2U)
+
+/*! @name PDRUNCFG - Power configuration register 0 */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK       (0x1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT      (0U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK       (0x2U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT      (1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK        (0x4U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT       (2U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK         (0x8U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT        (3U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK            (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT           (4U)
+#define SYSCON_PDRUNCFG_PDEN_FRO(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK         (0x20U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT        (5U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK             (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT            (6U)
+#define SYSCON_PDRUNCFG_PDEN_TS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK        (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT       (7U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK            (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT           (7U)
+#define SYSCON_PDRUNCFG_PDEN_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK       (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT      (8U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK        (0x200U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT       (9U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK           (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT          (10U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT         (13U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT         (14U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK      (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT     (15U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK        (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT       (16U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK            (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT           (17U)
+#define SYSCON_PDRUNCFG_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK           (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT          (19U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK        (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT       (20U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK       (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT      (21U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK        (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT       (22U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK          (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT         (23U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK            (0x4000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT           (26U)
+#define SYSCON_PDRUNCFG_PDEN_VD3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK            (0x8000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT           (27U)
+#define SYSCON_PDRUNCFG_PDEN_VD4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK            (0x10000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT           (28U)
+#define SYSCON_PDRUNCFG_PDEN_VD5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK            (0x20000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT           (29U)
+#define SYSCON_PDRUNCFG_PDEN_VD6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT                    (2U)
+
+/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT   (0U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT   (1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT    (2U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT     (3U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT        (4U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK      (0x20U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT     (5U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT         (6U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT    (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT        (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT   (8U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT    (9U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT       (10U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT      (13U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT      (14U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT  (15U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT    (16U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT        (17U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT       (19U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT    (20U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT   (21U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT    (22U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT      (23U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT        (26U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT        (27U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT        (28U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT        (29U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT                 (2U)
+
+/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT   (0U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT   (1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT    (2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT     (3U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT        (4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK      (0x20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT     (5U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT         (6U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT    (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT        (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT   (8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT    (9U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT       (10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT      (13U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT      (14U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT  (15U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT    (16U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT        (17U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT       (19U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT    (20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT   (21U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT    (22U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT      (23U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT        (26U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT        (27U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT        (28U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT        (29U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT                 (2U)
+
+/*! @name STARTER - Start logic 0 wake-up enable register */
+#define SYSCON_STARTER_WDT_BOD_MASK              (0x1U)
+#define SYSCON_STARTER_WDT_BOD_SHIFT             (0U)
+#define SYSCON_STARTER_WDT_BOD(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
+#define SYSCON_STARTER_PINT4_MASK                (0x1U)
+#define SYSCON_STARTER_PINT4_SHIFT               (0U)
+#define SYSCON_STARTER_PINT4(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
+#define SYSCON_STARTER_PINT5_MASK                (0x2U)
+#define SYSCON_STARTER_PINT5_SHIFT               (1U)
+#define SYSCON_STARTER_PINT5(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
+#define SYSCON_STARTER_DMA_MASK                  (0x2U)
+#define SYSCON_STARTER_DMA_SHIFT                 (1U)
+#define SYSCON_STARTER_DMA(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
+#define SYSCON_STARTER_GINT0_MASK                (0x4U)
+#define SYSCON_STARTER_GINT0_SHIFT               (2U)
+#define SYSCON_STARTER_GINT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
+#define SYSCON_STARTER_PINT6_MASK                (0x4U)
+#define SYSCON_STARTER_PINT6_SHIFT               (2U)
+#define SYSCON_STARTER_PINT6(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
+#define SYSCON_STARTER_GINT1_MASK                (0x8U)
+#define SYSCON_STARTER_GINT1_SHIFT               (3U)
+#define SYSCON_STARTER_GINT1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
+#define SYSCON_STARTER_PINT7_MASK                (0x8U)
+#define SYSCON_STARTER_PINT7_SHIFT               (3U)
+#define SYSCON_STARTER_PINT7(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
+#define SYSCON_STARTER_CTIMER2_MASK              (0x10U)
+#define SYSCON_STARTER_CTIMER2_SHIFT             (4U)
+#define SYSCON_STARTER_CTIMER2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)
+#define SYSCON_STARTER_PIN_INT0_MASK             (0x10U)
+#define SYSCON_STARTER_PIN_INT0_SHIFT            (4U)
+#define SYSCON_STARTER_PIN_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
+#define SYSCON_STARTER_CTIMER4_MASK              (0x20U)
+#define SYSCON_STARTER_CTIMER4_SHIFT             (5U)
+#define SYSCON_STARTER_CTIMER4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)
+#define SYSCON_STARTER_PIN_INT1_MASK             (0x20U)
+#define SYSCON_STARTER_PIN_INT1_SHIFT            (5U)
+#define SYSCON_STARTER_PIN_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
+#define SYSCON_STARTER_PIN_INT2_MASK             (0x40U)
+#define SYSCON_STARTER_PIN_INT2_SHIFT            (6U)
+#define SYSCON_STARTER_PIN_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
+#define SYSCON_STARTER_PIN_INT3_MASK             (0x80U)
+#define SYSCON_STARTER_PIN_INT3_SHIFT            (7U)
+#define SYSCON_STARTER_PIN_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
+#define SYSCON_STARTER_SPIFI_MASK                (0x80U)
+#define SYSCON_STARTER_SPIFI_SHIFT               (7U)
+#define SYSCON_STARTER_SPIFI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)
+#define SYSCON_STARTER_FLEXCOMM8_MASK            (0x100U)
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT           (8U)
+#define SYSCON_STARTER_FLEXCOMM8(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
+#define SYSCON_STARTER_UTICK_MASK                (0x100U)
+#define SYSCON_STARTER_UTICK_SHIFT               (8U)
+#define SYSCON_STARTER_UTICK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
+#define SYSCON_STARTER_MRT_MASK                  (0x200U)
+#define SYSCON_STARTER_MRT_SHIFT                 (9U)
+#define SYSCON_STARTER_MRT(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)
+#define SYSCON_STARTER_FLEXCOMM9_MASK            (0x200U)
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT           (9U)
+#define SYSCON_STARTER_FLEXCOMM9(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
+#define SYSCON_STARTER_CTIMER0_MASK              (0x400U)
+#define SYSCON_STARTER_CTIMER0_SHIFT             (10U)
+#define SYSCON_STARTER_CTIMER0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)
+#define SYSCON_STARTER_CTIMER1_MASK              (0x800U)
+#define SYSCON_STARTER_CTIMER1_SHIFT             (11U)
+#define SYSCON_STARTER_CTIMER1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)
+#define SYSCON_STARTER_SCT0_MASK                 (0x1000U)
+#define SYSCON_STARTER_SCT0_SHIFT                (12U)
+#define SYSCON_STARTER_SCT0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)
+#define SYSCON_STARTER_CTIMER3_MASK              (0x2000U)
+#define SYSCON_STARTER_CTIMER3_SHIFT             (13U)
+#define SYSCON_STARTER_CTIMER3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)
+#define SYSCON_STARTER_FLEXCOMM0_MASK            (0x4000U)
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT           (14U)
+#define SYSCON_STARTER_FLEXCOMM0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
+#define SYSCON_STARTER_FLEXCOMM1_MASK            (0x8000U)
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT           (15U)
+#define SYSCON_STARTER_FLEXCOMM1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
+#define SYSCON_STARTER_USB1_MASK                 (0x8000U)
+#define SYSCON_STARTER_USB1_SHIFT                (15U)
+#define SYSCON_STARTER_USB1(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
+#define SYSCON_STARTER_FLEXCOMM2_MASK            (0x10000U)
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT           (16U)
+#define SYSCON_STARTER_FLEXCOMM2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
+#define SYSCON_STARTER_USB1_ACT_MASK             (0x10000U)
+#define SYSCON_STARTER_USB1_ACT_SHIFT            (16U)
+#define SYSCON_STARTER_USB1_ACT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
+#define SYSCON_STARTER_ENET_INT1_MASK            (0x20000U)
+#define SYSCON_STARTER_ENET_INT1_SHIFT           (17U)
+#define SYSCON_STARTER_ENET_INT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)
+#define SYSCON_STARTER_FLEXCOMM3_MASK            (0x20000U)
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT           (17U)
+#define SYSCON_STARTER_FLEXCOMM3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
+#define SYSCON_STARTER_ENET_INT2_MASK            (0x40000U)
+#define SYSCON_STARTER_ENET_INT2_SHIFT           (18U)
+#define SYSCON_STARTER_ENET_INT2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)
+#define SYSCON_STARTER_FLEXCOMM4_MASK            (0x40000U)
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT           (18U)
+#define SYSCON_STARTER_FLEXCOMM4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
+#define SYSCON_STARTER_ENET_INT0_MASK            (0x80000U)
+#define SYSCON_STARTER_ENET_INT0_SHIFT           (19U)
+#define SYSCON_STARTER_ENET_INT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)
+#define SYSCON_STARTER_FLEXCOMM5_MASK            (0x80000U)
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT           (19U)
+#define SYSCON_STARTER_FLEXCOMM5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
+#define SYSCON_STARTER_FLEXCOMM6_MASK            (0x100000U)
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT           (20U)
+#define SYSCON_STARTER_FLEXCOMM6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
+#define SYSCON_STARTER_FLEXCOMM7_MASK            (0x200000U)
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT           (21U)
+#define SYSCON_STARTER_FLEXCOMM7(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
+#define SYSCON_STARTER_ADC0_SEQA_MASK            (0x400000U)
+#define SYSCON_STARTER_ADC0_SEQA_SHIFT           (22U)
+#define SYSCON_STARTER_ADC0_SEQA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)
+#define SYSCON_STARTER_SMARTCARD0_MASK           (0x800000U)
+#define SYSCON_STARTER_SMARTCARD0_SHIFT          (23U)
+#define SYSCON_STARTER_SMARTCARD0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)
+#define SYSCON_STARTER_ADC0_SEQB_MASK            (0x800000U)
+#define SYSCON_STARTER_ADC0_SEQB_SHIFT           (23U)
+#define SYSCON_STARTER_ADC0_SEQB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)
+#define SYSCON_STARTER_ADC0_THCMP_MASK           (0x1000000U)
+#define SYSCON_STARTER_ADC0_THCMP_SHIFT          (24U)
+#define SYSCON_STARTER_ADC0_THCMP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)
+#define SYSCON_STARTER_SMARTCARD1_MASK           (0x1000000U)
+#define SYSCON_STARTER_SMARTCARD1_SHIFT          (24U)
+#define SYSCON_STARTER_SMARTCARD1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)
+#define SYSCON_STARTER_DMIC_MASK                 (0x2000000U)
+#define SYSCON_STARTER_DMIC_SHIFT                (25U)
+#define SYSCON_STARTER_DMIC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
+#define SYSCON_STARTER_HWVAD_MASK                (0x4000000U)
+#define SYSCON_STARTER_HWVAD_SHIFT               (26U)
+#define SYSCON_STARTER_HWVAD(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK         (0x8000000U)
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT        (27U)
+#define SYSCON_STARTER_USB0_NEEDCLK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTER_USB0_MASK                 (0x10000000U)
+#define SYSCON_STARTER_USB0_SHIFT                (28U)
+#define SYSCON_STARTER_USB0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
+#define SYSCON_STARTER_RTC_MASK                  (0x20000000U)
+#define SYSCON_STARTER_RTC_SHIFT                 (29U)
+#define SYSCON_STARTER_RTC(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
+
+/* The count of SYSCON_STARTER */
+#define SYSCON_STARTER_COUNT                     (2U)
+
+/*! @name STARTERSET - Set bits in STARTER */
+#define SYSCON_STARTERSET_START_SET_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT        (0U)
+#define SYSCON_STARTERSET_START_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT                  (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTER0 */
+#define SYSCON_STARTERCLR_START_CLR_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT        (0U)
+#define SYSCON_STARTERCLR_START_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT                  (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK             (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT            (0U)
+#define SYSCON_HWWAKE_FORCEWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK                (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT               (1U)
+#define SYSCON_HWWAKE_FCWAKE(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK              (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT             (2U)
+#define SYSCON_HWWAKE_WAKEDMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK               (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT              (3U)
+#define SYSCON_HWWAKE_WAKEDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+#define SYSCON_AUTOCGOR_RAM0X_MASK               (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT              (1U)
+#define SYSCON_AUTOCGOR_RAM0X(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK                (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT               (2U)
+#define SYSCON_AUTOCGOR_RAM1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK                (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT               (3U)
+#define SYSCON_AUTOCGOR_RAM2(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+#define SYSCON_AUTOCGOR_RAM3_MASK                (0x10U)
+#define SYSCON_AUTOCGOR_RAM3_SHIFT               (4U)
+#define SYSCON_AUTOCGOR_RAM3(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK            (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT           (0U)
+#define SYSCON_JTAGIDCODE_JTAGID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+
+/*! @name DEVICE_ID0 - Part ID register */
+#define SYSCON_DEVICE_ID0_PARTID_MASK            (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT           (0U)
+#define SYSCON_DEVICE_ID0_PARTID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+#define SYSCON_DEVICE_ID1_REVID_MASK             (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT            (0U)
+#define SYSCON_DEVICE_ID1_REVID(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+
+/*! @name BODCTRL - Brown-Out Detect control */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK            (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT           (0U)
+#define SYSCON_BODCTRL_BODRSTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK            (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT           (2U)
+#define SYSCON_BODCTRL_BODRSTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK            (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT           (3U)
+#define SYSCON_BODCTRL_BODINTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK            (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT           (5U)
+#define SYSCON_BODCTRL_BODINTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK           (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT          (6U)
+#define SYSCON_BODCTRL_BODRSTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK           (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT          (7U)
+#define SYSCON_BODCTRL_BODINTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+  __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+  __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+  __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+  __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
+       uint8_t RESERVED_1[3536];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_4[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_6[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+#define USART_CFG_ENABLE_MASK                    (0x1U)
+#define USART_CFG_ENABLE_SHIFT                   (0U)
+#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK                   (0xCU)
+#define USART_CFG_DATALEN_SHIFT                  (2U)
+#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK                 (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT                (4U)
+#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK                   (0x40U)
+#define USART_CFG_STOPLEN_SHIFT                  (6U)
+#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK                   (0x80U)
+#define USART_CFG_MODE32K_SHIFT                  (7U)
+#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK                   (0x100U)
+#define USART_CFG_LINMODE_SHIFT                  (8U)
+#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK                     (0x200U)
+#define USART_CFG_CTSEN_SHIFT                    (9U)
+#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK                    (0x800U)
+#define USART_CFG_SYNCEN_SHIFT                   (11U)
+#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK                    (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT                   (12U)
+#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK                   (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT                  (14U)
+#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK                      (0x8000U)
+#define USART_CFG_LOOP_SHIFT                     (15U)
+#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK                      (0x40000U)
+#define USART_CFG_OETA_SHIFT                     (18U)
+#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT                 (19U)
+#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK                     (0x100000U)
+#define USART_CFG_OESEL_SHIFT                    (20U)
+#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK                     (0x200000U)
+#define USART_CFG_OEPOL_SHIFT                    (21U)
+#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK                     (0x400000U)
+#define USART_CFG_RXPOL_SHIFT                    (22U)
+#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK                     (0x800000U)
+#define USART_CFG_TXPOL_SHIFT                    (23U)
+#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+#define USART_CTL_TXBRKEN_MASK                   (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT                  (1U)
+#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK                   (0x4U)
+#define USART_CTL_ADDRDET_SHIFT                  (2U)
+#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK                     (0x40U)
+#define USART_CTL_TXDIS_SHIFT                    (6U)
+#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK                        (0x100U)
+#define USART_CTL_CC_SHIFT                       (8U)
+#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT                (9U)
+#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
+#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+#define USART_STAT_RXIDLE_MASK                   (0x2U)
+#define USART_STAT_RXIDLE_SHIFT                  (1U)
+#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK                   (0x8U)
+#define USART_STAT_TXIDLE_SHIFT                  (3U)
+#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK                      (0x10U)
+#define USART_STAT_CTS_SHIFT                     (4U)
+#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK                 (0x20U)
+#define USART_STAT_DELTACTS_SHIFT                (5U)
+#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK                (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT               (6U)
+#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK                    (0x400U)
+#define USART_STAT_RXBRK_SHIFT                   (10U)
+#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK               (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT              (11U)
+#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK                    (0x1000U)
+#define USART_STAT_START_SHIFT                   (12U)
+#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT              (13U)
+#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT            (14U)
+#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT              (15U)
+#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK                    (0x10000U)
+#define USART_STAT_ABERR_SHIFT                   (16U)
+#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
+#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
+#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK              (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT             (6U)
+#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
+#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK              (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT             (12U)
+#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
+#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
+#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
+#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK              (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT             (16U)
+#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
+#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
+#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
+#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
+#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
+#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
+#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
+#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
+#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
+#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT                   (0U)
+#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
+#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
+#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
+#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
+#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK                 (0x1000U)
+#define USART_INTSTAT_START_SHIFT                (12U)
+#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
+#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
+#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
+#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
+#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+#define USART_OSR_OSRVAL_MASK                    (0xFU)
+#define USART_OSR_OSRVAL_SHIFT                   (0U)
+#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+
+/*! @name ADDR - Address register for automatic address matching. */
+#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT                 (0U)
+#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
+#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
+#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
+#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT                (12U)
+#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT                (13U)
+#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
+#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
+#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
+#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
+#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
+#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
+#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
+#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
+#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
+#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
+#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
+#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
+#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
+#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
+#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
+#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
+#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
+#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
+#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
+#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
+#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
+#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
+#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
+#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
+#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT                (0U)
+#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT                (0U)
+#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT               (13U)
+#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT             (14U)
+#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT               (15U)
+#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
+#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
+#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
+#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
+#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define USART_ID_APERTURE_MASK                   (0xFFU)
+#define USART_ID_APERTURE_SHIFT                  (0U)
+#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK                  (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT                 (8U)
+#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT                 (12U)
+#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK                         (0xFFFF0000U)
+#define USART_ID_ID_SHIFT                        (16U)
+#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE                              (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0                                   ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE                              (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1                                   ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE                              (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2                                   ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE                              (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3                                   ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE                              (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4                                   ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE                              (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5                                   ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE                              (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6                                   ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE                              (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7                                   ((USART_Type *)USART7_BASE)
+/** Peripheral USART8 base address */
+#define USART8_BASE                              (0x40099000u)
+/** Peripheral USART8 base pointer */
+#define USART8                                   ((USART_Type *)USART8_BASE)
+/** Peripheral USART9 base address */
+#define USART9_BASE                              (0x4009A000u)
+/** Peripheral USART9 base pointer */
+#define USART9                                   ((USART_Type *)USART9_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
+#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
+#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
+#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
+#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
+#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
+#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
+#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
+#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
+#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
+#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
+#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
+#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
+#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
+#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
+#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+
+/*! @name INFO - USB Info register */
+#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT                  (0U)
+#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT                  (11U)
+#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+#define USB_INFO_MINREV_MASK                     (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT                    (16U)
+#define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+#define USB_INFO_MAJREV_MASK                     (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT                    (24U)
+#define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
+#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
+#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USB_LPM_HIRD_HW_MASK                     (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT                    (0U)
+#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT                    (4U)
+#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK                (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT               (8U)
+#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USB_EPSKIP_SKIP_MASK                     (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT                    (0U)
+#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USB_EPINUSE_BUF_MASK                     (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT                    (2U)
+#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
+#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
+#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
+#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
+#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
+#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
+#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
+#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
+#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
+#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
+#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
+#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
+#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
+#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
+#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
+#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
+#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
+#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
+#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
+#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
+#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBFSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t HCREVISION;                        /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+  __IO uint32_t HCCONTROL;                         /**< Defines the operating modes of the HC, offset: 0x4 */
+  __IO uint32_t HCCOMMANDSTATUS;                   /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+  __IO uint32_t HCINTERRUPTSTATUS;                 /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+  __IO uint32_t HCINTERRUPTENABLE;                 /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+  __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+  __IO uint32_t HCHCCA;                            /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+  __IO uint32_t HCPERIODCURRENTED;                 /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+  __IO uint32_t HCCONTROLHEADED;                   /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+  __IO uint32_t HCCONTROLCURRENTED;                /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+  __IO uint32_t HCBULKHEADED;                      /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+  __IO uint32_t HCBULKCURRENTED;                   /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+  __IO uint32_t HCDONEHEAD;                        /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+  __IO uint32_t HCFMINTERVAL;                      /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+  __IO uint32_t HCFMREMAINING;                     /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+  __IO uint32_t HCFMNUMBER;                        /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+  __IO uint32_t HCPERIODICSTART;                   /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+  __IO uint32_t HCLSTHRESHOLD;                     /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+  __IO uint32_t HCRHDESCRIPTORA;                   /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+  __IO uint32_t HCRHDESCRIPTORB;                   /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+  __IO uint32_t HCRHSTATUS;                        /**< This register is divided into two parts, offset: 0x50 */
+  __IO uint32_t HCRHPORTSTATUS;                    /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+} USBFSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
+ * @{
+ */
+
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
+#define USBFSH_HCREVISION_REV_MASK               (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT              (0U)
+#define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+
+/*! @name HCCONTROL - Defines the operating modes of the HC */
+#define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
+#define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+#define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
+#define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+#define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT                (3U)
+#define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+#define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
+#define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+#define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
+#define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+#define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
+#define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+#define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT                (8U)
+#define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+#define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
+#define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+#define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
+#define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
+#define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
+#define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
+#define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
+#define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
+#define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
+#define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
+#define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
+#define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
+#define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
+#define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
+#define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
+#define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
+#define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
+#define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
+#define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
+#define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
+#define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
+#define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
+#define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
+#define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
+#define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
+#define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
+#define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */
+#define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
+#define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
+#define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
+#define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
+#define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
+#define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
+#define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
+#define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
+#define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
+#define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
+#define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
+#define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+#define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
+#define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
+#define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
+#define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+#define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
+#define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
+#define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
+#define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
+#define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
+#define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
+#define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
+#define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
+#define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
+#define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
+#define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
+#define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
+#define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+
+/*! @name HCRHSTATUS - This register is divided into two parts */
+#define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
+#define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+#define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
+#define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+#define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
+#define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+#define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
+#define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+#define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
+#define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+#define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
+#define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
+#define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
+#define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
+#define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
+#define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
+#define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
+#define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
+#define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
+#define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
+#define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
+#define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
+#define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
+#define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBFSH_PORTMODE_ID_MASK                  (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT                 (0U)
+#define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+#define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
+#define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+#define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Register_Masks */
+
+
+/* USBFSH - Peripheral instance base addresses */
+/** Peripheral USBFSH base address */
+#define USBFSH_BASE                              (0x400A2000u)
+/** Peripheral USBFSH base pointer */
+#define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
+/** Array initializer of USBFSH peripheral base addresses */
+#define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
+/** Array initializer of USBFSH peripheral base pointers */
+#define USBFSH_BASE_PTRS                         { USBFSH }
+/** Interrupt vectors for the USBFSH peripheral type */
+#define USBFSH_IRQS                              { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __I  uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __I  uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ULPIDEBUG;                         /**< UTMI/ULPI debug register, offset: 0x3C */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK          (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT         (0U)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK            (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT           (7U)
+#define USBHSD_DEVCMDSTAT_DEV_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK             (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT            (8U)
+#define USBHSD_DEVCMDSTAT_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK     (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT    (9U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK        (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT       (10U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK           (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT          (11U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK       (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT      (12U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK       (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT      (13U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK       (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT      (14U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK       (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT      (15U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK              (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT             (16U)
+#define USBHSD_DEVCMDSTAT_DCON(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK              (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT             (17U)
+#define USBHSD_DEVCMDSTAT_DSUS(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK           (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT          (19U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK          (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT         (20U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_MASK             (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT            (22U)
+#define USBHSD_DEVCMDSTAT_Speed(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK            (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT           (24U)
+#define USBHSD_DEVCMDSTAT_DCON_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK            (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT           (25U)
+#define USBHSD_DEVCMDSTAT_DSUS_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK            (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT           (26U)
+#define USBHSD_DEVCMDSTAT_DRES_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK    (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT   (28U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+
+/*! @name INFO - USB Info register */
+#define USBHSD_INFO_FRAME_NR_MASK                (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT               (0U)
+#define USBHSD_INFO_FRAME_NR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK                (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT               (11U)
+#define USBHSD_INFO_ERR_CODE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_Minrev_MASK                  (0xFF0000U)
+#define USBHSD_INFO_Minrev_SHIFT                 (16U)
+#define USBHSD_INFO_Minrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
+#define USBHSD_INFO_Majrev_MASK                  (0xFF000000U)
+#define USBHSD_INFO_Majrev_SHIFT                 (24U)
+#define USBHSD_INFO_Majrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK      (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT     (8U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x)        (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK    (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT   (20U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USBHSD_DATABUFSTART_DA_BUF_MASK          (0xFFFFFFFFU)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT         (0U)
+#define USBHSD_DATABUFSTART_DA_BUF(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USBHSD_LPM_HIRD_HW_MASK                  (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT                 (0U)
+#define USBHSD_LPM_HIRD_HW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK                  (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT                 (4U)
+#define USBHSD_LPM_HIRD_SW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK             (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT            (8U)
+#define USBHSD_LPM_DATA_PENDING(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USBHSD_EPSKIP_SKIP_MASK                  (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT                 (0U)
+#define USBHSD_EPSKIP_SKIP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USBHSD_EPINUSE_BUF_MASK                  (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT                 (2U)
+#define USBHSD_EPINUSE_BUF(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK              (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT             (2U)
+#define USBHSD_EPBUFCFG_BUF_SB(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USBHSD_INTSTAT_EP0OUT_MASK               (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT              (0U)
+#define USBHSD_INTSTAT_EP0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK                (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT               (1U)
+#define USBHSD_INTSTAT_EP0IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK               (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT              (2U)
+#define USBHSD_INTSTAT_EP1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK                (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT               (3U)
+#define USBHSD_INTSTAT_EP1IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK               (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT              (4U)
+#define USBHSD_INTSTAT_EP2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK                (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT               (5U)
+#define USBHSD_INTSTAT_EP2IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK               (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT              (6U)
+#define USBHSD_INTSTAT_EP3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK                (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT               (7U)
+#define USBHSD_INTSTAT_EP3IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK               (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT              (8U)
+#define USBHSD_INTSTAT_EP4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK                (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT               (9U)
+#define USBHSD_INTSTAT_EP4IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK               (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT              (10U)
+#define USBHSD_INTSTAT_EP5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK                (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT               (11U)
+#define USBHSD_INTSTAT_EP5IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK            (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT           (30U)
+#define USBHSD_INTSTAT_FRAME_INT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK              (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT             (31U)
+#define USBHSD_INTSTAT_DEV_INT(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USBHSD_INTEN_EP_INT_EN_MASK              (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT             (0U)
+#define USBHSD_INTEN_EP_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK           (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT          (30U)
+#define USBHSD_INTEN_FRAME_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK             (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT            (31U)
+#define USBHSD_INTEN_DEV_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK        (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT       (0U)
+#define USBHSD_INTSETSTAT_EP_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK     (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT    (30U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK       (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT      (31U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK              (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT             (0U)
+#define USBHSD_EPTOGGLE_TOGGLE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+
+/*! @name ULPIDEBUG - UTMI/ULPI debug register */
+#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK           (0xFFU)
+#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT          (0U)
+#define USBHSD_ULPIDEBUG_PHY_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK          (0xFF00U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT         (8U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK          (0xFF0000U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT         (16U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RW_MASK             (0x1000000U)
+#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT            (24U)
+#define USBHSD_ULPIDEBUG_PHY_RW(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK         (0x2000000U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT        (25U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)
+#define USBHSD_ULPIDEBUG_PHY_MODE_MASK           (0x80000000U)
+#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT          (31U)
+#define USBHSD_ULPIDEBUG_PHY_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+/** Peripheral USBHSD base address */
+#define USBHSD_BASE                              (0x40094000u)
+/** Peripheral USBHSD base pointer */
+#define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
+/** Array initializer of USBHSD peripheral base addresses */
+#define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
+/** Array initializer of USBHSD peripheral base pointers */
+#define USBHSD_BASE_PTRS                         { USBHSD }
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS                              { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CAPLENGTH_CHIPID;                  /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x4 */
+  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x8 */
+  __IO uint32_t FLADJ_FRINDEX;                     /**< Frame Length Adjustment, offset: 0xC */
+  __IO uint32_t ATL_PTD_BASE_ADDR;                 /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+  __IO uint32_t ISO_PTD_BASE_ADDR;                 /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+  __IO uint32_t INT_PTD_BASE_ADDR;                 /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+  __IO uint32_t DATA_PAYLOAD_BASE_ADDR;            /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+  __IO uint32_t USBCMD;                            /**< USB Command register, offset: 0x20 */
+  __IO uint32_t USBSTS;                            /**< USB Interrupt Status register, offset: 0x24 */
+  __IO uint32_t USBINTR;                           /**< USB Interrupt Enable register, offset: 0x28 */
+  __IO uint32_t PORTSC1;                           /**< Port Status and Control register, offset: 0x2C */
+  __IO uint32_t ATL_PTD_DONE_MAP;                  /**< Done map for each ATL PTD, offset: 0x30 */
+  __IO uint32_t ATL_PTD_SKIP_MAP;                  /**< Skip map for each ATL PTD, offset: 0x34 */
+  __IO uint32_t ISO_PTD_DONE_MAP;                  /**< Done map for each ISO PTD, offset: 0x38 */
+  __IO uint32_t ISO_PTD_SKIP_MAP;                  /**< Skip map for each ISO PTD, offset: 0x3C */
+  __IO uint32_t INT_PTD_DONE_MAP;                  /**< Done map for each INT PTD, offset: 0x40 */
+  __IO uint32_t INT_PTD_SKIP_MAP;                  /**< Skip map for each INT PTD, offset: 0x44 */
+  __IO uint32_t LAST_PTD_INUSE;                    /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+  __IO uint32_t UTMIPLUS_ULPI_DEBUG;               /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK   (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT  (0U)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK      (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT     (16U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK            (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT           (0U)
+#define USBHSH_HCSPARAMS_N_PORTS(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK                (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT               (4U)
+#define USBHSH_HCSPARAMS_PPC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK        (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT       (16U)
+#define USBHSH_HCSPARAMS_P_INDICATOR(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters */
+#define USBHSH_HCCPARAMS_LPMC_MASK               (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT              (17U)
+#define USBHSH_HCCPARAMS_LPMC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK          (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT         (0U)
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK        (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT       (16U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK    (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT   (4U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK   (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT  (9U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK  (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT  (10U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK  (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT  (10U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+
+/*! @name USBCMD - USB Command register */
+#define USBHSH_USBCMD_RS_MASK                    (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT                   (0U)
+#define USBHSH_USBCMD_RS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK               (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT              (1U)
+#define USBHSH_USBCMD_HCRESET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK                   (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT                  (2U)
+#define USBHSH_USBCMD_FLS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK                  (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT                 (7U)
+#define USBHSH_USBCMD_LHCR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK                (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT               (8U)
+#define USBHSH_USBCMD_ATL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK                (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT               (9U)
+#define USBHSH_USBCMD_ISO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK                (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT               (10U)
+#define USBHSH_USBCMD_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK                  (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT                 (24U)
+#define USBHSH_USBCMD_HIRD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+#define USBHSH_USBCMD_LPM_RWU_MASK               (0x10000000U)
+#define USBHSH_USBCMD_LPM_RWU_SHIFT              (28U)
+#define USBHSH_USBCMD_LPM_RWU(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
+
+/*! @name USBSTS - USB Interrupt Status register */
+#define USBHSH_USBSTS_PCD_MASK                   (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT                  (2U)
+#define USBHSH_USBSTS_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK                   (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT                  (3U)
+#define USBHSH_USBSTS_FLR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK               (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT              (16U)
+#define USBHSH_USBSTS_ATL_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK               (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT              (17U)
+#define USBHSH_USBSTS_ISO_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK               (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT              (18U)
+#define USBHSH_USBSTS_INT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK               (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT              (19U)
+#define USBHSH_USBSTS_SOF_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+
+/*! @name USBINTR - USB Interrupt Enable register */
+#define USBHSH_USBINTR_PCDE_MASK                 (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT                (2U)
+#define USBHSH_USBINTR_PCDE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK                 (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT                (3U)
+#define USBHSH_USBINTR_FLRE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK            (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT           (16U)
+#define USBHSH_USBINTR_ATL_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK            (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT           (17U)
+#define USBHSH_USBINTR_ISO_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK            (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT           (18U)
+#define USBHSH_USBINTR_INT_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK                (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT               (19U)
+#define USBHSH_USBINTR_SOF_E(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+
+/*! @name PORTSC1 - Port Status and Control register */
+#define USBHSH_PORTSC1_CCS_MASK                  (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT                 (0U)
+#define USBHSH_PORTSC1_CCS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK                  (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT                 (1U)
+#define USBHSH_PORTSC1_CSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK                  (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT                 (2U)
+#define USBHSH_PORTSC1_PED(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK                 (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT                (3U)
+#define USBHSH_PORTSC1_PEDC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK                  (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT                 (4U)
+#define USBHSH_PORTSC1_OCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK                  (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT                 (5U)
+#define USBHSH_PORTSC1_OCC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK                  (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT                 (6U)
+#define USBHSH_PORTSC1_FPR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK                 (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT                (7U)
+#define USBHSH_PORTSC1_SUSP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK                   (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT                  (8U)
+#define USBHSH_PORTSC1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK               (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT              (9U)
+#define USBHSH_PORTSC1_SUS_L1(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK                   (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT                  (10U)
+#define USBHSH_PORTSC1_LS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK                   (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT                  (12U)
+#define USBHSH_PORTSC1_PP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK                  (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT                 (14U)
+#define USBHSH_PORTSC1_PIC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK                  (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT                 (16U)
+#define USBHSH_PORTSC1_PTC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK                 (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT                (20U)
+#define USBHSH_PORTSC1_PSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK                  (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT                 (22U)
+#define USBHSH_PORTSC1_WOO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK             (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT            (23U)
+#define USBHSH_PORTSC1_SUS_STAT(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK              (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT             (25U)
+#define USBHSH_PORTSC1_DEV_ADD(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT   (0U)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT   (0U)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT   (0U)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT   (0U)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT   (0U)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT   (0U)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+
+/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK      (0x1FU)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT     (0U)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK      (0x1F00U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT     (8U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK      (0x1F0000U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT     (16U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
+
+/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK   (0x1000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT  (24U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBHSH_PORTMODE_ID0_MASK                 (0x1U)
+#define USBHSH_PORTMODE_ID0_SHIFT                (0U)
+#define USBHSH_PORTMODE_ID0(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
+#define USBHSH_PORTMODE_ID0_EN_MASK              (0x100U)
+#define USBHSH_PORTMODE_ID0_EN_SHIFT             (8U)
+#define USBHSH_PORTMODE_ID0_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+#define USBHSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK       (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT      (18U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM_MASK            (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT           (19U)
+#define USBHSH_PORTMODE_SW_PDCOM(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+/** Peripheral USBHSH base address */
+#define USBHSH_BASE                              (0x400A3000u)
+/** Peripheral USBHSH base pointer */
+#define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
+/** Array initializer of USBHSH peripheral base addresses */
+#define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
+/** Array initializer of USBHSH peripheral base pointers */
+#define USBHSH_BASE_PTRS                         { USBHSH }
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS                              { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
+  __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+
+/*! @name STAT - Status register. */
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+
+/*! @name CFG - Capture configuration register. */
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+
+/*! @name CAPCLR - Capture clear register. */
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+
+/*! @name CAP - Capture register . */
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+  __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+  __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+
+/*! @name WINDOW - Watchdog Window compare value. */
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE                                (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT                                     ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS                                { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** EMC CS base address */
+#define EMC_CS0_BASE                                (0x80000000u)
+#define EMC_CS1_BASE                                (0x90000000u)
+#define EMC_CS2_BASE                                (0x98000000u)
+#define EMC_CS3_BASE                                (0x9C000000u)
+#define EMC_DYCS0_BASE                              (0xA0000000u)
+#define EMC_DYCS1_BASE                              (0xB0000000u)
+#define EMC_DYCS2_BASE                              (0xC0000000u)
+#define EMC_DYCS3_BASE                              (0xD0000000u)
+#define EMC_CS_ADDRESS                              {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
+#define EMC_DYCS_ADDRESS                            {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
+
+/** OTP API */
+typedef struct {
+  uint32_t (*otpInit)(void);                                    /** Initializes OTP controller */
+  uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask);        /** Unlock one or more OTP banks for write access */
+  uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask);       /** Lock one or more OTP banks for write access */
+  uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                          uint32_t lockWrite);  /** Locks or unlocks write access to a register of an OTP bank and the write lock */
+  uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                         uint32_t lockWrite);   /** Locks or unlocks read access to a register of an OTP bank and the write lock */
+  uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value);  /** Program a single register in an OTP bank */
+  uint32_t RESERVED_0[5];
+  uint32_t (*rngRead)(void);                                    /** Returns 32-bit number from hardware random number generator */
+  uint32_t (*otpGetDriverVersion)(void);                        /** Returns the version of the OTP driver in ROM */
+} OTP_API_Type;
+
+/** ROM API */
+typedef struct {
+  __I uint32_t usbdApiBase;                      /** USB API Base */
+      uint32_t RESERVED_0[13];
+  __I OTP_API_Type *otpApiBase;                  /** OTP API Base */
+  __I uint32_t aesApiBase;                       /** AES API Base */
+  __I uint32_t secureApiBase;                    /** Secure API Base */
+} ROM_API_Type;
+
+/** ROM API base address */
+#define ROM_API_BASE                             (0x03000200u)
+/** ROM API base pointer */
+#define ROM_API                                  (*(ROM_API_Type**) ROM_API_BASE)
+/** OTP API base pointer */
+#define OTP_API                                  (ROM_API->otpApiBase)
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _LPC54618_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,231 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170112
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54618_FEATURES_H_
+#define _LPC54618_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (10)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief EEPROM availability on the SoC. */
+#define FSL_FEATURE_SOC_EEPROM_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief LCD availability on the SoC. */
+#define FSL_FEATURE_SOC_LCD_COUNT (1)
+/* @brief CAN availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (0)
+/* @brief AES availability on the SoC. */
+#define FSL_FEATURE_SOC_AES_COUNT (0)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (1)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+
+/* CAN module features */
+
+/* @brief Support CANFD or not */
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+
+/* EEPROM module features */
+
+/* @brief Size of the EEPROM */
+#define FSL_FEATURE_EEPROM_SIZE (0x00004000)
+/* @brief Base address of the EEPROM */
+#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000)
+/* @brief Page count of the EEPROM */
+#define FSL_FEATURE_EEPROM_PAGE_COUNT (128)
+/* @brief Command number for eeprom program */
+#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6)
+/* @brief EEPROM internal clock freqency */
+#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+
+#endif /* _LPC54618_FEATURES_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,121 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+#define __ram_vector_table__            1
+
+#if (defined(__ram_vector_table__))
+  #define __ram_vector_table_size__    0x00000400
+#else
+  #define __ram_vector_table_size__    0x00000000
+#endif
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x00000400
+#define m_text_size                    0x0007FC00
+
+#define m_interrupts_ram_start         0x20000000
+#define m_interrupts_ram_size          __ram_vector_table_size__
+
+#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size                    (0x00028000 - m_interrupts_ram_size)
+
+#define m_usb_sram_start               0x40100000
+#define m_usb_sram_size                0x00002000
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__ram_vector_table__))
+  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+  }
+#else
+  VECTOR_RAM m_interrupts_start EMPTY 0 {
+  }
+#endif
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  RW_IRAM1 +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}
+
+LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
+  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (m_usb_bdt)
+  }
+}
+
+LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
+  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (m_usb_global)
+  }
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,713 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54618.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *           LPC54618
+; * @version: 1.1
+; * @date:    2016-11-25
+; *
+; * Copyright 1997 - 2016 Freescale Semiconductor, Inc.
+; * Copyright 2016 - 2017 NXP
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of the copyright holder nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemManage_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+__vector_table_0x1c
+                DCD     0                         ; Checksum of the first 7 words
+                DCD     0xFFFFFFFF                ; ECRP
+                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
+                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
+                DCD     SVC_Handler
+                DCD     DebugMon_Handler
+                DCD     0
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+                ; External Interrupts
+                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+                DCD     DMA0_IRQHandler  ; DMA controller
+                DCD     GINT0_IRQHandler  ; GPIO group 0
+                DCD     GINT1_IRQHandler  ; GPIO group 1
+                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+                DCD     MRT0_IRQHandler  ; Multi-rate timer
+                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+                DCD     SCT0_IRQHandler  ; SCTimer/PWM
+                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+                DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+                DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+                DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+                DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+                DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+                DCD     USB0_IRQHandler  ; USB device
+                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+                DCD     Reserved46_IRQHandler  ; Reserved interrupt
+                DCD     Reserved47_IRQHandler  ; Reserved interrupt
+                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+                DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
+                DCD     SPIFI0_IRQHandler  ; SPI flash interface
+                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+                DCD     SDIO_IRQHandler  ; SD/MMC
+                DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
+                DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
+                DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
+                DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
+                DCD     USB1_IRQHandler  ; USB1 interrupt
+                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
+                DCD     ETHERNET_IRQHandler  ; Ethernet
+                DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
+                DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
+                DCD     EEPROM_IRQHandler  ; EEPROM interrupt
+                DCD     LCD_IRQHandler  ; LCD interrupt
+                DCD     SHA_IRQHandler  ; SHA interrupt
+                DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
+                DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler               [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__main
+                BX      r0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler \
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+
+MemManage_Handler     PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+
+BusFault_Handler PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+
+UsageFault_Handler PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+WDT_BOD_IRQHandler\
+                PROC
+                EXPORT     WDT_BOD_IRQHandler        [WEAK]
+                LDR        R0, =WDT_BOD_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMA0_IRQHandler\
+                PROC
+                EXPORT     DMA0_IRQHandler        [WEAK]
+                LDR        R0, =DMA0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT0_IRQHandler\
+                PROC
+                EXPORT     GINT0_IRQHandler        [WEAK]
+                LDR        R0, =GINT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT1_IRQHandler\
+                PROC
+                EXPORT     GINT1_IRQHandler        [WEAK]
+                LDR        R0, =GINT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT0_IRQHandler\
+                PROC
+                EXPORT     PIN_INT0_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT1_IRQHandler\
+                PROC
+                EXPORT     PIN_INT1_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT2_IRQHandler\
+                PROC
+                EXPORT     PIN_INT2_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT3_IRQHandler\
+                PROC
+                EXPORT     PIN_INT3_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+UTICK0_IRQHandler\
+                PROC
+                EXPORT     UTICK0_IRQHandler        [WEAK]
+                LDR        R0, =UTICK0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+MRT0_IRQHandler\
+                PROC
+                EXPORT     MRT0_IRQHandler        [WEAK]
+                LDR        R0, =MRT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER0_IRQHandler\
+                PROC
+                EXPORT     CTIMER0_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER1_IRQHandler\
+                PROC
+                EXPORT     CTIMER1_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SCT0_IRQHandler\
+                PROC
+                EXPORT     SCT0_IRQHandler        [WEAK]
+                LDR        R0, =SCT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER3_IRQHandler\
+                PROC
+                EXPORT     CTIMER3_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM0_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM1_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM2_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM3_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM4_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM5_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM6_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM7_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQA_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQA_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQA_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQB_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQB_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQB_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_THCMP_IRQHandler\
+                PROC
+                EXPORT     ADC0_THCMP_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_THCMP_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMIC0_IRQHandler\
+                PROC
+                EXPORT     DMIC0_IRQHandler        [WEAK]
+                LDR        R0, =DMIC0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+HWVAD0_IRQHandler\
+                PROC
+                EXPORT     HWVAD0_IRQHandler        [WEAK]
+                LDR        R0, =HWVAD0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_NEEDCLK_IRQHandler\
+                PROC
+                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
+                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_IRQHandler\
+                PROC
+                EXPORT     USB0_IRQHandler        [WEAK]
+                LDR        R0, =USB0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+RTC_IRQHandler\
+                PROC
+                EXPORT     RTC_IRQHandler        [WEAK]
+                LDR        R0, =RTC_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Reserved46_IRQHandler\
+                PROC
+                EXPORT     Reserved46_IRQHandler        [WEAK]
+                LDR        R0, =Reserved46_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Reserved47_IRQHandler\
+                PROC
+                EXPORT     Reserved47_IRQHandler        [WEAK]
+                LDR        R0, =Reserved47_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT4_IRQHandler\
+                PROC
+                EXPORT     PIN_INT4_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT5_IRQHandler\
+                PROC
+                EXPORT     PIN_INT5_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT6_IRQHandler\
+                PROC
+                EXPORT     PIN_INT6_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT7_IRQHandler\
+                PROC
+                EXPORT     PIN_INT7_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER2_IRQHandler\
+                PROC
+                EXPORT     CTIMER2_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER4_IRQHandler\
+                PROC
+                EXPORT     CTIMER4_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+RIT_IRQHandler\
+                PROC
+                EXPORT     RIT_IRQHandler        [WEAK]
+                LDR        R0, =RIT_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SPIFI0_IRQHandler\
+                PROC
+                EXPORT     SPIFI0_IRQHandler        [WEAK]
+                LDR        R0, =SPIFI0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM8_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM8_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM9_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM9_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM9_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SDIO_IRQHandler\
+                PROC
+                EXPORT     SDIO_IRQHandler        [WEAK]
+                LDR        R0, =SDIO_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN0_IRQ0_IRQHandler\
+                PROC
+                EXPORT     CAN0_IRQ0_IRQHandler        [WEAK]
+                LDR        R0, =CAN0_IRQ0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN0_IRQ1_IRQHandler\
+                PROC
+                EXPORT     CAN0_IRQ1_IRQHandler        [WEAK]
+                LDR        R0, =CAN0_IRQ1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN1_IRQ0_IRQHandler\
+                PROC
+                EXPORT     CAN1_IRQ0_IRQHandler        [WEAK]
+                LDR        R0, =CAN1_IRQ0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN1_IRQ1_IRQHandler\
+                PROC
+                EXPORT     CAN1_IRQ1_IRQHandler        [WEAK]
+                LDR        R0, =CAN1_IRQ1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB1_IRQHandler\
+                PROC
+                EXPORT     USB1_IRQHandler        [WEAK]
+                LDR        R0, =USB1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB1_NEEDCLK_IRQHandler\
+                PROC
+                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
+                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_PMT_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_PMT_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_PMT_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_MACLP_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_MACLP_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_MACLP_DriverIRQHandler
+                BX         R0
+                ENDP
+
+EEPROM_IRQHandler\
+                PROC
+                EXPORT     EEPROM_IRQHandler        [WEAK]
+                LDR        R0, =EEPROM_DriverIRQHandler
+                BX         R0
+                ENDP
+
+LCD_IRQHandler\
+                PROC
+                EXPORT     LCD_IRQHandler        [WEAK]
+                LDR        R0, =LCD_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SHA_IRQHandler\
+                PROC
+                EXPORT     SHA_IRQHandler        [WEAK]
+                LDR        R0, =SHA_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SMARTCARD0_IRQHandler\
+                PROC
+                EXPORT     SMARTCARD0_IRQHandler        [WEAK]
+                LDR        R0, =SMARTCARD0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SMARTCARD1_IRQHandler\
+                PROC
+                EXPORT     SMARTCARD1_IRQHandler        [WEAK]
+                LDR        R0, =SMARTCARD1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Default_Handler PROC
+                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
+                EXPORT     DMA0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
+                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
+                EXPORT     MRT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
+                EXPORT     SCT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQA_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQB_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_THCMP_DriverIRQHandler        [WEAK]
+                EXPORT     DMIC0_DriverIRQHandler        [WEAK]
+                EXPORT     HWVAD0_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_DriverIRQHandler        [WEAK]
+                EXPORT     RTC_DriverIRQHandler        [WEAK]
+                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
+                EXPORT     Reserved47_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
+                EXPORT     RIT_DriverIRQHandler        [WEAK]
+                EXPORT     SPIFI0_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM9_DriverIRQHandler        [WEAK]
+                EXPORT     SDIO_DriverIRQHandler        [WEAK]
+                EXPORT     CAN0_IRQ0_DriverIRQHandler        [WEAK]
+                EXPORT     CAN0_IRQ1_DriverIRQHandler        [WEAK]
+                EXPORT     CAN1_IRQ0_DriverIRQHandler        [WEAK]
+                EXPORT     CAN1_IRQ1_DriverIRQHandler        [WEAK]
+                EXPORT     USB1_DriverIRQHandler        [WEAK]
+                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_PMT_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_MACLP_DriverIRQHandler        [WEAK]
+                EXPORT     EEPROM_DriverIRQHandler        [WEAK]
+                EXPORT     LCD_DriverIRQHandler        [WEAK]
+                EXPORT     SHA_DriverIRQHandler        [WEAK]
+                EXPORT     SMARTCARD0_DriverIRQHandler        [WEAK]
+                EXPORT     SMARTCARD1_DriverIRQHandler        [WEAK]
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+                END
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+**     Processors:          LPC54618J512
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    LPC54618 Series Reference Manual, Rev. 0 , 06/2017
+**     Version:             rev. 1.0, 2017-6-06
+**     Build:               b161214
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     1. Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     2. Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     3. Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+__ram_vector_table__ = 1;
+
+__stack_size__ = 0x8000;
+__heap_size__ = 0xC000;
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0;
+
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0007FC00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00028000
+  m_sramx               (RW)  : ORIGIN = 0x04000000, LENGTH = 0x00008000
+  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00002000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.ramfunc*)             /* for functions in ram */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  m_usb_bdt (NOLOAD) :
+  {
+    . = ALIGN(512);
+    *(m_usb_bdt)
+  } > m_usb_sram
+
+  m_usb_global (NOLOAD) :
+  {
+    *(m_usb_global)
+  } > m_usb_sram
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,863 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_LPC54618.S                                                          */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            LPC54618                                                                    */
+/*  @version: 1.0                                                                         */
+/*  @date:    2017-6-6                                                                    */
+/*  @build:   b161214                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                                      */
+/* Copyright 2016-2017 NXP                                                                */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* 1. Redistributions of source code must retain the above copyright notice, this list    */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* 2. Redistributions in binary form must reproduce the above copyright notice, this      */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* 3. Neither the name of the copyright holder nor the names of its                       */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler */
+    .long   HardFault_Handler                               /* Hard Fault Handler */
+    .long   MemManage_Handler                               /* MPU Fault Handler */
+    .long   BusFault_Handler                                /* Bus Fault Handler */
+    .long   UsageFault_Handler                              /* Usage Fault Handler */
+    .long   0                                               /* Reserved */
+    .long   0xFFFFFFFF                                      /* ECRP */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   SVC_Handler                                     /* SVCall Handler */
+    .long   DebugMon_Handler                                /* Debug Monitor Handler */
+    .long   0
+    .long   PendSV_Handler                                  /* PendSV Handler */
+    .long   SysTick_Handler                                 /* SysTick Handler */
+
+     /* External Interrupts */
+    .long   WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect */
+    .long   DMA0_IRQHandler                                 /* DMA controller */
+    .long   GINT0_IRQHandler                                /* GPIO group 0 */
+    .long   GINT1_IRQHandler                                /* GPIO group 1 */
+    .long   PIN_INT0_IRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long   PIN_INT1_IRQHandler                             /* Pin interrupt 1 or pattern match engine slice 1 */
+    .long   PIN_INT2_IRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long   PIN_INT3_IRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long   UTICK0_IRQHandler                               /* Micro-tick Timer */
+    .long   MRT0_IRQHandler                                 /* Multi-rate timer */
+    .long   CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long   CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long   SCT0_IRQHandler                                 /* SCTimer/PWM */
+    .long   CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long   FLEXCOMM0_IRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM1_IRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM2_IRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM3_IRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM4_IRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM5_IRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+    .long   FLEXCOMM6_IRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   FLEXCOMM7_IRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   ADC0_SEQA_IRQHandler                            /* ADC0 sequence A completion. */
+    .long   ADC0_SEQB_IRQHandler                            /* ADC0 sequence B completion. */
+    .long   ADC0_THCMP_IRQHandler                           /* ADC0 threshold compare and error. */
+    .long   DMIC0_IRQHandler                                /* Digital microphone and DMIC subsystem */
+    .long   HWVAD0_IRQHandler                               /* Hardware Voice Activity Detector */
+    .long   USB0_NEEDCLK_IRQHandler                         /* USB Activity Wake-up Interrupt */
+    .long   USB0_IRQHandler                                 /* USB device */
+    .long   RTC_IRQHandler                                  /* RTC alarm and wake-up interrupts */
+    .long   0                                               /* Reserved interrupt */
+    .long   0                                               /* Reserved interrupt */
+    .long   PIN_INT4_IRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long   PIN_INT5_IRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long   PIN_INT6_IRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long   PIN_INT7_IRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long   CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long   CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long   RIT_IRQHandler                                  /* Repetitive Interrupt Timer */
+    .long   SPIFI0_IRQHandler                               /* SPI flash interface */
+    .long   FLEXCOMM8_IRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM9_IRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+    .long   SDIO_IRQHandler                                 /* SD/MMC */
+    .long   CAN0_IRQ0_IRQHandler                            /* CAN0 interrupt0 */
+    .long   CAN0_IRQ1_IRQHandler                            /* CAN0 interrupt1 */
+    .long   CAN1_IRQ0_IRQHandler                            /* CAN1 interrupt0 */
+    .long   CAN1_IRQ1_IRQHandler                            /* CAN1 interrupt1 */
+    .long   USB1_IRQHandler                                 /* USB1 interrupt */
+    .long   USB1_NEEDCLK_IRQHandler                         /* USB1 activity */
+    .long   ETHERNET_IRQHandler                             /* Ethernet */
+    .long   ETHERNET_PMT_IRQHandler                         /* Ethernet power management interrupt */
+    .long   ETHERNET_MACLP_IRQHandler                       /* Ethernet MAC interrupt */
+    .long   EEPROM_IRQHandler                               /* EEPROM interrupt */
+    .long   LCD_IRQHandler                                  /* LCD interrupt */
+    .long   SHA_IRQHandler                                  /* SHA interrupt */
+    .long   SMARTCARD0_IRQHandler                           /* Smart card 0 interrupt */
+    .long   SMARTCARD1_IRQHandler                           /* Smart card 1 interrupt */
+    .size   __Vectors, . - __Vectors
+
+
+    
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+
+    /*      Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      __etext: End of code section, i.e., begin of data sections to copy from.
+     *      __data_start__/__data_end__: RAM address range that data should be
+     *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#else
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#endif
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    movs    r0, 0
+.LC2:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC2
+#endif /* __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak MemManage_Handler
+    .type MemManage_Handler, %function
+MemManage_Handler:
+    ldr   r0,=MemManage_Handler
+    bx    r0
+    .size MemManage_Handler, . - MemManage_Handler
+
+    .align 1
+    .thumb_func
+    .weak BusFault_Handler
+    .type BusFault_Handler, %function
+BusFault_Handler:
+    ldr   r0,=BusFault_Handler
+    bx    r0
+    .size BusFault_Handler, . - BusFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak UsageFault_Handler
+    .type UsageFault_Handler, %function
+UsageFault_Handler:
+    ldr   r0,=UsageFault_Handler
+    bx    r0
+    .size UsageFault_Handler, . - UsageFault_Handler
+    
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak DebugMon_Handler
+    .type DebugMon_Handler, %function
+DebugMon_Handler:
+    ldr   r0,=DebugMon_Handler
+    bx    r0
+    .size DebugMon_Handler, . - DebugMon_Handler
+    
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQA_IRQHandler
+    .type ADC0_SEQA_IRQHandler, %function
+ADC0_SEQA_IRQHandler:
+    ldr   r0,=ADC0_SEQA_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQB_IRQHandler
+    .type ADC0_SEQB_IRQHandler, %function
+ADC0_SEQB_IRQHandler:
+    ldr   r0,=ADC0_SEQB_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_THCMP_IRQHandler
+    .type ADC0_THCMP_IRQHandler, %function
+ADC0_THCMP_IRQHandler:
+    ldr   r0,=ADC0_THCMP_DriverIRQHandler
+    bx    r0
+    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMIC0_IRQHandler
+    .type DMIC0_IRQHandler, %function
+DMIC0_IRQHandler:
+    ldr   r0,=DMIC0_DriverIRQHandler
+    bx    r0
+    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HWVAD0_IRQHandler
+    .type HWVAD0_IRQHandler, %function
+HWVAD0_IRQHandler:
+    ldr   r0,=HWVAD0_DriverIRQHandler
+    bx    r0
+    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RIT_IRQHandler
+    .type RIT_IRQHandler, %function
+RIT_IRQHandler:
+    ldr   r0,=RIT_DriverIRQHandler
+    bx    r0
+    .size RIT_IRQHandler, . - RIT_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SPIFI0_IRQHandler
+    .type SPIFI0_IRQHandler, %function
+SPIFI0_IRQHandler:
+    ldr   r0,=SPIFI0_DriverIRQHandler
+    bx    r0
+    .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler
+ 
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM9_IRQHandler
+    .type FLEXCOMM9_IRQHandler, %function
+FLEXCOMM9_IRQHandler:
+    ldr   r0,=FLEXCOMM9_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ0_IRQHandler
+    .type CAN0_IRQ0_IRQHandler, %function
+CAN0_IRQ0_IRQHandler:
+    ldr   r0,=CAN0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ1_IRQHandler
+    .type CAN0_IRQ1_IRQHandler, %function
+CAN0_IRQ1_IRQHandler:
+    ldr   r0,=CAN0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ0_IRQHandler
+    .type CAN1_IRQ0_IRQHandler, %function
+CAN1_IRQ0_IRQHandler:
+    ldr   r0,=CAN1_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ1_IRQHandler
+    .type CAN1_IRQ1_IRQHandler, %function
+CAN1_IRQ1_IRQHandler:
+    ldr   r0,=CAN1_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_IRQHandler
+    .type ETHERNET_IRQHandler, %function
+ETHERNET_IRQHandler:
+    ldr   r0,=ETHERNET_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_PMT_IRQHandler
+    .type ETHERNET_PMT_IRQHandler, %function
+ETHERNET_PMT_IRQHandler:
+    ldr   r0,=ETHERNET_PMT_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_MACLP_IRQHandler
+    .type ETHERNET_MACLP_IRQHandler, %function
+ETHERNET_MACLP_IRQHandler:
+    ldr   r0,=ETHERNET_MACLP_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak EEPROM_IRQHandler
+    .type EEPROM_IRQHandler, %function
+EEPROM_IRQHandler:
+    ldr   r0,=EEPROM_DriverIRQHandler
+    bx    r0
+    .size EEPROM_IRQHandler, . - EEPROM_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak LCD_IRQHandler
+    .type LCD_IRQHandler, %function
+LCD_IRQHandler:
+    ldr   r0,=LCD_DriverIRQHandler
+    bx    r0
+    .size LCD_IRQHandler, . - LCD_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SHA_IRQHandler
+    .type SHA_IRQHandler, %function
+SHA_IRQHandler:
+    ldr   r0,=SHA_DriverIRQHandler
+    bx    r0
+    .size SHA_IRQHandler, . - SHA_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SMARTCARD0_IRQHandler
+    .type SMARTCARD0_IRQHandler, %function
+SMARTCARD0_IRQHandler:
+    ldr   r0,=SMARTCARD0_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SMARTCARD1_IRQHandler
+    .type SMARTCARD1_IRQHandler, %function
+SMARTCARD1_IRQHandler:
+    ldr   r0,=SMARTCARD1_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler
+    
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler   WDT_BOD_DriverIRQHandler                              /* Windowed watchdog timer, Brownout detect */
+    def_irq_handler   DMA0_DriverIRQHandler                                 /* DMA controller */
+    def_irq_handler   GINT0_DriverIRQHandler                                /* GPIO group 0 */
+    def_irq_handler   GINT1_DriverIRQHandler                                /* GPIO group 1 */
+    def_irq_handler   PIN_INT0_DriverIRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler   PIN_INT1_DriverIRQHandler                             /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler   PIN_INT2_DriverIRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler   PIN_INT3_DriverIRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler   UTICK0_DriverIRQHandler                               /* Micro-tick Timer */
+    def_irq_handler   MRT0_DriverIRQHandler                                 /* Multi-rate timer */
+    def_irq_handler   CTIMER0_DriverIRQHandler                              /* Standard counter/timer CTIMER0 */
+    def_irq_handler   CTIMER1_DriverIRQHandler                              /* Standard counter/timer CTIMER1 */
+    def_irq_handler   SCT0_DriverIRQHandler                                 /* SCTimer/PWM */
+    def_irq_handler   CTIMER3_DriverIRQHandler                              /* Standard counter/timer CTIMER3 */
+    def_irq_handler   FLEXCOMM0_DriverIRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM1_DriverIRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM2_DriverIRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM3_DriverIRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM4_DriverIRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM5_DriverIRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM6_DriverIRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM7_DriverIRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    def_irq_handler   ADC0_SEQA_DriverIRQHandler                            /* ADC0 sequence A completion. */
+    def_irq_handler   ADC0_SEQB_DriverIRQHandler                            /* ADC0 sequence B completion. */
+    def_irq_handler   ADC0_THCMP_DriverIRQHandler                           /* ADC0 threshold compare and error. */
+    def_irq_handler   DMIC0_DriverIRQHandler                                /* Digital microphone and DMIC subsystem */
+    def_irq_handler   HWVAD0_DriverIRQHandler                               /* Hardware Voice Activity Detector */
+    def_irq_handler   USB0_NEEDCLK_DriverIRQHandler                         /* USB Activity Wake-up Interrupt */
+    def_irq_handler   USB0_DriverIRQHandler                                 /* USB device */
+    def_irq_handler   RTC_DriverIRQHandler                                  /* RTC alarm and wake-up interrupts */
+    def_irq_handler   Reserved46_DriverIRQHandler                           /* Reserved interrupt */
+    def_irq_handler   Reserved47_DriverIRQHandler                           /* Reserved interrupt */
+    def_irq_handler   PIN_INT4_DriverIRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler   PIN_INT5_DriverIRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler   PIN_INT6_DriverIRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler   PIN_INT7_DriverIRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler   CTIMER2_DriverIRQHandler                              /* Standard counter/timer CTIMER2 */
+    def_irq_handler   CTIMER4_DriverIRQHandler                              /* Standard counter/timer CTIMER4 */
+    def_irq_handler   RIT_DriverIRQHandler                                  /* Repetitive Interrupt Timer */
+    def_irq_handler   SPIFI0_DriverIRQHandler                               /* SPI flash interface */
+    def_irq_handler   FLEXCOMM8_DriverIRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM9_DriverIRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   SDIO_DriverIRQHandler                                 /* SD/MMC */
+    def_irq_handler   CAN0_IRQ0_DriverIRQHandler                            /* CAN0 interrupt0 */
+    def_irq_handler   CAN0_IRQ1_DriverIRQHandler                            /* CAN0 interrupt1 */
+    def_irq_handler   CAN1_IRQ0_DriverIRQHandler                            /* CAN1 interrupt0 */
+    def_irq_handler   CAN1_IRQ1_DriverIRQHandler                            /* CAN1 interrupt1 */
+    def_irq_handler   USB1_DriverIRQHandler                                 /* USB1 interrupt */
+    def_irq_handler   USB1_NEEDCLK_DriverIRQHandler                         /* USB1 activity */
+    def_irq_handler   ETHERNET_DriverIRQHandler                             /* Ethernet */
+    def_irq_handler   ETHERNET_PMT_DriverIRQHandler                         /* Ethernet power management interrupt */
+    def_irq_handler   ETHERNET_MACLP_DriverIRQHandler                       /* Ethernet MAC interrupt */
+    def_irq_handler   EEPROM_DriverIRQHandler                               /* EEPROM interrupt */
+    def_irq_handler   LCD_DriverIRQHandler                                  /* LCD interrupt */
+    def_irq_handler   SHA_DriverIRQHandler                                  /* SHA interrupt */
+    def_irq_handler   SMARTCARD0_DriverIRQHandler                           /* Smart card 0 interrupt */
+    def_irq_handler   SMARTCARD1_DriverIRQHandler                           /* Smart card 1 interrupt */
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,123 @@
+/*
+** ###################################################################
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+define symbol __ram_vector_table__ = 1;
+
+define symbol __stack_size__=0x8000;
+define symbol __heap_size__=0xC000;
+
+define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
+define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_interrupts_ram_start   = 0x20000000;
+define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE  = m_interrupts_start;
+define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
+place in m_interrupts_ram_region            { section m_interrupts_ram };
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,615 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54618.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+; *           LPC54618
+; * @version: 1.1
+; * @date:    2016-11-25
+; *----------------------------------------------------------------------------
+; *
+; * Copyright 1997 - 2016 Freescale Semiconductor.
+; * Copyright 2016 - 2017 NXP
+; *
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of the copyright holder nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0xFFFFFFFF ;ECRP
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler  ; DMA controller
+        DCD     GINT0_IRQHandler  ; GPIO group 0
+        DCD     GINT1_IRQHandler  ; GPIO group 1
+        DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+        DCD     MRT0_IRQHandler  ; Multi-rate timer
+        DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler  ; SCTimer/PWM
+        DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler  ; USB device
+        DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler  ; Reserved interrupt
+        DCD     Reserved47_IRQHandler  ; Reserved interrupt
+        DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler  ; SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler  ; SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
+        DCD     USB1_IRQHandler  ; USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
+        DCD     ETHERNET_IRQHandler  ; Ethernet
+        DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler  ; EEPROM interrupt
+        DCD     LCD_IRQHandler  ; LCD interrupt
+        DCD     SHA_IRQHandler  ; SHA interrupt
+        DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__iar_program_start
+                BX      r0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC54608 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "fsl_device_registers.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+extern uint32_t Image$$VECTOR_RAM$$Base[];
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+extern uint32_t __VECTOR_RAM[];
+#endif
+
+/* Symbols defined by the linker script */
+#define NVIC_NUM_VECTORS        (16 + 57)         // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180))
+
+#define LPC54618_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54618.h"
+/* CPU specific feature definitions */
+#include "LPC54618_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,361 @@
+/*
+** ###################################################################
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170214
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54618
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief Device specific configuration file for LPC54618 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_MDEC_VAL_P (0)                                       /* MDEC is in bits  16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0)                                       /* PDEC is in bits  6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+    }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FF:
+            n = 0;
+            break;
+        case 0x302:
+            n = 1;
+            break;
+        case 0x202:
+            n = 2;
+            break;
+        default:
+            x = 0x080;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+    return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7F:
+            p = 0;
+            break;
+        case 0x62:
+            p = 1;
+            break;
+        case 0x42:
+            p = 2;
+            break;
+        default:
+            x = 0x10;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+    return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFF:
+            m = 0;
+            break;
+        case 0x18003:
+            m = 1;
+            break;
+        case 0x10003:
+            m = 2;
+            break;
+        default:
+            x = 0x04000;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+    return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FF);
+        if (preDiv == 0)
+        {
+            preDiv = 1;
+        }
+    }
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
+        if (postDiv == 0)
+        {
+            postDiv = 2;
+        }
+    }
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFF);
+    if (mMult == 0)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+    extern void(*const g_pfnVectors[]) (void);
+    SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+    extern void *__Vectors;
+    SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+    SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+  SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    uint64_t workRate;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+                    if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
+                    {
+                        clkRate = CLK_FRO_96MHZ;
+                    }
+                    else
+                    {
+                        clkRate = CLK_FRO_48MHZ;
+                    }
+                    break;
+            }
+            break;
+        case 0x02: /* System PLL clock (pll_clk)*/
+            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLK_RTC_32K_CLK;
+                    break;
+                default:
+                    break;
+            }
+            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+
+                /* MDEC used for rate */
+                workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+                clkRate = workRate / ((uint64_t)postdiv);
+                clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLK_RTC_32K_CLK;
+            break;
+        default:
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,121 @@
+/*
+** ###################################################################
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54618
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief Device specific configuration file for LPC54618 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54618_H_
+#define _SYSTEM_LPC54618_H_                      /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                            0u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC54618_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc.h"
+#include "fsl_clock.h"
+
+static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+static uint32_t ADC_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
+    {
+        if (s_adcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_adcBases));
+
+    return instance;
+}
+
+void ADC_Init(ADC_Type *base, const adc_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32 = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable clock. */
+    CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable the interrupts. */
+    base->INTEN = 0U; /* Quickly disable all the interrupts. */
+
+    /* Configure the ADC block. */
+    tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
+
+    /* Async or Sync clock mode. */
+    switch (config->clockMode)
+    {
+        case kADC_ClockAsynchronousMode:
+            tmp32 |= ADC_CTRL_ASYNMODE_MASK;
+            break;
+        default: /* kADC_ClockSynchronousMode */
+            break;
+    }
+
+    /* Resolution. */
+    tmp32 |= ADC_CTRL_RESOL(config->resolution);
+
+    /* Bypass calibration. */
+    if (config->enableBypassCalibration)
+    {
+        tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
+    }
+
+    /* Sample time clock count. */
+    tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
+
+    base->CTRL = tmp32;
+}
+
+void ADC_GetDefaultConfig(adc_config_t *config)
+{
+    config->clockMode = kADC_ClockSynchronousMode;
+    config->clockDividerNumber = 0U;
+    config->resolution = kADC_Resolution12bit;
+    config->enableBypassCalibration = false;
+    config->sampleTimeNumber = 0U;
+}
+
+void ADC_Deinit(ADC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+bool ADC_DoSelfCalibration(ADC_Type *base)
+{
+    uint32_t i;
+
+    /* Enable the converter. */
+    /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
+       This bit should be set after at least 10 ms after the ADC is powered on. */
+    base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
+    for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
+    {
+        __ASM("NOP");
+    }
+    if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
+    {
+        return false; /* ADC is not powered up. */
+    }
+
+    /* If not in by-pass mode, do the calibration. */
+    if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
+        (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
+    {
+        /* Calibration is needed, do it now. */
+        base->CALIB = ADC_CALIB_CALIB_MASK;
+        i = 0xF0000;
+        while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
+        {
+        }
+        if (i == 0U)
+        {
+            return false; /* Calibration timeout. */
+        }
+    }
+
+    /* A dummy conversion cycle will be performed. */
+    base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
+    i = 0x7FFFF;
+    while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
+    {
+    }
+    if (i == 0U)
+    {
+        return false;
+    }
+
+    return true;
+}
+
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityNegativeEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[0] = tmp32;
+}
+
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityPositiveEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[1] = tmp32;
+}
+
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
+{
+    assert(info != NULL);
+    assert(channel < ADC_DAT_COUNT);
+
+    uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
+
+    if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
+
+    return true;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,664 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC_H__
+#define __FSL_ADC_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_adc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief ADC driver version 2.0.0. */
+#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief Flags
+ */
+enum _adc_status_flags
+{
+    kADC_ThresholdCompareFlagOnChn0 = 1U << 0U,   /*!< Threshold comparison event on Channel 0. */
+    kADC_ThresholdCompareFlagOnChn1 = 1U << 1U,   /*!< Threshold comparison event on Channel 1. */
+    kADC_ThresholdCompareFlagOnChn2 = 1U << 2U,   /*!< Threshold comparison event on Channel 2. */
+    kADC_ThresholdCompareFlagOnChn3 = 1U << 3U,   /*!< Threshold comparison event on Channel 3. */
+    kADC_ThresholdCompareFlagOnChn4 = 1U << 4U,   /*!< Threshold comparison event on Channel 4. */
+    kADC_ThresholdCompareFlagOnChn5 = 1U << 5U,   /*!< Threshold comparison event on Channel 5. */
+    kADC_ThresholdCompareFlagOnChn6 = 1U << 6U,   /*!< Threshold comparison event on Channel 6. */
+    kADC_ThresholdCompareFlagOnChn7 = 1U << 7U,   /*!< Threshold comparison event on Channel 7. */
+    kADC_ThresholdCompareFlagOnChn8 = 1U << 8U,   /*!< Threshold comparison event on Channel 8. */
+    kADC_ThresholdCompareFlagOnChn9 = 1U << 9U,   /*!< Threshold comparison event on Channel 9. */
+    kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
+    kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
+    kADC_OverrunFlagForChn0 =
+        1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
+    kADC_OverrunFlagForChn1 =
+        1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
+    kADC_OverrunFlagForChn2 =
+        1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
+    kADC_OverrunFlagForChn3 =
+        1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
+    kADC_OverrunFlagForChn4 =
+        1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
+    kADC_OverrunFlagForChn5 =
+        1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
+    kADC_OverrunFlagForChn6 =
+        1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
+    kADC_OverrunFlagForChn7 =
+        1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
+    kADC_OverrunFlagForChn8 =
+        1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
+    kADC_OverrunFlagForChn9 =
+        1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
+    kADC_OverrunFlagForChn10 =
+        1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
+    kADC_OverrunFlagForChn11 =
+        1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
+    kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
+    kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
+    kADC_ConvSeqAInterruptFlag = 1U << 28U,    /*!< Sequence A interrupt/DMA trigger. */
+    kADC_ConvSeqBInterruptFlag = 1U << 29U,    /*!< Sequence B interrupt/DMA trigger. */
+    kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
+    kADC_OverrunInterruptFlag = 1U << 31U,          /*!< Overrun interrupt flag. */
+};
+
+/*!
+ * @brief Interrupts
+ * @note Not all the interrupt options are listed here
+ */
+enum _adc_interrupt_enable
+{
+    kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence A, or entire sequence. */
+    kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence B, or entire sequence. */
+    kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
+                                                                 the channel data registers will cause an overrun
+                                                                 interrupt/DMA trigger. */
+};
+
+/*!
+ * @brief Define selection of clock mode.
+ */
+typedef enum _adc_clock_mode
+{
+    kADC_ClockSynchronousMode =
+        0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
+    kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
+} adc_clock_mode_t;
+
+/*!
+ * @brief Define selection of resolution.
+ */
+typedef enum _adc_resolution
+{
+    kADC_Resolution6bit = 0U,  /*!< 6-bit resolution. */
+    kADC_Resolution8bit = 1U,  /*!< 8-bit resolution. */
+    kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
+    kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
+} adc_resolution_t;
+
+/*!
+ * @brief Define selection of polarity of selected input trigger for conversion sequence.
+ */
+typedef enum _adc_trigger_polarity
+{
+    kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
+    kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
+} adc_trigger_polarity_t;
+
+/*!
+ * @brief Define selection of conversion sequence's priority.
+ */
+typedef enum _adc_priority
+{
+    kADC_PriorityLow = 0U,  /*!< This sequence would be preempted when another sequence is started. */
+    kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */
+} adc_priority_t;
+
+/*!
+ * @brief Define selection of conversion sequence's interrupt.
+ */
+typedef enum _adc_seq_interrupt_mode
+{
+    kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
+                                               individual ADC conversion inside this conversion sequence. */
+    kADC_InterruptForEachSequence = 1U,   /*!< The sequence interrupt/DMA trigger will be set when the entire set of
+                                               this sequence conversions completes. */
+} adc_seq_interrupt_mode_t;
+
+/*!
+ * @brief Define status of threshold compare result.
+ */
+typedef enum _adc_threshold_compare_status
+{
+    kADC_ThresholdCompareInRange = 0U,    /*!< LOW threshold <= conversion value <= HIGH threshold. */
+    kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
+    kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
+} adc_threshold_compare_status_t;
+
+/*!
+ * @brief Define status of threshold crossing detection result.
+ */
+typedef enum _adc_threshold_crossing_status
+{
+    /* The conversion on this channel had the same relationship (above or below) to the threshold value established by
+     * the designated LOW threshold value as did the previous conversion on this channel. */
+    kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
+
+    /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
+     * channel was above the threshold value established by the designated LOW threshold value and the current sample is
+     * below that threshold. */
+    kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
+
+    /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
+     * channel was below the threshold value established by the designated LOW threshold value and the current sample is
+     * above that threshold. */
+    kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
+} adc_threshold_crossing_status_t;
+
+/*!
+ * @brief Define interrupt mode for threshold compare event.
+ */
+typedef enum _adc_threshold_interrupt_mode
+{
+    kADC_ThresholdInterruptDisabled = 0U,   /*!< Threshold comparison interrupt is disabled. */
+    kADC_ThresholdInterruptOnOutside = 1U,  /*!< Threshold comparison interrupt is enabled on outside threshold. */
+    kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
+} adc_threshold_interrupt_mode_t;
+
+/*!
+ * @brief Define structure for configuring the block.
+ */
+typedef struct _adc_config
+{
+    adc_clock_mode_t clockMode;   /*!< Select the clock mode for ADC converter. */
+    uint32_t clockDividerNumber;  /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
+                                       field. The divider would be plused by 1 based on the value in this field. The
+                                       available range is in 8 bits. */
+    adc_resolution_t resolution;  /*!< Select the conversion bits. */
+    bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
+                                       powered-up. Re-calibration may be warranted periodically - especially if
+                                       operating conditions have changed. To enable this option would avoid the need to
+                                       calibrate if offset error is not a concern in the application. */
+    uint32_t sampleTimeNumber;    /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
+                                       to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
+} adc_config_t;
+
+/*!
+ * @brief Define structure for configuring conversion sequence.
+ */
+typedef struct _adc_conv_seq_config
+{
+    uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
+                               sequence is launched. The masked channels would be involved in current conversion
+                               sequence, beginning with the lowest-order. The available range is in 12-bit. */
+    uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
+                               conversion sequence to be initiated. The available range is 6-bit.*/
+    adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
+    bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
+                                flip-flop stages and therefore shorten the time between the trigger input signal and the
+                                start of a conversion. */
+    bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
+                                channel in the sequence instead of the default response of launching an entire sequence
+                                of conversions. */
+    adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
+} adc_conv_seq_config_t;
+
+/*!
+ * @brief Define structure of keeping conversion result information.
+ */
+typedef struct _adc_result_info
+{
+    uint32_t result;                                         /*!< Keey the conversion data value. */
+    adc_threshold_compare_status_t thresholdCompareStatus;   /*!< Keep the threshold compare status. */
+    adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
+    uint32_t channelNumber;                                  /*!< Keep the channel number for this conversion. */
+    bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
+    /* The data available flag would be returned by the reading result API. */
+} adc_result_info_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization and Deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_config_t.
+ */
+void ADC_Init(ADC_Type *base, const adc_config_t *config);
+
+/*!
+ * @brief Deinitialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ */
+void ADC_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Gets an available pre-defined settings for initial configuration.
+ *
+ * This function initializes the initial configuration structure with an available settings. The default values are:
+ * @code
+ *   config->clockMode = kADC_ClockSynchronousMode;
+ *   config->clockDividerNumber = 0U;
+ *   config->resolution = kADC_Resolution12bit;
+ *   config->enableBypassCalibration = false;
+ *   config->sampleTimeNumber = 0U;
+ * @endcode
+ * @param config Pointer to configuration structure.
+ */
+void ADC_GetDefaultConfig(adc_config_t *config);
+
+/*!
+ * @brief Do the self hardware calibration.
+ *
+ * @param base ADC peripheral base address.
+ * @retval true  Calibration succeed.
+ * @retval false Calibration failed.
+ */
+bool ADC_DoSelfCalibration(ADC_Type *base);
+
+/*!
+ * @brief Enable the internal temperature sensor measurement.
+ *
+ * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
+ * instead of external pin.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
+    }
+    else
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence A.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence A.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence A.
+ *
+ * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence A.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence B.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence B.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
+{
+    base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence B.
+ *
+ * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence B.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Data result.
+ * @{
+ */
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the channel's ADC conversion completed under each conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel The indicated channel number.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
+
+/* @} */
+
+/*!
+ * @name Threshold function.
+ * @{
+ */
+
+/*!
+ * @brief Set the threshhold pair 0 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value.
+ * @param highValue HIGH threshold value.
+ */
+static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
+    base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set the threshhold pair 1 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value. The available value is with 12-bit.
+ * @param highValue HIGH threshold value. The available value is with 12-bit.
+ */
+static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
+    base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 0.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL &= ~(channelMask);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 1.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL |= channelMask;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enable interrupts for conversion sequences.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN |= (0x7 & mask);
+}
+
+/*!
+ * @brief Disable interrupts for conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN &= ~(0x7 & mask);
+}
+
+/*!
+ * @brief Enable the interrupt of shreshold compare event for each channel.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel Channel number.
+ * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
+ */
+static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
+                                                       uint32_t channel,
+                                                       adc_threshold_interrupt_mode_t mode)
+{
+    base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
+}
+
+/* @} */
+
+/*!
+ * @name Status.
+ * @{
+ */
+
+/*!
+ * @brief Get status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @return Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
+{
+    return base->FLAGS;
+}
+
+/*!
+ * @brief Clear status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+    base->FLAGS = mask; /* Write 1 to clear. */
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* __FSL_ADC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,2169 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define NVALMAX (0x100U)
+#define PVALMAX (0x20U)
+#define MVALMAX (0x8000U)
+
+#define USB_NVALMAX (0x4U)
+#define USB_PVALMAX (0x8U)
+#define USB_MVALMAX (0x100U)
+
+#define PLL_MAX_N_DIV 0x100U
+#define USB_PLL_MAX_N_DIV 0x100U
+
+#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U)
+#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU)
+/*--------------------------------------------------------------------------
+!!! If required these #defines can be moved to chip library file
+----------------------------------------------------------------------------*/
+
+#define PLL_MDEC_VAL_P (0U)                                      /*!<  MDEC is in bits  16 downto 0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)             /*!<  NDEC is in bits  9 downto 0 */
+#define PLL_NDEC_VAL_P (0U)                                      /*!<  NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U)                                      /*!<  PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
+#define PLL_LOWER_IN_LIMIT (4000U)                               /*!<  Minimum PLL input rate */
+#define PLL_MIN_IN_SSMODE (2000000U)
+#define PLL_MAX_IN_SSMODE (4000000U)
+
+/*!<  Middle of the range values for spread-spectrum */
+#define PLL_SSCG_MF_FREQ_VALUE 4U
+#define PLL_SSCG_MC_COMP_VALUE 2U
+#define PLL_SSCG_MR_DEPTH_VALUE 4U
+#define PLL_SSCG_DITHER_VALUE 0U
+
+/*!<  USB PLL CCO MAX AND MIN FREQ */
+#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)
+#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)
+#define USB_PLL_LOWER_IN_LIMIT (1000000U)                             /*!<  Minimum PLL input rate */
+
+#define USB_PLL_MSEL_VAL_P (0U)                                       /*!<  MSEL is in bits  7 downto 0 */
+#define USB_PLL_MSEL_VAL_M (0xFFU)
+#define USB_PLL_PSEL_VAL_P (8U)                                       /*!<  PDEC is in bits 9:8 */
+#define USB_PLL_PSEL_VAL_M (0x3U)
+#define USB_PLL_NSEL_VAL_P (10U)                                      /*!<  NDEC is in bits  11:10 */
+#define USB_PLL_NSEL_VAL_M (0x3U)
+
+/*!<  SWITCH USB POSTDIVIDER FOR REGITSER WRITING */
+#define SWITCH_USB_PSEL(x)    ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U)
+
+/*!<  SYS PLL NDEC reg */
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
+/*!<  SYS PLL PDEC reg */
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
+/*!<  SYS PLL MDEC reg */
+#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)
+
+/*!<  SYS PLL NSEL reg */
+#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)
+/*!<  SYS PLL PSEL reg */
+#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)
+/*!<  SYS PLL MSEL reg */
+#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)
+
+/*!<  FRAC control */
+#define AUDIO_PLL_FRACT_MD_P (0U)
+#define AUDIO_PLL_FRACT_MD_INT_P (15U)
+#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)
+#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)
+
+#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)
+#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)
+
+/* Saved value of PLL output rate, computed whenever needed to save run-time
+   computation on each call to retrive the PLL rate. */
+static uint32_t s_Pll_Freq;
+static uint32_t s_Usb_Pll_Freq;
+static uint32_t s_Audio_Pll_Freq;
+
+
+/** External clock rate on the CLKIN pin in Hz. If not used,
+    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+    being driven at. */
+const uint32_t g_I2S_Mclk_Freq = 0U;
+const uint32_t g_Ext_Clk_Freq = 12000000U;
+const uint32_t g_Lcd_Clk_In_Freq = 0U;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N);
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC);
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P);
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC);
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M);
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC);
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Get the greatest common divisor */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);
+
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Clock Selection for IP */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    bool final_descriptor = false;
+    uint8_t mux;
+    uint8_t pos;
+    uint32_t i;
+    volatile uint32_t *pClkSel;
+
+    pClkSel = &(SYSCON->MAINCLKSELA);
+
+    for (i = 0U; (i <= 2U) && (!final_descriptor); i++)
+    {
+        connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!<  pick up next descriptor */
+        mux = (uint8_t)connection;
+        if (connection)
+        {
+            pos = ((connection & 0xf00U) >> 8U) - 1U;
+            if (mux == CM_ASYNCAPB)
+            {
+                SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+                ASYNC_SYSCON->ASYNCAPBCLKSELA = pos;
+            }
+            else
+            {
+                pClkSel[mux] = pos;
+            }
+        }
+        else
+        {
+            final_descriptor = true;
+        }
+    }
+}
+
+/* Set IP Clock Divider */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
+{
+    volatile uint32_t *pClkDiv;
+
+    pClkDiv = &(SYSCON->SYSTICKCLKDIV);
+    if (reset)
+    {
+        pClkDiv[div_name] = 1U << 29U;
+    }
+    if (divided_by_value == 0U) /*!<  halt */
+    {
+        pClkDiv[div_name] = 1U << 30U;
+    }
+    else
+    {
+        pClkDiv[div_name] = (divided_by_value - 1U);
+    }
+}
+
+/* Set FRO Clocking */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq)
+{
+    uint32_t usb_adj;
+    if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))
+    {
+        return kStatus_Fail;
+    }
+    /* Power up the FRO and set this as the base clock */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
+    /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */
+    usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT;
+    if (iFreq > 12000000U)
+    {
+        if (iFreq == 96000000U)
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) |
+                                SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                                SYSCON_FROCTRL_HSPDCLK(1);
+        }
+        else
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) |
+                                SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                                SYSCON_FROCTRL_HSPDCLK(1);
+        }
+    }
+    else
+    {
+        SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1);
+    }
+
+    return 0U;
+}
+
+/* Get CLOCK OUT Clk */
+uint32_t CLOCK_GetClockOutClkFreq(void)
+{
+    return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq():
+           (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq():
+           (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U;
+}
+
+/* Get SPIFI Clk */
+uint32_t CLOCK_GetSpifiClkFreq(void)
+{
+    return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get ADC Clk */
+uint32_t CLOCK_GetAdcClkFreq(void)
+{
+    return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->ADCCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get USB0 Clk */
+uint32_t CLOCK_GetUsb0ClkFreq(void)
+{
+    return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->USB0CLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get USB1 Clk */
+uint32_t CLOCK_GetUsb1ClkFreq(void)
+{
+
+    return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->USB1CLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get MCLK Clk */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+    return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U):
+           (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get SCTIMER Clk */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+    return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SCTCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get SDIO Clk */
+uint32_t CLOCK_GetSdioClkFreq(void)
+{
+    return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get LCD Clk */
+uint32_t CLOCK_GetLcdClkFreq(void)
+{
+    return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn():
+           (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->LCDCLKSEL == 3U) ? 0U:0U;
+}
+
+/* Get LCD CLK IN Clk */
+uint32_t CLOCK_GetLcdClkIn(void)
+{
+  return g_Lcd_Clk_In_Freq;
+}
+
+/* Get FRO 12M Clk */
+uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U;
+}
+
+/* Get EXT OSC Clk */
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return g_Ext_Clk_Freq;
+}
+
+/* Get WATCH DOG Clk */
+uint32_t CLOCK_GetWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+    }
+}
+
+/* Get HF FRO Clk */
+uint32_t CLOCK_GetFroHfFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : 
+          !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 :
+           (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U;
+}
+
+/* Get SYSTEM PLL Clk */
+uint32_t CLOCK_GetPllOutFreq(void)
+{
+    return s_Pll_Freq;
+}
+
+/* Get AUDIO PLL Clk */
+uint32_t CLOCK_GetAudioPllOutFreq(void)
+{
+    return s_Audio_Pll_Freq;
+}
+
+/* Get USB PLL Clk */
+uint32_t CLOCK_GetUsbPllOutFreq(void)
+{
+    return s_Usb_Pll_Freq;
+}
+
+/* Get RTC OSC Clk */
+uint32_t CLOCK_GetOsc32KFreq(void)
+{
+    return CLK_RTC_32K_CLK;               /* Needs to be corrected to check that RTC Clock is enabled */
+}
+
+/* Get MAIN Clk */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() :
+           (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U;
+}
+
+/* Get I2S MCLK Clk */
+uint32_t CLOCK_GetI2SMClkFreq(void)
+{
+    return g_I2S_Mclk_Freq;
+}
+
+/* Get ASYNC APB Clk */
+uint32_t CLOCK_GetAsyncApbClkFreq(void)
+{
+    async_clock_src_t clkSrc;
+    uint32_t clkRate;
+
+    clkSrc = CLOCK_GetAsyncApbClkSrc();
+
+    switch (clkSrc)
+    {
+        case kCLOCK_AsyncMainClk:
+            clkRate = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_AsyncFro12Mhz:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Get FLEXCOMM Clk */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+    return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : 
+           (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() :
+           (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() :
+           (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U;
+}
+
+/* Get FRG Clk */
+uint32_t CLOCK_GetFRGInputClock(void)
+{
+    return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
+           (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : 
+           (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
+}
+
+/* Set FRG Clk */
+uint32_t CLOCK_SetFRGClock(uint32_t freq)
+{
+    uint32_t input = CLOCK_GetFRGInputClock();
+    uint32_t mul;
+
+    if ((freq > 48000000) || (freq > input) || (input / freq >= 2))
+    {
+        /* FRG output frequency should be less than equal to 48MHz */
+        return 0;
+    }
+    else
+    {
+        mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
+        SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
+        return 1;
+    }
+}
+
+/* Set IP Clk */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_ClockOut:
+            freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_SpiFi:
+            freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Adc:
+            freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Usb0:
+            freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Usb1:
+            freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Mclk:
+            freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_FroHf:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case kCLOCK_Fro12M:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case kCLOCK_ExtClk:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case kCLOCK_PllOut:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case kClock_WdtOsc:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+        case kCLOCK_Frg:
+            freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
+                   (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
+                   (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() :
+                   (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
+            break;
+        case kCLOCK_Dmic:
+            freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : 
+                   (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() :
+                   (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() :
+                   (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() :
+                   (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() :
+                   (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U;
+            freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
+            break;
+
+        case kCLOCK_AsyncApbClk:
+            freq = CLOCK_GetAsyncApbClkFreq();
+            break;
+        case kCLOCK_Sct:
+            freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_SDio:
+            freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_EMC:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_LCD:
+            freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_MCAN0:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_MCAN1:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_FlexI2S:
+            freq = CLOCK_GetI2SMClkFreq();
+            break;
+        case kCLOCK_Flexcomm0:
+            freq = CLOCK_GetFlexCommClkFreq(0U);
+            break;
+        case kCLOCK_Flexcomm1:
+            freq = CLOCK_GetFlexCommClkFreq(1U);
+            break;
+        case kCLOCK_Flexcomm2:
+            freq = CLOCK_GetFlexCommClkFreq(2U);
+            break;
+        case kCLOCK_Flexcomm3:
+            freq = CLOCK_GetFlexCommClkFreq(3U);
+            break;
+        case kCLOCK_Flexcomm4:
+            freq = CLOCK_GetFlexCommClkFreq(4U);
+            break;
+        case kCLOCK_Flexcomm5:
+            freq = CLOCK_GetFlexCommClkFreq(5U);
+            break;
+        case kCLOCK_Flexcomm6:
+            freq = CLOCK_GetFlexCommClkFreq(6U);
+            break;
+        case kCLOCK_Flexcomm7:
+            freq = CLOCK_GetFlexCommClkFreq(7U);
+            break;
+        case kCLOCK_Flexcomm8:
+            freq = CLOCK_GetFlexCommClkFreq(8U);
+            break;
+        case kCLOCK_Flexcomm9:
+            freq = CLOCK_GetFlexCommClkFreq(9U);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Set the FLASH wait states for the passed frequency */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
+{
+    if (iFreq <= 12000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle);
+    }
+    else if (iFreq <= 24000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle);
+    }
+    else if (iFreq <= 36000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle);
+    }
+    else if (iFreq <= 60000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle);
+    }
+    else if (iFreq <= 96000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle);
+    }
+    else if (iFreq <= 120000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle);
+    }
+    else if (iFreq <= 144000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash7Cycle);
+    }
+    else if (iFreq <= 168000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash8Cycle);
+    }
+    else
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash9Cycle);
+    }
+}
+
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N)
+{
+    uint32_t x, i;
+
+    /* Find NDec */
+    switch (N)
+    {
+        case 0U:
+            x = 0x3FFU;
+            break;
+
+        case 1U:
+            x = 0x302U;
+            break;
+
+        case 2U:
+            x = 0x202U;
+            break;
+
+        default:
+            x = 0x080U;
+            for (i = N; i <= NVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+            }
+            break;
+    }
+
+    return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FFU:
+            n = 0U;
+            break;
+
+        case 0x302U:
+            n = 1U;
+            break;
+
+        case 0x202U:
+            n = 2U;
+            break;
+
+        default:
+            x = 0x080U;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+
+    return n;
+}
+
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P)
+{
+    uint32_t x, i;
+
+    /* Find PDec */
+    switch (P)
+    {
+        case 0U:
+            x = 0x7FU;
+            break;
+
+        case 1U:
+            x = 0x62U;
+            break;
+
+        case 2U:
+            x = 0x42U;
+            break;
+
+        default:
+            x = 0x10U;
+            for (i = P; i <= PVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+            }
+            break;
+    }
+
+    return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7FU:
+            p = 0U;
+            break;
+
+        case 0x62U:
+            p = 1U;
+            break;
+
+        case 0x42U:
+            p = 2U;
+            break;
+
+        default:
+            x = 0x10U;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+
+    return p;
+}
+
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M)
+{
+    uint32_t i, x;
+
+    /* Find MDec */
+    switch (M)
+    {
+        case 0U:
+            x = 0x1FFFFU;
+            break;
+
+        case 1U:
+            x = 0x18003U;
+            break;
+
+        case 2U:
+            x = 0x10003U;
+            break;
+
+        default:
+            x = 0x04000U;
+            for (i = M; i <= MVALMAX; i++)
+            {
+                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+            }
+            break;
+    }
+
+    return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFFU:
+            m = 0U;
+            break;
+
+        case 0x18003U:
+            m = 1U;
+            break;
+
+        case 0x10003U:
+            m = 2U;
+            break;
+
+        default:
+            x = 0x04000U;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+
+    return m;
+}
+
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
+{
+    /* bandwidth: compute selP from Multiplier */
+    if (M < 60U)
+    {
+        *pSelP = (M >> 1U) + 1U;
+    }
+    else
+    {
+        *pSelP = PVALMAX - 1U;
+    }
+
+    /* bandwidth: compute selI from Multiplier */
+    if (M > 16384U)
+    {
+        *pSelI = 1U;
+    }
+    else if (M > 8192U)
+    {
+        *pSelI = 2U;
+    }
+    else if (M > 2048U)
+    {
+        *pSelI = 4U;
+    }
+    else if (M >= 501U)
+    {
+        *pSelI = 8U;
+    }
+    else if (M >= 60U)
+    {
+        *pSelI = 4U * (1024U / (M + 9U));
+    }
+    else
+    {
+        *pSelI = (M & 0x3CU) + 4U;
+    }
+
+    if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
+    {
+        *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
+    }
+
+    *pSelR = 0U;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFU);
+        if (preDiv == 0U)
+        {
+            preDiv = 1U;
+        }
+    }
+
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1U;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
+        if (postDiv == 0U)
+        {
+            postDiv = 2U;
+        }
+    }
+
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1U;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFU);
+
+    if (mMult == 0U)
+    {
+        mMult = 1U;
+    }
+
+    return mMult;
+}
+
+/* Find greatest common divisor between m and n */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
+{
+    uint32_t tmp;
+
+    while (n != 0U)
+    {
+        tmp = n;
+        n = m % n;
+        m = tmp;
+    }
+
+    return m;
+}
+
+/*
+ * Set PLL output based on desired output rate.
+ * In this function, the it calculates the PLL setting for output frequency from input clock
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
+ */
+static pll_error_t CLOCK_GetPllConfigInternal(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    uint32_t nDivOutHz, fccoHz, multFccoDiv;
+    uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
+    uint32_t pllDirectInput, pllDirectOutput;
+    uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
+
+    /* Baseline parameters (no input or output dividers) */
+    pllPreDivider = 1U;  /* 1 implies pre-divider will be disabled */
+    pllPostDivider = 0U; /* 0 implies post-divider will be disabled */
+    pllDirectOutput = 1U;
+    multFccoDiv = 2U;
+
+    /* Verify output rate parameter */
+    if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+    {
+        /* Maximum PLL output with post divider=1 cannot go above this frequency */
+        return kStatus_PLL_OutputTooHigh;
+    }
+    if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
+    {
+        /* Minmum PLL output with maximum post divider cannot go below this frequency */
+        return kStatus_PLL_OutputTooLow;
+    }
+
+    /* Verify input rate parameter */
+    if (finHz < PLL_LOWER_IN_LIMIT)
+    {
+        /* Input clock into the PLL cannot be lower than this */
+        return kStatus_PLL_InputTooLow;
+    }
+
+    /* Find the optimal CCO frequency for the output and input that
+       will keep it inside the PLL CCO range. This may require
+       tweaking the post-divider for the PLL. */
+    fccoHz = foutHz;
+    while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+    {
+        /* CCO output is less than minimum CCO range, so the CCO output
+           needs to be bumped up and the post-divider is used to bring
+           the PLL output back down. */
+        pllPostDivider++;
+        if (pllPostDivider > PVALMAX)
+        {
+            return kStatus_PLL_OutsideIntLimit;
+        }
+
+        /* Target CCO goes up, PLL output goes down */
+        fccoHz = foutHz * (pllPostDivider * 2U);
+        pllDirectOutput = 0U;
+    }
+
+    /* Determine if a pre-divider is needed to get the best frequency */
+    if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))
+    {
+        uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+
+        if (a > 20000U)
+        {
+            a = (multFccoDiv * finHz) / a;
+            if ((a != 0U) && (a < PLL_MAX_N_DIV))
+            {
+                pllPreDivider = a;
+            }
+        }
+    }
+
+    /* Bypass pre-divider hardware if pre-divider is 1 */
+    if (pllPreDivider > 1U)
+    {
+        pllDirectInput = 0U;
+    }
+    else
+    {
+        pllDirectInput = 1U;
+    }
+
+    /* Determine PLL multipler */
+    nDivOutHz = (finHz / pllPreDivider);
+    pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+
+    /* Find optimal values for filter */
+    /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+    if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
+    {
+        pllMultiplier++;
+    }
+
+    /* Setup filtering */
+    pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
+    uplimoff = 0U;
+
+    /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+    pSetup->pllmdec =
+        PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ;
+
+    /* Get encoded values for N (prediv) and P (postdiv) */
+    pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+    pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+
+    /* PLL control */
+    pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) |                  /* Filter coefficient */
+                         (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) |                  /* Filter coefficient */
+                         (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) |                  /* Filter coefficient */
+                         (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) |                      /* PLL bypass mode disabled */
+                         (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) |             /* SS/fractional mode disabled */
+                         (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
+                         (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
+
+    return kStatus_PLL_Success;
+}
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+/* Alloct the static buffer for cache. */
+pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
+uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+uint32_t gPllSetupCacheIdx = 0U;
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+/*
+ * Calculate the PLL setting values from input clock freq to output freq.
+ */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    pll_error_t retErr;
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    uint32_t i;
+
+    for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
+    {
+        if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) )
+        {
+            /* Hit the target in cache buffer. */
+            pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;
+            pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;
+            pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;
+            pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;
+            retErr = kStatus_PLL_Success;
+        }
+    }
+
+    if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    {
+        return retErr;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    /* No cache or did not hit the cache. */
+    retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    if (kStatus_PLL_Success == retErr)
+    {
+        /* Cache the most recent calulation result into buffer. */
+        gFinHzCache[gPllSetupCacheIdx] = finHz;
+        gFoutHzCache[gPllSetupCacheIdx] = foutHz;
+    
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;
+        /* Update the index for next available buffer. */
+        gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    return retErr;
+}
+
+/* Update SYSTEM PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
+}
+
+/* Update USB PLL rate variable */
+static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
+{
+    s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);
+}
+
+/* Return System PLL input clock rate */
+uint32_t CLOCK_GetSystemPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+
+        case 0x02U:
+            clkRate = CLOCK_GetWdtOscFreq();
+            break;
+
+        case 0x03U:
+            clkRate = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return Audio PLL input clock rate */
+uint32_t CLOCK_GetAudioPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+            
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return System PLL output clock rate from setup structure */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetSystemPLLInClockRate();
+    /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/
+    if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U;           /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Return Usb PLL output clock rate from setup structure */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)
+{
+    uint32_t nsel, psel, msel, inPllRate;
+    uint64_t workRate;
+    inPllRate = CLOCK_GetExtClkFreq();
+    msel = pSetup->msel;
+    psel = pSetup->psel;
+    nsel = pSetup->nsel;
+
+    if (pSetup->fbsel == 1U)
+       {   
+           /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+           workRate = (inPllRate) * (msel + 1U) / (nsel + 1U);
+       }
+       else
+       {
+           /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+           workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));
+       }
+   
+    return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from setup structure */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetAudioPLLInClockRate();
+    if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U;           /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Set the current PLL Rate */
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)
+{
+    s_Pll_Freq = rate;
+}
+
+/* Set the current Audio PLL Rate */
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)
+{
+    s_Audio_Pll_Freq = rate;
+}
+
+/* Set the current Usb PLL Rate */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)
+{
+    s_Usb_Pll_Freq = rate;
+}
+
+/* Return System PLL output clock rate */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->SYSPLLCTRL;
+        Setup.pllndec = SYSCON->SYSPLLNDEC;
+        Setup.pllpdec = SYSCON->SYSPLLPDEC;
+        Setup.pllmdec = SYSCON->SYSPLLMDEC;
+
+        CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Pll_Freq;
+
+    return rate;
+}
+
+/* Return AUDIO PLL output clock rate */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Audio_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->AUDPLLCTRL;
+        Setup.pllndec = SYSCON->AUDPLLNDEC;
+        Setup.pllpdec = SYSCON->AUDPLLPDEC;
+        Setup.pllmdec = SYSCON->AUDPLLMDEC;
+
+        CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Audio_Pll_Freq;
+    return rate;
+}
+
+/* Return USB PLL output clock rate */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)
+{
+    usb_pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Usb_Pll_Freq == 0U))
+    {
+        Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK;
+        Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK;
+        Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK;
+        Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK;
+        Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK;
+        Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; 
+        CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Usb_Pll_Freq;
+    return rate;
+}
+
+/* Set PLL output based on the passed PLL setup data */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetSystemPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+/* Set PLL output from PLL setup structure */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+    /*!< Set FLASH waitstates for core */
+    CLOCK_SetFLASHAccessCyclesForFreq(pSetup->pllRate);
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
+
+    /* System voltage adjustment, occurs prior to setting main system clock */
+    if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
+    {
+        POWER_SetVoltageForFreq(s_Pll_Freq);
+    }
+
+    return kStatus_PLL_Success;
+}
+
+
+/* Set AUDIO PLL output from AUDIO PLL setup structure */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->AUDPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->AUDPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->AUDPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->AUDPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);
+
+    return kStatus_PLL_Success;
+}
+
+/* Set Audio PLL output based on the passed Audio PLL setup data */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetAudioPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+
+
+/* Setup PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup Audio PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off Audio PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    /* Write Audio PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT);  /* latch */
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1);                              /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Audio_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup USB PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)
+{       
+    uint32_t usbpllctrl, fccoHz;
+    uint8_t msel, psel, nsel;
+    bool pllDirectInput, pllDirectOutput, pllfbsel;
+    volatile uint32_t delayX;
+
+    msel = pSetup->msel;
+    psel = pSetup->psel;
+    nsel = pSetup->nsel;
+    pllDirectInput = pSetup->direct;
+    pllDirectOutput = pSetup->bypass;
+    pllfbsel = pSetup->fbsel;
+    
+    /* Input clock into the PLL cannot be lower than this */
+    if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT )
+    {
+        return kStatus_PLL_InputTooLow;
+    }
+    
+    if (pllfbsel == 1U)
+    {   
+        /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+        fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ;
+        
+        /* USB PLL CCO out rate cannot be lower than this */        
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {       
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        { 
+            return kStatus_PLL_CCOTooHigh;
+        }
+    }
+    else
+    {
+        /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+        fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U);
+        
+        /* USB PLL CCO out rate cannot be lower than this */        
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {       
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        { 
+            return kStatus_PLL_CCOTooHigh;
+        }       
+    }
+    
+    /* If configure the USB HOST clock, VD5 power for USB PHY should be enable 
+       before the the PLL is working */
+    /* Turn on the ext clock for usb pll input */
+    CLOCK_Enable_SysOsc(true);
+    
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+
+    /* Power off USB PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);
+      
+    /* Write USB PLL setup data */
+    usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel)  |                  /* NSEL VALUE */
+                 USB_PLL_PSEL_VAL_SET(psel)  |                  /* PSEL VALUE */
+                 USB_PLL_MSEL_VAL_SET(msel)  |                  /* MSEL VALUE */
+                 (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT  |            /* BYPASS DISABLE */
+                 (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT |            /* DIRECTO DISABLE */
+                 (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT;                     /* FBSEL SELECT */   
+    
+    SYSCON->USBPLLCTRL = usbpllctrl;
+    
+    POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+  
+    /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */
+    for (delayX = 0U; delayX < 172U; ++delayX)
+    {
+    }
+    
+    while (CLOCK_IsUsbPLLLocked() == false)
+    {
+    }
+    CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);
+    return kStatus_PLL_Success;
+}
+
+/* Set System PLL clock based on the input frequency and multiplier */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
+{
+    uint32_t cco_freq = input_freq * multiply_by;
+    uint32_t pdec = 1U;
+    uint32_t selr;
+    uint32_t seli;
+    uint32_t selp;
+    uint32_t mdec, ndec;
+
+    uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);
+
+    while (cco_freq < 275000000U)
+    {
+        multiply_by <<= 1U; /* double value in each iteration */
+        pdec <<= 1U;        /* correspondingly double pdec to cancel effect of double msel */
+        cco_freq = input_freq * multiply_by;
+    }
+    selr = 0U;
+    if (multiply_by < 60U)
+    {
+        seli = (multiply_by & 0x3cU) + 4U;
+        selp = (multiply_by >> 1U) + 1U;
+    }
+    else
+    {
+        selp = 31U;
+        if (multiply_by > 16384U)
+        {
+            seli = 1U;
+        }
+        else if (multiply_by > 8192U)
+        {
+            seli = 2U;
+        }
+        else if (multiply_by > 2048U)
+        {
+            seli = 4U;
+        }
+        else if (multiply_by >= 501U)
+        {
+            seli = 8U;
+        }
+        else
+        {
+            seli = 4U * (1024U / (multiply_by + 9U));
+        }
+    }
+
+    if (pdec > 1U)
+    {
+        directo = 0U;     /* use post divider */
+        pdec = pdec / 2U; /* Account for minus 1 encoding */
+                          /* Translate P value */
+        switch (pdec)
+        {
+            case 1U:
+                pdec = 0x62U; /* 1  * 2 */
+                break;
+            case 2U:
+                pdec = 0x42U; /* 2  * 2 */
+                break;
+            case 4U:
+                pdec = 0x02U; /* 4  * 2 */
+                break;
+            case 8U:
+                pdec = 0x0bU; /* 8  * 2 */
+                break;
+            case 16U:
+                pdec = 0x11U; /* 16 * 2 */
+                break;
+            case 32U:
+                pdec = 0x08U; /* 32 * 2 */
+                break;
+            default:
+                pdec = 0x08U;
+                break;
+        }
+    }
+
+    mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));
+    ndec = 0x302U; /* pre divide by 1 (hardcoded) */
+
+    SYSCON->SYSPLLCTRL = directo |
+                         (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
+                         (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
+    SYSCON->SYSPLLPDEC = pdec | (1U << 7U);  /* set Pdec value and assert preq */
+    SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */
+    SYSCON->SYSPLLMDEC = (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+}
+
+/* Enable USB DEVICE FULL SPEED clock */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbd0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        uint32_t delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }
+    }
+    CLOCK_EnableClock(kCLOCK_Usbd0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+    
+    return ret;
+}
+
+/* Enable USB HOST FULL SPEED clock */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbhmr0);
+    CLOCK_DisableClock(kCLOCK_Usbhsl0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        uint32_t delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }
+    }
+    CLOCK_EnableClock(kCLOCK_Usbhmr0);
+    CLOCK_EnableClock(kCLOCK_Usbhsl0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+
+    return ret;
+}
+
+/* Enable USB DEVICE HIGH SPEED clock */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    uint32_t delay;
+    CLOCK_DisableClock(kCLOCK_Usbd1);
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {    
+        delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+      
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);  
+    }
+
+    delay = 100000;
+    while (delay --)
+    {
+        __asm("nop");
+    }
+    /* Enable USB1D and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbd1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}
+
+
+/* Enable USB HOST HIGH SPEED clock */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    uint32_t delay;
+    CLOCK_DisableClock(kCLOCK_Usbh1);
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {
+        delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+    }
+
+    delay = 100000;
+    while (delay --)
+    {
+        __asm("nop");
+    }
+    /* Enable USBh1 and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbh1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1277 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name ofcopyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could contol the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*!
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
+ *
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
+ * would cache the recent calulation and accelerate the execution to get the
+ * right settings.
+ */
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT  2U
+#endif
+
+/*! @brief Clock ip name array for ROM. */
+#define ADC_CLOCKS \
+    {              \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for ROM. */
+#define ROM_CLOCKS \
+    {              \
+        kCLOCK_Rom \
+    }
+/*! @brief Clock ip name array for SRAM. */
+#define SRAM_CLOCKS \
+    {               \
+        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
+    }
+/*! @brief Clock ip name array for FLASH. */
+#define FLASH_CLOCKS \
+    {                \
+        kCLOCK_Flash \
+    }
+/*! @brief Clock ip name array for FMC. */
+#define FMC_CLOCKS \
+    {              \
+        kCLOCK_Fmc \
+    }
+/*! @brief Clock ip name array for EEPROM. */
+#define EEPROM_CLOCKS  \
+    {                  \
+        kCLOCK_Eeprom  \
+    }
+/*! @brief Clock ip name array for SPIFI. */
+#define SPIFI_CLOCKS  \
+    {                 \
+        kCLOCK_Spifi  \
+    }
+/*! @brief Clock ip name array for INPUTMUX. */
+#define INPUTMUX_CLOCKS      \
+    {                        \
+        kCLOCK_InputMux      \
+    }
+/*! @brief Clock ip name array for IOCON. */
+#define IOCON_CLOCKS         \
+    {                        \
+        kCLOCK_Iocon         \
+    }
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS          \
+    {                        \
+        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5     \
+    }
+/*! @brief Clock ip name array for PINT. */
+#define PINT_CLOCKS          \
+    {                        \
+        kCLOCK_Pint          \
+    }
+/*! @brief Clock ip name array for GINT. */
+#define GINT_CLOCKS          \
+    {                        \
+        kCLOCK_Gint, kCLOCK_Gint          \
+    }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS          \
+    {                       \
+        kCLOCK_Dma          \
+    }
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS          \
+    {                       \
+        kCLOCK_Crc          \
+    }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS          \
+    {                        \
+        kCLOCK_Wwdt          \
+    }
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS          \
+    {                       \
+        kCLOCK_Rtc          \
+    }
+/*! @brief Clock ip name array for ADC0. */
+#define ADC0_CLOCKS          \
+    {                        \
+        kCLOCK_Adc0          \
+    }
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS           \
+    {                        \
+        kCLOCK_Mrt           \
+    }
+/*! @brief Clock ip name array for RIT. */
+#define RIT_CLOCKS           \
+    {                        \
+        kCLOCK_Rit           \
+    }
+/*! @brief Clock ip name array for SCT0. */
+#define SCT_CLOCKS          \
+    {                        \
+        kCLOCK_Sct0          \
+    }
+/*! @brief Clock ip name array for MCAN. */
+#define MCAN_CLOCKS          \
+    {                        \
+        kCLOCK_Mcan0, kCLOCK_Mcan1          \
+    }
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS         \
+    {                        \
+        kCLOCK_Utick         \
+    }
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                        \
+    {                                                                          \
+        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
+					kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \
+                                        kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
+    }
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                                                                         \
+    {                                                                                                         \
+        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
+            kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9     \
+    }
+
+/*! @brief Clock ip name array for BI2C. */
+#define BI2C_CLOCKS                                                                                                     \
+    {                                                                                                                   \
+        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \
+        kCLOCK_BI2c8, kCLOCK_BI2c9  \
+    }
+/*! @brief Clock ip name array for LSPI. */
+#define LPSI_CLOCKS                                                                                                     \
+    {                                                                                                                   \
+        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \
+        kCLOCK_LSpi8, kCLOCK_LSpi9  \
+    }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define FLEXI2S_CLOCKS                                                                                        \
+    {                                                                                                         \
+        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
+            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9                                                                  \
+    }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+    {               \
+        kCLOCK_DMic \
+    }
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS                                                               \
+    {                                                                               \
+        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4   \
+    }
+/*! @brief Clock ip name array for LCD. */
+#define LCD_CLOCKS  \
+    {               \
+        kCLOCK_Lcd  \
+    }
+/*! @brief Clock ip name array for SDIO. */
+#define SDIO_CLOCKS  \
+    {                \
+        kCLOCK_Sdio  \
+    }
+/*! @brief Clock ip name array for USBRAM. */
+#define USBRAM_CLOCKS    \
+    {                    \
+        kCLOCK_UsbRam1   \
+    }
+/*! @brief Clock ip name array for EMC. */
+#define EMC_CLOCKS       \
+    {                    \
+        kCLOCK_Emc       \
+    }
+/*! @brief Clock ip name array for ETH. */
+#define ETH_CLOCKS       \
+    {                    \
+        kCLOCK_Eth       \
+    }
+/*! @brief Clock ip name array for AES. */
+#define AES_CLOCKS       \
+    {                    \
+        kCLOCK_Aes       \
+    }
+/*! @brief Clock ip name array for OTP. */
+#define OTP_CLOCKS       \
+    {                    \
+        kCLOCK_Otp       \
+    }
+/*! @brief Clock ip name array for RNG. */
+#define RNG_CLOCKS       \
+    {                    \
+        kCLOCK_Rng       \
+    }
+/*! @brief Clock ip name array for USBHMR0. */
+#define USBHMR0_CLOCKS       \
+    {                        \
+        kCLOCK_Usbhmr0       \
+    }
+/*! @brief Clock ip name array for USBHSL0. */
+#define USBHSL0_CLOCKS       \
+    {                        \
+        kCLOCK_Usbhsl0       \
+    }
+/*! @brief Clock ip name array for SHA0. */
+#define SHA0_CLOCKS       \
+    {                     \
+        kCLOCK_Sha0       \
+    }
+/*! @brief Clock ip name array for SMARTCARD. */
+#define SMARTCARD_CLOCKS  \
+    {                     \
+        kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
+    }
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS  \
+    {                \
+        kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
+    }
+/*! @brief Clock ip name array for USBH. */
+#define USBH_CLOCKS  \
+    {                \
+        kCLOCK_Usbh1 \
+    }
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define AHB_CLK_CTRL2 2
+#define ASYNC_CLK_CTRL0 3
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+    kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
+    kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
+    kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
+    kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
+    kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
+    kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
+    kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9),
+    kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
+    kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
+    kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
+    kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
+    kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
+    kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
+    kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
+    kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
+    kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
+    kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
+    kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
+    kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
+    kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
+    kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
+    kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
+    kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
+    kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
+    kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
+    kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
+    kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
+    kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
+    kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
+    kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
+    kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
+    kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
+    kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
+    kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
+    kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
+    kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
+    kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
+    kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
+    kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
+    kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
+    kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8),
+    kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
+    kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
+    kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
+    kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
+    kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
+    kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
+    kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
+    kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
+    kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
+    kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
+
+    kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
+    kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_CoreSysClk,  /*!< Core/system clock  (aka MAIN_CLK)                       */
+    kCLOCK_BusClk,      /*!< Bus clock (AHB clock)                                   */
+    kCLOCK_ClockOut,    /*!< CLOCKOUT                                                */
+    kCLOCK_FroHf,       /*!< FRO48/96                                                */
+    kCLOCK_SpiFi,       /*!< SPIFI                                                   */
+    kCLOCK_Adc,         /*!< ADC                                                     */
+    kCLOCK_Usb0,        /*!< USB0                                                    */
+    kCLOCK_Usb1,        /*!< USB1                                                    */
+    kCLOCK_UsbPll,      /*!< USB1 PLL                                                */
+    kCLOCK_Mclk,        /*!< MCLK                                                    */
+    kCLOCK_Sct,         /*!< SCT                                                     */
+    kCLOCK_SDio,        /*!< SDIO                                                    */
+    kCLOCK_EMC,         /*!< EMC                                                     */
+    kCLOCK_LCD,         /*!< LCD                                                     */
+    kCLOCK_MCAN0,       /*!< MCAN0                                                   */
+    kCLOCK_MCAN1,       /*!< MCAN1                                                   */
+    kCLOCK_Fro12M,      /*!< FRO12M                                                  */
+    kCLOCK_ExtClk,      /*!< External Clock                                          */
+    kCLOCK_PllOut,      /*!< PLL Output                                              */
+    kCLOCK_UsbClk,      /*!< USB input                                               */
+    kClock_WdtOsc,      /*!< Watchdog Oscillator                                     */
+    kCLOCK_Frg,         /*!< Frg Clock                                               */
+    kCLOCK_Dmic,        /*!< Digital Mic clock                                       */
+    kCLOCK_AsyncApbClk, /*!< Async APB clock										 */
+    kCLOCK_FlexI2S,     /*!< FlexI2S clock                                           */
+    kCLOCK_Flexcomm0,   /*!< Flexcomm0Clock                                          */
+    kCLOCK_Flexcomm1,   /*!< Flexcomm1Clock                                          */
+    kCLOCK_Flexcomm2,   /*!< Flexcomm2Clock                                          */
+    kCLOCK_Flexcomm3,   /*!< Flexcomm3Clock                                          */
+    kCLOCK_Flexcomm4,   /*!< Flexcomm4Clock                                          */
+    kCLOCK_Flexcomm5,   /*!< Flexcomm5Clock                                          */
+    kCLOCK_Flexcomm6,   /*!< Flexcomm6Clock                                          */
+    kCLOCK_Flexcomm7,   /*!< Flexcomm7Clock                                          */
+    kCLOCK_Flexcomm8,   /*!< Flexcomm8Clock                                          */
+    kCLOCK_Flexcomm9,   /*!< Flexcomm9Clock                                          */
+
+} clock_name_t;
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum _async_clock_src
+{
+    kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
+    kCLOCK_AsyncFro12Mhz,    /*!< 12MHz FRO */
+    kCLOCK_AsyncAudioPllClk,
+    kCLOCK_AsyncI2cClkFc6,
+
+} async_clock_src_t;
+
+/*! @brief Clock Mux Switches
+*  The encoding is as follows each connection identified is 64bits wide
+*  starting from LSB upwards
+*
+*  [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
+*
+*/
+
+#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
+#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
+#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
+#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
+#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
+
+#define CM_MAINCLKSELA 0
+#define CM_MAINCLKSELB 1
+#define CM_CLKOUTCLKSELA 2
+#define CM_SYSPLLCLKSEL 4
+#define CM_AUDPLLCLKSEL 6
+#define CM_SPIFICLKSEL 8
+#define CM_ADCASYNCCLKSEL 9
+#define CM_USB0CLKSEL 10
+#define CM_USB1CLKSEL 11
+#define CM_FXCOMCLKSEL0 12
+#define CM_FXCOMCLKSEL1 13
+#define CM_FXCOMCLKSEL2 14
+#define CM_FXCOMCLKSEL3 15
+#define CM_FXCOMCLKSEL4 16
+#define CM_FXCOMCLKSEL5 17
+#define CM_FXCOMCLKSEL6 18
+#define CM_FXCOMCLKSEL7 19
+#define CM_FXCOMCLKSEL8 20
+#define CM_FXCOMCLKSEL9 21
+#define CM_MCLKCLKSEL 24
+#define CM_FRGCLKSEL 26
+#define CM_DMICCLKSEL 27
+#define CM_SCTCLKSEL  28
+#define CM_LCDCLKSEL  29
+#define CM_SDIOCLKSEL 30
+
+#define CM_ASYNCAPB 31
+
+typedef enum _clock_attach_id
+{
+
+    kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
+    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
+    kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
+    kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
+    kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
+    kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
+
+    kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
+    kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
+    kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
+    kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
+    kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
+    kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
+    kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
+    kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
+
+    kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
+    kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
+    kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
+    kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
+    kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
+
+    kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
+    kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
+    kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
+
+    kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
+    kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
+    kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
+    kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
+    kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
+    kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
+
+    kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
+    kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
+    kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
+    kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
+    kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
+
+    kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
+    kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
+    kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
+    kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
+
+    kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
+    kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
+    kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
+    kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
+
+    kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
+    kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
+    kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
+    kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
+    kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
+    kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
+
+    kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
+    kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
+    kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
+    kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
+    kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
+    kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
+
+    kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
+    kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
+    kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
+    kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
+    kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
+    kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
+
+    kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
+    kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
+    kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
+    kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
+    kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
+    kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
+
+    kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
+    kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
+    kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
+    kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
+    kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
+    kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
+
+    kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
+    kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
+    kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
+    kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
+    kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
+    kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
+
+    kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
+    kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
+    kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
+    kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
+    kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
+    kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
+
+    kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
+    kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
+    kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
+    kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
+    kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
+    kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
+
+    kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
+    kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
+    kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
+    kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
+    kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
+    kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
+
+    kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
+    kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
+    kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
+    kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
+    kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
+    kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
+
+    kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
+    kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
+    kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
+
+    kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
+    kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
+    kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
+    kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
+    kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
+
+    kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
+    kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
+    kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
+    kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
+    kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
+
+    kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
+    kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
+    kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
+    kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
+    kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
+
+    kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
+    kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
+    kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
+    kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
+    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
+    kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
+
+    kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
+    kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
+    kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
+    kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
+
+    kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
+    kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
+    kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
+    kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
+    kNONE_to_NONE = 0x80000000U,
+} clock_attach_id_t;
+
+/*  Clock dividers */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivSystickClk = 0,
+    kCLOCK_DivArmTrClkDiv = 1,
+    kCLOCK_DivCan0Clk = 2,
+    kCLOCK_DivCan1Clk = 3,
+    kCLOCK_DivSmartCard0Clk = 4,
+    kCLOCK_DivSmartCard1Clk = 5,
+    kCLOCK_DivAhbClk = 32,
+    kCLOCK_DivClkOut = 33,
+    kCLOCK_DivFrohfClk = 34,
+    kCLOCK_DivSpifiClk = 36,
+    kCLOCK_DivAdcAsyncClk = 37,
+    kCLOCK_DivUsb0Clk = 38,
+    kCLOCK_DivUsb1Clk = 39,
+    kCLOCK_DivFrg = 40,
+    kCLOCK_DivDmicClk = 42,
+    kCLOCK_DivMClk = 43,
+    kCLOCK_DivLcdClk = 44,
+    kCLOCK_DivSctClk = 45,
+    kCLOCK_DivEmcClk = 46,
+    kCLOCK_DivSdioClk = 47
+} clock_div_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3)
+    {
+        SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3)
+    {
+        SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
+
+    }
+}
+/**
+ * @brief FLASH Access time definitions
+ */
+typedef enum _clock_flashtim
+{
+    kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
+    kCLOCK_Flash2Cycle,     /*!< Flash accesses use 2 CPU clocks */
+    kCLOCK_Flash3Cycle,     /*!< Flash accesses use 3 CPU clocks */
+    kCLOCK_Flash4Cycle,     /*!< Flash accesses use 4 CPU clocks */
+    kCLOCK_Flash5Cycle,     /*!< Flash accesses use 5 CPU clocks */
+    kCLOCK_Flash6Cycle,     /*!< Flash accesses use 6 CPU clocks */
+    kCLOCK_Flash7Cycle,     /*!< Flash accesses use 7 CPU clocks */
+    kCLOCK_Flash8Cycle,     /*!< Flash accesses use 8 CPU clocks */
+    kCLOCK_Flash9Cycle      /*!< Flash accesses use 9 CPU clocks */
+} clock_flashtim_t;
+
+/**
+ * @brief	Set FLASH memory access time in clocks
+ * @param	clks	: Clock cycles for FLASH access
+ * @return	Nothing
+ */
+static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
+{
+    uint32_t tmp;
+
+    tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
+
+    /* Don't alter lower bits */
+    SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
+}
+
+/**
+ * @brief	Initialize the Core clock to given frequency (12, 48 or 96 MHz).
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
+ * enabled.
+ * @param	iFreq	: Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
+ * @return	returns success or fail status.
+ */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq);
+/**
+ * @brief	Configure the clock selection muxes.
+ * @param	connection	: Clock to be configured.
+ * @return	Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+/**
+ * @brief	Setup peripheral clock dividers.
+ * @param	div_name	: Clock divider name
+ * @param divided_by_value: Value to be divided
+ * @param reset :  Whether to reset the divider counter.
+ * @return	Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+/**
+ * @brief	Set the flash wait states for the input freuqency.
+ * @param	iFreq	: Input frequency
+ * @return	Nothing
+ */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
+/*! @brief	Return Frequency of selected clock
+ *  @return	Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+/*! @brief	Return Frequency of FRO 12MHz
+ *  @return	Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void);
+/*! @brief	Return Frequency of ClockOut
+ *  @return	Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void);
+/*! @brief	Return Frequency of Spifi Clock
+ *  @return	Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void);
+/*! @brief	Return Frequency of Adc Clock
+ *  @return	Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void);
+/*! @brief	Return Frequency of Usb0 Clock
+ *  @return	Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void);
+/*! @brief	Return Frequency of Usb1 Clock
+ *  @return	Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void);
+/*! @brief	Return Frequency of MClk Clock
+ *  @return	Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+/*! @brief	Return Frequency of SCTimer Clock
+ *  @return	Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+/*! @brief	Return Frequency of SDIO Clock
+ *  @return	Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void);
+/*! @brief	Return Frequency of LCD Clock
+ *  @return	Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void);
+/*! @brief	Return Frequency of LCD CLKIN Clock
+ *  @return	Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void);
+/*! @brief	Return Frequency of External Clock
+ *  @return	Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+/*! @brief	Return Frequency of Watchdog Oscillator
+ *  @return	Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void);
+/*! @brief	Return Frequency of High-Freq output of FRO
+ *  @return	Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void);
+/*! @brief	Return Frequency of PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void);
+/*! @brief	Return Frequency of USB PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void);
+/*! @brief	Return Frequency of AUDIO PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void);
+/*! @brief	Return Frequency of 32kHz osc
+ *  @return	Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void);
+/*! @brief	Return Frequency of Core System
+ *  @return	Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+/*! @brief	Return Frequency of I2S MCLK Clock
+ *  @return	Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void);
+/*! @brief	Return Frequency of Flexcomm functional Clock
+ *  @return	Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+/*! @brief	Return Asynchronous APB Clock source
+ *  @return	Asynchronous APB CLock source
+ */
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
+{
+    return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
+}
+/*! @brief	Return Frequency of Asynchronous APB Clock
+ *  @return	Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void);
+/*! @brief	Return Audio PLL input clock rate
+ *  @return	Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void);
+/*! @brief	Return System PLL input clock rate
+ *  @return	System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void);
+
+/*! @brief	Return System PLL output clock rate
+ *  @param	recompute	: Forces a PLL rate recomputation if true
+ *  @return	System PLL output clock rate
+ *  @note	The PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
+
+/*! @brief	Return System AUDIO PLL output clock rate
+ *  @param	recompute	: Forces a AUDIO PLL rate recomputation if true
+ *  @return	System AUDIO PLL output clock rate
+ *  @note	The AUDIO PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
+
+/*! @brief	Return System USB PLL output clock rate
+ *  @param	recompute	: Forces a USB PLL rate recomputation if true
+ *  @return	System USB PLL output clock rate
+ *  @note	The USB PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute);
+
+/*! @brief	Enables and disables PLL bypass mode
+ *  @brief	bypass	: true to bypass PLL (PLL output = PLL input, false to disable bypass
+ *  @return	System PLL output clock rate
+ */
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
+{
+    if (bypass)
+    {
+        SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+    else
+    {
+        SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+}
+
+/*! @brief	Check if PLL is locked or not
+ *  @return	true if the PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
+{
+    return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Check if USB PLL is locked or not
+ *  @return	true if the USB PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
+{
+    return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Check if AUDIO PLL is locked or not
+ *  @return	true if the AUDIO PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
+{
+    return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Enables and disables SYS OSC
+ *  @brief	enable	: true to enable SYS OSC, false to disable SYS OSC
+*/
+__STATIC_INLINE  void CLOCK_Enable_SysOsc(bool enable)
+{
+    if(enable)
+    {
+        SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+    }
+
+    else
+    {
+        SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+
+    }
+}
+
+/*! @brief Store the current PLL rate
+ *  @param	rate: Current rate of the PLL
+ *  @return	Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);
+
+/*! @brief Store the current AUDIO PLL rate
+ *  @param	rate: Current rate of the PLL
+ *  @return	Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
+
+/*! @brief PLL configuration structure flags for 'flags' field
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
+ *
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
+ * configuration structure must be assigned with the expected PLL frequency. If the
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
+ * function and the driver will determine the PLL rate from the currently selected
+ * PLL source. This flag might be used to configure the PLL input clock more accurately
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
+ *
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
+ * are not used.<br>
+ */
+#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
+#define PLL_CONFIGFLAG_FORCENOFRACT                                                                                    \
+    (1                                                                                                                 \
+     << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
+                \ \ \                                                                                                                     \
+                  \ \ \ \ \                                                                                                                     \
+                    \ \ \ \ \ \ \                                                                                                                     \
+                      hardware */
+
+/*! @brief PLL configuration structure
+ *
+ * This structure can be used to configure the settings for a PLL
+ * setup structure. Fill in the desired configuration for the PLL
+ * and call the PLL setup function to fill in a PLL setup structure.
+ */
+typedef struct _pll_config
+{
+    uint32_t desiredRate; /*!< Desired PLL rate in Hz */
+    uint32_t inputRate;   /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
+    uint32_t flags;       /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
+} pll_config_t;
+
+/*! @brief PLL setup structure flags for 'flags' field
+* These flags control how the PLL setup function sets up the PLL
+*/
+#define PLL_SETUPFLAG_POWERUP (1 << 0)  /*!< Setup will power on the PLL after setup */
+#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
+#define PLL_SETUPFLAG_ADGVOLT (1 << 2)  /*!< Optimize system voltage for the new PLL rate */
+
+/*! @brief PLL setup structure
+* This structure can be used to pre-build a PLL setup configuration
+* at run-time and quickly set the PLL to the configuration. It can be
+* populated with the PLL setup function. If powering up or waiting
+* for PLL lock, the PLL input clock source should be configured prior
+* to PLL setup.
+*/
+typedef struct _pll_setup
+{
+    uint32_t pllctrl;         /*!< PLL control register SYSPLLCTRL */
+    uint32_t pllndec;         /*!< PLL NDEC register SYSPLLNDEC */
+    uint32_t pllpdec;         /*!< PLL PDEC register SYSPLLPDEC */
+    uint32_t pllmdec;         /*!< PLL MDEC registers SYSPLLPDEC */
+    uint32_t pllRate;         /*!< Acutal PLL rate */
+    uint32_t audpllfrac;      /*!< only aduio PLL has this function*/
+    uint32_t flags;           /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
+} pll_setup_t;
+
+/*! @brief PLL status definitions
+ */
+typedef enum _pll_error
+{
+    kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),         /*!< PLL operation was successful */
+    kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),    /*!< PLL output rate request was too low */
+    kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),   /*!< PLL output rate request was too high */
+    kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),     /*!< PLL input rate is too low */
+    kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),    /*!< PLL input rate is too high */
+    kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
+    kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6),       /*!< Requested CCO rate isn't possible */
+    kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7)       /*!< Requested CCO rate isn't possible */
+} pll_error_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,            /*!< Use FRO 96 or 48 MHz. */
+    kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,     /*!< Use System PLL output. */
+    kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock.    */
+    kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll,        /*!< Use USB PLL clock.    */
+
+    kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7)          /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
+} clock_usb_src_t;
+
+/*! @brief USB PDEL Divider. */
+typedef enum _usb_pll_psel
+{
+    pSel_Divide_1 = 0U,
+    pSel_Divide_2,
+    pSel_Divide_4,
+    pSel_Divide_8
+}usb_pll_psel;
+
+/*! @brief PLL setup structure
+* This structure can be used to pre-build a USB PLL setup configuration
+* at run-time and quickly set the usb PLL to the configuration. It can be
+* populated with the USB PLL setup function. If powering up or waiting
+* for USB PLL lock, the PLL input clock source should be configured prior
+* to USB PLL setup.
+*/
+typedef struct _usb_pll_setup
+{
+  uint8_t msel;           /*!< USB PLL control register msel:1U-256U */
+  uint8_t psel;           /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
+  uint8_t nsel;           /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
+  bool direct;            /*!< USB PLL CCO output control */
+  bool bypass;            /*!< USB PLL inout clock bypass control  */
+  bool fbsel;             /*!< USB PLL ineter mode and non-integer mode control*/
+  uint32_t inputRate;     /*!< USB PLL input rate */
+} usb_pll_setup_t;
+
+/*! @brief	Return System PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief	Return System AUDIO PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief	Return System USB PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the passed PLL setup data
+ *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
+ *  @param	pSetup		: Pointer to PLL setup structure to be filled
+ *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note	Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief	Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
+ *  @param	pSetup		: Pointer to PLL setup structure to be filled
+ *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note	Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief	Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/**
+ * @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+ * @return	kStatus_PLL_Success on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief	Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+ * @return	kStatus_PLL_Success on success, or Audio PLL setup error code
+ * @note	This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief	Set USB PLL output from USB PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated USB PLL setup structure
+ * @return	kStatus_PLL_Success on success, or USB PLL setup error code
+ * @note	This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the multiplier and input frequency
+ * @param	multiply_by	: multiplier
+ * @param	input_freq	: Clock input frequency of the PLL
+ * @return	Nothing
+ * @note	Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
+
+/*! @brief Disable USB clock.
+ *
+ * Disable USB clock.
+ */
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
+{
+    CLOCK_DisableClock(clk);
+}
+
+/*! @brief Enable USB Device FS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST FS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB Device HS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST HS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+/* This is not needed for mbed */
+#if 0
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif(defined(__REDLIB__))
+
+#if SDK_DEBUGCONSOLE
+void __assertion_failed(char *_Expr)
+{
+    PRINTF("%s\n", _Expr);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#endif
+
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+#endif
+#ifndef __GIC_PRIO_BITS
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif
+
+#ifndef CPU_QN908X
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+#else
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    /*   SYSCON->STARTERSET[index] = 1u << intNumber; */
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+                           /*   SYSCON->STARTERCLR[index] = 1u << intNumber; */
+}
+#endif /*CPU_QN908X */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+        NVIC_DisableIRQ(interrupt);
+#endif
+    }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
+/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
+#define CRC_DRIVER_DEFAULT_REVERSE_IN false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
+/*< Default is without complement of written data */
+#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to CRC */
+    CLOCK_EnableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* configure CRC module and write the seed */
+    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
+                 CRC_MODE_CMPL_SUM(config->complementOut);
+    base->SEED = config->seed;
+}
+
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
+
+    *config = default_config;
+}
+
+void CRC_Reset(CRC_Type *base)
+{
+    crc_config_t config;
+    CRC_GetDefaultConfig(&config);
+    CRC_Init(base, &config);
+}
+
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
+{
+    /* extract CRC mode settings */
+    uint32_t mode = base->MODE;
+    config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
+    config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
+    config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
+    config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
+    config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
+
+    /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
+    base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
+
+    /* now we can obtain intermediate raw CRC sum value */
+    config->seed = base->SUM;
+
+    /* restore original CRC sum bit reverse and 1's complement setting */
+    base->MODE = mode;
+}
+
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((dataSize) && ((uint32_t)data & 3U))
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        *((__O uint32_t *)&(base->WR_DATA)) = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize)
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ * - Version 2.0.1
+ *   - add explicit type cast when writing to WR_DATA
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
+#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC polynomials to use. */
+typedef enum _crc_polynomial
+{
+    kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
+    kCRC_Polynomial_CRC_16 = 1U,    /*!< x^16+x^15+x^2+1 */
+    kCRC_Polynomial_CRC_32 = 2U     /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
+} crc_polynomial_t;
+
+/*!
+* @brief CRC protocol configuration.
+*
+* This structure holds the configuration for the CRC protocol.
+*
+*/
+typedef struct _crc_config
+{
+    crc_polynomial_t polynomial; /*!< CRC polynomial. */
+    bool reverseIn;              /*!< Reverse bits on input. */
+    bool complementIn;           /*!< Perform 1's complement on input. */
+    bool reverseOut;             /*!< Reverse bits on output. */
+    bool complementOut;          /*!< Perform 1's complement on output. */
+    uint32_t seed;               /*!< Starting checksum value. */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the CRC peripheral clock in the LPC SYSCON block.
+ * It also configures the CRC engine and starts checksum computation by writing the seed.
+ *
+ * @param base   CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This functions disables the CRC peripheral clock in the LPC SYSCON block.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* disable clock to CRC */
+    CLOCK_DisableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief resets CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ */
+void CRC_Reset(CRC_Type *base);
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
+ *   config->reverseIn = false;
+ *   config->complementIn = false;
+ *   config->reverseOut = false;
+ *   config->complementOut = false;
+ *   config->seed = 0xFFFFU;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
+ *
+ * The values, including seed, can be used to resume CRC calculation later.
+
+ * @param base   CRC peripheral address.
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ *
+ * @param base     CRC peripheral address.
+ * @param data     Input data stream, MSByte in data[0].
+ * @param dataSize Size of the input data buffer in bytes.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 32-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->SUM;
+}
+
+/*!
+ * @brief Reads 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 16-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    return (uint16_t)base->SUM;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ctimer.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The Timer instance
+ */
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to Timer bases for each instance. */
+static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to Timer clocks for each instance. */
+static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to Timer resets for each instance. */
+static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
+
+/*! @brief Pointers real ISRs installed by drivers for each instance. */
+static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
+
+/*! @brief Callback type installed by drivers for each instance. */
+static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
+
+/*! @brief Array to map timer instance to IRQ number. */
+static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
+{
+    uint32_t instance;
+    uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ctimerArrayCount; instance++)
+    {
+        if (s_ctimerBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ctimerArrayCount);
+
+    return instance;
+}
+
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the timer clock*/
+    CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
+
+    /* Setup the cimer mode and count select */
+    base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
+
+    /* Setup the timer prescale value */
+    base->PR = CTIMER_PR_PRVAL(config->prescale);
+}
+
+void CTIMER_Deinit(CTIMER_Type *base)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    /* Stop the timer */
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the timer clock*/
+    CLOCK_DisableClock(s_ctimerClocks[index]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable IRQ at NVIC Level */
+    DisableIRQ(s_ctimerIRQ[index]);
+}
+
+void CTIMER_GetDefaultConfig(ctimer_config_t *config)
+{
+    assert(config);
+
+    /* Run as a timer */
+    config->mode = kCTIMER_TimerMode;
+    /* This field is ignored when mode is timer */
+    config->input = kCTIMER_Capture_0;
+    /* Timer counter is incremented on every APB bus clock */
+    config->prescale = 0;
+}
+
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt)
+{
+    assert(pwmFreq_Hz > 0);
+
+    uint32_t reg;
+    uint32_t period, pulsePeriod = 0;
+    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
+    uint32_t index = CTIMER_GetInstance(base);
+
+    if (matchChannel == kCTIMER_Match_3)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Enable PWM mode on the channel */
+    base->PWMC |= (1U << matchChannel);
+
+    /* Clear the stop, reset and interrupt bits for this channel */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+
+    /* If call back function is valid then enable match interrupt for the channel */
+    if (enableInt)
+    {
+        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    }
+
+    /* Reset the counter when match on channel 3 */
+    reg |= CTIMER_MCR_MR3R_MASK;
+
+    base->MCR = reg;
+
+    /* Calculate PWM period match value */
+    period = (timerClock / pwmFreq_Hz) - 1;
+
+    /* Calculate pulse width match value */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Match on channel 3 will define the PWM period */
+    base->MR[kCTIMER_Match_3] = period;
+
+    /* This will define the PWM pulse period */
+    base->MR[matchChannel] = pulsePeriod;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If call back function is valid then enable interrupt and update the call back function */
+    if (enableInt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+
+    return kStatus_Success;
+}
+
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
+{
+    uint32_t pulsePeriod = 0, period;
+
+    /* Match channel 3 defines the PWM period */
+    period = base->MR[kCTIMER_Match_3];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Update dutycycle */
+    base->MR[matchChannel] = pulsePeriod;
+}
+
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
+{
+    uint32_t reg;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the counter operation when a match on this channel occurs */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    base->MCR = reg;
+
+    reg = base->EMR;
+    /* Set the match output operation when a match on this channel occurs */
+    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
+    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
+
+    /* Set the initial state of the EM bit/output */
+    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
+    reg |= (uint32_t)config->outPinInitState << matchChannel;
+    base->EMR = reg;
+
+    /* Set the match value */
+    base->MR[matchChannel] = config->matchValue;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If interrupt is enabled then enable interrupt and update the call back function */
+    if (config->enableInterrupt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+}
+
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt)
+{
+    uint32_t reg = base->CCR;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the capture edge */
+    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
+    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
+    /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
+    if (enableInt)
+    {
+        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+    base->CCR = reg;
+}
+
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    s_ctimerCallback[index] = cb_func;
+    ctimerCallbackType[index] = cb_type;
+}
+
+void CTIMER_GenericIRQHandler(uint32_t index)
+{
+    uint32_t int_stat, i, mask;
+    /* Get Interrupt status flags */
+    int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
+    /* Clear the status flags that were set */
+    CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
+    if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
+    {
+        if (s_ctimerCallback[index][0])
+        {
+            s_ctimerCallback[index][0](int_stat);
+        }
+    }
+    else
+    {
+        for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
+        {
+            mask = 0x01 << i;
+            /* For each status flag bit that was set call the callback function if it is valid */
+            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
+            {
+                s_ctimerCallback[index][i](int_stat);
+            }
+        }
+    }
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(CTIMER0)
+void CTIMER0_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(0);
+}
+#endif
+
+#if defined(CTIMER1)
+void CTIMER1_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(1);
+}
+#endif
+
+#if defined(CTIMER2)
+void CTIMER2_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(2);
+}
+#endif
+
+#if defined(CTIMER3)
+void CTIMER3_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(3);
+}
+#endif
+
+#if defined(CTIMER4)
+void CTIMER4_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(4);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_CTIMER_H_
+#define _FSL_CTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of Timer capture channels */
+typedef enum _ctimer_capture_channel
+{
+    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
+    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
+    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+    kCTIMER_Capture_3       /*!< Timer capture channel 3 */
+} ctimer_capture_channel_t;
+
+/*! @brief List of capture edge options */
+typedef enum _ctimer_capture_edge
+{
+    kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
+    kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
+    kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
+} ctimer_capture_edge_t;
+
+/*! @brief List of Timer match registers */
+typedef enum _ctimer_match
+{
+    kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
+    kCTIMER_Match_1,      /*!< Timer match register 1 */
+    kCTIMER_Match_2,      /*!< Timer match register 2 */
+    kCTIMER_Match_3       /*!< Timer match register 3 */
+} ctimer_match_t;
+
+/*! @brief List of output control options */
+typedef enum _ctimer_match_output_control
+{
+    kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
+    kCTIMER_Output_Clear,         /*!< Clear the EM bit/output to 0 */
+    kCTIMER_Output_Set,           /*!< Set the EM bit/output to 1 */
+    kCTIMER_Output_Toggle         /*!< Toggle the EM bit/output */
+} ctimer_match_output_control_t;
+
+/*! @brief List of Timer modes */
+typedef enum _ctimer_timer_mode
+{
+    kCTIMER_TimerMode = 0U,     /* TC is incremented every rising APB bus clock edge */
+    kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
+    kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
+    kCTIMER_IncreaseOnBothEdge  /* TC is incremented on both edges of input signal */
+} ctimer_timer_mode_t;
+
+/*! @brief List of Timer interrupts */
+typedef enum _ctimer_interrupt_enable
+{
+    kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK,    /*!< Match 0 interrupt */
+    kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK,    /*!< Match 1 interrupt */
+    kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK,    /*!< Match 2 interrupt */
+    kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK,    /*!< Match 3 interrupt */
+    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
+    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
+} ctimer_interrupt_enable_t;
+
+/*! @brief List of Timer flags */
+typedef enum _ctimer_status_flags
+{
+    kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK,   /*!< Match 0 interrupt flag */
+    kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK,   /*!< Match 1 interrupt flag */
+    kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK,   /*!< Match 2 interrupt flag */
+    kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK,   /*!< Match 3 interrupt flag */
+    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
+    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
+} ctimer_status_flags_t;
+
+typedef void (*ctimer_callback_t)(uint32_t flags);
+
+/*! @brief Callback type when registering for a callback. When registering a callback
+ *         an array of function pointers is passed the size could be 1 or 8, the callback
+ *         type will tell that.
+ */
+typedef enum
+{
+    kCTIMER_SingleCallback,  /*!< Single Callback type where there is only one callback for the timer. 
+                                 based on the status flags different channels needs to be handled differently */
+    kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. 
+                                 for both match/capture */
+} ctimer_callback_type_t;
+
+/*!
+ * @brief Match configuration
+ *
+ * This structure holds the configuration settings for each match register.
+ */
+typedef struct _ctimer_match_config
+{
+    uint32_t matchValue;                      /*!< This is stored in the match register */
+    bool enableCounterReset;                  /*!< true: Match will reset the counter
+                                                   false: Match will not reser the counter */
+    bool enableCounterStop;                   /*!< true: Match will stop the counter
+                                                   false: Match will not stop the counter */
+    ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
+    bool outPinInitState;                     /*!< Initial value of the EM bit/output */
+    bool enableInterrupt;                     /*!< true: Generate interrupt upon match
+                                                   false: Do not generate interrupt on match */
+
+} ctimer_match_config_t;
+
+/*!
+ * @brief Timer configuration structure
+ *
+ * This structure holds the configuration settings for the Timer peripheral. To initialize this
+ * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _ctimer_config
+{
+    ctimer_timer_mode_t mode;       /*!< Timer mode */
+    ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
+                                        modes that rely on this input signal to increment TC */
+    uint32_t prescale;              /*!< Prescale value */
+} ctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application before using the driver.
+ *
+ * @param base   Ctimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
+
+/*!
+ * @brief Gates the timer clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+void CTIMER_Deinit(CTIMER_Type *base);
+
+/*!
+ * @brief  Fills in the timers configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *   config->mode = kCTIMER_TimerMode;
+ *   config->input = kCTIMER_Capture_0;
+ *   config->prescale = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_GetDefaultConfig(ctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * @note When setting PWM output from multiple output pins, all should use the same PWM
+ * frequency
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
+ * @param pwmFreq_Hz       PWM signal frequency in Hz
+ * @param srcClock_Hz      Timer counter clock in Hz
+ * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ */
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
+ */
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+
+/*! @}*/
+
+/*!
+ * @brief Setup the match register.
+ *
+ * User configuration is used to setup the match value and action to be taken when a match occurs.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel Match register to configure
+ * @param config       Pointer to the match configuration structure
+ */
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
+
+/*!
+ * @brief Setup the capture.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param capture   Capture channel to configure
+ * @param edge      Edge on the channel that will trigger a capture
+ * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
+ *                  is called upon capture
+ */
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt);
+
+/*!
+ * @brief Register callback.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param cb_func   callback function
+ * @param cb_type   callback function type, singular or multiple
+ */
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Enable match interrupts */
+    base->MCR |= mask;
+
+    /* Enable capture interrupts */
+    base->CCR |= mask;
+}
+
+/*!
+ * @brief Disables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Disable match interrupts */
+    base->MCR &= ~mask;
+
+    /* Disable capture interrupts */
+    base->CCR &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::ctimer_interrupt_enable_t
+ */
+static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
+{
+    uint32_t enabledIntrs = 0;
+
+    /* Get all the match interrupts enabled */
+    enabledIntrs =
+        base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT);
+
+    /* Get all the capture interrupts enabled */
+    enabledIntrs |=
+        base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT);
+
+    return enabledIntrs;
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::ctimer_status_flags_t
+ */
+static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
+{
+    return base->IR;
+}
+
+/*!
+ * @brief Clears the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::ctimer_status_flags_t
+ */
+static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
+{
+    base->IR = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StartTimer(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CEN_MASK;
+}
+
+/*!
+ * @brief Stops the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StopTimer(CTIMER_Type *base)
+{
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Reset the counter.
+ *
+ * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_Reset(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CRST_MASK;
+    base->TCR &= ~CTIMER_TCR_CRST_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMA.
+ *
+ * @param base DMA peripheral base address.
+ */
+static int32_t DMA_GetInstance(DMA_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMA instance number to base pointer. */
+static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
+
+/*! @brief Array to map DMA instance number to IRQ number. */
+static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
+
+/*! @brief Pointers to transfer handle for each DMA channel. */
+static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS];
+
+/*! @brief Static table of descriptors */
+#if defined(__ICCARM__)
+#pragma data_alignment = 512
+dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static int32_t DMA_GetInstance(DMA_Type *base)
+{
+    int32_t instance;
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
+    {
+        if (s_dmaBases[instance] == base)
+        {
+            break;
+        }
+    }
+    assert(instance < ARRAY_SIZE(s_dmaBases));
+    return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1;
+}
+
+void DMA_Init(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable dma clock gate */
+    CLOCK_EnableClock(kCLOCK_Dma);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    /* set descriptor table */
+    base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
+    /* enable dma peripheral */
+    base->CTRL |= DMA_CTRL_ENABLE_MASK;
+}
+
+void DMA_Deinit(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable DMA peripheral */
+    base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
+{
+    assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
+
+    uint32_t tmp = (
+        DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+        DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
+        DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK
+    );
+    tmp = base->CHANNEL[channel].CFG & (~tmp);
+    tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
+    base->CHANNEL[channel].CFG = tmp;
+}
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+
+    /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes 
+     * impossible to distinguish between:
+     * - transfer finishes (represented by value '0x3FF')
+     * - and remaining 1024 bytes to transfer (value 0x3FF)
+     * for all descriptor in chain, except the last one.
+     * If you decide to use this function, please use 1023 transfers as maximal value */
+
+    /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
+    if (
+        (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && 
+        (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))
+    )
+    {
+        return 0;
+    }
+
+    return base->CHANNEL[channel].XFERCFG + 1;
+}
+
+static void DMA_SetupDescriptor(
+    dma_descriptor_t    *desc,
+    uint32_t            xfercfg,
+    void                *srcEndAddr,
+    void                *dstEndAddr,
+    void                *nextDesc
+)
+{
+    desc->xfercfg = xfercfg;
+    desc->srcEndAddr = srcEndAddr;
+    desc->dstEndAddr = dstEndAddr;
+    desc->linkToNextDesc = nextDesc;
+}
+
+/* Verify and convert dma_xfercfg_t to XFERCFG register */
+static void DMA_SetupXferCFG(
+    dma_xfercfg_t *xfercfg,
+    uint32_t *xfercfg_addr
+)
+{
+    assert(xfercfg != NULL);
+    /* check source increment */
+    assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
+    /* check destination increment */
+    assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
+    /* check data width */
+    assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
+    /* check transfer count */
+    assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
+
+    uint32_t xfer = 0, tmp;
+    /* set valid flag - descriptor is ready now */
+    xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
+    /* set reload - allow link to next descriptor */
+    xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
+    /* set swtrig flag - start transfer */
+    xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0);
+    /* set INTA */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
+    /* set INTB */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
+    /* set data width */
+    tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
+    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
+    /* set source increment value */
+    tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
+    xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
+    /* set destination increment value */
+    tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
+    xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
+
+    /* store xferCFG */
+    *xfercfg_addr = xfer;
+}
+
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+)
+{
+    uint32_t xfercfg_reg = 0;
+
+    assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
+    assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
+    assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
+    assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
+
+    /* Setup channel configuration */
+    DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
+
+    /* Set descriptor structure */
+    DMA_SetupDescriptor(desc, xfercfg_reg,
+        (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        nextDesc
+    );
+}
+
+void DMA_AbortTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    DMA_DisableChannel(handle->base, handle->channel);
+    while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
+    { }
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+    DMA_EnableChannel(handle->base, handle->channel);
+}
+
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+    int32_t dmaInstance;
+    assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS));
+
+    /* base address is invalid DMA instance */
+    dmaInstance = DMA_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    handle->base = base;
+    handle->channel = channel;
+    s_DMAHandle[channel] = handle;
+    /* Enable NVIC interrupt */
+    EnableIRQ(s_dmaIRQNumber[dmaInstance]);
+}
+
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc)
+{
+    uint32_t xfer_count;
+    assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
+    assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
+
+    /* check max */
+    xfer_count = transferBytes / byteWidth;
+    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
+
+    memset(config, 0, sizeof(*config));
+    switch (type)
+    {
+    case kDMA_MemoryToMemory:
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = false;
+        break;
+    case kDMA_PeripheralToMemory:
+        /* Peripheral register - source doesn't increment */
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = true;
+        break;
+    case kDMA_MemoryToPeripheral:
+        /* Peripheral register - destination doesn't increment */
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    case kDMA_StaticToStatic:
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    default:
+        return;
+    }
+
+    config->dstAddr = (uint8_t*)dstAddr;
+    config->srcAddr = (uint8_t*)srcAddr;
+    config->nextDesc = (uint8_t*)nextDesc;
+    config->xfercfg.transferCount = xfer_count;
+    config->xfercfg.byteWidth = byteWidth;
+    config->xfercfg.intA = true;
+    config->xfercfg.reload = nextDesc != NULL;
+    config->xfercfg.valid = true;
+}
+
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
+{
+    assert((NULL != handle) && (NULL != config));
+
+    /* Previous transfer has not finished */
+    if (DMA_ChannelIsActive(handle->base, handle->channel))
+    {
+         return kStatus_DMA_Busy;
+    }
+
+    /* enable/disable peripheral request */
+    if (config->isPeriph)
+    {
+        DMA_EnableChannelPeriphRq(handle->base, handle->channel);
+    }
+    else
+    {
+        DMA_DisableChannelPeriphRq(handle->base, handle->channel);
+    }
+
+    DMA_CreateDescriptor(
+        &s_dma_descriptor_table[ handle->channel ], &config->xfercfg,
+        config->srcAddr, config->dstAddr, config->nextDesc
+    );
+
+    return kStatus_Success;
+}
+
+void DMA_StartTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Enable channel interrupt */
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+
+    /* If HW trigger is enabled - disable SW trigger */
+    if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
+    }
+    /* Otherwise enable SW trigger */
+    else
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
+    }
+
+    /* Set channel XFERCFG register according first channel descriptor. */
+    handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg;
+    /* At this moment, the channel ACTIVE bit is set and application cannot modify 
+     * or start another transfer using this channel. Channel ACTIVE bit is cleared by 
+    * 'AbortTransfer' function or when the transfer finishes */
+}
+
+void DMA0_DriverIRQHandler(void)
+{
+    dma_handle_t *handle;
+    int32_t channel_group;
+    int32_t channel_index;
+
+    /* Find channels that have completed transfer */
+    for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++)
+    {
+        handle = s_DMAHandle[i];
+        /* Handle is not present */
+        if (NULL == handle)
+        {
+            continue;
+        }
+        channel_group = DMA_CHANNEL_GROUP(handle->channel);
+        channel_index = DMA_CHANNEL_INDEX(handle->channel);
+        /* Channel uses INTA flag */
+        if (handle->base->COMMON[channel_group].INTA & (1U << channel_index))
+        {
+            /* Clear INTA flag */
+            handle->base->COMMON[channel_group].INTA = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntA);
+            }
+        }
+        /* Channel uses INTB flag */
+        if (handle->base->COMMON[channel_group].INTB & (1U << channel_index))
+        {
+            /* Clear INTB flag */
+            handle->base->COMMON[channel_group].INTB = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntB);
+            }
+        }
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,476 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMA_H_
+#define _FSL_DMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dma
+ * @{
+ */
+
+/*! @file */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DMA driver version */
+#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+#define DMA_MAX_TRANSFER_COUNT 0x400
+
+/* Channel group consists of 32 channels. channel_group = (channel / 32) */
+#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
+/* Channel index in channel group. channel_index = (channel % 32) */
+#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
+
+
+/*! @brief DMA descriptor structure */
+typedef struct _dma_descriptor {
+    uint32_t xfercfg;       /*!< Transfer configuration */
+    void *srcEndAddr;       /*!< Last source address of DMA transfer */
+    void *dstEndAddr;       /*!< Last destination address of DMA transfer */
+    void *linkToNextDesc;   /*!< Address of next DMA descriptor in chain */
+} dma_descriptor_t;
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_xfercfg {
+    bool valid;             /*!< Descriptor is ready to transfer */
+    bool reload;            /*!< Reload channel configuration register after
+                                 current descriptor is exhausted */
+    bool swtrig;            /*!< Perform software trigger. Transfer if fired
+                                 when 'valid' is set */
+    bool clrtrig;           /*!< Clear trigger */
+    bool intA;              /*!< Raises IRQ when transfer is done and set IRQA status register flag */
+    bool intB;              /*!< Raises IRQ when transfer is done and set IRQB status register flag */
+    uint8_t byteWidth;      /*!< Byte width of data to transfer */
+    uint8_t srcInc;         /*!< Increment source address by 'srcInc' x 'byteWidth' */
+    uint8_t dstInc;         /*!< Increment destination address by 'dstInc' x 'byteWidth' */
+    uint16_t transferCount; /*!< Number of transfers */
+} dma_xfercfg_t;
+
+/*! @brief DMA channel priority */
+typedef enum _dma_priority {
+    kDMA_ChannelPriority0 = 0,  /*!< Highest channel priority - priority 0 */
+    kDMA_ChannelPriority1,      /*!< Channel priority 1 */
+    kDMA_ChannelPriority2,      /*!< Channel priority 2 */
+    kDMA_ChannelPriority3,      /*!< Channel priority 3 */
+    kDMA_ChannelPriority4,      /*!< Channel priority 4 */
+    kDMA_ChannelPriority5,      /*!< Channel priority 5 */
+    kDMA_ChannelPriority6,      /*!< Channel priority 6 */
+    kDMA_ChannelPriority7,      /*!< Lowest channel priority - priority 7 */
+} dma_priority_t;
+
+/*! @brief DMA interrupt flags */
+typedef enum _dma_int {
+    kDMA_IntA,  /*!< DMA interrupt flag A */
+    kDMA_IntB,  /*!< DMA interrupt flag B */
+} dma_irq_t;
+
+/*! @brief DMA trigger type*/
+typedef enum _dma_trigger_type {
+    kDMA_NoTrigger = 0, /*!< Trigger is disabled */
+    kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
+    kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
+    kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
+    kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
+} dma_trigger_type_t;
+
+/*! @brief DMA trigger burst */
+typedef enum _dma_trigger_burst {
+    kDMA_SingleTransfer = 0,                                                    /*!< Single transfer */
+    kDMA_LevelBurstTransfer  = DMA_CHANNEL_CFG_TRIGBURST(1),                            /*!< Burst transfer driven by level trigger */
+    kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1),                             /*!< Perform 1 transfer by edge trigger */
+    kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1),     /*!< Perform 2 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2),     /*!< Perform 4 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3),     /*!< Perform 8 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4),    /*!< Perform 16 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5),    /*!< Perform 32 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6),    /*!< Perform 64 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7),   /*!< Perform 128 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8),   /*!< Perform 256 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9),   /*!< Perform 512 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
+} dma_trigger_burst_t;  
+
+/*! @brief DMA burst wrapping */
+typedef enum _dma_burst_wrap {
+    kDMA_NoWrap = 0,                                                            /*!< Wrapping is disabled */
+    kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1),                                     /*!< Wrapping is enabled for source */
+    kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1),                                     /*!< Wrapping is enabled for destination */
+    kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1),     /*!< Wrapping is enabled for source and destination */
+} dma_burst_wrap_t;
+
+/*! @brief DMA transfer type */
+typedef enum _dma_transfer_type
+{
+    kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
+    kDMA_PeripheralToMemory,    /*!< Transfer from peripheral to memory (increment only destination) */
+    kDMA_MemoryToPeripheral,    /*!< Transfer from memory to peripheral (increment only source)*/
+    kDMA_StaticToStatic,        /*!< Peripheral to static memory (do not increment source or destination) */
+} dma_transfer_type_t;
+
+/*! @brief DMA channel trigger */
+typedef struct _dma_channel_trigger {
+    dma_trigger_type_t type;
+    dma_trigger_burst_t burst;
+    dma_burst_wrap_t wrap;
+} dma_channel_trigger_t;
+
+/*! @brief DMA transfer status */
+enum _dma_transfer_status
+{
+    kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0),      /*!< Channel is busy and can't handle the
+                                                                     transfer request. */
+};
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_transfer_config
+{
+    uint8_t             *srcAddr;       /*!< Source data address */
+    uint8_t             *dstAddr;       /*!< Destination data address */
+    uint8_t             *nextDesc;      /*!< Chain custom descriptor */
+    dma_xfercfg_t       xfercfg;        /*!< Transfer options */
+    bool                isPeriph;       /*!< DMA transfer is driven by peripheral */
+} dma_transfer_config_t;
+
+/*! @brief Callback for DMA */
+struct _dma_handle;
+
+/*! @brief Define Callback function for DMA. */
+typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*! @brief DMA transfer handle structure */
+typedef struct _dma_handle
+{
+    dma_callback callback;  /*!< Callback function. Invoked when transfer 
+                                of descriptor with interrupt flag finishes */
+    void *userData;         /*!< Callback function parameter */
+    DMA_Type *base;         /*!< DMA peripheral base address */
+    uint8_t channel;        /*!< DMA channel number */
+} dma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMA initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes DMA peripheral.
+ *
+ * This function enable the DMA clock, set descriptor table and
+ * enable DMA peripheral.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Init(DMA_Type *base);
+
+/*!
+ * @brief Deinitializes DMA peripheral.
+ *
+ * This function gates the DMA clock.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Deinit(DMA_Type *base);
+
+/* @} */
+/*!
+ * @name DMA Channel Operation
+ * @{
+ */
+
+ /*!
+ * @brief Return whether DMA channel is processing transfer
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for active state, false otherwise.
+ */
+static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
+}
+
+/*!
+ * @brief Enables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Enable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Set PERIPHREQEN of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Get PERIPHREQEN value of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for enabled PeriphRq, false for disabled.
+ */
+static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Set trigger settings of DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param trigger trigger configuration.
+ */
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Set priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param priority Channel priority value.
+ */
+static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
+}
+
+/*!
+ * @brief Get priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return Channel priority value.
+ */
+static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
+}
+
+/*!
+ * @brief Create application specific DMA descriptor 
+ *        to be used in a chain in transfer
+ *
+ * @param desc DMA descriptor address.
+ * @param xfercfg Transfer configuration for DMA descriptor.
+ * @param srcAddr Address of last item to transmit
+ * @param dstAddr Address of last item to receive.
+ * @param nextDesc Address of next descriptor in chain.
+ */
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+);
+
+/* @} */
+
+/*!
+ * @name DMA Transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Abort running transfer by handle.
+ *
+ * This function aborts DMA transfer specified by handle.
+ *
+ * @param handle DMA handle pointer. 
+ */
+void DMA_AbortTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief Creates the DMA handle.
+ *
+ * This function is called if using transaction API for DMA. This function
+ * initializes the internal state of DMA handle.
+ *
+ * @param handle DMA handle pointer. The DMA handle stores callback function and
+ *               parameters.
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Installs a callback function for the DMA transfer.
+ *
+ * This callback is called in DMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes.
+ *
+ * @param handle DMA handle pointer.
+ * @param callback DMA callback function pointer.
+ * @param userData Parameter for callback function.
+ */
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the DMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config The user configuration structure of type dma_transfer_t.
+ * @param srcAddr DMA transfer source address.
+ * @param dstAddr DMA transfer destination address.
+ * @param byteWidth DMA transfer destination address width(bytes).
+ * @param transferBytes DMA transfer bytes to be transferred.
+ * @param type DMA transfer type.
+ * @param nextDesc Chain custom descriptor to transfer.
+ * @note The data address and the data width must be consistent. For example, if the SRC
+ *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
+ *       source address error(SAE).
+ */
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc);
+
+/*!
+ * @brief Submits the DMA transfer request.
+ *
+ * This function submits the DMA transfer request according to the transfer configuration structure.
+ * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * a TCD and enables scatter/gather feature to process it in the next time.
+ *
+ * @param handle DMA handle pointer.
+ * @param config Pointer to DMA transfer configuration structure.
+ * @retval kStatus_DMA_Success It means submit transfer request succeed.
+ * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
+
+/*!
+ * @brief DMA start transfer.
+ *
+ * This function enables the channel request. User can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle DMA handle pointer.
+ */
+void DMA_StartTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief DMA IRQ handler for descriptor transfer complete.
+ *
+ * This function clears the channel major interrupt flag and call
+ * the callback function if it is not NULL.
+ */
+void DMA_HandleIRQ(void);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of DMIC peripheral base address. */
+static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS;
+
+/* Array of DMIC clock name. */
+static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS;
+
+/* Array of DMIC IRQ number. */
+static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS;
+
+/*! @brief Callback function array for DMIC(s). */
+static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/* Array of HWVAD IRQ number. */
+static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS;
+
+/*! @brief Callback function array for HWVAD(s). */
+static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++)
+    {
+        if (s_dmicBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dmicBases));
+
+    return instance;
+}
+
+void DMIC_Init(DMIC_Type *base)
+{
+    assert(base);
+
+    /* Enable the clock to the register interface */
+    CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
+
+    /* Disable DMA request*/
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+
+    /* Disable DMIC interrupt. */
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+}
+
+void DMIC_DeInit(DMIC_Type *base)
+{
+    assert(base);
+    /* Disable the clock to the register interface */
+    CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]);
+}
+
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config)
+{
+    base->IOCFG = config;
+}
+
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode)
+{
+    if (mode == kDMIC_OperationModeInterrupt)
+    {
+        /* Enable DMIC interrupt. */
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    }
+    if (mode == kDMIC_OperationModeDma)
+    {
+        /* enable DMA request*/
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    }
+}
+
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config)
+{
+    base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk;
+    base->CHANNEL[channel].OSR = channel_config->osr;
+    base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft;
+    base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef;
+    base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef;
+    base->CHANNEL[channel].PHY_CTRL =
+        DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate);
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit);
+}
+
+void DMIC_CfgChannelDc(DMIC_Type *base,
+                       dmic_channel_t channel,
+                       dc_removal_t dc_cut_level,
+                       uint32_t post_dc_gain_reduce,
+                       bool saturate16bit)
+{
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit);
+}
+
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs)
+{
+    base->USE2FS = (use2fs) ? 0x1 : 0x0;
+}
+
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask)
+{
+    base->CHANEN = channelmask;
+}
+
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn)
+{
+    base->CHANNEL[channel].FIFO_CTRL |=
+        (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) |
+        DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) |
+        DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn);
+}
+
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicCallback[instance] = cb;
+    EnableIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicIRQ[instance]);
+    s_dmicCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicHwvadCallback[instance] = vadcb;
+    EnableIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicHwvadIRQ[instance]);
+    s_dmicHwvadCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(DMIC0)
+/*DMIC0 IRQ handler */
+void DMIC0_DriverIRQHandler(void)
+{
+    if (s_dmicCallback[0] != NULL)
+    {
+        s_dmicCallback[0]();
+    }
+}
+/*DMIC0 HWVAD IRQ handler */
+void HWVAD0_IRQHandler(void)
+{
+    if (s_dmicHwvadCallback[0] != NULL)
+    {
+        s_dmicHwvadCallback[0]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMIC_H_
+#define _FSL_DMIC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmic_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name DMIC version
+ * @{
+ */
+
+/*! @brief DMIC driver version 2.0.0. */
+#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief DMIC different operation modes. */
+typedef enum _operation_mode
+{
+    kDMIC_OperationModePoll = 0U,      /*!< Polling mode */
+    kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
+    kDMIC_OperationModeDma = 2U,       /*!< DMA mode */
+} operation_mode_t;
+
+/*! @brief DMIC left/right values. */
+typedef enum _stereo_side
+{
+    kDMIC_Left = 0U,  /*!< Left Stereo channel */
+    kDMIC_Right = 1U, /*!< Right Stereo channel */
+} stereo_side_t;
+
+/*! @brief DMIC Clock pre-divider values. */
+typedef enum
+{
+    kDMIC_PdmDiv1 = 0U,    /*!< DMIC pre-divider set in divide by 1 */
+    kDMIC_PdmDiv2 = 1U,    /*!< DMIC pre-divider set in divide by 2 */
+    kDMIC_PdmDiv3 = 2U,    /*!< DMIC pre-divider set in divide by 3 */
+    kDMIC_PdmDiv4 = 3U,    /*!< DMIC pre-divider set in divide by 4 */
+    kDMIC_PdmDiv6 = 4U,    /*!< DMIC pre-divider set in divide by 6 */
+    kDMIC_PdmDiv8 = 5U,    /*!< DMIC pre-divider set in divide by 8 */
+    kDMIC_PdmDiv12 = 6U,   /*!< DMIC pre-divider set in divide by 12 */
+    kDMIC_PdmDiv16 = 7U,   /*!< DMIC pre-divider set in divide by 16*/
+    kDMIC_PdmDiv24 = 8U,   /*!< DMIC pre-divider set in divide by 24*/
+    kDMIC_PdmDiv32 = 9U,   /*!< DMIC pre-divider set in divide by 32 */
+    kDMIC_PdmDiv48 = 10U,  /*!< DMIC pre-divider set in divide by 48 */
+    kDMIC_PdmDiv64 = 11U,  /*!< DMIC pre-divider set in divide by 64*/
+    kDMIC_PdmDiv96 = 12U,  /*!< DMIC pre-divider set in divide by 96*/
+    kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
+} pdm_div_t;
+
+/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
+typedef enum _compensation
+{
+    kDMIC_CompValueZero = 0U,            /*!< Compensation 0 */
+    kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
+    kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
+    kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
+} compensation_t;
+
+/*! @brief DMIC DC filter control values. */
+typedef enum _dc_removal
+{
+    kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
+    kDMIC_DcCut155 = 1U,   /*!< Cut off Frequency is 155 Hz  */
+    kDMIC_DcCut78 = 2U,    /*!< Cut off Frequency is 78 Hz  */
+    kDMIC_DcCut39 = 3U,    /*!< Cut off Frequency is 39 Hz  */
+} dc_removal_t;
+
+/*! @brief DMIC IO configiration. */
+typedef enum _dmic_io
+{
+    kDMIC_PdmDual = 0U,       /*!< Two separate pairs of PDM wires */
+    kDMIC_PdmStereo = 4U,     /*!< Stereo Mic */
+    kDMIC_PdmBypass = 3U,     /*!< Clk Bypass clocks both channels */
+    kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */
+    kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */
+} dmic_io_t;
+
+/*! @brief DMIC Channel number. */
+typedef enum _dmic_channel
+{
+    kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
+    kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
+} dmic_channel_t;
+
+/*! @brief DMIC and decimator sample rates. */
+typedef enum _dmic_phy_sample_rate
+{
+    kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
+    kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
+} dmic_phy_sample_rate_t;
+
+/*! @brief DMIC transfer status.*/
+enum _dmic_status
+{
+    kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0),          /*!< DMIC is busy */
+    kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1),          /*!< DMIC is idle */
+    kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2),  /*!< DMIC  over run Error */
+    kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
+};
+
+/*! @brief DMIC Channel configuration structure. */
+typedef struct _dmic_channel_config
+{
+    pdm_div_t divhfclk;                 /*!< DMIC Clock pre-divider values */
+    uint32_t osr;                       /*!< oversampling rate(CIC decimation rate) for PCM */
+    int32_t gainshft;                   /*!< 4FS PCM data gain control */
+    compensation_t preac2coef;          /*!< Pre-emphasis Filter coefficient value for 2FS */
+    compensation_t preac4coef;          /*!< Pre-emphasis Filter coefficient value for 4FS */
+    dc_removal_t dc_cut_level;          /*!< DMIC DC filter control values. */
+    uint32_t post_dc_gain_reduce;       /*!< Fine gain adjustment in the form of a number of bits to downshift */
+    dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
+    bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
+                1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
+                0x8000 for negative overflow.*/
+} dmic_channel_config_t;
+
+/*! @brief DMIC Callback function. */
+typedef void (*dmic_callback_t)(void);
+
+/*! @brief HWVAD Callback function. */
+typedef void (*dmic_hwvad_callback_t)(void);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock on
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_Init(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock off
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_DeInit(DMIC_Type *base);
+
+/*!
+ * @brief	Configure DMIC io
+ * @param	base	: The base address of DMIC interface
+ * @param	config		: DMIC io configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
+
+/*!
+ * @brief	Set DMIC operating mode
+ * @param	base	: The base address of DMIC interface
+ * @param	mode	: DMIC mode
+ * @return	Nothing
+ */
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
+
+/*!
+ * @brief	Configure DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param side     : stereo_side_t, choice of left or right
+ * @param	channel_config	: Channel configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config);
+
+/*!
+ * @brief	Configure Clock scaling
+ * @param	base		: The base address of DMIC interface
+ * @param	use2fs		: clock scaling
+ * @return	Nothing
+ */
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
+
+/*!
+ * @brief	Enable a particualr channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channelmask	: Channel selection
+ * @return	Nothing
+ */
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
+
+/*!
+ * @brief	Configure fifo settings for DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	trig_level	: FIFO trigger level
+ * @param	enable		: FIFO level
+ * @param	resetn		: FIFO reset
+ * @return	Nothing
+ */
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
+
+/*!
+ * @brief	Get FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO status
+ */
+static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_STATUS;
+}
+
+/*!
+ * @brief	Clear FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	mask		: Bits to be cleared
+ * @return	FIFO status
+ */
+static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].FIFO_STATUS = mask;
+}
+
+/*!
+ * @brief	Get FIFO data
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO data
+ */
+static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_DATA;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected DMIC peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/**
+ * @}
+ */
+
+/*!
+ * @name hwvad
+ * @{
+ */
+
+/*!
+ * @brief Sets the gain value for the noise estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the noise estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGN = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the gain value for the signal estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the signal estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGS = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the hwvad filter cutoff frequency parameter.
+ *
+ * @param base DMIC base pointer
+ * @param value cut off frequency value.
+ * @retval None.
+ */
+static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADHPFS = value & 0x3u;
+}
+
+/*!
+ * @brief Sets the input gain of hwvad.
+ *
+ * @param base DMIC base pointer
+ * @param value input gain value for hwvad.
+ * @retval None.
+ */
+static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADGAIN = value & 0xFu;
+}
+
+/*!
+ * @brief Clears hwvad internal interrupt flag.
+ *
+ * @param base DMIC base pointer
+ * @param st10 bit value.
+ * @retval None.
+ */
+static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
+{
+    assert(NULL != base);
+    base->HWVADST10 = (st10) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Resets hwvad filters.
+ *
+ * @param base DMIC base pointer
+ * @param rstt Reset bit value.
+ * @retval None.
+ */
+static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
+{
+    assert(NULL != base);
+    base->HWVADRSTT = (rstt) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Gets the value from output of the filter z7.
+ *
+ * @param base DMIC base pointer
+ * @retval output of filter z7.
+ */
+static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
+{
+    assert(NULL != base);
+    return (base->HWVADLOWZ & 0xFFFFu);
+}
+
+/*!
+ * @brief	Enable hwvad callback.
+
+ * This function enables the hwvad interrupt for the selected DMIC  peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the hwvad interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_DMIC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic_dma.h"
+#include "fsl_dmic.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DMIC_HANDLE_ARRAY_SIZE 1
+
+/*<! Structure definition for dmic_dma_handle_t. The structure is private. */
+typedef struct _dmic_dma_private_handle
+{
+    DMIC_Type *base;
+    dmic_dma_handle_t *handle;
+} dmic_dma_private_handle_t;
+
+/*! @brief DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */
+enum _dmic_dma_states_t
+{
+    kDMIC_Idle = 0x0, /*!< DMIC is idle state */
+    kDMIC_Busy        /*!< DMIC is busy tranferring data. */
+};
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+extern uint32_t DMIC_GetInstance(DMIC_Type *base);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*<! Private handle only used for internally. */
+static dmic_dma_private_handle_t s_dmaPrivateHandle[DMIC_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Code
+********************************************************************************/
+
+static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    dmic_dma_private_handle_t *dmicPrivateHandle = (dmic_dma_private_handle_t *)param;
+    dmicPrivateHandle->handle->state = kDMIC_Idle;
+
+    if (dmicPrivateHandle->handle->callback)
+    {
+        dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle,
+                                            dmicPrivateHandle->handle->userData);
+    }
+}
+
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check DMIC instance by 'base'*/
+    instance = DMIC_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+
+    /* Set DMIC state to idle */
+    handle->state = kDMIC_Idle;
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* Check if the device is busy. If previous RX not finished.*/
+    if (handle->state == kDMIC_Busy)
+    {
+        status = kStatus_DMIC_Busy;
+    }
+    else
+    {
+        handle->state = kDMIC_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+    return status;
+}
+
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->state = kDMIC_Idle;
+}
+
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kDMIC_Idle == handle->state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DMIC_DMA_H_
+#define _FSL_DMIC_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup dmic_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DMIC transfer structure. */
+typedef struct _dmic_transfer
+{
+    uint16_t *data;  /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} dmic_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _dmic_dma_handle dmic_dma_handle_t;
+
+/*! @brief DMIC transfer callback function. */
+typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base,
+                                             dmic_dma_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+* @brief DMIC DMA handle
+*/
+struct _dmic_dma_handle
+{
+    DMIC_Type *base;                       /*!< DMIC peripheral base address. */
+    dma_handle_t *rxDmaHandle;             /*!< The DMA RX channel used. */
+    dmic_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< DMIC callback function parameter.*/
+    size_t transferSize;                   /*!< Size of the data to receive. */
+    volatile uint8_t state;                /*!< Internal state of DMIC DMA transfer */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMIC handle which is used in transactional functions.
+ * @param base DMIC peripheral base address.
+ * @param handle Pointer to dmic_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t.
+ * @param dmic_channel DMIC channel 
+ * @retval kStatus_Success
+ */
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base DMIC peripheral base address
+ * @param handle Pointer to dmic_dma_handle_t structure
+ */
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base DMIC peripheral base address.
+ * @param handle DMIC handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter count;
+ */
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_DMIC_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_eeprom.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the EEPROM instance from peripheral base address.
+ *
+ * @param base EEPROM peripheral base address.
+ * @return EEPROM instance.
+ */
+static uint32_t EEPROM_GetInstance(EEPROM_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of EEPROM peripheral base address. */
+static EEPROM_Type *const s_eepromBases[] = EEPROM_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of EEPROM clock name. */
+static const clock_ip_name_t s_eepromClock[] = EEPROM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t EEPROM_GetInstance(EEPROM_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_eepromBases); instance++)
+    {
+        if (s_eepromBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_eepromBases));
+
+    return instance;
+}
+
+void EEPROM_GetDefaultConfig(eeprom_config_t *config)
+{
+    config->autoProgram = kEEPROM_AutoProgramWriteWord;
+    config->writeWaitPhase1 = 0x5U;
+    config->writeWaitPhase2 = 0x9U;
+    config->writeWaitPhase3 = 0x3U;
+    config->readWaitPhase1 = 0xFU;
+    config->readWaitPhase2 = 0x8U;
+    config->lockTimingParam = false;
+}
+
+void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz)
+{
+    assert(config);
+
+    uint32_t clockDiv = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_EnableClock(s_eepromClock[EEPROM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set the clock divider */
+    clockDiv = sourceClock_Hz / FSL_FEATURE_EEPROM_INTERNAL_FREQ;
+    if ((sourceClock_Hz % FSL_FEATURE_EEPROM_INTERNAL_FREQ) > (FSL_FEATURE_EEPROM_INTERNAL_FREQ / 2U))
+    {
+        clockDiv += 1U;
+    }
+    base->CLKDIV = clockDiv - 1U;
+
+    /* Set the auto program feature */
+    EEPROM_SetAutoProgram(base, config->autoProgram);
+
+    /* Set time delay parameter */
+    base->RWSTATE =
+        EEPROM_RWSTATE_RPHASE1(config->readWaitPhase1 - 1U) | EEPROM_RWSTATE_RPHASE2(config->readWaitPhase2 - 1U);
+    base->WSTATE = EEPROM_WSTATE_PHASE1(config->writeWaitPhase1 - 1U) |
+                   EEPROM_WSTATE_PHASE2(config->writeWaitPhase2 - 1U) |
+                   EEPROM_WSTATE_PHASE3(config->writeWaitPhase3 - 1U);
+    base->WSTATE |= EEPROM_WSTATE_LCK_PARWEP(config->lockTimingParam);
+ 
+    /* Clear the remaining write operation  */
+    base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+}
+
+void EEPROM_Deinit(EEPROM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_DisableClock(s_eepromClock[EEPROM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data)
+{
+    uint32_t *addr = 0;
+
+    if ((offset % 4U) || (offset > FSL_FEATURE_EEPROM_SIZE))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set auto program settings */
+    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
+    {
+        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramWriteWord);
+    }
+
+    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
+
+    /* Compute the page */
+    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + offset);
+    *addr = data;
+
+    /* Check if need to do program erase manually */
+    if (base->AUTOPROG != kEEPROM_AutoProgramWriteWord)
+    {
+        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    }
+
+    /* Waiting for operation finished */
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+
+    return kStatus_Success;
+}
+
+status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data)
+{
+    uint32_t i = 0;
+    uint32_t *addr = NULL;
+
+    if ((pageNum > FSL_FEATURE_EEPROM_PAGE_COUNT) || (!data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set auto program settings */
+    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
+    {
+        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramLastWord);
+    }
+
+    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
+
+    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + pageNum * (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT));
+    for (i = 0; i < (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT) / 4U; i++)
+    {
+        addr[i] = data[i];
+    }
+
+    if (base->AUTOPROG == kEEPROM_AutoProgramDisable)
+    {
+        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    }
+
+    /* Waiting for operation finished */
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_EEPROM_H_
+#define _FSL_EEPROM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup eeprom
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EEPROM driver version 2.0.0. */
+#define FSL_EEPROM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief EEPROM automatic program option */
+typedef enum _eeprom_auto_program
+{
+    kEEPROM_AutoProgramDisable = 0x0,   /*!< Disable auto program */
+    kEEPROM_AutoProgramWriteWord = 0x1, /*!< Auto program triggered after 1 word is written */
+    kEEPROM_AutoProgramLastWord = 0x2   /*!< Auto program triggered after last word of a page written */
+} eeprom_auto_program_t;
+
+/*! @brief EEPROM interrupt source */
+typedef enum _eeprom_interrupt_enable
+{
+    kEEPROM_ProgramFinishInterruptEnable = EEPROM_INTENSET_PROG_SET_EN_MASK, /*!< Interrupt while program finished */
+} eeprom_interrupt_enable_t;
+
+/*!
+ * @brief EEPROM region configuration structure.
+ */
+typedef struct _eeprom_config
+{
+    eeprom_auto_program_t autoProgram; /*!< Automatic program feature. */
+    uint8_t readWaitPhase1;            /*!< EEPROM read waiting phase 1 */
+    uint8_t readWaitPhase2;            /*!< EEPROM read waiting phase 2 */
+    uint8_t writeWaitPhase1;           /*!< EEPROM write waiting phase 1 */
+    uint8_t writeWaitPhase2;           /*!< EEPROM write waiting phase 2 */
+    uint8_t writeWaitPhase3;           /*!< EEPROM write waiting phase 3 */
+    bool lockTimingParam;              /*!< If lock the read and write wait phase settings */
+} eeprom_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the EEPROM with the user configuration structure.
+ *
+ * This function configures the EEPROM module with the user-defined configuration. This function also sets the
+ * internal clock frequency to about 155kHz according to the source clock frequency.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ * @param sourceClock_Hz EEPROM source clock frequency in Hz.
+ */
+void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz);
+
+/*!
+ * @brief Get EEPROM default configure settings.
+ *
+ * @param config  EEPROM config structure pointer.
+ */
+void EEPROM_GetDefaultConfig(eeprom_config_t *config);
+
+/*!
+ * @brief Deinitializes the EEPROM regions.
+ *
+ * @param base     EEPROM peripheral base address.
+ */
+void EEPROM_Deinit(EEPROM_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Set EEPROM automatic program feature.
+ *
+ * EEPROM write always needs a program and erase cycle to write the data into EEPROM. This program and erase cycle can
+ * be finished automaticlly or manually. If users want to use or disable auto program feature, users can call this API.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param autoProgram EEPROM auto program feature need to set.
+ */
+static inline void EEPROM_SetAutoProgram(EEPROM_Type *base, eeprom_auto_program_t autoProgram)
+{
+    base->AUTOPROG = autoProgram;
+}
+
+/*!
+ * @brief Set EEPROM to in/out power down mode.
+ *
+ * This function make EEPROM eneter or out of power mode. Notice that, users shall not put EEPROM into power down mode
+ * while there is still any pending EEPROM operation. While EEPROM is wakes up from power down mode, any EEPROM
+ * operation has to be suspended for 100 us.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param enable   True means enter to power down mode, false means wake up.
+ */
+static inline void EEPROM_SetPowerDownMode(EEPROM_Type *base, bool enable)
+{
+    base->PWRDWN = enable;
+}
+
+/*!
+ * @brief Enable EEPROM interrupt.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_EnableInterrupt(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTENSET = mask;
+}
+
+/*!
+ * @brief Disable EEPROM interrupt.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_DisableInterrupt(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTENCLR = mask;
+}
+
+/*!
+ * @brief Get the status of all interrupt flags for ERPROM.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @return EEPROM interrupt flag status
+ */
+static inline uint32_t EEPROM_GetInterruptStatus(EEPROM_Type *base)
+{
+    return base->INTSTAT;
+}
+
+/*!
+ * @brief Get the status of enabled interrupt flags for ERPROM.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @return EEPROM enabled interrupt flag status
+ */
+static inline uint32_t EEPROM_GetEnabledInterruptStatus(EEPROM_Type *base)
+{
+    return base->INTEN;
+}
+
+/*!
+ * @brief Set interrupt flags manually.
+ *
+ * This API trigger a interrupt manually, users can no need to wait for hardware trigger interrupt. Call this API will
+ * set the corresponding bit in INSTAT register.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt flag need to be set. It is a logic OR of members of
+ *                 enumeration:: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_SetInterruptFlag(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTSTATSET = mask;
+}
+
+/*!
+ * @brief Clear interrupt flags manually.
+ *
+ * This API clears interrupt flags manually. Call this API will clear the corresponding bit in INSTAT register.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt flag need to be cleared. It is a logic OR of members of
+ *                 enumeration:: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_ClearInterruptFlag(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTSTATCLR = mask;
+}
+
+/*!
+ * @brief Write a word data in address of EEPROM.
+ *
+ * Users can write a page or at least a word data into EEPROM address.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param offset   Offset from the begining address of EEPROM. This value shall be 4-byte aligned.
+ * @param data     Data need be write.
+ */
+status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data);
+
+/*!
+ * @brief Write a page data into EEPROM.
+ *
+ * Users can write a page or at least a word data into EEPROM address.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param pageNum  Page number to be written.
+ * @param data     Data need be write. This array data size shall equals to the page size.
+ */
+status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EEPROM_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_emc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define macros for EMC driver. */
+#define EMC_REFRESH_CLOCK_PARAM   (16U)
+#define EMC_SDRAM_WAIT_CYCLES  (2000U)
+#define EMC_DYNCTL_COLUMNBASE_OFFSET  (0U)
+#define EMC_DYNCTL_COLUMNBASE_MASK    (0x3U)
+#define EMC_DYNCTL_COLUMNPLUS_OFFSET  (3U)
+#define EMC_DYNCTL_COLUMNPLUS_MASK    (0x18U)
+#define EMC_DYNCTL_BUSWIDTH_MASK      (0x80U)
+#define EMC_DYNCTL_BUSADDRMAP_MASK    (0x20U)
+#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
+#define EMC_SDRAM_BANKCS_BA0_MASK   (uint32_t)(0x2000)
+#define EMC_SDRAM_BANKCS_BA1_MASK   (uint32_t)(0x4000)
+#define EMC_SDRAM_BANKCS_BA_MASK    (EMC_SDRAM_BANKCS_BA0_MASK|EMC_SDRAM_BANKCS_BA1_MASK)
+#define EMC_DIV_ROUND_UP(n, m)   ((n + m -1)/m)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for EMC module.
+ *
+ * @param base EMC peripheral base address
+ */
+static uint32_t EMC_GetInstance(EMC_Type *base);
+
+/*!
+ * @brief Get the clock cycles of EMC clock.
+ * The function is used to calculate the multiple of the 
+ * 16 EMCCLKs between the timer_Ns period.
+ *
+ * @param base EMC peripheral base address
+ * @param timer_Ns The timer/period in unit of nanosecond
+ * @param plus The plus added to the register settings to reach the calculated cycles.
+ * @return The calculated cycles. 
+ */
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);
+
+/*!
+ * @brief Get the shift value to shift the mode register content by.
+ *
+ * @param addrMap EMC address map for the dynamic memory configuration. 
+ *                It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.
+ * @return The offset value to shift the mode register content by. 
+ */
+static uint32_t EMC_ModeOffset(uint32_t addrMap);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to EMC clocks for each instance. */
+static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;
+
+/*! @brief Pointers to EMC bases for each instance. */
+static EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;
+
+/*! @brief Define the the start address for each chip controlled by EMC. */
+static uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EMC_GetInstance(EMC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)
+    {
+        if (s_EMCBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_EMCBases));
+
+    return instance;
+}
+
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
+{
+    uint32_t cycles;
+
+    cycles = CLOCK_GetFreq(kCLOCK_EMC) / EMC_HZ_ONEMHZ * timer_Ns;
+    cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
+
+    /* Decrese according to the plus. */
+    if (cycles >= plus)
+    {
+        cycles = cycles - plus;
+    }
+    else
+    {
+        cycles = 0;
+    }
+    
+    return cycles;
+}
+
+static uint32_t EMC_ModeOffset(uint32_t addrMap)
+{
+    uint8_t offset = 0;
+    uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
+
+    /* First calculate the column length. */
+    if (columbase == 0x10)
+    {
+        offset = 8;
+    }
+    else
+    {
+        if (!columbase)
+        {
+            offset = 9;          
+        }
+        else
+        {
+            offset = 8;
+        }
+        /* Add column length increase check. */
+        if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1)
+        {
+            offset += 1;   
+        }
+        else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2)
+        {
+            offset += 2;
+        }
+        else
+        {
+            /* To avoid MISRA rule 14.10 error. */
+        }        
+    }
+
+    /* Add Buswidth/16. */
+    if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK)
+    {
+        offset += 2;
+    }
+    else
+    {
+        offset += 1;
+    }
+
+    /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
+    if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
+    {
+        if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
+        {
+          offset += 1; 
+        }
+        else
+        {
+          offset += 2;
+        }
+    }
+
+    return offset;
+}
+
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config)
+{
+    /* Enable EMC clock. */
+    CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));
+
+    /* Reset the EMC. */
+    SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
+    SYSCON->PRESETCTRL[2] &= ~ SYSCON_PRESETCTRL_EMC_RESET_MASK;
+    
+    /* Set the EMC sytem configure. */
+    SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);
+
+    SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);
+
+    /* Set the endian mode. */
+    base->CONFIG = config->endian;
+    /* Enable the EMC module with normal memory map mode and normal work mode. */
+    base->CONTROL = EMC_CONTROL_E_MASK;
+}
+
+void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
+        emc_dynamic_chip_config_t *config, uint32_t totalChips)
+{
+    assert(config);
+    assert(timing);
+    assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);
+
+    uint32_t count;
+    uint8_t casLatency;
+    uint32_t addr;
+    uint32_t offset;
+    uint32_t data;
+    emc_dynamic_chip_config_t *dynamicConfig = config;
+
+    /* Setting for dynamic memory controller chip independent configuration. */
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG  = EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) |
+            EMC_ADDRMAP(dynamicConfig->devAddrMap);
+        /* Abstract CAS latency from the sdram mode reigster setting values. */
+        casLatency = (dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS  =  EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) |
+        EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
+        
+        dynamicConfig ++;
+    }
+
+    /* Configure the Dynamic Memory controller timing/latency for all chips. */
+    base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
+    base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
+    base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
+    base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
+    base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
+    base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
+    base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
+    base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
+    base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) &EMC_DYNAMICRFC_TRFC_MASK;
+    base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
+    base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
+    base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0)?timing->tMrd_Nclk - 1:0);
+
+    /* Initialize the SDRAM.*/ 
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
+    {
+    }
+    /* Step 2. issue nop command. */
+    base->DYNAMICCONTROL  = 0x00000183;
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
+    {
+    }
+    /* Step 3. issue precharge all command. */
+    base->DYNAMICCONTROL  = 0x00000103;
+
+    /* Step 4. issue two auto-refresh command. */
+    base->DYNAMICREFRESH = 2;
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES/2; count ++)
+    {
+    }
+
+    base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0)/EMC_REFRESH_CLOCK_PARAM;
+
+    /* Step 5. issue a mode command and set the mode value. */
+    base->DYNAMICCONTROL  = 0x00000083;
+
+    /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        /* Get the shift value first. */
+        offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+        addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | 
+            ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset));
+        /* Set the right mode setting value. */
+        data = *(volatile uint32_t *)addr;
+        data = data;
+        dynamicConfig ++;
+    }
+
+    if (config->dynamicDevice)
+    {
+        /* Add extended mode register if the low-power sdram is used. */
+        base->DYNAMICCONTROL  = 0x00000083;
+        /* Calculate the mode settings for extended mode register. */
+        dynamicConfig = config;
+        for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+        {
+            /* Get the shift value first. */
+            offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+            addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |
+                EMC_SDRAM_BANKCS_BA1_MASK) << offset));
+            /* Set the right mode setting value. */
+            data = *(volatile uint32_t *)addr;
+            data = data;
+            dynamicConfig ++;
+        }        
+    }
+
+    /* Step 6. issue normal operation command. */
+    base->DYNAMICCONTROL  = 0x00000000; /* Issue NORMAL command */
+
+    /* The buffer shall be disabled when do the sdram initialization and
+     * enabled after the initialization during normal opeation.
+     */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;        
+        dynamicConfig ++;
+    }
+}
+
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, 
+         emc_static_chip_config_t *config, uint32_t totalChips)
+{
+    assert(config);
+
+    uint32_t count;
+    emc_static_chip_config_t *staticConfig = config;
+
+    /* Initialize extended wait. */
+    if (extWait_Ns)
+    {   
+        for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
+        {
+            assert(staticConfig->specailConfig & kEMC_AsynchronosPageEnable);
+        }
+
+        base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);
+        staticConfig ++;
+    }
+
+    /* Initialize the static memory chip specific configure. */
+    staticConfig = config;
+    for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
+    {
+
+        base->STATIC[staticConfig->chipIndex].STATICCONFIG = 
+            (staticConfig->specailConfig | staticConfig->memWidth);
+        base->STATIC[staticConfig->chipIndex].STATICWAITWEN =
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITOEN = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);
+        base->STATIC[staticConfig->chipIndex].STATICWAITRD = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITPAGE = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITWR = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);
+        base->STATIC[staticConfig->chipIndex].STATICWAITTURN = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);
+        
+        staticConfig ++;
+    }
+}   
+
+void EMC_Deinit(EMC_Type *base)
+{
+    /* Deinit the EMC. */
+    base->CONTROL &= ~EMC_CONTROL_E_MASK;
+
+    /* Disable EMC clock. */
+    CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_EMC_H_
+#define _FSL_EMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup emc
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EMC driver version 2.0.0. */
+#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Define the chip numbers for dynamic and static memory devices. */
+#define EMC_STATIC_MEMDEV_NUM        (4U)
+#define EMC_DYNAMIC_MEMDEV_NUM       (4U)
+#define EMC_ADDRMAP_SHIFT        EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
+#define EMC_ADDRMAP_MASK         (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK |EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_ADDRMAP(x)    (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)     
+#define EMC_HZ_ONEMHZ   (1000000U)
+#define EMC_MILLISECS_ONESEC   (1000U)
+#define EMC_SDRAM_MODE_CL_SHIFT   (4U)
+#define EMC_SDRAM_MODE_CL_MASK   (0x70U)
+
+/*!
+ * @brief Define EMC memory width for static memory device.
+ */
+typedef enum _emc_static_memwidth
+{
+    kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */
+    kEMC_16BitWidth,       /*!< 16 bit memory width. */
+    kEMC_32BitWidth        /*!< 32 bit memory width. */
+} emc_static_memwidth_t;
+
+/*!
+ * @brief Define EMC static configuration.
+ */
+typedef enum _emc_static_special_config
+{ 
+    kEMC_AsynchronosPageEnable = 0x0008U,/*!< Enable the asynchronous page mode. page length four. */
+    kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */
+    kEMC_ByteLaneStateAllLow = 0x0080U,  /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */
+    kEMC_ExtWaitEnable = 0x0100U,        /*!< Extended wait enable. */
+    kEMC_BufferEnable = 0x80000U         /*!< Buffer enable. */
+} emc_static_special_config_t;
+
+/*! @brief EMC dynamic memory device. */
+typedef enum _emc_dynamic_device
+{
+    kEMC_Sdram = 0x0U,   /*!< Dynamic memory device: SDRAM. */
+    kEMC_Lpsdram,        /*!< Dynamic memory device: Low-power SDRAM. */
+} emc_dynamic_device_t;
+
+/*! @brief EMC dynamic read strategy. */
+typedef enum _emc_dynamic_read
+{
+    kEMC_NoDelay = 0x0U,        /*!< No delay. */ 
+    kEMC_Cmddelay,              /*!< Command delayed strategy, using EMCCLKDELAY. */
+    kEMC_CmdDelayPulseOneclk,   /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
+    kEMC_CmddelayPulsetwoclk,   /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
+} emc_dynamic_read_t;
+
+/*! @brief EMC endian mode. */
+typedef enum _emc_endian_mode
+{
+    kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */
+    kEMC_BigEndian,           /*!< Big endian mode. */
+} emc_endian_mode_t;
+
+/*! @brief EMC Feedback clock input source select. */
+typedef enum _emc_fbclk_src
+{
+    kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */
+    kEMC_EMCFbclkInput    /*!< Use the external EMC_FBCLK input. */
+} emc_fbclk_src_t;
+
+/*! @brief EMC dynamic timing/delay configure structure. */
+typedef struct _emc_dynamic_timing_config
+{
+    emc_dynamic_read_t readConfig;   /* Dynamic read strategy. */
+    uint32_t refreshPeriod_Nanosec;  /*!< The refresh period in unit of nanosecond. */
+    uint32_t tRp_Ns;      /*!< Precharge command period in unit of nanosecond. */
+    uint32_t tRas_Ns;     /*!< Active to precharge command period in unit of nanosecond. */
+    uint32_t tSrex_Ns;    /*!< Self-refresh exit time in unit of nanosecond. */
+    uint32_t tApr_Ns;     /*!< Last data out to active command time in unit of nanosecond. */
+    uint32_t tDal_Ns;     /*!< Data-in to active command in unit of nanosecond. */
+    uint32_t tWr_Ns;      /*!< Write recovery time in unit of nanosecond. */
+    uint32_t tRc_Ns;      /*!< Active to active command period in unit of nanosecond. */       
+    uint32_t tRfc_Ns;     /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
+    uint32_t tXsr_Ns;     /*!< Exit self-refresh to active command time in unit of nanosecond. */
+    uint32_t tRrd_Ns;     /*!< Active bank A to active bank B latency in unit of nanosecond. */
+    uint8_t tMrd_Nclk;     /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
+} emc_dynamic_timing_config_t;
+
+/*!
+ * @brief EMC dynamic memory controller independent chip configuration structure.
+ * Please take refer to the address mapping table in the RM in EMC chapter when you 
+ * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
+ * according to the bus width/banks/row/colum length for you device.
+ * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7) 
+ * and inset the bit 13 with 0.
+ * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
+ * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length. 
+ * Set devAddrMap with 0x81.
+ */
+typedef struct _emc_dynamic_chip_config
+{
+    uint8_t chipIndex;    /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
+    emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */
+    uint8_t rAS_Nclk;    /*!< Active to read/write delay tRCD. */
+    uint16_t sdramModeReg;   /*!< Sdram mode register setting. */
+    uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
+    uint8_t devAddrMap;  /*!< dynamic device address mapping, choose the address mapping for your specific device. */
+} emc_dynamic_chip_config_t;
+
+/*!
+ * @brief EMC static memory controller independent chip configuration structure.
+ */
+typedef struct _emc_static_chip_config
+{
+    uint8_t chipIndex;
+    emc_static_memwidth_t memWidth; /*!< Memory width. */
+    uint32_t specailConfig;     /*!< Static configuration,a logical OR of "emc_static_special_config_t". */
+    uint32_t tWaitWriteEn_Ns;/*!< The delay form chip select to write enable in unit of nanosecond. */
+    uint32_t tWaitOutEn_Ns;  /*!< The delay from chip selcet to output enable in unit of nanosecond. */
+    uint32_t tWaitReadNoPage_Ns;/*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */
+    uint32_t tWaitReadPage_Ns;  /*!< In page mode, the read after the first read wait states in unit of nanosecond. */ 
+    uint32_t tWaitWrite_Ns;     /*!< The delay from chip select to write access in unit of nanosecond. */
+    uint32_t tWaitTurn_Ns;      /*!< The Bus turn-around time in unit of nanosecond. */
+} emc_static_chip_config_t;
+
+/*!
+ * @brief EMC module basic configuration structure.
+ *
+ * Defines the static memory controller configure structure and 
+ * uses the EMC_Init() function to make necessary initializations.
+ *
+ */
+typedef struct _emc_basic_config
+{
+    emc_endian_mode_t endian;   /*!< Endian mode . */
+    emc_fbclk_src_t fbClkSrc;    /*!< The feedback clock source. */
+    uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
+} emc_basic_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EMC Initialize and de-initialize opeartion
+ * @{
+ */
+/*!
+ * @brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config);
+
+/*!
+ * @brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param timing The timing and latency for dynamica memory controller setting. It shall
+ *        be used for all dynamica memory chips, threfore the worst timing value for all
+ *        used chips must be given.
+ * @param configure The EMC dynamic memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total dynamic memory chip numbers been used or the length of the 
+ *        "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
+        emc_dynamic_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param extWait_Ns The extended wait timeout or the read/write transfer time.
+ *        This is common for all static memory chips and set with NULL if not required.
+ * @param configure The EMC static memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total static memory chip numbers been used or the length of the 
+ *        "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * @param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base);
+
+/* @} */
+
+/*!
+ * @name EMC Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the EMC module.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC module, false disable.
+ */
+static inline void EMC_Enable(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_E_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~EMC_CONTROL_E_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC Dynaimc memory controller.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC dynamic memory controller, false disable.
+ */
+static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC address mirror.
+ * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0
+ * and EMC_DYCS0 memory areas. Disable the address mirror enables
+ * EMC_cS0 and EMC_DYCS0 memory to be accessed.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable the address mirror, false disable the address mirror.
+ */
+static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)
+{
+    if (enable) 
+    {
+        base->CONTROL |= EMC_CONTROL_M_MASK;
+    }
+    else 
+    {
+        base->CONTROL &= ~EMC_CONTROL_M_MASK;
+    }
+}
+
+/*!
+ * @brief Enter the self-refresh mode for dynamic memory controller.
+ * This function provided self-refresh mode enter or exit for application. 
+ *
+ * @param base EMC peripheral base address.
+ * @param enable   True enter the self-refresh mode, false to exit self-refresh
+ *                 and enter the normal mode.
+ */
+static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;
+    }
+}
+
+/*!
+ * @brief Get the operating mode of the EMC.
+ * This function can be used to get the operating mode of the EMC. 
+ *
+ * @param base EMC peripheral base address.
+ * @return The EMC in self-refresh mode if true, else in normal mode.
+ */
+static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)
+{
+    return ((base->STATUS & EMC_STATUS_SA_MASK) ? true : false);
+}
+
+/*!
+ * @brief Enter/exit the low-power mode.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True Enter the low-power mode, false exit low-power mode
+ *        and return to normal mode. 
+ */
+static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_L_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~ EMC_CONTROL_L_MASK;
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EMC_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1810 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_enet.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief IPv4 PTP message IP version offset. */
+#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
+/*! @brief IPv4 PTP message UDP protocol offset. */
+#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U
+/*! @brief IPv4 PTP message UDP port offset. */
+#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U
+/*! @brief IPv4 PTP message UDP message type offset. */
+#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU
+/*! @brief IPv4 PTP message UDP version offset. */
+#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU
+/*! @brief IPv4 PTP message UDP clock id offset. */
+#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU
+/*! @brief IPv4 PTP message UDP sequence id offset. */
+#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U
+/*! @brief IPv4 PTP message UDP control offset. */
+#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU
+/*! @brief IPv6 PTP message UDP protocol offset. */
+#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U
+/*! @brief IPv6 PTP message UDP port offset. */
+#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U
+/*! @brief IPv6 PTP message UDP message type offset. */
+#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU
+/*! @brief IPv6 PTP message UDP version offset. */
+#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU
+/*! @brief IPv6 PTP message UDP clock id offset. */
+#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U
+/*! @brief IPv6 PTP message UDP sequence id offset. */
+#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU
+/*! @brief IPv6 PTP message UDP control offset. */
+#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU
+/*! @brief PTPv2 message Ethernet packet type offset. */
+#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU
+/*! @brief PTPv2 message Ethernet message type offset. */
+#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU
+/*! @brief PTPv2 message Ethernet version type offset. */
+#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU
+/*! @brief PTPv2 message Ethernet clock id offset. */
+#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22
+/*! @brief PTPv2 message Ethernet sequence id offset. */
+#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c
+/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */
+#define ENET_ETHERNETL2 0x88F7U
+/*! @brief Packet type IPv4. */
+#define ENET_IPV4 0x0800U
+/*! @brief Packet type IPv6. */
+#define ENET_IPV6 0x86ddU
+/*! @brief Packet type VLAN. */
+#define ENET_8021QVLAN 0x8100U
+/*! @brief UDP protocol type. */
+#define ENET_UDPVERSION 0x0011U
+/*! @brief Packet IP version IPv4. */
+#define ENET_IPV4VERSION 0x0004U
+/*! @brief Packet IP version IPv6. */
+#define ENET_IPV6VERSION 0x0006U
+
+/*! @brief Defines 10^9 nanosecond. */
+#define ENET_NANOSECS_ONESECOND (1000000000U)
+/*! @brief Defines 10^6 microsecond.*/
+#define ENET_MICRSECS_ONESECOND (1000000U)
+
+/*! @brief Rx buffer LSB ignore bits. */
+#define ENET_RXBUFF_IGNORELSB_BITS (2U)
+/*! @brief ENET FIFO size unit. */
+#define ENET_FIFOSIZE_UNIT (256U)
+/*! @brief ENET half-dulpex default IPG. */
+#define ENET_HALFDUPLEX_DEFAULTIPG (4U)
+/*! @breif ENET miminum ring length. */
+#define ENET_MIN_RINGLEN (4U)
+/*! @breif ENET wakeup filter numbers. */
+#define ENET_WAKEUPFILTER_NUM (8U)
+/*! @breif Requried systime timer frequency. */
+#define ENET_SYSTIME_REQUIRED_CLK_MHZ (50U)
+/*! @brief Ethernet VLAN tag length. */
+#define ENET_FRAME_VLAN_TAGLEN 4U
+
+/*! @brief AVB TYPE */
+#define ENET_AVBTYPE 0x22F0U
+#define ENET_HEAD_TYPE_OFFSET (12)
+#define ENET_HEAD_AVBTYPE_OFFSET (16)
+
+/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
+#define ENET_HTONS(n) __REV16(n)
+#define ENET_HTONL(n) __REV(n)
+#define ENET_NTOHS(n) __REV16(n)
+#define ENET_NTOHL(n) __REV(n)
+
+/* Typedef for interrupt handler. */
+typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+uint32_t ENET_GetInstance(ENET_Type *base);
+
+/*!
+ * @brief Increase the index in the ring.
+ *
+ * @param index The current index.
+ * @param max The size.
+ * @return the increased index.
+ */
+static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max);
+
+/*!
+ * @brief Set ENET system configuration.
+ *  This function reset the ethernet module and set the phy selection.
+ *  It should be called before any other ethernet operation.
+ *
+ * @param miiMode  The MII/RMII mode for interface between the phy and ethernet.
+ */
+static void ENET_SetSYSControl(enet_mii_mode_t miiMode);
+
+/*!
+ * @brief Set ENET DMA controller with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ */
+static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config);
+
+/*!
+ * @brief Set ENET MAC controller with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ * @param macAddr ENET six-byte mac address.
+ */
+static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr);
+/*!
+ * @brief Set ENET MTL with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ */
+static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config);
+
+/*!
+ * @brief Set ENET DMA transmit buffer descriptors for one channel.
+ *
+ * @param base ENET peripheral base address.
+ * @param bufferConfig ENET buffer configuration.
+ * @param intTxEnable tx interrupt enable.
+ * @param channel The channel number, 0 , 1.
+ */
+static status_t ENET_TxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intTxEnable,
+                                       uint8_t channel);
+
+/*!
+ * @brief Set ENET DMA receive buffer descriptors for one channel.
+ *
+ * @param base ENET peripheral base address.
+ * @param bufferConfig ENET buffer configuration.
+ * @param intRxEnable tx interrupt enable.
+ * @param channel The channel number, 0 , 1.
+ * @param doubleBuffEnable Two buffers are enabled.
+ */
+static status_t ENET_RxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intRxEnable,
+                                       uint8_t channel,
+                                       bool doubleBuffEnable);
+
+/*!
+ * @brief Set ENET get transmit ring descriptors.
+ *
+ * @param data The ENET data to be transfered.
+ * @param handle ENET handler.
+ */
+static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle);
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*!
+ * @brief Sets the ENET 1588 feature.
+ *
+ * Enable the enhacement 1588 buffer descriptor mode and start
+ * the 1588 timer.
+ *
+ * @param base ENET peripheral base address.
+ * @param config The ENET configuration.
+ * @param refClk_Hz The reference clock for ptp 1588.
+ */
+static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz);
+
+/*!
+ * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame.
+ *
+ * @param data  The ENET read data for frame parse.
+ * @param ptpTsData The ENET PTP message and time-stamp data pointer.
+ * @param isFastEnabled The fast parse flag.
+ *        - true , Fast processing, only check if this is a PTP message.
+ *        - false, Store the PTP message data after check the PTP message.
+ */
+static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled);
+
+/*!
+ * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring.
+ *
+ * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
+ * @param ptpTimeData   The new PTP 1588 time-stamp data pointer.
+ */
+static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData);
+
+/*!
+ * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring.
+ *
+ * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
+ * @param ptpTimeData   The find out right PTP 1588 time-stamp data pointer with the specific PTP message.
+ */
+static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata);
+
+/*!
+ * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring.
+ *
+ * @param base   ENET peripheral base address.
+ * @param handle ENET handler.
+ * @param rxDesc The ENET receive descriptor pointer.
+ * @param channel The rx channel.
+ * @param ptpTimeData The PTP 1588 time-stamp data pointer.
+ */
+static status_t ENET_StoreRxFrameTime(ENET_Type *base,
+                                      enet_handle_t *handle,
+                                      enet_rx_bd_struct_t *rxDesc,
+                                      uint8_t channel,
+                                      enet_ptp_time_data_t *ptpTimeData);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to enet handles for each instance. */
+static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_LPC_ENET_COUNT] = {NULL};
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT] = ETH_CLOCKS;
+#endif /*  FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to enet bases for each instance. */
+static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
+
+/*! @brief Pointers to enet IRQ number for each instance. */
+static const IRQn_Type s_enetIrqId[] = ENET_IRQS;
+
+/* ENET ISR for transactional APIs. */
+static enet_isr_t s_enetIsr;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max)
+{
+    /* Increase the index. */
+    index++;
+    if (index >= max)
+    {
+        index = 0;
+    }
+    return index;
+}
+
+static void ENET_SetSYSControl(enet_mii_mode_t miiMode)
+{
+    /* Reset first. */
+    SYSCON->PRESETCTRL[2] = SYSCON_PRESETCTRL_ETH_RST_MASK;
+    SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_ETH_RST_MASK;
+    /* Set MII/RMII before the peripheral ethernet dma reset. */
+    SYSCON->ETHPHYSEL = (SYSCON->ETHPHYSEL & ~SYSCON_ETHPHYSEL_PHY_SEL_MASK) | SYSCON_ETHPHYSEL_PHY_SEL(miiMode);
+}
+
+static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config)
+{
+    assert(config);
+
+    uint8_t index;
+    uint32_t reg;
+    uint32_t burstLen;
+
+    /* Reset first and wait for the complete
+     * The reset bit will automatically be cleared after complete. */
+    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
+    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
+    {
+    }
+
+    /* Set the burst length. */
+    for (index = 0; index < ENET_RING_NUM_MAX; index++)
+    {
+        burstLen = kENET_BurstLen1;
+        if (config->multiqueueCfg)
+        {
+            burstLen = config->multiqueueCfg->burstLen;
+        }
+        base->DMA_CH[index].DMA_CHX_CTRL = burstLen & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK;
+
+        reg = base->DMA_CH[index].DMA_CHX_TX_CTRL & ~ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK;
+        base->DMA_CH[index].DMA_CHX_TX_CTRL = reg | ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(burstLen & 0x3F);
+
+        reg = base->DMA_CH[index].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK;
+        base->DMA_CH[index].DMA_CHX_RX_CTRL = reg | ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(burstLen & 0x3F);
+    }
+}
+
+static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config)
+{
+    assert(config);
+
+    uint32_t txqOpreg = 0;
+    uint32_t rxqOpReg = 0;
+    enet_multiqueue_config_t *multiqCfg = config->multiqueueCfg;
+    uint8_t index;
+
+    /* Set transmit operation mode. */
+    if (config->specialControl & kENET_StoreAndForward)
+    {
+        txqOpreg = ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK;
+        rxqOpReg = ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK;
+    }
+    txqOpreg |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK |
+                ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(ENET_MTL_TXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
+    base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = txqOpreg | ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
+    base->MTL_QUEUE[1].MTL_TXQX_OP_MODE = txqOpreg;
+
+    /* Set receive operation mode. */
+    rxqOpReg |= ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK |
+                ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(ENET_MTL_RXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
+    base->MTL_QUEUE[0].MTL_RXQX_OP_MODE = rxqOpReg;
+
+    /* Set the schedule/arbitration(set for multiple queues). */
+    if (multiqCfg)
+    {
+        base->MTL_OP_MODE = ENET_MTL_OP_MODE_SCHALG(multiqCfg->mtltxSche) | ENET_MTL_OP_MODE_RAA(multiqCfg->mtlrxSche);
+        /* Set the rx queue mapping to dma channel. */
+        base->MTL_RXQ_DMA_MAP = multiqCfg->mtlrxQuemap;
+        /* Set the tx/rx queue operation mode for multi-queue. */
+        base->MTL_QUEUE[1].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
+        base->MTL_QUEUE[1].MTL_RXQX_OP_MODE = rxqOpReg;
+
+        /* Set the tx/rx queue weight. */
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            base->MTL_QUEUE[index].MTL_TXQX_QNTM_WGHT = multiqCfg->txqueweight[index];
+            base->MTL_QUEUE[index].MTL_RXQX_CTRL = ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(multiqCfg->rxqueweight[index]);
+        }
+    }
+}
+
+static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr)
+{
+    assert(config);
+
+    uint32_t reg = 0;
+
+    /* Set Macaddr */
+    /* The dma channel 0 is set as to which the rx packet
+     * whose DA matches the MAC address content is routed. */
+    if (macAddr)
+    {
+        ENET_SetMacAddr(base, macAddr);
+    }
+
+    /* Set the receive filter. */
+    reg = ENET_MAC_FRAME_FILTER_PR(!!(config->specialControl & kENET_PromiscuousEnable)) |
+          ENET_MAC_FRAME_FILTER_DBF(!!(config->specialControl & kENET_BroadCastRxDisable)) |
+          ENET_MAC_FRAME_FILTER_PM(!!(config->specialControl & kENET_MulticastAllEnable));
+    base->MAC_FRAME_FILTER = reg;
+    /* Flow control. */
+    if (config->specialControl & kENET_FlowControlEnable)
+    {
+        base->MAC_RX_FLOW_CTRL = ENET_MAC_RX_FLOW_CTRL_RFE_MASK | ENET_MAC_RX_FLOW_CTRL_UP_MASK;
+        base->MAC_TX_FLOW_CTRL_Q[0] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
+        base->MAC_TX_FLOW_CTRL_Q[1] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
+    }
+
+    /* Set the 1us ticket. */
+    reg = CLOCK_GetFreq(kCLOCK_CoreSysClk) / ENET_MICRSECS_ONESECOND - 1;
+    base->MAC_1US_TIC_COUNTR = ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(reg);
+
+    /* Set the speed and duplex. */
+    reg = ENET_MAC_CONFIG_ECRSFD_MASK | ENET_MAC_CONFIG_PS_MASK | ENET_MAC_CONFIG_DM(config->miiDuplex) |
+          ENET_MAC_CONFIG_FES(config->miiSpeed) |
+          ENET_MAC_CONFIG_S2KP(!!(config->specialControl & kENET_8023AS2KPacket));
+    if (config->miiDuplex == kENET_MiiHalfDuplex)
+    {
+        reg |= ENET_MAC_CONFIG_IPG(ENET_HALFDUPLEX_DEFAULTIPG);
+    }
+    base->MAC_CONFIG = reg;
+
+    /* Enable channel. */
+    base->MAC_RXQ_CTRL[0] = ENET_MAC_RXQ_CTRL_RXQ0EN(1) | ENET_MAC_RXQ_CTRL_RXQ1EN(1);
+}
+
+static status_t ENET_TxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intTxEnable,
+                                       uint8_t channel)
+{
+    uint16_t j;
+    enet_tx_bd_struct_t *txbdPtr;
+    uint32_t control = intTxEnable ? ENET_TXDESCRIP_RD_IOC_MASK : 0;
+    const enet_buffer_config_t *buffCfg = bufferConfig;
+
+    if (!buffCfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check the ring length. */
+    if (buffCfg->txRingLen < ENET_MIN_RINGLEN)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Set the tx descriptor start/tail pointer, shall be word aligned. */
+    base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR =
+        (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR =
+        (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
+    /* Set the tx ring length. */
+    base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH =
+        (uint16_t)(buffCfg->txRingLen - 1) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;
+
+    /* Init the txbdPtr to the transmit descriptor start address. */
+    txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign);
+    for (j = 0; j < buffCfg->txRingLen; j++)
+    {
+        txbdPtr->buff1Addr = 0;
+        txbdPtr->buff2Addr = 0;
+        txbdPtr->buffLen = control;
+        txbdPtr->controlStat = 0;
+        txbdPtr++;
+    }
+
+    return kStatus_Success;
+}
+
+static status_t ENET_RxDescriptorsInit(
+    ENET_Type *base, const enet_buffer_config_t *bufferConfig, bool intRxEnable, uint8_t channel, bool doubleBuffEnable)
+{
+    uint16_t j;
+    uint32_t reg;
+    enet_rx_bd_struct_t *rxbdPtr;
+    uint16_t index;
+    const enet_buffer_config_t *buffCfg = bufferConfig;
+    uint32_t control = ENET_RXDESCRIP_WR_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
+
+    if (!buffCfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (intRxEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_IOC_MASK;
+    }
+
+    if (doubleBuffEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
+    }
+
+    /* Check the ring length. */
+    if (buffCfg->rxRingLen < ENET_MIN_RINGLEN)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set the rx descriptor start/tail pointer, shall be word aligned. */
+    base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR =
+        (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
+    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR =
+        (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
+    base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH =
+        (uint16_t)(buffCfg->rxRingLen - 1) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK;
+    reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK;
+    reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS);
+    base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg;
+
+    /* Init the rxbdPtr to the receive descriptor start address. */
+    rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign);
+
+    for (j = 0; j < buffCfg->rxRingLen; j++)
+    {
+        if (doubleBuffEnable)
+        {
+            index = 2 * j;
+        }
+        else
+        {
+            index = j;
+        }
+        rxbdPtr->buff1Addr = *(buffCfg->rxBufferStartAddr + index);
+        /* The second buffer is set with 0 because it is not required for normal case. */
+        if (doubleBuffEnable)
+        {
+            rxbdPtr->buff2Addr = *(buffCfg->rxBufferStartAddr + index + 1);
+        }
+        else
+        {
+            rxbdPtr->buff2Addr = 0;
+        }
+
+        /* Set the valid and DMA own flag.*/
+        rxbdPtr->control = control;
+        rxbdPtr++;
+    }
+
+    return kStatus_Success;
+}
+
+static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle)
+{
+    /* Defuault use the queue/ring 0. */
+    uint8_t ringId = 0;
+
+    if (handle->multiQueEnable)
+    {
+        /* Parse the frame and choose the queue id for different avb frames
+         *  AVB Class frame in queue 1.
+         *  non-AVB frame in queue 0.
+         */
+        if ((*(uint16_t *)(data + ENET_HEAD_TYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) &&
+            ((*(uint16_t *)(data + ENET_HEAD_AVBTYPE_OFFSET)) == ENET_HTONS(ENET_AVBTYPE)))
+        {
+            /* AVBTP stream data frame. */
+            ringId = 1;
+        }
+    }
+
+    return ringId;
+}
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz)
+{
+    assert(config);
+    assert(config->ptpConfig);
+    assert(refClk_Hz);
+
+    uint32_t control;
+    enet_ptp_config_t *ptpConfig = config->ptpConfig;
+
+    /* Clear the timestamp interrupt first. */
+    base->MAC_INTR_EN &= ~ENET_MAC_INTR_EN_TSIE_MASK;
+
+    if (ptpConfig->fineUpdateEnable)
+    {
+        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK;
+        /* Set the initial added value for the fine update. */
+        control = 100000000U / (refClk_Hz / ENET_MICRSECS_ONESECOND / ENET_SYSTIME_REQUIRED_CLK_MHZ);
+        base->MAC_SYS_TIMESTMP_ADDEND = control;
+        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
+        while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+        {
+        }
+    }
+
+    /* Enable the IEEE 1588 timestamping and snapshot for event message. */
+    control = ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK | ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(ptpConfig->tsRollover);
+
+    if (ptpConfig->ptp1588V2Enable)
+    {
+        control |= ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK;
+    }
+
+    /* Initialize the sub-second increment register. */
+    if (ptpConfig->tsRollover)
+    {
+        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(ENET_NANOSECS_ONESECOND / refClk_Hz);
+        base->MAC_SYS_TIME_NSCND_UPD = 0;
+    }
+    else
+    {
+        /* round up. */
+        uint32_t data = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK / refClk_Hz;
+        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(data);
+        base->MAC_SYS_TIME_NSCND_UPD = 0;
+    }
+    /* Set the second.*/
+    base->MAC_SYS_TIME_SCND_UPD = 0;
+    base->MAC_SYS_TIME_HWORD_SCND = 0;
+
+    /* Initialize the system timer. */
+    base->MAC_TIMESTAMP_CTRL = control | ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK;
+}
+
+static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled)
+{
+    assert(data);
+    if (!isFastEnabled)
+    {
+        assert(ptpTsData);
+    }
+
+    bool isPtpMsg = false;
+    uint8_t *buffer = data;
+    uint16_t ptpType;
+
+    /* Check for VLAN frame. */
+    if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN))
+    {
+        buffer += ENET_FRAME_VLAN_TAGLEN;
+    }
+
+    ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET);
+    switch (ENET_HTONS(ptpType))
+    { /* Ethernet layer 2. */
+        case ENET_ETHERNETL2:
+            if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType)
+            {
+                isPtpMsg = true;
+                if (!isFastEnabled)
+                {
+                    /* It's a ptpv2 message and store the ptp header information. */
+                    ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F;
+                    ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F;
+                    ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET));
+                    memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET),
+                           kENET_PtpSrcPortIdLen);
+                }
+            }
+            break;
+        /* IPV4. */
+        case ENET_IPV4:
+            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION)
+            {
+                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
+                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
+                {
+                    /* Set the PTP message flag. */
+                    isPtpMsg = true;
+                    if (!isFastEnabled)
+                    {
+                        /* It's a IPV4 ptp message and store the ptp header information. */
+                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F;
+                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F;
+                        ptpTsData->sequenceId =
+                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET));
+                        memcpy((void *)&ptpTsData->sourcePortId[0],
+                               (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
+                    }
+                }
+            }
+            break;
+        /* IPV6. */
+        case ENET_IPV6:
+            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION)
+            {
+                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
+                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
+                {
+                    /* Set the PTP message flag. */
+                    isPtpMsg = true;
+                    if (!isFastEnabled)
+                    {
+                        /* It's a IPV6 ptp message and store the ptp header information. */
+                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F;
+                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F;
+                        ptpTsData->sequenceId =
+                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET));
+                        memcpy((void *)&ptpTsData->sourcePortId[0],
+                               (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
+                    }
+                }
+            }
+            break;
+        default:
+            break;
+    }
+    return isPtpMsg;
+}
+
+static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(ptpTsDataRing);
+    assert(ptpTsDataRing->ptpTsData);
+    assert(ptpTimeData);
+
+    uint16_t usedBuffer = 0;
+
+    /* Check if the buffers ring is full. */
+    if (ptpTsDataRing->end >= ptpTsDataRing->front)
+    {
+        usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+    }
+    else
+    {
+        usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
+    }
+
+    if (usedBuffer == ptpTsDataRing->size)
+    {
+        return kStatus_ENET_PtpTsRingFull;
+    }
+
+    /* Copy the new data into the buffer. */
+    memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t));
+
+    /* Increase the buffer pointer to the next empty one. */
+    ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size;
+
+    return kStatus_Success;
+}
+
+static status_t ENET_StoreRxFrameTime(ENET_Type *base,
+                                      enet_handle_t *handle,
+                                      enet_rx_bd_struct_t *rxDesc,
+                                      uint8_t channel,
+                                      enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(ptpTimeData);
+
+    uint32_t nanosecond;
+    uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
+
+    /* Get transmit time stamp second. */
+    nanosecond = rxDesc->reserved | rxDesc->buff1Addr;
+    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+    {
+        /* Binary rollover. */
+        nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+    }
+    ptpTimeData->timeStamp.second = nanosecond / nanoOverSize;
+    ptpTimeData->timeStamp.nanosecond = nanosecond % nanoOverSize;
+
+    /* Store the timestamp to the receive time stamp ring. */
+    /* Check if the buffers ring is full. */
+    return ENET_Ptp1588UpdateTimeRing(&handle->rxBdRing[channel].rxPtpTsDataRing, ptpTimeData);
+}
+
+static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata)
+{
+    assert(ptpTsDataRing);
+    assert(ptpTsDataRing->ptpTsData);
+    assert(ptpTimedata);
+
+    uint32_t index;
+    uint32_t size;
+    uint16_t usedBuffer = 0;
+
+    /* Check the PTP 1588 timestamp ring. */
+    if (ptpTsDataRing->front == ptpTsDataRing->end)
+    {
+        return kStatus_ENET_PtpTsRingEmpty;
+    }
+
+    /* Search the element in the ring buffer */
+    index = ptpTsDataRing->front;
+    size = ptpTsDataRing->size;
+    while (index != ptpTsDataRing->end)
+    {
+        if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) &&
+            (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]),
+                     (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) &&
+            ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) &&
+            ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType))
+        {
+            break;
+        }
+
+        /* Increase the ptp ring index. */
+        index = (index + 1) % size;
+    }
+
+    if (index == ptpTsDataRing->end)
+    {
+        /* Check if buffers is full. */
+        if (ptpTsDataRing->end >= ptpTsDataRing->front)
+        {
+            usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+        }
+        else
+        {
+            usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
+        }
+
+        if (usedBuffer == ptpTsDataRing->size)
+        { /* Drop one in the front. */
+            ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+        }
+        return kStatus_ENET_PtpTsRingFull;
+    }
+
+    /* Get the right timestamp of the required ptp messag. */
+    ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second;
+    ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond;
+
+    /* Increase the index. */
+    ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+
+    return kStatus_Success;
+}
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+uint32_t ENET_GetInstance(ENET_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++)
+    {
+        if (s_enetBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_LPC_ENET_COUNT);
+
+    return instance;
+}
+
+void ENET_GetDefaultConfig(enet_config_t *config)
+{
+    /* Checks input parameter. */
+    assert(config);
+
+    /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */
+    config->miiMode = kENET_RmiiMode;
+    config->miiSpeed = kENET_MiiSpeed100M;
+    config->miiDuplex = kENET_MiiFullDuplex;
+
+    /* Sets default configuration for other options. */
+    config->specialControl = false;
+    config->multiqueueCfg = NULL;
+    config->pauseDuration = 0;
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    config->ptpConfig = NULL;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz)
+{
+    assert(config);
+
+    uint32_t instance = ENET_GetInstance(base);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate ENET clock. */
+    CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    /* System configure fistly. */
+    ENET_SetSYSControl(config->miiMode);
+
+    /* Initializes the ENET DMA with basic function. */
+    ENET_SetDMAControl(base, config);
+
+    /* Initializes the ENET MTL with basic function. */
+    ENET_SetMTL(base, config);
+
+    /* Initializes the ENET MAC with basic function. */
+    ENET_SetMacControl(base, config, macAddr);
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    ENET_SetPtp1588(base, config, refclkSrc_Hz);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ENET_Deinit(ENET_Type *base)
+{
+    /* Reset first and wait for the complete
+     * The reset bit will automatically be cleared after complete. */
+    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
+    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
+    {
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disables the clock source. */
+    CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig)
+{
+    assert(config);
+    assert(bufferConfig);
+
+    bool intTxEnable;
+    bool intRxEnable;
+    bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false;
+    uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2;
+    uint8_t channel;
+
+    for (channel = 0; channel < ringNum; channel++)
+    {
+        intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false;
+
+        if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+        intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false;
+
+        if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+
+        bufferConfig++;
+        if (!bufferConfig)
+        {
+            return kStatus_InvalidArgument;
+        }
+    }
+    return kStatus_Success;
+}
+
+void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum)
+{
+    assert(txRingNum);
+    assert(rxRingNum);
+
+    uint8_t index;
+
+    if (txRingNum > ENET_RING_NUM_MAX)
+    {
+        txRingNum = ENET_RING_NUM_MAX;
+    }
+    if (rxRingNum > ENET_RING_NUM_MAX)
+    {
+        rxRingNum = ENET_RING_NUM_MAX;
+    }
+    /* Start/Acive the DMA first. */
+    for (index = 0; index < rxRingNum; index++)
+    {
+        base->DMA_CH[index].DMA_CHX_RX_CTRL |= ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK;
+    }
+    for (index = 0; index < txRingNum; index++)
+    {
+        base->DMA_CH[index].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    }
+
+    /* Enable the RX/TX then. */
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
+}
+
+void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
+{
+    uint32_t interrupt = mask & 0xFFFFU;
+    uint8_t index;
+
+    /* For dma interrupt. */
+    if (interrupt)
+    {
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            /* Set for all abnormal interrupts. */
+            if (ENET_ABNORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
+            }
+            /* Set for all normal interrupts. */
+            if (ENET_NORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+            }
+            base->DMA_CH[index].DMA_CHX_INT_EN = interrupt;
+        }
+    }
+    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    if (interrupt)
+    {
+        /* MAC interrupt */
+        base->MAC_INTR_EN |= interrupt;
+    }
+}
+
+void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask)
+{
+    volatile uint32_t dummy;
+
+    if (mask & kENET_MacTimestamp)
+    {
+       dummy = base->MAC_SYS_TIMESTMP_STAT;
+    }
+    else if (mask & kENET_MacPmt)
+    {
+       dummy = base->MAC_PMT_CRTL_STAT;
+    }
+    else
+    {
+        /* Add for avoid the misra 2004 rule 14.10 */
+    }
+    (void)dummy;
+}
+
+void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
+{
+    uint32_t interrupt = mask & 0xFFFFU;
+    uint8_t index;
+
+    /* For dma interrupt. */
+    if (interrupt)
+    {
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            /* Set for all abnormal interrupts. */
+            if (ENET_ABNORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
+            }
+            /* Set for all normal interrupts. */
+            if (ENET_NORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+            }
+            base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt;
+        }
+    }
+    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    if (interrupt)
+    {
+        /* MAC interrupt */
+        base->MAC_INTR_EN &= ~interrupt;
+    }
+}
+
+void ENET_CreateHandler(ENET_Type *base,
+                        enet_handle_t *handle,
+                        enet_config_t *config,
+                        enet_buffer_config_t *bufferConfig,
+                        enet_callback_t callback,
+                        void *userData)
+{
+    assert(config);
+    assert(bufferConfig);
+    assert(callback);
+
+    uint8_t ringNum = 1;
+    uint8_t count = 0;
+    uint8_t rxIntEnable = 0;
+    enet_buffer_config_t *buffConfig = bufferConfig;
+
+    if (config->multiqueueCfg)
+    {
+        ringNum = 2;
+        handle->multiQueEnable = true;
+    }
+
+    /* Store transfer parameters in handle pointer. */
+    memset(handle, 0, sizeof(enet_handle_t));
+    if (config->specialControl & kENET_DescDoubleBuffer)
+    {
+        handle->doubleBuffEnable = true;
+    }
+    if (config->multiqueueCfg)
+    {
+        handle->multiQueEnable = true;
+    }
+    for (count = 0; count < ringNum; count++)
+    {
+        handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign;
+        handle->rxBdRing[count].rxGenIdx = 0;
+        handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen;
+        handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign;
+
+        handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign;
+        handle->txBdRing[count].txRingLen = buffConfig->txRingLen;
+        handle->txBdRing[count].txGenIdx = 0;
+        handle->txBdRing[count].txConsumIdx = 0;
+        handle->txBdRing[count].txDescUsed = 0;
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        assert(bufferConfig->rxPtpTsData);
+        assert(bufferConfig->txPtpTsData);
+        assert(buffConfig->rxRingLen <= ENET_RXBUFFSTORE_NUM);
+
+        uint32_t index;
+
+        handle->rxBdRing[count].rxPtpTsDataRing.ptpTsData = buffConfig->rxPtpTsData;
+        handle->rxBdRing[count].rxPtpTsDataRing.front = 0;
+        handle->rxBdRing[count].rxPtpTsDataRing.end = 0;
+        handle->rxBdRing[count].rxPtpTsDataRing.size = buffConfig->ptpTsRxBuffNum;
+        handle->txBdRing[count].txPtpTsDataRing.ptpTsData = buffConfig->txPtpTsData;
+        handle->txBdRing[count].txPtpTsDataRing.front = 0;
+        handle->txBdRing[count].txPtpTsDataRing.end = 0;
+        handle->txBdRing[count].txPtpTsDataRing.size = buffConfig->ptpTsTxBuffNum;
+
+        for (index = 0; index < buffConfig->rxRingLen; index++)
+        {
+            handle->rxbuffers[index] = *(buffConfig->rxBufferStartAddr + index);
+        }
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+        /* Enable tx interrupt for use transactional API to do tx buffer free/requeue. */
+        base->DMA_CH[count].DMA_CHX_INT_EN |= ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+        /* Check if the rx interrrupt is enabled. */
+        rxIntEnable |= (base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK);
+        buffConfig++;
+    }
+
+    handle->rxintEnable = rxIntEnable ? true : false;
+
+    /* Save the handle pointer in the global variables. */
+    s_ENETHandle[ENET_GetInstance(base)] = handle;
+
+    /* Set callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable the NVIC for tx. */
+    s_enetIsr = ENET_IRQHandler;
+    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+}
+
+void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
+{
+    assert(macAddr);
+
+    uint32_t address = base->MAC_ADDR_LOW;
+
+    /* Get from physical address lower register. */
+    macAddr[2] = 0xFFU & (address >> 24U);
+    macAddr[3] = 0xFFU & (address >> 16U);
+    macAddr[4] = 0xFFU & (address >> 8U);
+    macAddr[5] = 0xFFU & address;
+
+    /* Get from physical address high register. */
+    address = base->MAC_ADDR_HIGH;
+    macAddr[0] = 0xFFU & (address >> 8U);
+    macAddr[1] = 0xFFU & address;
+}
+
+void ENET_SetSMI(ENET_Type *base)
+{
+    uint32_t crDiv;
+    uint32_t srcClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000000U;
+
+    if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35))
+    {
+        crDiv = 2;
+    }
+    else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60))
+    {
+        crDiv = 3;
+    }
+    else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150))
+    {
+        crDiv = 1;
+    }
+    else
+    {
+        crDiv = 0;
+    }
+
+    base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv);
+}
+
+void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
+
+    /* Build MII write command. */
+    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiWriteFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
+                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
+    base->MAC_MDIO_DATA = data;
+    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
+}
+
+void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
+{
+    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
+
+    /* Build MII read command. */
+    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiReadFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
+                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
+    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
+}
+
+void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter)
+{
+    uint8_t index;
+    uint32_t *reg = wakeFilter;
+
+    /* Disable the tx dma. */
+    base->DMA_CH[0].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->DMA_CH[1].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+
+    /* Disable the mac tx/rx. */
+    base->MAC_CONFIG &= ~(ENET_MAC_CONFIG_RE_MASK | ENET_MAC_CONFIG_TE_MASK);
+    /* Enable the remote wakeup packet and enable the power down mode. */
+    if (wakeFilter)
+    {
+        for (index = 0; index < ENET_WAKEUPFILTER_NUM; index++)
+        {
+            base->MAC_RWAKE_FRFLT = *reg;
+            reg++;
+        }
+    }
+    base->MAC_PMT_CRTL_STAT = ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK | ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK |
+                              ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
+
+    /* Enable the MAC rx. */
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
+}
+
+status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel)
+{
+    assert(handle);
+    assert(length);
+
+    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
+    enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+    uint16_t index;
+
+    /* Reset the length to zero. */
+    *length = 0;
+
+    if (rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK)
+    {
+        return kStatus_ENET_RxFrameEmpty;
+    }
+    else
+    {
+        do
+        {
+            /* Application owns the buffer descriptor, get the length. */
+            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+                if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK)
+                {
+                    return kStatus_ENET_RxFrameError;
+                }
+                *length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK;
+                return kStatus_Success;
+            }
+
+            index = ENET_IncreaseIndex(index, rxBdRing->rxRingLen);
+            rxDesc = rxBdRing->rxBdBase + index;
+        } while (index != rxBdRing->rxGenIdx);
+
+        return kStatus_ENET_RxFrameError;
+    }
+}
+
+status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel)
+{
+    assert(handle);
+
+    uint32_t len = 0;
+    uint32_t offset = 0;
+    uint32_t control;
+    bool isLastBuff = false;
+    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
+    enet_rx_bd_struct_t *rxDesc;
+    status_t result = kStatus_Fail;
+    uint16_t index = rxBdRing->rxGenIdx;
+    bool suspend = false;
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint32_t buffer;
+    uint32_t bufferAdd;
+#endif /* ENET_PTP1588FEATURE_REQUIRED  */
+
+    /* Suspend and command for rx. */
+    if (base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+    {
+        suspend = true;
+    }
+
+    /* For data-NULL input, only update the buffer descriptor. */
+    if ((!data))
+    {
+        do
+        {
+            /* Get the control flag. */
+            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+            control = rxDesc->control;
+            /* Updates the receive buffer descriptors. */
+            ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+
+            /* Find the last buffer descriptor for the frame. */
+            if (control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+                /* Reinit for the context descritor which has been updated by DMA. */
+                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
+                {
+                    if (!handle->doubleBuffEnable)
+                    {
+                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    else
+                    {
+                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
+                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+                }
+#endif /*  ENET_PTP1588FEATURE_REQUIRED */
+                break;
+            }
+        } while (rxBdRing->rxGenIdx != index);
+
+        result = kStatus_Success;
+    }
+    else
+    {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        enet_ptp_time_data_t ptpTsData;
+        bool ptp1588 = false;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+        while ((!isLastBuff))
+        {
+            /* The last buffer descriptor of a frame. */
+            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+            if (rxDesc->control & ENET_RXDESCRIP_WR_FD_MASK)
+            {
+                ptp1588 = ENET_Ptp1588ParseFrame((uint8_t *)rxDesc->buff1Addr, &ptpTsData, false);
+            }
+#endif
+            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+                /* This is a valid frame. */
+                isLastBuff = true;
+                if (length == (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK))
+                {
+                    /* Copy the frame to user's buffer. */
+                    len = (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK) - offset;
+                    if (len > rxBdRing->rxBuffSizeAlign)
+                    {
+                        memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
+                        offset += rxBdRing->rxBuffSizeAlign;
+                        memcpy(data + offset, (void *)rxDesc->buff2Addr, len - rxBdRing->rxBuffSizeAlign);
+                    }
+                    else
+                    {
+                        memcpy(data + offset, (void *)rxDesc->buff1Addr, len);
+                    }
+
+                    result = kStatus_Success;
+                }
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+                /* Store the rx timestamp which is in the next buffer descriptor of the last
+                 * descriptor of a frame. */
+                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+
+                /* Reinit for the context descritor which has been updated by DMA. */
+                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
+                {
+                    if (ptp1588)
+                    {
+                        ENET_StoreRxFrameTime(base, handle, rxDesc, channel, &ptpTsData);
+                    }
+
+                    if (!handle->doubleBuffEnable)
+                    {
+                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    else
+                    {
+                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
+                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+                }
+                base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+            }
+            else
+            {
+                /* Store a frame on several buffer descriptors. */
+                isLastBuff = false;
+                /* Length check. */
+                if (offset >= length)
+                {
+                    /* Updates the receive buffer descriptors. */
+                    ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+                    break;
+                }
+
+                memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
+                offset += rxBdRing->rxBuffSizeAlign;
+                if ((rxDesc->buff2Addr) && (handle->doubleBuffEnable))
+                {
+                    memcpy(data + offset, (void *)rxDesc->buff2Addr, rxBdRing->rxBuffSizeAlign);
+                    offset += rxBdRing->rxBuffSizeAlign;
+                }
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+            }
+        }
+    }
+
+    /* Set command for rx when it is suspend. */
+    if (suspend)
+    {
+        base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
+    }
+
+    return result;
+}
+
+void ENET_UpdateRxDescriptor(
+    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable)
+{
+    assert(rxDesc);
+    uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
+
+    if (intEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_IOC_MASK;
+    }
+
+    if (doubleBuffEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
+    }
+
+    /* Update the buffer if needed. */
+    if (buffer1)
+    {
+        rxDesc->buff1Addr = (uint32_t)buffer1;
+    }
+    if (buffer2)
+    {
+        rxDesc->buff2Addr = (uint32_t)buffer2;
+    }
+    else
+    {
+        rxDesc->buff2Addr = 0;
+    }
+
+    rxDesc->reserved = 0;
+    rxDesc->control = control;
+}
+
+void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
+                            void *buffer1,
+                            uint32_t bytes1,
+                            void *buffer2,
+                            uint32_t bytes2,
+                            uint32_t framelen,
+                            bool intEnable,
+                            bool tsEnable,
+                            enet_desc_flag flag,
+                            uint8_t slotNum)
+{
+    uint32_t control = ENET_TXDESCRIP_RD_BL1(bytes1) | ENET_TXDESCRIP_RD_BL2(bytes2);
+
+    if (tsEnable)
+    {
+        control |= ENET_TXDESCRIP_RD_TTSE_MASK;
+    }
+    else
+    {
+        control &= ~ENET_TXDESCRIP_RD_TTSE_MASK;
+    }
+
+    if (intEnable)
+    {
+        control |= ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+    else
+    {
+        control &= ~ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+
+    /* Preare the descriptor for transmit. */
+    txDesc->buff1Addr = (uint32_t)buffer1;
+    txDesc->buff2Addr = (uint32_t)buffer2;
+    txDesc->buffLen = control;
+
+    control = ENET_TXDESCRIP_RD_FL(framelen) | ENET_TXDESCRIP_RD_LDFD(flag) | ENET_TXDESCRIP_RD_OWN_MASK;
+
+    txDesc->controlStat = control;
+}
+
+void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel)
+{
+    enet_tx_bd_ring_t *txBdRing = &handle->txBdRing[channel];
+    enet_tx_bd_struct_t *txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
+
+    /* Need to update the first index for transmit buffer free. */
+    while ((txBdRing->txDescUsed > 0) && (!(txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK)))
+    {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        uint32_t nanosecond;
+        uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
+
+        if (txDesc->controlStat & ENET_TXDESCRIP_RD_LD_MASK)
+        {
+            enet_ptp_time_data_t *ptpTsData = txBdRing->txPtpTsDataRing.ptpTsData + txBdRing->txPtpTsDataRing.end;
+            if (txDesc->controlStat & ENET_TXDESCRIP_WB_TTSS_MASK)
+            {
+                /* Get transmit time stamp second. */
+                nanosecond = txDesc->buff2Addr | txDesc->buff1Addr;
+                if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+                {
+                    /* Binary rollover. */
+                    nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+                }
+                ptpTsData->timeStamp.second = nanosecond / nanoOverSize;
+                ptpTsData->timeStamp.nanosecond = nanosecond % nanoOverSize;
+
+                /* Store the timestamp to the transmit timestamp ring. */
+                ENET_Ptp1588UpdateTimeRing(&txBdRing->txPtpTsDataRing, ptpTsData);
+            }
+        }
+#endif  /* ENET_PTP1588FEATURE_REQUIRED */
+
+        /* For tx buffer free or requeue for each descriptor.
+         * The tx interrupt callback should free/requeue the tx buffer. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kENET_TxIntEvent, channel, handle->userData);
+        }
+
+        txBdRing->txDescUsed--;
+
+        /* Update the txConsumIdx/txDesc. */
+        txBdRing->txConsumIdx = ENET_IncreaseIndex(txBdRing->txConsumIdx, txBdRing->txRingLen);
+        txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
+    }
+}
+
+status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
+{
+    assert(handle);
+    assert(data);
+
+    enet_tx_bd_ring_t *txBdRing;
+    enet_tx_bd_struct_t *txDesc;
+    uint8_t channel = 0;
+    bool ptp1588 = false;
+
+    if (length > 2 * ENET_TXDESCRIP_RD_BL1_MASK)
+    {
+        return kStatus_ENET_TxFrameOverLen;
+    }
+
+    /* Choose the transit queue. */
+    channel = ENET_GetTxRingId(data, handle);
+
+    /* Check if the DMA owns the descriptor. */
+    txBdRing = (enet_tx_bd_ring_t *)&handle->txBdRing[channel];
+    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
+    if (txBdRing->txRingLen == txBdRing->txDescUsed)
+    {
+        return kStatus_ENET_TxFrameBusy;
+    }
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_t ptpTsData;
+
+    ptp1588 = ENET_Ptp1588ParseFrame(data, &ptpTsData, true);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+    /* Fill the descriptor. */
+    if (length <= ENET_TXDESCRIP_RD_BL1_MASK)
+    {
+        ENET_SetupTxDescriptor(txDesc, data, length, NULL, 0, length, true, ptp1588, kENET_FirstLastFlag, 0);
+    }
+    else
+    {
+        ENET_SetupTxDescriptor(txDesc, data, ENET_TXDESCRIP_RD_BL1_MASK, data + ENET_TXDESCRIP_RD_BL1_MASK,
+                               (length - ENET_TXDESCRIP_RD_BL1_MASK), length, true, ptp1588, kENET_FirstLastFlag, 0);
+    }
+
+    /* Increase the index. */
+    txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen);
+    /* Disable interrupt first and then enable interrupt to avoid the race condition. */
+    DisableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+    txBdRing->txDescUsed++;
+    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+
+    /* Update the transmit tail address. */
+    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
+    if (!txBdRing->txGenIdx)
+    {
+        txDesc = txBdRing->txBdBase + txBdRing->txRingLen;
+    }
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_ADDR_ALIGNMENT;
+
+    return kStatus_Success;
+}
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond)
+{
+    assert(second);
+    assert(nanosecond);
+
+    uint32_t primask;
+
+    /* Disables the interrupt. */
+    primask = DisableGlobalIRQ();
+
+    /* Get the current PTP time. */
+    *second = ((uint64_t)(base->MAC_SYS_TIME_HWORD_SCND & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) << 32U) |
+              base->MAC_SYS_TIME_SCND;
+    *nanosecond = base->MAC_SYS_TIME_NSCND & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+    {
+        /* Binary rollover, the unit of the increment is ~ 0.466 ns. */
+        *nanosecond = *nanosecond / 1000U * 466U;
+    }
+
+    /* Enables the interrupt. */
+    EnableGlobalIRQ(primask);
+}
+
+void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond)
+{
+    uint32_t corrSecond = second;
+    uint32_t corrNanosecond;
+
+    /* Set the system timer. */
+    if (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+    {
+        if (operation == kENET_SystimeSubtract)
+        {
+            /* Set with the complement of the sub-second. */
+            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
+                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_NANOSECS_ONESECOND - nanosecond);
+        }
+        else
+        {
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
+        }
+    }
+    else
+    {
+        nanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK / ENET_NANOSECS_ONESECOND * nanosecond;
+        if (operation == kENET_SystimeSubtract)
+        {
+            /* Set with the complement of the sub-second. */
+            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
+                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK + 1 - nanosecond);
+        }
+        else
+        {
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
+        }
+    }
+
+    base->MAC_SYS_TIME_SCND_UPD = corrSecond;
+    base->MAC_SYS_TIME_NSCND_UPD = corrNanosecond;
+
+    /* Update the timer. */
+    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK;
+    while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+        ;
+}
+
+status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(handle);
+    assert(ptpTimeData);
+
+    uint32_t result = kStatus_Success;
+    uint8_t count;
+    uint8_t index = handle->multiQueEnable ? 2 : 1;
+
+    for (count = 0; count < index; count++)
+    {
+        result = ENET_Ptp1588SearchTimeRing(&handle->txBdRing[count].txPtpTsDataRing, ptpTimeData);
+        if (result == kStatus_Success)
+        {
+            break;
+        }
+    }
+
+    return result;
+}
+
+status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(handle);
+    assert(ptpTimeData);
+
+    uint32_t result = kStatus_Success;
+    uint8_t count;
+    uint8_t index = handle->multiQueEnable ? 2 : 1;
+
+    for (count = 0; count < index; count++)
+    {
+        result = ENET_Ptp1588SearchTimeRing(&handle->rxBdRing[count].rxPtpTsDataRing, ptpTimeData);
+        if (result == kStatus_Success)
+        {
+            break;
+        }
+    }
+
+    return result;
+}
+
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle)
+{
+    /* Check for the interrupt source type. */
+    /* DMA CHANNEL 0. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC0IS_MASK)
+    {
+        uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT;
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+        {
+            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_RxIntEvent, 0, handle->userData);
+            }
+        }
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+        {
+            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            ENET_ReclaimTxDescriptor(base, handle, 0);
+        }
+    }
+
+    /* DMA CHANNEL 1. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC1IS_MASK)
+    {
+        uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT;
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+        {
+            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_RxIntEvent, 1, handle->userData);
+            }
+        }
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+        {
+            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            ENET_ReclaimTxDescriptor(base, handle, 1);
+        }
+    }
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    /* MAC TIMESTAMP. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_MACIS_MASK)
+    {
+        if (base->MAC_INTR_STAT & ENET_MAC_INTR_STAT_TSIS_MASK)
+        {
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_TimeStampIntEvent, 0, handle->userData);
+            }
+        }
+    }
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ETHERNET_DriverIRQHandler(void)
+{
+    s_enetIsr(ENET, s_ENETHandle[0]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1178 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_ENET_H_
+#define _FSL_ENET_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_enet
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines the driver version. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+/*! @name Control and status region bit masks of the receive buffer descriptor. */
+/*@{*/
+/*! @brief Defines for read format. */
+#define ENET_RXDESCRIP_RD_BUFF1VALID_MASK (1U << 24) /*!< Buffer1 address valid. */
+#define ENET_RXDESCRIP_RD_BUFF2VALID_MASK (1U << 25) /*!< Buffer2 address valid. */
+#define ENET_RXDESCRIP_RD_IOC_MASK (1U << 30)        /*!< Interrupt enable on complete. */
+#define ENET_RXDESCRIP_RD_OWN_MASK (1U << 31)        /*!< Own bit. */
+
+/*! @brief Defines for write back format. */
+#define ENET_RXDESCRIP_WR_ERR_MASK ((1U << 3) | (1U << 7))
+#define ENET_RXDESCRIP_WR_PYLOAD_MASK (0x7U)
+#define ENET_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00U)
+#define ENET_RXDESCRIP_WR_PTPTYPE_MASK (1U << 12)
+#define ENET_RXDESCRIP_WR_PTPVERSION_MASK (1U << 13)
+#define ENET_RXDESCRIP_WR_PTPTSA_MASK (1U << 14)
+#define ENET_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFU)
+#define ENET_RXDESCRIP_WR_ERRSUM_MASK (1U << 15)
+#define ENET_RXDESCRIP_WR_TYPE_MASK (0x30000U)
+#define ENET_RXDESCRIP_WR_DE_MASK (1U << 19)
+#define ENET_RXDESCRIP_WR_RE_MASK (1U << 20)
+#define ENET_RXDESCRIP_WR_OE_MASK (1U << 21)
+#define ENET_RXDESCRIP_WR_RS0V_MASK (1U << 25)
+#define ENET_RXDESCRIP_WR_RS1V_MASK (1U << 26)
+#define ENET_RXDESCRIP_WR_RS2V_MASK (1U << 27)
+#define ENET_RXDESCRIP_WR_LD_MASK (1U << 28)
+#define ENET_RXDESCRIP_WR_FD_MASK (1U << 29)
+#define ENET_RXDESCRIP_WR_CTXT_MASK (1U << 30)
+#define ENET_RXDESCRIP_WR_OWN_MASK (1U << 31)
+/*@}*/
+
+/*! @name Control and status bit masks of the transmit buffer descriptor. */
+/*@{*/
+/*! @brief Defines for read format. */
+#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU)
+#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16)
+#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK)
+#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16)
+#define ENET_TXDESCRIP_RD_TTSE_MASK (1U << 30)
+#define ENET_TXDESCRIP_RD_IOC_MASK (1U << 31)
+
+#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU)
+#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK)
+#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3) << 16)
+#define ENET_TXDESCRIP_RD_TSE_MASK (1U << 18)
+#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0f) << 19)
+#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07) << 23)
+#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03) << 26)
+#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03) << 28)
+#define ENET_TXDESCRIP_RD_LD_MASK (1U << 28)
+#define ENET_TXDESCRIP_RD_FD_MASK (1U << 29)
+#define ENET_TXDESCRIP_RD_CTXT_MASK (1U << 30)
+#define ENET_TXDESCRIP_RD_OWN_MASK (1UL << 31)
+
+/*! @brief Defines for write back format. */
+#define ENET_TXDESCRIP_WB_TTSS_MASK (1UL << 17)
+/*@}*/
+
+/*! @name Bit mask for interrupt enable type. */
+/*@{*/
+#define ENET_ABNORM_INT_MASK                                                      \
+    (ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_NORM_INT_MASK                                                        \
+    (ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+/*@}*/
+
+/*! @name Defines some Ethernet parameters. */
+/*@{*/
+
+#define ENET_FRAME_MAX_FRAMELEN (1518U)/*!< Default maximum Ethernet frame size. */
+#define ENET_ADDR_ALIGNMENT (0x3U)     /*!< Recommended ethernet buffer alignment. */
+#define ENET_BUFF_ALIGNMENT (4U)       /*!< Receive buffer alignment shall be 4bytes-aligned. */
+#define ENET_RING_NUM_MAX (2U)         /*!< The Maximum number of tx/rx descriptor rings. */
+#define ENET_MTL_RXFIFOSIZE (2048U)    /*!< The rx fifo size. */
+#define ENET_MTL_TXFIFOSIZE (2048U)    /*!< The tx fifo size. */
+#define ENET_MACINT_ENUM_OFFSET (16U)  /*!< The offest for mac interrupt in enum type. */
+/*@}*/
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/* Define the buffer length to store the rx buffers address.
+ * because the context descriptor will be updated for store the time
+ * stamp for rx frame. so we need to reinit the descriptors.
+ * This macro shall at least equal to the rxRingLen
+ * assigned in the enet_buffer_config. That means if the rx descriptor
+ * length is larger than 5, please increse this macro.  */
+#define ENET_RXBUFFSTORE_NUM (6)
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*! @brief Defines the status return codes for transaction. */
+enum _enet_status
+{
+    kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U),  /*!< A frame received but data error happen. */
+    kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U),   /*!< Failed to receive a frame. */
+    kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U),  /*!< No frame arrive. */
+    kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 3U),   /*!< Transmit descriptors are under process. */
+    kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U),   /*!< Transmit frame fail. */
+    kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit oversize. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    ,
+    kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */
+    kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */
+#endif                                                               /* ENET_PTP1588FEATURE_REQUIRED */
+};
+
+/*! @brief Defines the MII/RMII mode for data interface between the MAC and the PHY. */
+typedef enum _enet_mii_mode {
+    kENET_MiiMode = 0U, /*!< MII mode for data interface. */
+    kENET_RmiiMode = 1U /*!< RMII mode for data interface. */
+} enet_mii_mode_t;
+
+/*! @brief Defines the 10/100 Mbps speed for the MII data interface. */
+typedef enum _enet_mii_speed {
+    kENET_MiiSpeed10M = 0U,  /*!< Speed 10 Mbps. */
+    kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */
+} enet_mii_speed_t;
+
+/*! @brief Defines the half or full duplex for the MII data interface. */
+typedef enum _enet_mii_duplex {
+    kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
+    kENET_MiiFullDuplex       /*!< Full duplex mode. */
+} enet_mii_duplex_t;
+
+/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
+typedef enum _enet_mii_normal_opcode {
+    kENET_MiiWriteFrame = 1U, /*!< Write frame operation for a valid MII management frame. */
+    kENET_MiiReadFrame = 3U   /*!< Read frame operation for a valid MII management frame. */
+} enet_mii_normal_opcode;
+
+/*! @brief Define the DMA maximum transmit burst length. */
+typedef enum _enet_dma_burstlen {
+    kENET_BurstLen1 = 0x00001U,   /*!< DMA burst length 1. */
+    kENET_BurstLen2 = 0x00002U,   /*!< DMA burst length 2. */
+    kENET_BurstLen4 = 0x00004U,   /*!< DMA burst length 4. */
+    kENET_BurstLen8 = 0x00008U,   /*!< DMA burst length 8. */
+    kENET_BurstLen16 = 0x00010U,  /*!< DMA burst length 16. */
+    kENET_BurstLen32 = 0x00020U,  /*!< DMA burst length 32. */
+    kENET_BurstLen64 = 0x10008U,  /*!< DMA burst length 64. eight times enabled. */
+    kENET_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
+    kENET_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
+} enet_dma_burstlen;
+
+/*! @brief Define the flag for the descriptor. */
+typedef enum _enet_desc_flag {
+    kENET_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
+    kENET_FirstFlagOnly,  /*!< It's the first descriptor of the frame. */
+    kENET_LastFlagOnly,   /*!< It's the last descriptor of the frame. */
+    kENET_FirstLastFlag   /*!< It's the first and last descriptor of the frame. */
+} enet_desc_flag;
+
+/*! @brief Define the system time adjust operation control. */
+typedef enum _enet_systime_op {
+    kENET_SystimeAdd = 0U,     /*!< System time add to. */
+    kENET_SystimeSubtract = 1U /*!< System time subtract. */
+} enet_systime_op;
+
+/*! @brief Define the system time rollover control. */
+typedef enum _enet_ts_rollover_type {
+    kENET_BinaryRollover = 0, /*!< System time binary rollover.*/
+    kENET_DigitalRollover = 1 /*!< System time digital rollover.*/
+} enet_ts_rollover_type;
+
+/*! @brief Defines some special configuration for ENET.
+ *
+ * These control flags are provided for special user requirements.
+ * Normally, these is no need to set this control flags for ENET initialization.
+ * But if you have some special requirements, set the flags to specialControl
+ * in the enet_config_t.
+ * @note "kENET_StoreAndForward" is recommended to be set when the
+ * ENET_PTP1588FEATURE_REQUIRED is defined or else the timestamp will be mess-up
+ * when the overflow happens.
+ */
+typedef enum _enet_special_config {
+
+    /***********************DMA CONFGI**********************************************/
+    kENET_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
+    /**************************MTL************************************/
+    kENET_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
+    /***********************MAC****************************************/
+    kENET_PromiscuousEnable = 0x0004U,  /*!< The promiscuous enabled. */
+    kENET_FlowControlEnable = 0x0008U,  /*!< The flow control enabled. */
+    kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
+    kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
+    kENET_8023AS2KPacket = 0x0040U      /*!< 8023as support for 2K packets. */
+} enet_special_config_t;
+
+/*! @brief List of DMA interrupts supported by the ENET interrupt. This
+ * enumeration uses one-bot encoding to allow a logical OR of multiple
+ * members.
+ */
+typedef enum _enet_dma_interrupt_enable {
+    kENET_DmaTx = ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK,                 /*!< Tx interrupt. */
+    kENET_DmaTxStop = ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK,             /*!< Tx stop interrupt. */
+    kENET_DmaTxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK,     /*!< Tx buffer unavailable. */
+    kENET_DmaRx = ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK,                 /*!< Rx interrupt. */
+    kENET_DmaRxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK,     /*!< Rx buffer unavailable. */
+    kENET_DmaRxStop = ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK,             /*!< Rx stop. */
+    kENET_DmaRxWatchdogTimeout = ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
+    kENET_DmaEarlyTx = ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK,           /*!< Early transmit. */
+    kENET_DmaEarlyRx = ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK,           /*!< Early receive. */
+    kENET_DmaBusErr = ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK,            /*!< Fatal bus error. */
+} enet_dma_interrupt_enable_t;
+
+/*! @brief List of mac interrupts supported by the ENET interrupt. This
+ * enumeration uses one-bot encoding to allow a logical OR of multiple
+ * members.
+ */
+typedef enum _enet_mac_interrupt_enable {
+    kENET_MacPmt = (ENET_MAC_INTR_EN_PMTIE_MASK << ENET_MACINT_ENUM_OFFSET),
+    kENET_MacTimestamp = (ENET_MAC_INTR_EN_TSIE_MASK << ENET_MACINT_ENUM_OFFSET),
+} enet_mac_interrupt_enable_t;
+
+/*! @brief Defines the common interrupt event for callback use. */
+typedef enum _enet_event {
+    kENET_RxIntEvent,     /*!< Receive interrupt event. */
+    kENET_TxIntEvent,     /*!< Transmit interrupt event. */
+    kENET_WakeUpIntEvent, /*!< Wake up interrupt event. */
+    kENET_TimeStampIntEvent, /*!< Time stamp interrupt event. */
+} enet_event_t;
+
+/*! @brief Define the DMA transmit arbitration for multi-queue. */
+typedef enum _enet_dma_tx_sche {
+    kENET_FixPri = 0,      /*!< Fixed priority. channel 0 has lower priority than channel 1. */
+    kENET_WeightStrPri,    /*!< Weighted(burst length) strict priority. */
+    kENET_WeightRoundRobin /*!< Weighted (weight factor) round robin. */
+} enet_dma_tx_sche;
+
+/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
+typedef enum _enet_mtl_multiqueue_txsche {
+    kENET_txWeightRR = 0U, /*!< Tx weight round-robin. */
+    kENET_txStrPrio = 3U,  /*!< Tx strict priority. */
+} enet_mtl_multiqueue_txsche;
+
+/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
+typedef enum _enet_mtl_multiqueue_rxsche {
+    kENET_rxStrPrio = 0U,  /*!< Tx weight round-robin, rx strict priority. */
+    kENET_rxWeightStrPrio, /*!< Tx strict priority, rx weight strict priority. */
+} enet_mtl_multiqueue_rxsche;
+
+/*! @brief Define the MTL rx queue and DMA channel mapping. */
+typedef enum _enet_mtl_rxqueuemap {
+    kENET_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) direclty map to dma channel n. */
+    kENET_DynamicMap =
+        0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
+                    */
+} enet_mtl_rxqueuemap;
+
+/*! @brief Defines the ENET PTP message related constant. */
+typedef enum _enet_ptp_event_type {
+    kENET_PtpEventMsgType = 3U,  /*!< PTP event message type. */
+    kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
+    kENET_PtpEventPort = 319U,   /*!< PTP event port number. */
+    kENET_PtpGnrlPort = 320U     /*!< PTP general port number. */
+} enet_ptp_event_type_t;
+
+/*! @brief Defines the receive descriptor structure
+ *  has the read-format and write-back format structure. They both
+ *  has the same size with different region definition. so
+ *  we define the read-format region as the recive descriptor structure
+ *  Use the read-format region mask bits in the descriptor initialization
+ *  Use the write-back format region mask bits in the receive data process.
+ */
+typedef struct _enet_rx_bd_struct
+{
+    __IO uint32_t buff1Addr; /*!< Buffer 1 address */
+    __IO uint32_t reserved;  /*!< Reserved */
+    __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
+    __IO uint32_t control;   /*!< Buffer 1/2 byte counts and control */
+} enet_rx_bd_struct_t;
+
+/*! @brief Defines the transmit descriptor structure
+ *  has the read-format and write-back format structure. They both
+ *  has the same size with different region definition. so
+ *  we define the read-format region as the transmit descriptor structure
+ *  Use the read-format region mask bits in the descriptor initialization
+ *  Use the write-back format region mask bits in the transmit data process.
+ */
+typedef struct _enet_tx_bd_struct
+{
+    __IO uint32_t buff1Addr;   /*!< Buffer 1 address */
+    __IO uint32_t buff2Addr;   /*!< Buffer 2 address */
+    __IO uint32_t buffLen;     /*!< Buffer 1/2 byte counts */
+    __IO uint32_t controlStat; /*!< TDES control and status word */
+} enet_tx_bd_struct_t;
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*! @brief Defines the ENET PTP time stamp structure. */
+typedef struct _enet_ptp_time
+{
+    uint64_t second;     /*!< Second. */
+    uint32_t nanosecond; /*!< Nanosecond. */
+} enet_ptp_time_t;
+
+/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/
+typedef struct _enet_ptp_time_data
+{
+    uint8_t version;                             /*!< PTP version. */
+    uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */
+    uint16_t sequenceId;                         /*!< PTP sequence ID. */
+    uint8_t messageType;                         /*!< PTP message type. */
+    enet_ptp_time_t timeStamp;                   /*!< PTP timestamp. */
+} enet_ptp_time_data_t;
+
+/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/
+typedef struct _enet_ptp_time_data_ring
+{
+    uint32_t front;                  /*!< The first index of the ring. */
+    uint32_t end;                    /*!< The end index of the ring. */
+    uint32_t size;                   /*!< The size of the ring. */
+    enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */
+} enet_ptp_time_data_ring_t;
+
+/*! @brief Defines the ENET PTP configuration structure. */
+typedef struct _enet_ptp_config
+{
+    bool fineUpdateEnable;            /*!< Use the fine update. */
+    bool ptp1588V2Enable;             /*!< ptp 1588 version 2 is used. */
+    enet_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
+} enet_ptp_config_t;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*! @brief Defines the buffer descriptor configure structure.
+ *
+ * Notes:
+ * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
+ * 2. The recommended minimum tx/rx ring length is 4.
+ * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
+ *    of the last last descriptor. because only the descriptors between the start address and the
+ *    tail address will be used by DMA.
+ * 4. The decriptor address is the start address of all used contiguous memory.
+ *    for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memorise
+ *    for rx descriptor ring 0.
+ * 5. The "*rxBufferstartAddr" is the first element of  rxRingLen (2*rxRingLen for double buffers)
+ *    rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
+ *    the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
+ *    the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
+ *    address of a rxRingLen or 2*rxRingLen array.
+ */
+typedef struct _enet_buffer_config
+{
+    uint8_t rxRingLen;                         /*!< The length of receive buffer descriptor ring. */
+    uint8_t txRingLen;                         /*!< The length of transmit buffer descriptor ring. */
+    enet_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
+    enet_tx_bd_struct_t *txDescTailAddrAlign;  /*!< Aligned transmit descriptor tail address. */
+    enet_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
+    enet_rx_bd_struct_t *rxDescTailAddrAlign;  /*!< Aligned receive descriptor tail address. */
+    uint32_t *rxBufferStartAddr;               /*!< Start address of the rx buffers. */
+    uint32_t rxBuffSizeAlign;                  /*!< Aligned receive data buffer size. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint8_t ptpTsRxBuffNum;            /*!< Receive 1588 timestamp buffer number*/
+    uint8_t ptpTsTxBuffNum;            /*!< Transmit 1588 timestamp buffer number*/
+    enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */
+    enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */
+#endif                                 /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_buffer_config_t;
+
+/*! @brief Defines the configuration when multi-queue is used. */
+typedef struct enet_multiqueue_config
+{
+    /***********************DMA block*******************************/
+    enet_dma_tx_sche dmaTxSche;                /*!< Transmit arbitation. */
+    enet_dma_burstlen burstLen;                /*!< Burset len for the queue 1. */
+    uint8_t txdmaChnWeight[ENET_RING_NUM_MAX]; /*!< Transmit channel weight. */
+    /***********************MTL block*******************************/
+    enet_mtl_multiqueue_txsche mtltxSche;    /*!< Transmit schedule for multi-queue. */
+    enet_mtl_multiqueue_rxsche mtlrxSche;    /*!< Receive schedule for multi-queue. */
+    uint8_t rxqueweight[ENET_RING_NUM_MAX];  /*!< Refer to the MTL RxQ Control register. */
+    uint32_t txqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL TxQ Quantum Weight register. */
+    uint8_t rxqueuePrio[ENET_RING_NUM_MAX];  /*!< Receive queue priority. */
+    uint8_t txqueuePrio[ENET_RING_NUM_MAX];  /*!< Refer to Transmit Queue Priority Mapping register. */
+    enet_mtl_rxqueuemap mtlrxQuemap;         /*!< Rx queue DMA Channel mapping. */
+} enet_multiqueue_config_t;
+
+/*! @brief Defines the basic configuration structure for the ENET device.
+ *
+ * Note:
+ *  1. Default the signal queue is used so the "*multiqueueCfg" is set default
+ *  with NULL. Set the pointer with a valid configration pointer if the multiple
+ *  queues are required. If multiple queue is enabled, please make sure the
+ *  buffer configuration for all are prepared also.
+ */
+typedef struct _enet_config
+{
+    uint16_t specialControl;                 /*!< The logicl or of enet_special_config_t */
+    enet_multiqueue_config_t *multiqueueCfg; /*!< Use both tx/rx queue(dma channel) 0 and 1. */
+    /* -----------------MAC block-------------------------------*/
+    enet_mii_mode_t miiMode;     /*!< MII mode. */
+    enet_mii_speed_t miiSpeed;   /*!< MII Speed. */
+    enet_mii_duplex_t miiDuplex; /*!< MII duplex. */
+    uint16_t pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_FlowControlEnable is set. */
+/* -----------------Timestamp -------------------------------*/
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
+#endif                            /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_config_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _enet_handle enet_handle_t;
+
+/*! @brief ENET callback function. */
+typedef void (*enet_callback_t)(
+    ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *userData);
+
+/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
+typedef struct _enet_tx_bd_ring
+{
+    enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
+    uint16_t txGenIdx;             /*!< tx generate index. */
+    uint16_t txConsumIdx;          /*!< tx consum index. */
+    volatile uint16_t txDescUsed;  /*!< tx descriptor used number. */
+    uint16_t txRingLen;            /*!< tx ring length. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */
+#endif                                         /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_tx_bd_ring_t;
+
+/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
+typedef struct _enet_rx_bd_ring
+{
+    enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
+    uint16_t rxGenIdx;             /*!< The current available receive buffer descriptor pointer. */
+    uint16_t rxRingLen;            /*!< Receive ring length. */
+    uint32_t rxBuffSizeAlign;      /*!< Receive buffer size. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */
+#endif                                         /* ENET_PTP1588FEATURE_REQUIRED*/
+} enet_rx_bd_ring_t;
+
+/*! @brief Defines the ENET handler structure. */
+struct _enet_handle
+{
+    bool multiQueEnable;                           /*!< Enable multi-queue. */
+    bool doubleBuffEnable;                         /*!< The double buffer is used in the descriptor. */
+    bool rxintEnable;                              /*!< Rx interrup enabled. */
+    enet_rx_bd_ring_t rxBdRing[ENET_RING_NUM_MAX]; /*!< Receive buffer descriptor.  */
+    enet_tx_bd_ring_t txBdRing[ENET_RING_NUM_MAX]; /*!< Transmit buffer descriptor.  */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint32_t rxbuffers[ENET_RXBUFFSTORE_NUM]; /*!< The Initi-rx buffers will be used for reInitialize. */
+#endif
+    enet_callback_t callback; /*!< Callback function. */
+    void *userData;           /*!< Callback function parameter.*/
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+  * @name Initialization and De-initialization
+  * @{
+  */
+
+/*!
+ * @brief Gets the ENET default configuration structure.
+ *
+ * The purpose of this API is to get the default ENET configure
+ * structure for ENET_Init(). User may use the initialized
+ * structure unchanged in ENET_Init(), or modify some fields of the
+ * structure before calling ENET_Init().
+ * Example:
+   @code
+   enet_config_t config;
+   ENET_GetDefaultConfig(&config);
+   @endcode
+ * @param config The ENET mac controller configuration structure pointer.
+ */
+void ENET_GetDefaultConfig(enet_config_t *config);
+
+/*!
+ * @brief Initializes the ENET module.
+ *
+ * This function ungates the module clock and initializes it with the ENET basic
+ * configuration.
+ *
+ * @param base    ENET peripheral base address.
+ * @param config  ENET mac configuration structure pointer.
+ *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
+ *        can be used directly. It is also possible to verify the Mac configuration using other methods.
+ * @param macAddr  ENET mac address of Ethernet device. This MAC address should be
+ *        provided.
+ * @param refclkSrc_Hz ENET input reference clock.
+ */
+void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz);
+
+/*!
+ * @brief Deinitializes the ENET module.
+
+ * This function gates the module clock and disables the ENET module.
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_Deinit(ENET_Type *base);
+
+/*!
+ * @brief Initialize for all ENET descriptors.
+ *
+ * @note This function is do all tx/rx descriptors initialization. Because this API 
+ *  read all interrupt registers first and then set the interrupt flag for all descriptos, 
+ * if the interrupt register is set. so the descriptor initialization should be called
+ * after ENET_Init(), ENET_EnableInterrupts() and ENET_CreateHandle()(if transactional APIs
+ * are used).
+ *
+ * @param base  ENET peripheral base address.
+ * @param config The configuration for ENET.
+ * @param bufferConfig All buffers configuration.
+ */
+status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig);
+
+/*!
+ * @brief Starts the ENET rx/tx.
+ *  This function enable the tx/rx and starts the rx/tx DMA.
+ * This shall be set after ENET initialization and before
+ * starting to receive the data.
+ *
+ * @param base  ENET peripheral base address.
+ * @param rxRingNum  The number of the used rx rings. It shall not be
+ * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
+ * 1, the ring 0 will be used.
+ * @param txRingNum  The number of the used tx rings. It shall not be
+ * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
+ * 1, the ring 0 will be used.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
+
+/* @} */
+
+/*!
+ * @name MII interface operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the ENET MII speed and duplex.
+ *
+ * This API is provided to dynamically change the speed and dulpex for MAC.
+ *
+ * @param base  ENET peripheral base address.
+ * @param speed The speed of the RMII mode.
+ * @param duplex The duplex of the RMII mode.
+ */
+static inline void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
+{
+    uint32_t reg = base->MAC_CONFIG & ~(ENET_MAC_CONFIG_DM_MASK | ENET_MAC_CONFIG_FES_MASK);
+    reg |= ENET_MAC_CONFIG_DM(duplex) | ENET_MAC_CONFIG_FES(speed);
+
+    base->MAC_CONFIG = reg;
+}
+
+/*!
+ * @brief Sets the ENET SMI(serial management interface)- MII management interface.
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_SetSMI(ENET_Type *base);
+
+/*!
+ * @brief Checks if the SMI is busy.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The status of MII Busy status.
+ */
+static inline bool ENET_IsSMIBusy(ENET_Type *base)
+{
+    return (base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_MB_MASK) ? true : false;
+}
+
+/*!
+ * @brief Reads data from the PHY register through SMI interface.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The data read from PHY
+ */
+static inline uint16_t ENET_ReadSMIData(ENET_Type *base)
+{
+    return (uint16_t)(base->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_MD_MASK);
+}
+
+/*!
+ * @brief Starts an SMI read command.
+ * support both MDIO IEEE802.3 Clause 22 and clause 45.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ */
+void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg);
+
+/*!
+ * @brief Starts a SMI write command.
+ * support both MDIO IEEE802.3 Clause 22 and clause 45.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param data The data written to PHY.
+ */
+void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+/* @} */
+
+/*!
+ * @name Other basic operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the ENET module Mac address.
+ *
+ * @param base  ENET peripheral base address.
+ * @param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
+static inline void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
+{
+    assert(macAddr);
+
+    /* Set Macaddr */
+    base->MAC_ADDR_LOW = ((uint32_t)macAddr[3] << 24) | ((uint32_t)macAddr[2] << 16) | ((uint32_t)macAddr[1] << 8) |
+                         ((uint32_t)macAddr[0]);
+    base->MAC_ADDR_HIGH = ((uint32_t)macAddr[5] << 8) | ((uint32_t)macAddr[4]);
+}
+
+/*!
+ * @brief Gets the ENET module Mac address.
+ *
+ * @param base  ENET peripheral base address.
+ * @param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
+void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr);
+
+/*!
+ * @brief Set the MAC to enter into power down mode.
+ * the remote power wake up frame and magic frame can wake up
+ * the ENET from the power down mode.
+ *
+ * @param base    ENET peripheral base address.
+ * @param wakeFilter  The wakeFilter provided to configure the wake up frame fitlter.
+ *  Set the wakeFilter to NULL is not required. But if you have the filter requirement,
+ *  please make sure the wakeFilter pointer shall be eight continous
+ *  32-bits configuration.
+ */
+void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter);
+
+/*!
+ * @brief Set the MAC to exit power down mode.
+ * Eixt from the power down mode and recover to noraml work mode.
+ *
+ * @param base    ENET peripheral base address.
+ */
+static inline void ENET_ExitPowerDown(ENET_Type *base)
+{
+    /* Clear and status ans reset the power down. */
+    base->MAC_PMT_CRTL_STAT &= ~ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
+
+    /* Restore the tx which is disabled when enter power down mode. */
+    base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enables the ENET DMA and MAC interrupts.
+ *
+ * This function enables the ENET interrupt according to the provided mask. The mask
+ * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ * For example, to enable the dma and mac interrupt, do the following.
+ * @code
+ *     ENET_EnableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupts to enable. This is a logical OR of both 
+ *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ */
+void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the ENET DMA and MAC interrupts.
+ *
+ * This function disables the ENET interrupt according to the provided mask. The mask
+ * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ * For example, to disable the dma and mac interrupt, do the following.
+ * @code
+ *     ENET_DisableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupts to disables. This is a logical OR of both 
+ *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ */
+void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask);
+    
+/*!
+ * @brief Gets the ENET DMA interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
+ * @return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: enet_dma_interrupt_enable_t.
+ */
+static inline uint32_t ENET_GetDmaInterruptStatus(ENET_Type *base, uint8_t channel)
+{
+    return base->DMA_CH[channel].DMA_CHX_STAT;
+}
+
+/*!
+ * @brief Clear the ENET DMA interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
+ * @return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: enet_dma_interrupt_enable_t.
+ */
+static inline void ENET_ClearDmaInterruptStatus(ENET_Type *base, uint8_t channel, uint32_t mask)
+{
+    /* Clear the dam interrupt status bit in dma channel interrupt status register. */
+    base->DMA_CH[channel].DMA_CHX_STAT = mask;
+}
+
+/*!
+ * @brief Gets the ENET MAC interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The event status of the interrupt source. 
+ *       Use the enum in enet_mac_interrupt_enable_t and right shift
+ *       ENET_MACINT_ENUM_OFFSET to mask the returned value to get the 
+ *       exact interrupt status.
+ */
+static inline uint32_t ENET_GetMacInterruptStatus(ENET_Type *base)
+{
+    return base->MAC_INTR_STAT;
+}
+
+/*!
+ * @brief Clears the ENET mac interrupt events status flag.
+ *
+ * This function clears enabled ENET interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref enet_mac_interrupt_enable_t.
+ * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
+ * @code
+ *     ENET_ClearMacInterruptStatus(ENET, kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupt source to be cleared.
+ * This is the logical OR of members of the enumeration :: enet_mac_interrupt_enable_t.
+ */
+void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Functional operation.
+ * @{
+ */
+
+/*!
+ * @brief Get the tx descriptor DMA Own flag.
+ *
+ * @param txDesc  The given tx descriptor.
+ * @retval True the dma own tx descriptor, false application own tx descriptor.
+ *
+ */
+static inline bool ENET_IsTxDescriptorDmaOwn(enet_tx_bd_struct_t *txDesc)
+{
+    return (txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK) ? true : false;
+}
+
+/*!
+ * @brief Setup a given tx descriptor.
+ *  This function is a low level functional API to setup or prepare
+ *  a given tx descriptor.
+ *
+ * @param txDesc  The given tx descriptor.
+ * @param buffer1  The first buffer address in the descriptor.
+ * @param bytes1  The bytes in the fist buffer.
+ * @param buffer2  The second buffer address in the descriptor.
+ * @param bytes1  The bytes in the second buffer.
+ * @param framelen  The length of the frame to be transmitted.
+ * @param intEnable Interrupt enable flag.
+ * @param tsEnable The timestamp enable.
+ * @param flag The flag of this tx desciriptor, see "enet_desc_flag" .
+ * @param slotNum The slot num used for AV  only.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
+ * memory until the packet has been fully transmitted. The buffers
+ * should be free or requeued in the transmit interrupt irq handler.
+ */
+void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
+                            void *buffer1,
+                            uint32_t bytes1,
+                            void *buffer2,
+                            uint32_t bytes2,
+                            uint32_t framelen,
+                            bool intEnable,
+                            bool tsEnable,
+                            enet_desc_flag flag,
+                            uint8_t slotNum);
+
+/*!
+ * @brief Update the tx descriptor tail pointer.
+ *  This function is a low level functional API to update the
+ *  the tx descriptor tail.
+ *  This is called after you setup a new tx descriptor to update
+ *  the tail pointer to make the new descritor accessable by DMA.
+ *
+ * @param base    ENET peripheral base address.
+ * @param channel  The tx DMA channel.
+ * @param txDescTailAddrAlign  The new tx tail pointer address.
+ *
+ */
+static inline void ENET_UpdateTxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
+{
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
+}
+
+/*!
+ * @brief Update the rx descriptor tail pointer.
+ *  This function is a low level functional API to update the
+ *  the rx descriptor tail.
+ *  This is called after you setup a new rx descriptor to update
+ *  the tail pointer to make the new descritor accessable by DMA
+ *  and to anouse the rx poll command for DMA.
+ *
+ * @param base    ENET peripheral base address.
+ * @param channel  The rx DMA channel.
+ * @param rxDescTailAddrAlign  The new rx tail pointer address.
+ *
+ */
+static inline void ENET_UpdateRxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
+{
+    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
+}
+
+/*!
+ * @brief Gets the context in the ENET rx descriptor.
+ *  This function is a low level functional API to get the
+ *  the status flag from a given rx descriptor.
+ *
+ * @param rxDesc  The given rx descriptor.
+ * @retval The RDES3 regions for write-back format rx buffer descriptor.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+static inline uint32_t ENET_GetRxDescriptor(enet_rx_bd_struct_t *rxDesc)
+{
+    assert(rxDesc);
+
+    return rxDesc->control;
+}
+/*!
+ * @brief Updates the buffers and the own status for a given rx descriptor.
+ *  This function is a low level functional API to Updates the
+ *  buffers and the own status for a given rx descriptor.
+ *
+ * @param rxDesc  The given rx descriptor.
+ * @param buffer1  The first buffer address in the descriptor.
+ * @param buffer2  The second buffer address in the descriptor.
+ * @param intEnable Interrupt enable flag.
+ * @param doubleBuffEnable The double buffer enable flag.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+void ENET_UpdateRxDescriptor(
+    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
+
+/* @} */
+
+/*!
+ * @name Transactional operation
+ * @{
+ */
+
+/*!
+ * @brief Create ENET Handler 
+ *
+ * This is a transactional API and it's provided to store all datas which are needed
+ * during the whole transactional process. This API should not be used when you use
+ * functional APIs to do data tx/rx. This is funtion will store many data/flag for 
+ * transactional use, so all configure API such as ENET_Init(), ENET_DescriptorInit(),
+ * ENET_EnableInterrupts() etc.
+ *
+ * @note as our transactional transmit API use the zero-copy transmit buffer.
+ * so there are two thing we emphasize here:
+ *  1. tx buffer free/requeue for application should be done in the tx 
+ *  interrupt handler. Please set callback: kENET_TxIntEvent with tx buffer free/requeue
+ *  process APIs.
+ *  2. the tx interrupt is forced to open.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle ENET handler.
+ * @param config ENET configuration.
+ * @param bufferConfig ENET buffer configuration.
+ * @param callback The callback function.
+ * @param userData The application data.
+ */
+void ENET_CreateHandler(ENET_Type *base,
+                        enet_handle_t *handle,
+                        enet_config_t *config,
+                        enet_buffer_config_t *bufferConfig,
+                        enet_callback_t callback,
+                        void *userData);
+
+/*!
+* @brief Gets the size of the read frame.
+* This function gets a received frame size from the ENET buffer descriptors.
+* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+*
+* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+* @param length The length of the valid frame received.
+* @param channel The DMAC channel for the rx.
+* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+*         and NULL length to update the receive buffers.
+* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+*         should be called with the right data buffer and the captured data length input.
+*/
+status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel);
+
+/*!
+ * @brief Reads a frame from the ENET device.
+ * This function reads a frame from the ENET DMA descriptors.
+ * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
+ * For example use rx dma channel 0:
+ * @code
+ *       uint32_t length;
+ *       enet_handle_t g_handle;
+ *       //Get the received frame size firstly.
+ *       status = ENET_GetRxFrameSize(&g_handle, &length, 0);
+ *       if (length != 0)
+ *       {
+ *           //Allocate memory here with the size of "length"
+ *           uint8_t *data = memory allocate interface;
+ *           if (!data)
+ *           {
+ *               ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
+ *               //Add the console warning log.
+ *           }
+ *           else
+ *           {
+ *              status = ENET_ReadFrame(ENET, &g_handle, data, length, 0);
+ *              //Call stack input API to deliver the data to stack
+ *           }
+ *       }
+ *       else if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *          //Update the received buffer when a error frame is received.
+ *           ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
+ *       }
+ * @endcode
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
+ * @param length The size of the data buffer which is still the length of the received frame.
+ * @param channel The rx DMA channel. shall not be larger than 2.
+ * @return The execute status, successful or failure.
+ */
+status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel);
+
+/*!
+ * @brief Transmits an ENET frame.
+ * @note The CRC is automatically appended to the data. Input the data
+ * to send without the CRC.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * @param data The data buffer provided by user to be send.
+ * @param length The length of the data to be send.
+ * @retval kStatus_Success  Send frame succeed.
+ * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
+ */
+status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Reclaim tx descriptors.
+ *  This function is used to update the tx descriptor status and
+ *  store the tx timestamp when the 1588 feature is enabled.
+ *  This is called by the transmit interupt IRQ handler after the
+ *  complete of a frame transmission.
+ *
+ * @param base    ENET peripheral base address.
+ * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * @param channel  The tx DMA channnel.
+ *
+ */
+void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel);
+
+/*!
+ * @brief The ENET PMT IRQ handler.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer.
+ */
+void ENET_PMTIRQHandler(ENET_Type *base, enet_handle_t *handle);
+
+/*!
+ * @brief The ENET IRQ handler.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer.
+ */
+void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle);
+
+/* @} */
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*!
+ * @name ENET Enhanced function operation
+ * @{
+ */
+
+/*!
+ * @brief Starts the ENET PTP 1588 Timer.
+ * This function is used to initialize the PTP timer. After the PTP starts,
+ * the PTP timer starts running.
+ *
+ * @param base  ENET peripheral base address.
+ * @param ptpClkSrc The clock source of the PTP timer.
+ */
+void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc);
+
+/*!
+ * @brief Coreect the ENET PTP 1588 timer in coarse method.
+ *
+ * @param base  ENET peripheral base address.
+ * @param operation The system time operation, refer to "enet_systime_op"
+ * @param second The correction second.
+ * @param nanosecond The correction nanosecond.
+ */
+void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond);
+
+/*!
+ * @brief Coreect the ENET PTP 1588 timer in fine method.
+ *
+ *
+ * @param base  ENET peripheral base address.
+ * @param addend The addend value to be set in the fine method
+ * @note Should take refer to the chapter "System time corretion" and
+ * see the description for the "fine correction method".
+ */
+static inline void ENET_Ptp1588CorrectTimerInFine(ENET_Type *base, uint32_t addend)
+{
+    /* Set the freqCompensation value. */
+    base->MAC_SYS_TIMESTMP_ADDEND = addend;
+    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
+}
+
+/*!
+ * @brief Get the ENET Time stamp current addend value.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The addend value.
+ */
+static inline uint32_t ENET_Ptp1588GetAddend(ENET_Type *base)
+{
+    return base->MAC_SYS_TIMESTMP_ADDEND;
+}
+
+/*!
+ * @brief Gets the current ENET time from the PTP 1588 timer.
+ *
+ * @param base  ENET peripheral base address.
+ * @param second The PTP 1588 system timer second.
+ * @param nanosecond The PTP 1588 system timer nanosecond.
+ * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
+ */
+void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond);
+
+/*!
+ * @brief Gets the time stamp of the received frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * @param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * @retval kStatus_Success Get 1588 timestamp success.
+ * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
+status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
+
+/*!
+ * @brief Gets the time stamp of the transmit frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * @param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * @retval kStatus_Success Get 1588 timestamp success.
+ * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
+status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_ENET_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flashiap.h"
+
+#define HZ_TO_KHZ_DIV 1000
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t translate_iap_status(uint32_t status)
+{
+    /* Translate IAP return code to sdk status code */
+    if (status == kStatus_Success)
+    {
+        return status;
+    }
+    else
+    {
+        return MAKE_STATUS(kStatusGroup_FLASHIAP, status);
+    }
+}
+
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_CopyRamToFlash;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_EraseSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_ErasePage;
+    command[1] = startPage;
+    command[2] = endPage;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_BlankCheckSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_Compare;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLASHIAP_H_
+#define _FSL_FLASHIAP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flashiap_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*!
+ * @brief Flashiap status codes.
+ */
+enum _flashiap_status
+{
+    kStatus_FLASHIAP_Success = kStatus_Success,                               /*!< Api is executed successfully */
+    kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */
+    kStatus_FLASHIAP_SrcAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */
+    kStatus_FLASHIAP_DstAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */
+    kStatus_FLASHIAP_SrcAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */
+    kStatus_FLASHIAP_DstAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */
+    kStatus_FLASHIAP_CountError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */
+    kStatus_FLASHIAP_InvalidSector =
+        MAKE_STATUS(kStatusGroup_FLASHIAP,
+                    7), /*!< Sector number is invalid or end sector number is greater than start sector number */
+    kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */
+    kStatus_FLASHIAP_NotPrepared =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */
+    kStatus_FLASHIAP_CompareError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */
+    kStatus_FLASHIAP_Busy =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */
+    kStatus_FLASHIAP_ParamError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */
+    kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */
+    kStatus_FLASHIAP_AddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 14U),                        /*!< Address is not mapped in the memory map */
+    kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */
+    kStatus_FLASHIAP_NoClock =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */
+};
+
+/*!
+ * @brief Flashiap command codes.
+ */
+enum _flashiap_commands
+{
+    kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */
+    kIapCmd_FLASHIAP_CopyRamToFlash = 51U,        /*!< Copy RAM to flash */
+    kIapCmd_FLASHIAP_EraseSector = 52U,           /*!< Erase Sector */
+    kIapCmd_FLASHIAP_BlankCheckSector = 53U,      /*!< Blank check sector */
+    kIapCmd_FLASHIAP_ReadPartId = 54U,            /*!< Read part id */
+    kIapCmd_FLASHIAP_Read_BootromVersion = 55U,   /*!< Read bootrom version */
+    kIapCmd_FLASHIAP_Compare = 56U,               /*!< Compare */
+    kIapCmd_FLASHIAP_ReinvokeISP = 57U,           /*!< Reinvoke ISP */
+    kIapCmd_FLASHIAP_ReadUid = 58U,               /*!< Read Uid isp */
+    kIapCmd_FLASHIAP_ErasePage = 59U,             /*!< Erase Page */
+    kIapCmd_FLASHIAP_ReadMisr = 70U,              /*!< Read Misr */
+    kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U      /*!< Reinvoke I2C/SPI isp */
+};
+
+/*! @brief IAP_ENTRY API function type */
+typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief IAP_ENTRY API function type
+ *
+ * Wrapper for rom iap call
+ *
+ * @param cmd_param IAP command and relevant parameter array.
+ * @param status_result IAP status result array.
+ *
+ * @retval None. Status/Result is returned via status_result array.
+ */
+static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
+{
+    ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
+}
+
+/*!
+ * @brief	Prepare sector for write operation
+
+ * This function prepares sector(s) for write/erase operation. This function must be
+ * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or
+ * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to
+ * start sector number.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief	Copy RAM to flash.
+
+ * This function programs the flash memory. Corresponding sectors must be prepared
+ * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses
+ * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
+ *
+ * @param dstAddr Destination flash address where data bytes are to be written.
+ * @param srcAddr Source ram address from where data bytes are to be read.
+ * @param numOfBytes Number of bytes to be written.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary.
+ * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock);
+
+/*!
+ * @brief	Erase sector
+
+ * This function erases sector(s). The end sector must be greater than or equal to
+ * start sector number. FLASHIAP_PrepareSectorForWrite must be called before
+ * calling this function.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
+
+/*!
+
+ * This function erases page(s). The end page must be greater than or equal to
+ * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite
+ * before calling calling this function.
+ *
+ * @param startPage Start page number
+ * @param endPage End page number
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number
+ *         is greater than start page number
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock);
+
+/*!
+ * @brief Blank check sector(s)
+ *
+ * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
+ * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call.
+ *
+ * @param	startSector	: Start sector number. Must be greater than or equal to start sector number
+ * @param	endSector	: End sector number
+ * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank.
+ */
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief Compare memory contents of flash with ram.
+
+ * This function compares the contents of flash and ram. It can be used to verify the flash
+ * memory contents after FLASHIAP_CopyRamToFlash call.
+ *
+ * @param dstAddr Destination flash address.
+ * @param srcAddr Source ram address.
+ * @param numOfBytes Number of bytes to be compared.
+ *
+ * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match.
+ */
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLASHIAP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX))
+    {
+        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1 << 7)) > 0 ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if ((uint32_t)base == s_flexcommBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+/* Changes FLEXCOMM mode */
+status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    int idx = FLEXCOMM_GetInstance(base);
+
+    if (idx < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance] = handle;
+    s_flexcommIrqHandler[instance] = handler;
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[0]);
+    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[1]);
+    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[2]);
+    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[3]);
+    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[4]);
+    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[5]);
+    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[6]);
+    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[7]);
+    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[8]);
+    s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[9]);
+    s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fmc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void FMC_GetDefaultConfig(fmc_config_t *config)
+{
+    config->waitStates = 0x05;
+}
+
+void FMC_Init(FMC_Type *base, fmc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to FMC */
+    CLOCK_EnableClock(kCLOCK_Fmc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set control register, FS_RD0 = 0, FS_RD1 = 1. */
+    base->FCTR &= ~(FMC_FCTR_FS_RD0_MASK | FMC_FCTR_FS_RD1_MASK);
+    base->FCTR |= FMC_FCTR_FS_RD1_MASK;
+
+    /* Set wait state, same as FLASHTIM in SYSCON->FLASHCFG register. */
+    base->FBWST &= ~FMC_FBWST_WAITSTATES_MASK;
+    base->FBWST |= config->waitStates;
+}
+
+void FMC_Denit(FMC_Type *base)
+{
+    /* Reset FMC module */
+    RESET_PeripheralReset(kFMC_RST_SHIFT_RSTn);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to FMC */
+    CLOCK_DisableClock(kCLOCK_Fmc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void FMC_GenerateFlashSignature(FMC_Type *base,
+                                uint32_t startAddress,
+                                uint32_t length,
+                                fmc_flash_signature_t *flashSignature)
+{
+    uint32_t stopAddress;
+
+    /* Clear generation done flag. */
+    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
+
+    /* Calculate flash stop address */
+    stopAddress = ((startAddress + length - 1) >> 4) & FMC_FMSSTOP_STOP_MASK;
+
+    /* Calculate flash start address. */
+    startAddress = (startAddress >> 4) & FMC_FMSSTART_START_MASK;
+
+    /* Start flash signature generation. */
+    base->FMSSTART = startAddress;
+    base->FMSSTOP = stopAddress;
+
+    base->FMSSTOP |= FMC_FMSSTOP_SIG_START_MASK;
+
+    /* Wait for signature done. */
+    while ((base->FMSTAT & kFMC_SignatureGenerationDoneFlag) != kFMC_SignatureGenerationDoneFlag)
+    {
+    }
+
+    /* Clear generation done flag. */
+    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
+
+    /* Get the generated flash signature. */
+    flashSignature->word0 = base->FMSW[0];
+    flashSignature->word1 = base->FMSW[1];
+    flashSignature->word2 = base->FMSW[2];
+    flashSignature->word3 = base->FMSW[3];
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FMC_H_
+#define _FSL_FMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup fmc
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_FMC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+/*@}*/
+
+/*!
+ * @addtogroup fmc_driver
+ * @{
+ */
+
+/*!
+ * @brief fmc peripheral flag.
+ *
+ */
+enum _fmc_flags
+{
+    kFMC_SignatureGenerationDoneFlag = FMC_FMSTAT_SIG_DONE_MASK, /*!< Flash signature generation done. */
+};
+
+/*! @brief Defines the generated 128-bit signature. */
+typedef struct _fmc_flash_signature
+{
+    uint32_t word0; /* Signature bits [31:0]. */
+    uint32_t word1; /* Signature bits [63:32]. */
+    uint32_t word2; /* Signature bits [95:64]. */
+    uint32_t word3; /* Signature bits [127:96]. */
+} fmc_flash_signature_t;
+
+/*! @brief fmc config structure. */
+typedef struct _fmc_config
+{
+    uint8_t waitStates; /* flash timing value for flash signature generation. */
+} fmc_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize FMC module.
+ *
+ * This function initialize FMC module with user configuration
+ *
+ * @param base The FMC peripheral base address.
+ * @param config pointer to user configuration structure.
+ */
+void FMC_Init(FMC_Type *base, fmc_config_t *config);
+
+/*!
+ * @brief Deinit FMC module.
+ *
+ * This function De-initialize FMC module.
+ *
+ * @param base The FMC peripheral base address.
+ */
+void FMC_Deinit(FMC_Type *base);
+
+/*!
+ * @brief Provides default configuration for fmc module.
+ *
+ * This function provides default configuration for fmc module, the default wait states value is
+ * 5.
+ *
+ * @param config pointer to user configuration structure.
+ */
+void FMC_GetDefaultConfig(fmc_config_t *config);
+
+/*!
+ * @brief Generate hardware flash signature.
+ *
+ * This function generates hardware flash signature for specified address range.
+ *
+ * @note This function needs to be excuted out of flash memory.
+ * @param base The FMC peripheral base address.
+ * @param startAddress Flash start address for signature generation.
+ * @param length Length of address range.
+ * @param flashSignature Pointer which stores the generated flash signarue.
+ */
+void FMC_GenerateFlashSignature(FMC_Type *base,
+                                uint32_t startAddress,
+                                uint32_t length,
+                                fmc_flash_signature_t *flashSignature);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fmeas.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Target clock counter value.
+ * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */
+#define TARGET_CLOCK_COUNT(base) \
+    ((uint32_t)(                 \
+        ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2))
+
+/*! @brief Reference clock counter value. */
+#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate)
+{
+    uint32_t targetClockCount = TARGET_CLOCK_COUNT(base);
+    uint64_t clkrate = 0;
+
+    if (targetClockCount > 0)
+    {
+        clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT;
+    }
+
+    return (uint32_t)clkrate;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FMEAS_H_
+#define _FSL_FMEAS_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup fmeas
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC Frequency Measure driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name FMEAS Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief    Starts a frequency measurement cycle.
+ *
+ * @param    base : SYSCON peripheral base address.
+ */
+static inline void FMEAS_StartMeasure(SYSCON_Type *base)
+{
+    base->FREQMECTRL = 0;
+    base->FREQMECTRL = (1UL << 31);
+}
+
+/*!
+ * @brief    Indicates when a frequency measurement cycle is complete.
+ *
+ * @param    base : SYSCON peripheral base address.
+ * @return   true if a measurement cycle is active, otherwise false.
+ */
+static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base)
+{
+    return (bool)((base->FREQMECTRL & (1UL << 31)) == 0);
+}
+
+/*!
+ * @brief    Returns the computed value for a frequency measurement cycle
+ *
+ * @param    base         : SYSCON peripheral base address.
+ * @param    refClockRate : Reference clock rate used during the frequency measurement cycle.
+ *
+ * @return   Frequency in Hz.
+ */
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_FMEAS_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to GINT bases for each instance. */
+static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Clocks for each instance. */
+static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Resets for each instance. */
+static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
+
+/* @brief Irq number for each instance */
+static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
+
+/*! @brief Callback function array for GINT(s). */
+static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GINT_GetInstance(GINT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
+    {
+        if (s_gintBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gintBases));
+
+    return instance;
+}
+
+void GINT_Init(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    s_gintCallback[instance] = NULL;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_gintClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+}
+
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
+
+    /* Save callback pointer */
+    s_gintCallback[instance] = callback;
+}
+
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
+    *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
+    *callback = s_gintCallback[instance];
+}
+
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
+{
+    base->PORT_POL[port] = polarityMask;
+    base->PORT_ENA[port] = enableMask;
+}
+
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
+{
+    *polarityMask = base->PORT_POL[port];
+    *enableMask = base->PORT_ENA[port];
+}
+
+void GINT_EnableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    /* If GINT is configured in "AND" mode a spurious interrupt is generated.
+       Clear status and pending interrupt before enabling the irq in NVIC. */
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+    EnableIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_DisableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    DisableIRQ(s_gintIRQ[instance]);
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_Deinit(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    /* Cleanup */
+    GINT_DisableCallback(base);
+    s_gintCallback[instance] = NULL;
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(s_gintClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(GINT0)
+void GINT0_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[0] != NULL)
+    {
+        s_gintCallback[0]();
+    }
+}
+#endif
+
+#if defined(GINT1)
+void GINT1_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[1] != NULL)
+    {
+        s_gintCallback[1]();
+    }
+}
+#endif
+
+#if defined(GINT2)
+void GINT2_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[2] != NULL)
+    {
+        s_gintCallback[2]();
+    }
+}
+#endif
+
+#if defined(GINT3)
+void GINT3_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[3] != NULL)
+    {
+        s_gintCallback[3]();
+    }
+}
+#endif
+
+#if defined(GINT4)
+void GINT4_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[4] != NULL)
+    {
+        s_gintCallback[4]();
+    }
+}
+#endif
+
+#if defined(GINT5)
+void GINT5_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[5] != NULL)
+    {
+        s_gintCallback[5]();
+    }
+}
+#endif
+
+#if defined(GINT6)
+void GINT6_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[6] != NULL)
+    {
+        s_gintCallback[6]();
+    }
+}
+#endif
+
+#if defined(GINT7)
+void GINT7_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[7] != NULL)
+    {
+        s_gintCallback[7]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_GINT_H_
+#define _FSL_GINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+/*! @brief GINT combine inputs type */
+typedef enum _gint_comb
+{
+    kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
+    kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
+} gint_comb_t;
+
+/*! @brief GINT trigger type */
+typedef enum _gint_trig
+{
+    kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
+    kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
+} gint_trig_t;
+
+/* @brief GINT port type */
+typedef enum _gint_port
+{
+    kGINT_Port0 = 0U,
+    kGINT_Port1 = 1U,
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
+    kGINT_Port2 = 2U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
+    kGINT_Port3 = 3U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
+    kGINT_Port4 = 4U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
+    kGINT_Port5 = 5U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
+    kGINT_Port6 = 6U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
+    kGINT_Port7 = 7U,
+#endif
+} gint_port_t;
+
+/*! @brief GINT Callback function. */
+typedef void (*gint_cb_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize GINT peripheral.
+
+ * This function initializes the GINT peripheral and enables the clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Init(GINT_Type *base);
+
+/*!
+ * @brief	Setup GINT peripheral control parameters.
+
+ * This function sets the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
+ * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
+ * @param callback This function is called when configured group interrupt is generated.
+ *
+ * @retval None.
+ */
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
+
+/*!
+ * @brief	Get GINT peripheral control parameters.
+
+ * This function returns the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Pointer to store combine input value.
+ * @param trig Pointer to store trigger value.
+ * @param callback Pointer to store callback function.
+ *
+ * @retval None.
+ */
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
+
+/*!
+ * @brief	Configure GINT peripheral pins.
+
+ * This function enables and controls the polarity of enabled pin(s) of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Each bit position selects if the corresponding pin is enabled or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
+
+/*!
+ * @brief	Get GINT peripheral pin configuration.
+
+ * This function returns the pin configuration of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
+ enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
+ or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_EnableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected GINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void GINT_DisableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Clear GINT status.
+
+ * This function clears the GINT status bit.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void GINT_ClrStatus(GINT_Type *base)
+{
+    base->CTRL |= GINT_CTRL_INT_MASK;
+}
+
+/*!
+ * @brief	Get GINT status.
+
+ * This function returns the GINT status.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval status = 0 No group interrupt request.  = 1 Group interrupt request active.
+ */
+static inline uint32_t GINT_GetStatus(GINT_Type *base)
+{
+    return (base->CTRL & GINT_CTRL_INT_MASK);
+}
+
+/*!
+ * @brief	Deinitialize GINT peripheral.
+
+ * This function disables the GINT clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Deinit(GINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_GINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+* Prototypes
+************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->DIR[port] &= ~(1U << pin);
+    }
+    else
+    {
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1U << pin);
+        }
+        else
+        {
+            base->SET[port] = (1U << pin);
+        }
+        /* Set pin direction */
+        base->DIR[port] |= 1U << pin;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version 2.0.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1398 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c.h"
+#include "fsl_flexcomm.h"
+#include <stdlib.h>
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i2c_flag_constants
+{
+    kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK,
+    kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK,
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base);
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal);
+static uint32_t I2C_SlavePollPending(I2C_Type *base);
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event);
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map i2c instance number to base address. */
+static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS;
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Returns an instance number given a base address.
+ *
+ * If an invalid base address is passed, debug builds will assert. Release builds will just return
+ * instance number 0.
+ *
+ * @param base The I2C peripheral base address.
+ * @return I2C instance number starting from 0.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+    int i;
+    for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++)
+    {
+        if ((uint32_t)base == s_i2cBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+    assert(false);
+    return 0;
+}
+
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+    masterConfig->enableMaster = true;
+    masterConfig->baudRate_Bps = 100000U;
+    masterConfig->enableTimeout = false;
+}
+
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+    I2C_MasterEnable(base, masterConfig->enableMaster);
+    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
+}
+
+void I2C_MasterDeinit(I2C_Type *base)
+{
+    I2C_MasterEnable(base, false);
+}
+
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t scl, divider;
+    uint32_t best_scl, best_div;
+    uint32_t err, best_err;
+
+    best_err = 0;
+
+    for (scl = 9; scl >= 2; scl--)
+    {
+        /* calculated ideal divider value for given scl */
+        divider = srcClock_Hz / (baudRate_Bps * scl * 2u);
+
+        /* adjust it if it is out of range */
+        divider = (divider > 0x10000u) ? 0x10000 : divider;
+
+        /* calculate error */
+        err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider);
+        if ((err < best_err) || (best_err == 0))
+        {
+            best_div = divider;
+            best_scl = scl;
+            best_err = err;
+        }
+
+        if ((err == 0) || (divider >= 0x10000u))
+        {
+            /* either exact value was found
+               or divider is at its max (it would even greater in the next iteration for sure) */
+            break;
+        }
+    }
+
+    base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1);
+    base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u);
+}
+
+static uint32_t I2C_PendingStatusWait(I2C_Type *base)
+{
+    uint32_t status;
+
+    do
+    {
+        status = I2C_GetStatusFlags(base);
+    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+    /* Clear controller state. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    return status;
+}
+
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    I2C_PendingStatusWait(base);
+
+    /* Write Address and RW bit to data register */
+    base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u);
+    /* Start the transfer */
+    base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterStop(I2C_Type *base)
+{
+    I2C_PendingStatusWait(base);
+
+    base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+    return kStatus_Success;
+}
+
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)
+{
+    uint32_t status;
+    uint32_t master_state;
+    status_t err;
+
+    const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff;
+
+    assert(txBuff);
+
+    err = kStatus_Success;
+    while (txSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & I2C_STAT_MSTARBLOSS_MASK)
+        {
+            return kStatus_I2C_ArbitrationLost;
+        }
+
+        if (status & I2C_STAT_MSTSTSTPERR_MASK)
+        {
+            return kStatus_I2C_StartStopError;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_TXREADY:
+                /* ready to send next byte */
+                base->MSTDAT = *buf++;
+                txSize--;
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    status = I2C_PendingStatusWait(base);
+
+    if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0)
+    {
+        if (!(flags & kI2C_TransferNoStopFlag))
+        {
+            /* Initiate stop */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            status = I2C_PendingStatusWait(base);
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
+{
+    uint32_t status = 0;
+    uint32_t master_state;
+    status_t err;
+
+    uint8_t *buf = (uint8_t *)(rxBuff);
+
+    assert(rxBuff);
+
+    err = kStatus_Success;
+    while (rxSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK))
+        {
+            break;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_RXREADY:
+                /* ready to send next byte */
+                *(buf++) = base->MSTDAT;
+                if (--rxSize)
+                {
+                    base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                }
+                else
+                {
+                    if ((flags & kI2C_TransferNoStopFlag) == 0)
+                    {
+                        /* initiate NAK and stop */
+                        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                        status = I2C_PendingStatusWait(base);
+                    }
+                }
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
+{
+    status_t result = kStatus_Success;
+    uint32_t subaddress;
+    uint8_t subaddrBuf[4];
+    int i;
+
+    assert(xfer);
+
+    /* If repeated start is requested, send repeated start. */
+    if (!(xfer->flags & kI2C_TransferNoStartFlag))
+    {
+        if (xfer->subaddressSize)
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write);
+            if (result == kStatus_Success)
+            {
+                /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+                subaddress = xfer->subaddress;
+                for (i = xfer->subaddressSize - 1; i >= 0; i--)
+                {
+                    subaddrBuf[i] = subaddress & 0xff;
+                    subaddress >>= 8;
+                }
+                /* Send subaddress. */
+                result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag);
+                if ((result == kStatus_Success) && (xfer->direction == kI2C_Read))
+                {
+                    result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+                }
+            }
+        }
+        else if (xfer->flags & kI2C_TransferRepeatedStartFlag)
+        {
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+        }
+        else
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction);
+        }
+    }
+
+    if (result == kStatus_Success)
+    {
+        if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
+        {
+            /* Transmit data. */
+            result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+        }
+        else
+        {
+            if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
+            {
+                /* Receive Data. */
+                result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+            }
+        }
+    }
+
+    if (result == kStatus_I2C_Nak)
+    {
+        I2C_MasterStop(base);
+    }
+
+    return result;
+}
+
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+    EnableIRQ(s_i2cIRQ[instance]);
+}
+
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachine(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_MasterIrqFlags);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    uint32_t status;
+    uint32_t master_state;
+
+    if (handle->state != kIdleState)
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Wait until module is ready */
+        status = I2C_PendingStatusWait(base);
+
+        /* Get the state of the I2C module */
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        {
+            /* Send a stop command to finalize the transfer. */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+            /* Wait until the STOP is completed */
+            I2C_PendingStatusWait(base);
+        }
+
+        /* Reset handle. */
+        handle->state = kIdleState;
+    }
+}
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytes = transfer->dataSize;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Execute states until FIFOs are exhausted.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    status_t err;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+    switch (handle->state)
+    {
+        case kStartState:
+            if (handle->remainingSubaddr)
+            {
+                /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = kTransmitSubaddrState;
+            }
+            else if (transfer->direction == kI2C_Write)
+            {
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = handle->remainingBytes ? kTransmitDataState : kStopState;
+            }
+            else
+            {
+                base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+                handle->state = handle->remainingBytes ? kReceiveDataState : kStopState;
+            }
+            /* Send start condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+            break;
+
+        case kTransmitSubaddrState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            /* Most significant subaddress byte comes first */
+            base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr];
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--(handle->remainingSubaddr))
+            {
+                /* There are still subaddress bytes to be transmitted */
+                break;
+            }
+            if (handle->remainingBytes)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            base->MSTDAT = *(handle->buf)++;
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--handle->remainingBytes == 0)
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kReceiveDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            *(handle->buf)++ = base->MSTDAT;
+            if (--handle->remainingBytes)
+            {
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            }
+            else
+            {
+                /* No more data expected, issue NACK and STOP right away */
+                base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                handle->state = kWaitForCompletionState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachine(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+/*!
+ * @brief Sets the hardware slave state machine to reset
+ *
+ * Per documentation, the only the state machine is reset, the configuration settings remain.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */
+}
+
+/*!
+ * @brief Compute CLKDIV
+ *
+ * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency.
+ * This setting is used by hardware during slave clock stretching.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status of the operation
+ */
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal)
+{
+    uint32_t dataSetupTime_ns;
+
+    switch (busSpeed)
+    {
+        case kI2C_SlaveStandardMode:
+            dataSetupTime_ns = 250u;
+            break;
+
+        case kI2C_SlaveFastMode:
+            dataSetupTime_ns = 100u;
+            break;
+
+        case kI2C_SlaveFastModePlus:
+            dataSetupTime_ns = 50u;
+            break;
+
+        case kI2C_SlaveHsMode:
+            dataSetupTime_ns = 10u;
+            break;
+
+        default:
+            dataSetupTime_ns = 0;
+            break;
+    }
+
+    if (0 == dataSetupTime_ns)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */
+    *divVal = srcClock_Hz / 1000u;
+    *divVal = (*divVal) * dataSetupTime_ns;
+    *divVal = (*divVal) / 1000000u;
+
+    if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK)
+    {
+        *divVal = I2C_CLKDIV_DIVVAL_MASK;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Poll wait for the SLVPENDING flag.
+ *
+ * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status register at time the SLVPENDING bit is read as set
+ */
+static uint32_t I2C_SlavePollPending(I2C_Type *base)
+{
+    uint32_t stat;
+
+    do
+    {
+        stat = base->STAT;
+    } while (0u == (stat & I2C_STAT_SLVPENDING_MASK));
+
+    return stat;
+}
+
+/*!
+ * @brief Invoke event from I2C_SlaveTransferHandleIRQ().
+ *
+ * Sets the event type to transfer structure and invokes the event callback, if it has been
+ * enabled by eventMask.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle The I2C slave handle for non-blocking APIs.
+ * @param event The I2C slave event to invoke.
+ */
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event)
+{
+    handle->transfer.event = event;
+    if ((handle->callback) && (handle->transfer.eventMask & event))
+    {
+        handle->callback(base, &handle->transfer, handle->userData);
+
+        /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */
+        if (false == handle->isBusy)
+        {
+            if (((handle->transfer.txData) && (handle->transfer.txSize)) ||
+                ((handle->transfer.rxData) && (handle->transfer.rxSize)))
+            {
+                handle->isBusy = true;
+            }
+        }
+
+        /* Clear the transferred count now that we have a new buffer. */
+        if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent))
+        {
+            handle->transfer.transferredCount = 0;
+        }
+    }
+}
+
+/*!
+ * @brief Handle slave address match event.
+ *
+ * Called by Slave interrupt routine to ACK or NACK the matched address.
+ * It also determines master direction (read or write).
+ *
+ * @param base The I2C peripheral base address.
+ * @return true if the matched address is ACK'ed
+ * @return false if the matched address is NACK'ed
+ */
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint8_t addressByte0;
+
+    addressByte0 = (uint8_t)base->SLVDAT;
+
+    /* store the matched address */
+    handle->transfer.receivedAddress = addressByte0;
+
+    /* R/nW */
+    if (addressByte0 & 1u)
+    {
+        /* if we have no data in this transfer, call callback to get new */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+        }
+
+        /* NACK if we have no data in this transfer. */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants to read, so slave transmit is next state */
+        handle->slaveFsm = kI2C_SlaveFsmTransmit;
+    }
+    else
+    {
+        /* if we have no receive buffer in this transfer, call callback to get new */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+        }
+
+        /* NACK if we have no data in this transfer */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants write, so slave receive is next state */
+        handle->slaveFsm = kI2C_SlaveFsmReceive;
+    }
+
+    /* continue transaction */
+    base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+    return true;
+}
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only.
+ * @param txSize Size of txData buffer in bytes.
+ * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL
+ *               if slave TX only.
+ * @param rxSize Size of rxData buffer in bytes.
+ *
+ * @retval #kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask)
+{
+    status_t status;
+
+    assert(handle);
+
+    status = kStatus_Success;
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->isBusy)
+    {
+        status = kStatus_I2C_Busy;
+    }
+
+    /* Save transfer into handle. */
+    handle->transfer.txData = (const uint8_t *)(uintptr_t)txData;
+    handle->transfer.txSize = txSize;
+    handle->transfer.rxData = (uint8_t *)rxData;
+    handle->transfer.rxSize = rxSize;
+    handle->transfer.transferredCount = 0;
+    handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+    handle->isBusy = true;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* Clear w1c flags. */
+    base->STAT |= 0u;
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    return status;
+}
+
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask);
+}
+
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable)
+{
+    base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable);
+}
+
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    i2c_slave_config_t mySlaveConfig = {0};
+
+    /* default config enables slave address 0 match to general I2C call address zero */
+    mySlaveConfig.enableSlave = true;
+    mySlaveConfig.address1.addressDisable = true;
+    mySlaveConfig.address2.addressDisable = true;
+    mySlaveConfig.address3.addressDisable = true;
+
+    *slaveConfig = mySlaveConfig;
+}
+
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
+{
+    status_t status;
+    uint32_t divVal = 0;
+
+    /* configure data setup time used when slave stretches clock */
+    status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+
+    /* I2C Clock Divider register */
+    base->CLKDIV = divVal;
+
+    /* set Slave address */
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address,
+                        slaveConfig->address0.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address,
+                        slaveConfig->address1.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address,
+                        slaveConfig->address2.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address,
+                        slaveConfig->address3.addressDisable);
+
+    /* set Slave address 0 qual */
+    base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress);
+
+    /* set Slave enable */
+    base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave);
+
+    return status;
+}
+
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false);
+}
+
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    const uint8_t *buf = txBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveTransmit;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+    /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */
+    if (!(slaveAddress || slaveTransmit))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* send bytes up to txSize */
+    while (txSize)
+    {
+        slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+        if (!slaveTransmit)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Write 8 bits of data to the SLVDAT register */
+        base->SLVDAT = I2C_SLVDAT_DATA(*buf);
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        txSize--;
+
+        if (txSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    uint8_t *buf = rxBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveReceive;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+    /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */
+    if (!(slaveAddress || slaveReceive))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* receive bytes up to rxSize */
+    while (rxSize)
+    {
+        slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+        if (!slaveReceive)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Read 8 bits of data from the SLVDAT register */
+        *buf = (uint8_t)base->SLVDAT;
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        rxSize--;
+
+        if (rxSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* initialize fsm */
+    handle->slaveFsm = kI2C_SlaveFsmAddressMatch;
+
+    /* store pointer to handle into transfer struct */
+    handle->transfer.handle = handle;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+    EnableIRQ(s_i2cIRQ[instance]);
+}
+
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (!handle->isBusy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* For an active transfer, just return the count from the handle. */
+    *count = handle->transfer.transferredCount;
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Set the SLVEN bit to 0 in the CFG register. */
+    I2C_SlaveEnable(base, false);
+
+    handle->isBusy = false;
+    handle->transfer.txSize = 0;
+    handle->transfer.rxSize = 0;
+}
+
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint32_t i2cStatus = base->STAT;
+
+    if (i2cStatus & I2C_STAT_SLVDESEL_MASK)
+    {
+        I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent);
+        I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK);
+    }
+
+    /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */
+    if (i2cStatus & I2C_STAT_SLVPENDING_MASK)
+    {
+        bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+
+        if (slaveAddress)
+        {
+            I2C_SlaveAddressIRQ(base, handle);
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent);
+        }
+        else
+        {
+            switch (handle->slaveFsm)
+            {
+                case kI2C_SlaveFsmReceive:
+                {
+                    bool slaveReceive =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+                    if (slaveReceive)
+                    {
+                        /* if we have no receive buffer in this transfer, call callback to get new */
+                        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+                        }
+
+                        /* receive a byte */
+                        if ((handle->transfer.rxData) && (handle->transfer.rxSize))
+                        {
+                            *(handle->transfer.rxData) = (uint8_t)base->SLVDAT;
+                            (handle->transfer.rxSize)--;
+                            (handle->transfer.rxData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                case kI2C_SlaveFsmTransmit:
+                {
+                    bool slaveTransmit =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+                    if (slaveTransmit)
+                    {
+                        /* if we have no data in this transfer, call callback to get new */
+                        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+                        }
+
+                        /* transmit a byte */
+                        if ((handle->transfer.txData) && (handle->transfer.txSize))
+                        {
+                            base->SLVDAT = *(handle->transfer.txData);
+                            (handle->transfer.txSize)--;
+                            (handle->transfer.txData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                default:
+                    /* incorrect state, slv_abort()? */
+                    break;
+            }
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1039 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_H_
+#define _FSL_I2C_H_
+
+#include <stddef.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define I2C_CFG_MASK 0x1f
+
+/*!
+ * @addtogroup i2c_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C driver version 1.0.0. */
+#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* definitions for MSTCODE bits in I2C Status register STAT */
+#define I2C_STAT_MSTCODE_IDLE (0)    /*!< Master Idle State Code */
+#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
+#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
+#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
+#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
+
+/* definitions for SLVSTATE bits in I2C Status register STAT */
+#define I2C_STAT_SLVST_ADDR (0)
+#define I2C_STAT_SLVST_RX (1)
+#define I2C_STAT_SLVST_TX (2)
+
+/*! @brief I2C status return codes. */
+enum _i2c_status
+{
+    kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */
+    kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */
+    kStatus_I2C_Nak =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */
+    kStatus_I2C_InvalidParameter =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */
+    kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */
+    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */
+    kStatus_I2C_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
+    kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
+    kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
+    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*!
+ * @brief I2C master peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_master_flags
+{
+    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
+    kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
+};
+
+/*! @brief Direction of master and slave transfers. */
+typedef enum _i2c_direction
+{
+    kI2C_Write = 0U, /*!< Master transmit. */
+    kI2C_Read = 1U   /*!< Master receive. */
+} i2c_direction_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C master module.
+ *
+ * This structure holds configuration settings for the I2C peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_master_config
+{
+    bool enableMaster;     /*!< Whether to enable master mode. */
+    uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */
+    bool enableTimeout;    /*!< Enable internal timeout function. */
+} i2c_master_config_t;
+
+/* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief I2C master transfer typedef */
+typedef struct _i2c_master_transfer i2c_master_transfer_t;
+
+/*! @brief I2C master handle typedef */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*!
+ * @brief Master completion callback function pointer type.
+ *
+ * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use
+ * in the call to I2C_MasterTransferCreateHandle().
+ *
+ * @param base The I2C peripheral base address.
+ * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+                                               i2c_master_handle_t *handle,
+                                               status_t completionStatus,
+                                               void *userData);
+
+/*!
+ * @brief Transfer option flags.
+ *
+ * @note These enumerations are intended to be OR'd together to form a bit mask of options for
+ * the #_i2c_master_transfer::flags field.
+ */
+enum _i2c_master_transfer_flags
+{
+    kI2C_TransferDefaultFlag = 0x00U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x01U,       /*!< Don't send a start condition, address, and sub address */
+    kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
+    kI2C_TransferNoStopFlag = 0x04U,        /*!< Don't send a stop condition. */
+};
+
+/*! @brief States for the state machine used by transactional APIs. */
+enum _i2c_transfer_states
+{
+    kIdleState = 0,
+    kTransmitSubaddrState,
+    kTransmitDataState,
+    kReceiveDataState,
+    kReceiveLastDataState,
+    kStartState,
+    kStopState,
+    kWaitForCompletionState
+};
+
+/*!
+ * @brief Non-blocking transfer descriptor structure.
+ *
+ * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API.
+ */
+struct _i2c_master_transfer
+{
+    uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available
+                       options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */
+    uint16_t slaveAddress;     /*!< The 7-bit slave address. */
+    i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */
+    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
+    size_t subaddressSize;     /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
+    void *data;                /*!< Pointer to data to transfer. */
+    size_t dataSize;           /*!< Number of bytes to transfer. */
+};
+
+/*!
+ * @brief Driver handle for master non-blocking APIs.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_master_handle
+{
+    uint8_t state;           /*!< Transfer state machine current state. */
+    uint32_t transferCount;  /*!< Indicates progress of the transfer */
+    uint32_t remainingBytes; /*!< Remaining byte count in current state. */
+    uint8_t *buf;            /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    i2c_master_transfer_t transfer;                    /*!< Copy of the current transfer info. */
+    i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */
+    void *userData;                                    /*!< Application data passed to callback. */
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+ /*!
+ * @brief I2C slave peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_slave_flags
+{
+    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
+    kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
+    kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
+};
+ 
+/*! @brief I2C slave address register. */
+typedef enum _i2c_slave_address_register
+{
+    kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */
+    kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */
+    kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */
+    kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */
+} i2c_slave_address_register_t;
+
+/*! @brief Data structure with 7-bit Slave address and Slave address disable. */
+typedef struct _i2c_slave_address
+{
+    uint8_t address;     /*!< 7-bit Slave address SLVADR. */
+    bool addressDisable; /*!< Slave address disable SADISABLE. */
+} i2c_slave_address_t;
+
+/*! @brief I2C slave address match options. */
+typedef enum _i2c_slave_address_qual_mode
+{
+    kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */
+    kI2C_QualModeExtend =
+        1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */
+} i2c_slave_address_qual_mode_t;
+
+/*! @brief I2C slave bus speed options. */
+typedef enum _i2c_slave_bus_speed
+{
+    kI2C_SlaveStandardMode = 0U,
+    kI2C_SlaveFastMode = 1U,
+    kI2C_SlaveFastModePlus = 2U,
+    kI2C_SlaveHsMode = 3U,
+} i2c_slave_bus_speed_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C slave module.
+ *
+ * This structure holds configuration settings for the I2C slave peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_slave_config
+{
+    i2c_slave_address_t address0;           /*!< Slave's 7-bit address and disable. */
+    i2c_slave_address_t address1;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address2;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address3;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */
+    uint8_t qualAddress;                    /*!< Slave address qualifier for address 0. */
+    i2c_slave_bus_speed_t
+        busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must
+                       provide sufficient data setup time to the master before releasing the stretched clock.
+                       This is accomplished by inserting one clock time of CLKDIV at that point.
+                       The #busSpeed value is used to configure CLKDIV
+                       such that one clock time is greater than the tSU;DAT value noted
+                       in the I2C bus specification for the I2C mode that is being used.
+                       If the #busSpeed mode is unknown at compile time, use the longest data setup time
+                       kI2C_SlaveStandardMode (250 ns) */
+    bool enableSlave; /*!< Enable slave mode. */
+} i2c_slave_config_t;
+
+/*!
+ * @brief Set of events sent to the callback for non blocking slave transfers.
+ *
+ * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
+ * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
+ * parameter.
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask of events.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+                                                (slave-transmitter role). */
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+                                                 data (slave-receiver role). */
+    kI2C_SlaveCompletionEvent = 0x20U,   /*!< All data in the active transfer have been consumed. */
+    kI2C_SlaveDeselectedEvent =
+        0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */
+
+    /*! Bit mask of all available events. */
+    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent,
+} i2c_slave_transfer_event_t;
+
+/*! @brief I2C slave handle typedef. */
+typedef struct _i2c_slave_handle i2c_slave_handle_t;
+
+/*! @brief I2C slave transfer structure */
+typedef struct _i2c_slave_transfer
+{
+    i2c_slave_handle_t *handle;       /*!< Pointer to handle that contains this transfer. */
+    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
+    uint8_t receivedAddress;          /*!< Matching address send by master. 7-bits plus R/nW bit0 */
+    uint32_t eventMask;               /*!< Mask of enabled events. */
+    uint8_t *rxData;                  /*!< Transfer buffer for receive data */
+    const uint8_t *txData;            /*!< Transfer buffer for transmit data */
+    size_t txSize;                    /*!< Transfer size */
+    size_t rxSize;                    /*!< Transfer size */
+    size_t transferredCount;          /*!< Number of bytes transferred during this transfer. */
+    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
+                                         #kI2C_SlaveCompletionEvent. */
+} i2c_slave_transfer_t;
+
+/*!
+ * @brief Slave event callback function pointer type.
+ *
+ * This callback is used only for the slave non-blocking transfer API. To install a callback,
+ * use the I2C_SlaveSetCallback() function after you have created a handle.
+ *
+ * @param base Base address for the I2C instance on which the event occurred.
+ * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData);
+
+/*!
+ * @brief I2C slave software finite state machine states.
+ */
+typedef enum _i2c_slave_fsm
+{
+    kI2C_SlaveFsmAddressMatch = 0u,
+    kI2C_SlaveFsmReceive = 2u,
+    kI2C_SlaveFsmTransmit = 3u,
+} i2c_slave_fsm_t;
+
+/*!
+ * @brief I2C slave handle structure.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_slave_handle
+{
+    volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */
+    volatile bool isBusy;                   /*!< Whether transfer is busy. */
+    volatile i2c_slave_fsm_t slaveFsm;      /*!< slave transfer state machine. */
+    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
+    void *userData;                         /*!< Callback parameter passed to callback. */
+};
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*! @name Initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C master peripheral.
+ *
+ * This function provides the following default configuration for the I2C master peripheral:
+ * @code
+ *  masterConfig->enableMaster            = true;
+ *  masterConfig->baudRate_Bps            = 100000U;
+ *  masterConfig->enableTimeout           = false;
+ * @endcode
+ *
+ * After calling this function, you can override any settings in order to customize the configuration,
+ * prior to initializing the master driver with I2C_MasterInit().
+ *
+ * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t.
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Initializes the I2C master peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user
+ * provided configuration. A software reset is performed prior to configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of
+ * defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors,
+ *      filter widths, and timeout periods.
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+* @brief Deinitializes the I2C master peripheral.
+*
+ * This function disables the I2C master peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief Performs a software reset.
+ *
+ * Restores the I2C master peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static inline void I2C_MasterReset(I2C_Type *base)
+{
+}
+
+/*!
+ * @brief Enables or disables the I2C module as master.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable Pass true to enable or false to disable the specified I2C as master.
+ */
+static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
+    }
+    else
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
+    }
+}
+
+/*@}*/
+
+/*! @name Status */
+/*@{*/
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit
+ * in the return value is set if the flag is asserted.
+ *
+ * @param base The I2C peripheral base address.
+ * @return State of the status flags:
+ *         - 1: related status flag is set.
+ *         - 0: related status flag is not set.
+ * @see _i2c_master_flags
+ */
+static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
+{
+    return base->STAT;
+}
+
+/*!
+ * @brief Clears the I2C master status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - #kI2C_MasterArbitrationLostFlag
+ * - #kI2C_MasterStartStopErrorFlag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_GetStatusFlags().
+ * @see _i2c_master_flags.
+ */
+static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just master status flags */
+    base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+}
+
+/*@}*/
+
+/*! @name Interrupts */
+/*@{*/
+
+/*!
+ * @brief Enables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the
+ *      set of enabled interrupts.
+ */
+static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
+{
+    return base->INTSTAT;
+}
+
+/*@}*/
+
+/*! @name Bus operations */
+/*@{*/
+
+/*!
+ * @brief Sets the I2C bus frequency for master transactions.
+ *
+ * The I2C master is automatically disabled and re-enabled as necessary to configure the baud
+ * rate. Do not call this function during a transfer, or the transfer is aborted.
+ *
+ * @param base The I2C peripheral base address.
+ * @param srcClock_Hz I2C functional clock frequency in Hertz.
+ * @param baudRate_Bps Requested bus frequency in bits per second.
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Returns whether the bus is idle.
+ *
+ * Requires the master mode to be enabled.
+ *
+ * @param base The I2C peripheral base address.
+ * @retval true Bus is busy.
+ * @retval false Bus is idle.
+ */
+static inline bool I2C_MasterGetBusIdleState(I2C_Type *base)
+{
+    /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */
+    return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK);
+}
+
+/*!
+ * @brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * @retval kStatus_Success Successfully send the stop signal.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base);
+
+/*!
+ * @brief Sends a REPEATED START on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    return I2C_MasterStart(base, address, direction);
+}
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
+ * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
+ * function returns #kStatus_I2C_Nak.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was sent successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was received successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C peripheral base address.
+ * @param xfer Pointer to the transfer structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
+
+/*@}*/
+
+/*! @name Non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C master non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_MasterTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C master driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Performs a non-blocking transaction on the I2C bus.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param xfer The pointer to the transfer descriptor.
+ * @retval kStatus_Success The transaction was started successfully.
+ * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking
+ *      transaction is already in progress.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Busy
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Terminates a non-blocking I2C master transmission early.
+ *
+ * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      I2C peripheral's IRQ priority.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @retval kStatus_Success A transaction was successfully aborted.
+ * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress.
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @name IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle master interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @} */ /* end of i2c_master_driver */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+/*! @name Slave initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C slave peripheral.
+ *
+ * This function provides the following default configuration for the I2C slave peripheral:
+ * @code
+ *  slaveConfig->enableSlave = true;
+ *  slaveConfig->address0.disable = false;
+ *  slaveConfig->address0.address = 0u;
+ *  slaveConfig->address1.disable = true;
+ *  slaveConfig->address2.disable = true;
+ *  slaveConfig->address3.disable = true;
+ *  slaveConfig->busSpeed = kI2C_SlaveStandardMode;
+ * @endcode
+ *
+ * After calling this function, override any settings  to customize the configuration,
+ * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a
+ * address0.address member of the configuration structure with the desired slave address.
+ *
+ * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
+ *      #i2c_slave_config_t.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Initializes the I2C slave peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user
+ * provided configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide
+ * enough
+ *                       data setup time for master when slave stretches the clock.
+ */
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures Slave Address n register.
+ *
+ * This function writes new value to Slave Address register.
+ *
+ * @param base The I2C peripheral base address.
+ * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed.
+ * @param address The slave address to be stored to the address register for matching.
+ * @param addressDisable Disable matching of the specified address register.
+  */
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable);
+
+/*!
+* @brief Deinitializes the I2C slave peripheral.
+*
+ * This function disables the I2C slave peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+
+/*!
+ * @brief Enables or disables the I2C module as slave.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable True to enable or flase to disable.
+ */
+static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)
+{
+    /* Set or clear the SLVEN bit in the CFG register. */
+    base->CFG = I2C_CFG_SLVEN(enable);
+}
+
+/*@}*/ /* end of Slave initialization and deinitialization */
+
+/*! @name Slave status */
+/*@{*/
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - slave deselected flag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_SlaveGetStatusFlags().
+ * @see _i2c_slave_flags.
+ */
+static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just slave status flags */
+    base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK;
+}
+
+/*@}*/ /* end of Slave status */
+
+/*! @name Slave bus operations */
+/*@{*/
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been sent.
+ * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected).
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been received.
+ * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected).
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*@}*/ /* end of Slave bus operations */
+
+/*! @name Slave non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C slave non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C slave driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback.
+ * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master read from slave requests.
+ *
+ * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param txData Pointer to data to send to master.
+ * @param txSize Size of txData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master write to slave requests.
+  *
+ * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param rxData Pointer to data to store data from master.
+ * @param rxSize Size of rxData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask);
+
+/*!
+ * @brief Returns the slave address sent by the I2C master.
+ *
+ * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer The I2C slave transfer.
+ * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and
+ *      the 7-bit slave address is in the upper 7 bits.
+ */
+static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer)
+{
+    return transfer->receivedAddress;
+}
+
+/*!
+ * @brief Aborts the slave non-blocking transfers.
+ * @note This API could be called at any time to stop slave for handling the bus events.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Idle
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*!
+ * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*@}*/ /* end of Slave non-blocking */
+
+/*! @name Slave IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle slave interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  non blocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*@}*/ /* end of Slave IRQ handler */
+
+/*! @} */ /* end of i2c_slave_driver */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2C_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,579 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_dma.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
+typedef struct _i2c_master_dma_private_handle
+{
+    I2C_Type *base;
+    i2c_master_dma_handle_t *handle;
+} i2c_master_dma_private_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA callback for I2C master DMA driver.
+ *
+ * @param handle DMA handler for I2C master DMA driver
+ * @param userData user param passed to the callback function
+ */
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief Set up master transfer, send slave address and sub address(if any), wait until the
+ * wait until address sent status return.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get the I2C instance from peripheral base address.
+ *
+ * @param base I2C peripheral base address.
+ * @return I2C instance.
+ */
+extern uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytesDMA = 0;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = xfer->dataSize = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    int transfer_size;
+    dma_transfer_config_t xferConfig;
+
+    /* Update transfer count */
+    handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
+
+    /* Check if there is anything to be transferred at all */
+    if (handle->remainingBytesDMA == 0)
+    {
+        /* No data to be transferrred, disable DMA */
+        base->MSTCTL = 0;
+        return;
+    }
+
+    /* Calculate transfer size */
+    transfer_size = handle->remainingBytesDMA;
+    if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
+    {
+        transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
+    }
+
+    switch (handle->transfer.direction)
+    {
+        case kI2C_Write:
+            DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
+                                kDMA_MemoryToPeripheral, NULL);
+            break;
+
+        case kI2C_Read:
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
+                                kDMA_PeripheralToMemory, NULL);
+            break;
+
+        default:
+            /* This should never happen */
+            assert(0);
+            break;
+    }
+
+    DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    DMA_StartTransfer(handle->dmaHandle);
+
+    handle->remainingBytesDMA -= transfer_size;
+    handle->buf += transfer_size;
+}
+
+/*!
+ * @brief Execute states until the transfer is done.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    dma_transfer_config_t xferConfig;
+    status_t err;
+    uint32_t start_flag = 0;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+
+    if (handle->state == kStartState)
+    {
+        /* set start flag for later use */
+        start_flag = I2C_MSTCTL_MSTSTART_MASK;
+
+        if (handle->remainingSubaddr)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            handle->state = kTransmitSubaddrState;
+        }
+        else if (transfer->direction == kI2C_Write)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            if (transfer->dataSize == 0)
+            {
+                /* No data to be transferred, initiate start and schedule stop */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kStopState;
+                return err;
+            }
+            handle->state = kTransmitDataState;
+        }
+        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
+        {
+            base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+            if (transfer->dataSize == 1)
+            {
+                /* The very last byte is always received by means of SW */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kReceiveLastDataState;
+                return err;
+            }
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            handle->state = kIdleState;
+            err = kStatus_I2C_UnexpectedState;
+            return err;
+        }
+    }
+
+    switch (handle->state)
+    {
+        case kTransmitSubaddrState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+
+            /* Prepare and submit DMA transfer. */
+            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
+                                handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+
+            handle->remainingSubaddr = 0;
+            if (transfer->dataSize)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule stop condition */
+            handle->state = kStopState;
+            break;
+
+        case kReceiveDataState:
+            if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize - 1;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule reception of last data byte */
+            handle->state = kReceiveLastDataState;
+            break;
+
+        case kReceiveLastDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
+            handle->transferCount++;
+
+            /* No more data expected, issue NACK and STOP right away */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kStartState:
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base,
+                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
+{
+    i2c_master_dma_private_handle_t *dmaPrivateHandle;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
+    I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
+}
+
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle)
+{
+    uint32_t instance;
+
+    assert(handle);
+    assert(dmaHandle);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Set the user callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base,
+                          I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+    EnableIRQ(s_i2cIRQ[instance]);
+
+    /* Set the handle for DMA. */
+    handle->dmaHandle = dmaHandle;
+
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
+}
+
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources */
+    I2C_EnableInterrupts(base,
+                         I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    uint32_t status;
+    uint32_t master_state;
+
+    if (handle->state != kIdleState)
+    {
+        DMA_AbortTransfer(handle->dmaHandle);
+
+        /* Disable DMA */
+        base->MSTCTL = 0;
+
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base,
+                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+
+        /* Wait until module is ready */
+        do
+        {
+            status = I2C_GetStatusFlags(base);
+        } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+        /* Clear controller state. */
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+        /* Get the state of the I2C module */
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        {
+            /* Send a stop command to finalize the transfer. */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+            /* Wait until module is ready */
+            do
+            {
+                status = I2C_GetStatusFlags(base);
+            } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+            /* Clear controller state. */
+            I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+        }
+
+        /* Reset the state to idle. */
+        handle->state = kIdleState;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_DMA_H_
+#define _FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup i2c_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
+#define I2C_MAX_DMA_TRANSFER_COUNT 1024
+
+/*! @brief I2C master dma handle typedef. */
+typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
+
+/*! @brief I2C master dma transfer callback typedef. */
+typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
+                                                   i2c_master_dma_handle_t *handle,
+                                                   status_t status,
+                                                   void *userData);
+
+/*! @brief I2C master dma transfer structure. */
+struct _i2c_master_dma_handle
+{
+    uint8_t state;              /*!< Transfer state machine current state. */
+    uint32_t transferCount;     /*!< Indicates progress of the transfer */
+    uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
+    uint8_t *buf;               /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
+    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
+    void *userData;                                        /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block DMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Init the I2C handle which is used in transcational functions
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param callback pointer to user callback function
+ * @param userData user param passed to the callback function
+ * @param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a master dma non-blocking transfer on the I2C bus
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param xfer pointer to transfer structure of i2c_master_transfer_t
+ * @retval kStatus_Success Sucessully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get master transfer status during a dma non-blocking transfer
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a master dma non-blocking transfer in a early time
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,825 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2s.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* TODO - absent in device header files, should be there */
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+
+/*! @brief I2S states. */
+enum _i2s_state
+{
+    kI2S_StateIdle = 0x0,             /*!< Not performing transfer */
+    kI2S_StateTx,                     /*!< Performing transmit */
+    kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */
+    kI2S_StateTxWaitForEmptyFifo,     /*!< Wait for FIFO to be flushed */
+    kI2S_StateRx,                     /*!< Performing receive */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config);
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLETX(1U);                 /* enable TX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYTX(1U);                  /* empty TX FIFO */
+    cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);       /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_TXLVLENA(1U);               /* enable TX FIFO trigger */
+    trig |= I2S_FIFOTRIG_TXLVL(config->watermark);   /* set TX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLERX(1U);               /* enable RX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYRX(1U);                /* empty RX FIFO */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);     /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_RXLVLENA(1U);             /* enable RX FIFO trigger */
+    trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_TxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalMaster;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = true;
+    config->pack48 = false;
+}
+
+void I2S_RxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalSlave;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = false;
+    config->pack48 = false;
+}
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config)
+{
+    assert(config);
+
+    uint32_t cfg1 = 0U;
+    uint32_t cfg2 = 0U;
+
+    /* set master/slave configuration */
+    cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave);
+
+    /* set I2S mode */
+    cfg1 |= I2S_CFG1_MODE(config->mode);
+
+    /* set right low (channel swap) */
+    cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow);
+
+    /* set data justification */
+    cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust);
+
+    /* set source to PDM dmic */
+    cfg1 |= I2S_CFG1_PDMDATA(config->pdmData);
+
+    /* set SCLK polarity */
+    cfg1 |= I2S_CFG1_SCK_POL(config->sckPol);
+
+    /* set WS polarity */
+    cfg1 |= I2S_CFG1_WS_POL(config->wsPol);
+
+    /* set mono mode */
+    cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel);
+
+    /* set data length */
+    cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U);
+
+    /* set frame length */
+    cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U);
+
+    /* set data position of this channel pair within the frame */
+    cfg2 |= I2S_CFG2_POSITION(config->position);
+
+    /* write to registers */
+    base->CFG1 = cfg1;
+    base->CFG2 = cfg2;
+
+    /* set the clock divider */
+    base->DIV = I2S_DIV_DIV(config->divider - 1U);
+}
+
+void I2S_Deinit(I2S_Type *base)
+{
+    /* TODO gate FLEXCOMM clock via FLEXCOMM driver */
+}
+
+void I2S_TxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+void I2S_RxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer)
+{
+    assert(transfer->data);
+    if (!transfer->data)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer->dataSize > 0U);
+    if (transfer->dataSize <= 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->dataLength == 4U)
+    {
+        /* No alignment and data length requirements */
+    }
+    else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U))
+    {
+        assert((((uint32_t)transfer->data) % 2U) == 0U);
+        if ((((uint32_t)transfer->data) % 2U) != 0U)
+        {
+            /* Data not 2-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 2U) == 0U);
+        if ((transfer->dataSize % 2U) != 0U)
+        {
+            /* Data not in pairs of left/right channel bytes */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U))
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 4U) == 0U);
+        if ((transfer->dataSize % 4U) != 0U)
+        {
+            /* Data lenght not multiply of 4 */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U))
+    {
+        assert((transfer->dataSize % 6U) == 0U);
+        if ((transfer->dataSize % 6U) != 0U)
+        {
+            /* Data lenght not multiply of 6 */
+            return kStatus_InvalidArgument;
+        }
+
+        assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)));
+        if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else /* if (handle->dataLength >= 25U) */
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        if (handle->oneChannel)
+        {
+            assert((transfer->dataSize % 4U) == 0U);
+            if ((transfer->dataSize % 4U) != 0U)
+            {
+                /* Data lenght not multiply of 4 */
+                return kStatus_InvalidArgument;
+            }
+        }
+        else
+        {
+            assert((transfer->dataSize % 8U) == 0U);
+            if ((transfer->dataSize % 8U) != 0U)
+            {
+                /* Data lenght not multiply of 8 */
+                return kStatus_InvalidArgument;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle);
+}
+
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateTx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark);
+    I2S_TxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_TxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle);
+}
+
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateRx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark);
+    I2S_RxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_RxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferCount;
+
+    return kStatus_Success;
+}
+
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->errorCount;
+
+    return kStatus_Success;
+}
+
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_TXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear TX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK)
+    {
+        if (handle->state == kI2S_StateTx)
+        {
+            /* Send data */
+
+            while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) &&
+                   (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+            {
+                /* Write output data */
+                if (handle->dataLength == 4U)
+                {
+                    data = *(handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU);
+                    handle->i2sQueue[handle->queueDriver].data++;
+                    handle->transferCount++;
+                    handle->i2sQueue[handle->queueDriver].dataSize--;
+                }
+                else if (handle->dataLength <= 8U)
+                {
+                    data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU);
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                    handle->transferCount += sizeof(uint16_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                }
+                else if (handle->dataLength <= 16U)
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+                else if (handle->dataLength <= 24U)
+                {
+                    if (handle->pack48)
+                    {
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                            handle->transferCount += sizeof(uint16_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                            handle->transferCount += sizeof(uint32_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                            handle->useFifo48H = true;
+                        }
+                    }
+                    else
+                    {
+                        data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++));
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U;
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U;
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = data;
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = data;
+                            handle->useFifo48H = true;
+                        }
+                        handle->transferCount += 3U;
+                        handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                    }
+                }
+                else /* if (handle->dataLength <= 32U) */
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* Actual data buffer sent out, switch to a next one */
+                    handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                    }
+
+                    /* Check if the next buffer contains anything to send */
+                    if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                    {
+                        /* Everything has been written to FIFO */
+                        handle->state = kI2S_StateTxWaitToWriteDummyData;
+                        break;
+                    }
+                }
+            }
+        }
+        else if (handle->state == kI2S_StateTxWaitToWriteDummyData)
+        {
+            /* Write dummy data */
+            if ((handle->dataLength > 16U) && (handle->dataLength < 25U))
+            {
+                if (handle->useFifo48H)
+                {
+                    base->FIFOWR48H = 0U;
+                    handle->useFifo48H = false;
+                }
+                else
+                {
+                    base->FIFOWR = 0U;
+                    base->FIFOWR48H = 0U;
+                }
+            }
+            else
+            {
+                base->FIFOWR = 0U;
+            }
+
+            /* Next time invoke this handler when FIFO becomes empty (TX level 0) */
+            base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK;
+            handle->state = kI2S_StateTxWaitForEmptyFifo;
+        }
+        else if (handle->state == kI2S_StateTxWaitForEmptyFifo)
+        {
+            /* FIFO, including additional dummy data, has been emptied now,
+             * all relevant data should have been output from peripheral */
+
+            /* Stop transfer */
+            I2S_Disable(base);
+            I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+            base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+
+            /* Reset state */
+            handle->state = kI2S_StateIdle;
+
+            /* Notify user */
+            if (handle->completionCallback)
+            {
+                handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        /* Clear TX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U);
+    }
+}
+
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_RXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear RX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK)
+    {
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+        {
+            /* Read input data */
+            if (handle->dataLength == 4U)
+            {
+                data = base->FIFORD;
+                *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU);
+                handle->i2sQueue[handle->queueDriver].data++;
+                handle->transferCount++;
+                handle->i2sQueue[handle->queueDriver].dataSize--;
+            }
+            else if (handle->dataLength <= 8U)
+            {
+                data = base->FIFORD;
+                *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU);
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                handle->transferCount += sizeof(uint16_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+            }
+            else if (handle->dataLength <= 16U)
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+            else if (handle->dataLength <= 24U)
+            {
+                if (handle->pack48)
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+
+                        *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                        handle->transferCount += sizeof(uint16_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+
+                        *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                        handle->transferCount += sizeof(uint32_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                    }
+                }
+                else
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+                    }
+
+                    *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU;
+                    handle->transferCount += 3U;
+                    handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                }
+            }
+            else /* if (handle->dataLength <= 32U) */
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+
+            if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+            {
+                /* Actual data buffer filled with input data, switch to a next one */
+                handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                /* Notify user */
+                if (handle->completionCallback)
+                {
+                    handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* No other buffer prepared to receive data into */
+
+                    /* Disable I2S operation and interrupts */
+                    I2S_Disable(base);
+                    I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+                    base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+
+                    /* Reset state */
+                    handle->state = kI2S_StateIdle;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+                    }
+
+                    /* Clear RX level interrupt flag */
+                    base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+
+                    return;
+                }
+            }
+        }
+
+        /* Clear RX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_H_
+#define _FSL_I2S_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#ifndef I2S_NUM_BUFFERS
+
+/*! @brief Number of buffers . */
+#define I2S_NUM_BUFFERS (4)
+
+#endif
+
+/*! @brief I2S status codes. */
+enum _i2s_status
+{
+    kStatus_I2S_BufferComplete =
+        MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
+    kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */
+    kStatus_I2S_Busy =
+        MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */
+};
+
+/*!
+ * @brief I2S flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+typedef enum _i2s_flags
+{
+    kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */
+    kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */
+    kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */
+    kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK  /*!< RX level interrupt */
+} i2s_flags_t;
+
+/*! @brief Master / slave mode. */
+typedef enum _i2s_master_slave
+{
+    kI2S_MasterSlaveNormalSlave = 0x0,  /*!< Normal slave */
+    kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */
+    kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */
+    kI2S_MasterSlaveNormalMaster = 0x3  /*!< Normal master */
+} i2s_master_slave_t;
+
+/*! @brief I2S mode. */
+typedef enum _i2s_mode
+{
+    kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */
+    kI2S_ModeDspWs50 = 0x1,    /*!< DSP mode, WS having 50% duty cycle */
+    kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */
+    kI2S_ModeDspWsLong = 0x3   /*!< DSP mode, WS having one data slot long pulse */
+} i2s_mode_t;
+
+/*! @brief I2S configuration structure. */
+typedef struct _i2s_config
+{
+    i2s_master_slave_t masterSlave; /*!< Master / slave configuration */
+    i2s_mode_t mode;                /*!< I2S mode */
+    bool rightLow;                  /*!< Right channel data in low portion of FIFO */
+    bool leftJust;                  /*!< Left justify data in FIFO */
+    bool pdmData;                   /*!< Data source is the D-Mic subsystem */
+    bool sckPol;                    /*!< SCK polarity */
+    bool wsPol;                     /*!< WS polarity */
+    uint16_t divider;               /*!< Flexcomm function clock divider (1 - 4096) */
+    bool oneChannel;                /*!< true mono, false stereo */
+    uint8_t dataLength;             /*!< Data length (4 - 32) */
+    uint16_t frameLength;           /*!< Frame width (4 - 512) */
+    uint16_t position;              /*!< Data position in the frame */
+    uint8_t watermark;              /*!< FIFO trigger level */
+    bool txEmptyZero;               /*!< Transmit zero when buffer becomes empty or last item */
+    bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                    values) */
+} i2s_config_t;
+
+/*! @brief Buffer to transfer from or receive audio data into. */
+typedef struct _i2s_transfer
+{
+    volatile uint8_t *data;   /*!< Pointer to data buffer. */
+    volatile size_t dataSize; /*!< Buffer size in bytes. */
+} i2s_transfer_t;
+
+/*! @brief Transactional state of the intialized transfer or receive I2S operation. */
+typedef struct _i2s_handle i2s_handle_t;
+
+/*!
+ * @brief Callback function invoked from transactional API
+ *        on completion of a single buffer transfer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
+                                        i2s_handle_t *handle,
+                                        status_t completionStatus,
+                                        void *userData);
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+struct _i2s_handle
+{
+    uint32_t state;                             /*!< State of transfer */
+    i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
+    void *userData;                             /*!< Application data passed to callback */
+    bool oneChannel;                            /*!< true mono, false stereo */
+    uint8_t dataLength;                         /*!< Data length (4 - 32) */
+    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                        values) */
+    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+    volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
+    volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
+    volatile uint8_t watermark;                        /*!< FIFO trigger level */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S transmission using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_TxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S receive using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_RxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Tx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_TxInit().
+ * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified
+ * before calling I2S_TxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_TxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalMaster;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = true;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Rx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_RxInit().
+ * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified
+ * before calling I2S_RxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_RxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalSlave;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = false;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief De-initializes the I2S peripheral.
+ *
+ * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit
+ * or I2S_RxInit is called to enable the clock.
+ *
+ * @param base I2S base pointer.
+ */
+void I2S_Deinit(I2S_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Non-blocking API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts sending of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full.
+ */
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts receiving of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of bytes transferred so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Returns number of buffer underruns or overruns.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of transmit errors encountered so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*! @} */
+
+/*!
+ * @name Enable / disable
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Enable(I2S_Type *base)
+{
+    base->CFG1 |= I2S_CFG1_MAINENABLE(1U);
+}
+
+/*!
+ * @brief Disables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Disable(I2S_Type *base)
+{
+    base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U));
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ *
+ * @return A bitmask composed of #i2s_flags_t enumerators OR'd together
+ *         to indicate the set of enabled interrupts.
+ */
+static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
+{
+    return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Invoked from interrupt handler when transmit FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Invoked from interrupt handler when receive FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,626 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dma.h"
+#include "fsl_i2s_dma.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
+#define DMA_DESCRIPTORS (2U)
+
+/*<! @brief Structure for statically allocated private data. */
+typedef struct _i2s_dma_private_handle
+{
+    I2S_Type *base;           /*!< I2S base address */
+    i2s_dma_handle_t *handle; /*!< I2S handle */
+
+    volatile uint16_t enqueuedBytes[DMA_DESCRIPTORS]; /*!< Number of bytes being transferred by DMA descriptors */
+    volatile uint8_t enqueuedBytesStart;              /*!< First item in enqueuedBytes (for reading) */
+    volatile uint8_t enqueuedBytesEnd;                /*!< Last item in enqueuedBytes (for adding) */
+
+    volatile uint8_t
+        dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
+    volatile uint8_t
+        descriptor; /*!< Index of next DMA descriptor in s_DmaDescriptors to be configured with data (does not include
+                       I2S instance offset) */
+
+    volatile uint8_t queueDescriptor;                         /*!< Queue index of buffer to be actually consumed by DMA
+                                                                * (queueUser - advanced when user adds a buffer,
+                                                                *  queueDescriptor - advanced when user buffer queued to DMA,
+                                                                *  queueDriver - advanced when DMA queued buffer sent out to I2S) */
+    volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data to be queued to DMA */
+
+    volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */
+} i2s_dma_private_handle_t;
+
+/*! @brief I2S DMA transfer private state. */
+enum _i2s_dma_state
+{
+    kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
+    kI2S_DmaStateTx,          /*!< I2S is busy transmitting data */
+    kI2S_DmaStateRx,          /*!< I2S is busy receiving data */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+static uint32_t I2S_GetInstance(I2S_Type *base);
+static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle);
+static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle);
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
+static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer);
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! @brief DMA transfer descriptors. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#endif
+
+/*<! @brief Buffer with dummy TX data. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#endif
+
+/*<! @brief Buffer to fill with RX data to discard. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#endif
+
+/*<! @brief Private array of data associated with available I2S peripherals. */
+static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
+
+/*<! @brief Base addresses of available I2S peripherals. */
+static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    /* Validate input data and tranfer buffer */
+
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert((((uint32_t)transfer.data) % 4U) == 0U);
+    if ((((uint32_t)transfer.data) % 4U) != 0U)
+    {
+        /* Data not 4-bytes aligned */
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer.dataSize != 0U);
+    if (transfer.dataSize == 0U)
+    {
+        /* No data to send or receive */
+        return kStatus_InvalidArgument;
+    }
+
+    assert((transfer.dataSize % 4U) == 0U);
+    if ((transfer.dataSize % 4U) != 0U)
+    {
+        /* Data length not multiply of 4 bytes */
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet, reject request */
+        return kStatus_I2S_Busy;
+    }
+
+    /* Enqueue data */
+    privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
+    privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    return kStatus_Success;
+}
+
+static uint32_t I2S_GetInstance(I2S_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++)
+    {
+        if ((uint32_t)base == s_I2sBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0U;
+}
+
+static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
+{
+    DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
+}
+
+static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
+{
+    if (handle->state != kI2S_DmaStateIdle)
+    {
+        DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+}
+
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    assert(handle);
+    assert(dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    memset(handle, 0U, sizeof(*handle));
+    handle->state = kI2S_DmaStateIdle;
+    handle->dmaHandle = dmaHandle;
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    memset(privateHandle, 0U, sizeof(*privateHandle));
+    privateHandle->base = base;
+    privateHandle->handle = handle;
+
+    DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
+}
+
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    status_t status;
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Enqueue transfer buffer */
+    status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        I2S_EnableDMAInterrupts(handle);
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateTx;
+        status = I2S_StartTransferDMA(base, handle);
+        if (status != kStatus_Success)
+        {
+            I2S_EnableDMAInterrupts(handle);
+            return status;
+        }
+    }
+
+    I2S_AddTransferDMA(base, handle);
+    I2S_EnableDMAInterrupts(handle);
+
+    return kStatus_Success;
+}
+
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    assert(handle);
+    assert(handle->dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Abort operation */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        /* Wait until all transmitted data get out of FIFO */
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
+        {
+        }
+        /* The last piece of valid data can be still being transmitted from I2S at this moment */
+
+        /* Write additional data to FIFO */
+        base->FIFOWR = 0U;
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
+        {
+        }
+        /* At this moment the additional data are out of FIFO, starting being transmitted.
+         * This means the preceding valid data has been just transmitted and we can stop I2S. */
+        I2S_TxEnableDMA(base, false);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, false);
+    }
+
+    I2S_Disable(base);
+
+    /* Reset state */
+    handle->state = kI2S_DmaStateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+
+    /* Clear internal state */
+    memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
+    memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
+    privateHandle->enqueuedBytesStart = 0U;
+    privateHandle->enqueuedBytesEnd = 0U;
+    privateHandle->dmaDescriptorsUsed = 0U;
+    privateHandle->descriptor = 0U;
+    privateHandle->queueDescriptor = 0U;
+    privateHandle->intA = false;
+}
+
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
+}
+
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    status_t status;
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Enqueue transfer buffer */
+    status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        I2S_EnableDMAInterrupts(handle);
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateRx;
+        status = I2S_StartTransferDMA(base, handle);
+        if (status != kStatus_Success)
+        {
+            I2S_EnableDMAInterrupts(handle);
+            return status;
+        }
+    }
+
+    I2S_AddTransferDMA(base, handle);
+    I2S_EnableDMAInterrupts(handle);
+
+    return kStatus_Success;
+}
+
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
+{
+    assert(transfer);
+
+    uint16_t transferBytes;
+
+    if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
+    {
+        transferBytes = DMA_MAX_TRANSFER_BYTES;
+    }
+    else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
+    {
+        transferBytes = transfer->dataSize / 2U;
+        if ((transferBytes % 4U) != 0U)
+        {
+            transferBytes -= (transferBytes % 4U);
+        }
+    }
+    else
+    {
+        transferBytes = transfer->dataSize;
+    }
+
+    return transferBytes;
+}
+
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    status_t status;
+    dma_transfer_config_t xferConfig = {0};
+    i2s_dma_private_handle_t *privateHandle;
+    volatile i2s_transfer_t *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    int i;
+    dma_descriptor_t *descriptor;
+    dma_descriptor_t *nextDescriptor;
+    dma_xfercfg_t xfercfg;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+    transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+    transferBytes = I2S_GetTransferBytes(transfer);
+
+    /* Prepare transfer of data via initial DMA transfer descriptor */
+    DMA_PrepareTransfer(
+        &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+        (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t),
+        transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
+        (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
+
+    /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
+    privateHandle->dmaDescriptorsUsed = 1U;
+    privateHandle->intA = false;
+
+    privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+    privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
+
+    transfer->dataSize -= transferBytes;
+    transfer->data += transferBytes;
+
+    if (transfer->dataSize == 0U)
+    {
+        transfer->data = NULL;
+        privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+    }
+
+    /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */
+    for (i = 0; i < DMA_DESCRIPTORS; i++)
+    {
+        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]);
+        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]);
+
+        xfercfg.valid = true;
+        xfercfg.reload = true;
+        xfercfg.swtrig = false;
+        xfercfg.clrtrig = false;
+        xfercfg.intA = false;
+        xfercfg.intB = false;
+        xfercfg.byteWidth = sizeof(uint32_t);
+        xfercfg.srcInc = 0U;
+        xfercfg.dstInc = 0U;
+        xfercfg.transferCount = 8U;
+
+        DMA_CreateDescriptor(descriptor, &xfercfg,
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD),
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx,
+                             (void *)nextDescriptor);
+    }
+
+    /* Submit and start initial DMA transfer */
+
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        I2S_TxEnableDMA(base, true);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, true);
+    }
+
+    status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    DMA_StartTransfer(handle->dmaHandle);
+
+    I2S_Enable(base);
+    return kStatus_Success;
+}
+
+static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    dma_xfercfg_t xfercfg;
+    volatile i2s_transfer_t *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    i2s_dma_private_handle_t *privateHandle;
+    dma_descriptor_t *descriptor;
+    dma_descriptor_t *nextDescriptor;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
+    {
+        transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+        if (transfer->dataSize == 0U)
+        {
+            /* Nothing to be added */
+            return;
+        }
+
+        /* Determine currently configured descriptor and the other which it will link to */
+        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
+        privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
+        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
+
+        transferBytes = I2S_GetTransferBytes(transfer);
+        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+        privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
+
+        /* Configure descriptor */
+
+        xfercfg.valid = true;
+        xfercfg.reload = true;
+        xfercfg.swtrig = false;
+        xfercfg.clrtrig = false;
+        xfercfg.intA = privateHandle->intA;
+        xfercfg.intB = !privateHandle->intA;
+        xfercfg.byteWidth = sizeof(uint32_t);
+        xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
+        xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
+        xfercfg.transferCount = transferBytes / sizeof(uint32_t);
+
+        DMA_CreateDescriptor(descriptor, &xfercfg,
+                             (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data,
+                             (void *)nextDescriptor);
+
+        /* Advance internal state */
+
+        privateHandle->dmaDescriptorsUsed++;
+        privateHandle->intA = !privateHandle->intA;
+
+        transfer->dataSize -= transferBytes;
+        transfer->data += transferBytes;
+        if (transfer->dataSize == 0U)
+        {
+            transfer->data = NULL;
+            privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+        }
+    }
+}
+
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
+{
+    i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
+    i2s_dma_handle_t *i2sHandle = privateHandle->handle;
+    I2S_Type *base = privateHandle->base;
+
+    if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
+    {
+        return;
+    }
+
+    if (privateHandle->dmaDescriptorsUsed > 0U)
+    {
+        /* Finished descriptor, decrease amount of data to be processed */
+
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
+        privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
+
+        privateHandle->dmaDescriptorsUsed--;
+
+        if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+        {
+            /* Entire user buffer sent or received - advance to next one */
+            i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
+            i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+            /* Notify user about buffer completion */
+            if (i2sHandle->completionCallback)
+            {
+                (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
+            }
+        }
+    }
+
+    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+    {
+        /* All user buffers processed */
+        I2S_TransferAbortDMA(base, i2sHandle);
+
+        /* Notify user about completion of the final buffer */
+        if (i2sHandle->completionCallback)
+        {
+            (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
+        }
+    }
+    else
+    {
+        /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
+        I2S_AddTransferDMA(base, i2sHandle);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_DMA_H_
+#define _FSL_I2S_DMA_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_dma.h"
+#include "fsl_i2s.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S DMA driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+typedef struct _i2s_dma_handle i2s_dma_handle_t;
+
+/*!
+ * @brief Callback function invoked from DMA API on completion.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base,
+                                            i2s_dma_handle_t *handle,
+                                            status_t completionStatus,
+                                            void *userData);
+
+struct _i2s_dma_handle
+{
+    uint32_t state;                                    /*!< Internal state of I2S DMA transfer */
+    i2s_dma_transfer_callback_t completionCallback;    /*!< Callback function pointer */
+    void *userData;                                    /*!< Application data passed to callback */
+    dma_handle_t *dmaHandle;                           /*!< DMA handle */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*! @} */
+
+/*!
+ * @name DMA API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts transfer of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers
+ *         which are not full.
+ */
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Invoked from DMA interrupt handler.
+ *
+ * @param handle pointer to DMA handle structure.
+ * @param userData argument for user callback.
+ * @param transferDone if transfer was done.
+ * @param tcds
+ */
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_InputMux);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & 0xffffU;
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
+}
+
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_InputMux);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+*/
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+/*!
+ * @brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2013-2016, NXP Semiconductors.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_CONNECTIONS_
+#define _FSL_INPUTMUX_CONNECTIONS_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*!
+ * @name Input multiplexing connections
+ * @{
+ */
+
+/*! @brief Periphinmux IDs */
+#define SCT0_PMUX_ID 0x00U
+#define PINTSEL_PMUX_ID 0xC0U
+#define DMA_TRIG0_PMUX_ID 0xE0U
+#define DMA_OTRIG_PMUX_ID 0x160U
+#define FREQMEAS_PMUX_ID 0x180U
+#define PMUX_SHIFT 20U
+
+/*! @brief INPUTMUX connections type */
+typedef enum _inputmux_connection_t
+{
+    /*!< SCT INMUX. */
+    kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Frequency measure. */
+    kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Pin Interrupt. */
+    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA ITRIG. */
+    kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA OTRIG. */
+    kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+} inputmux_connection_t;
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_CONNECTIONS_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.0.0. */
+#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+    uint32_t port : 8;      /* Pin port */
+    uint32_t pin : 8;       /* Pin number */
+    uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+    #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4)
+    #define IOCON_FUNC0             0x0             /*!< Selects pin function 0 */
+    #define IOCON_FUNC1             0x1             /*!< Selects pin function 1 */
+    #define IOCON_FUNC2             0x2             /*!< Selects pin function 2 */
+    #define IOCON_FUNC3             0x3             /*!< Selects pin function 3 */
+    #define IOCON_FUNC4             0x4             /*!< Selects pin function 4 */
+    #define IOCON_FUNC5             0x5             /*!< Selects pin function 5 */
+    #define IOCON_FUNC6             0x6             /*!< Selects pin function 6 */
+    #define IOCON_FUNC7             0x7             /*!< Selects pin function 7 */
+    #define IOCON_FUNC8             0x8             /*!< Selects pin function 8 */
+    #define IOCON_FUNC9             0x9             /*!< Selects pin function 9 */
+    #define IOCON_FUNC10            0xA             /*!< Selects pin function 10 */
+    #define IOCON_FUNC11            0xB             /*!< Selects pin function 11 */
+    #define IOCON_FUNC12            0xC             /*!< Selects pin function 12 */
+    #define IOCON_FUNC13            0xD             /*!< Selects pin function 13 */
+    #define IOCON_FUNC14            0xE             /*!< Selects pin function 14 */
+    #define IOCON_FUNC15            0xF             /*!< Selects pin function 15 */
+    #define IOCON_MODE_INACT        (0x0 << 4)      /*!< No addition pin function */
+    #define IOCON_MODE_PULLDOWN     (0x1 << 4)      /*!< Selects pull-down function */
+    #define IOCON_MODE_PULLUP       (0x2 << 4)      /*!< Selects pull-up function */
+    #define IOCON_MODE_REPEATER     (0x3 << 4)      /*!< Selects pin repeater function */
+    #define IOCON_HYS_EN            (0x1 << 6)      /*!< Enables hysteresis */
+    #define IOCON_GPIO_MODE         (0x1 << 6)      /*!< GPIO Mode */
+    #define IOCON_I2C_SLEW          (0x1 << 6)      /*!< I2C Slew Rate Control */
+    #define IOCON_INV_EN            (0x1 << 7)      /*!< Enables invert function on input */
+    #define IOCON_ANALOG_EN         (0x0 << 8)      /*!< Enables analog function by setting 0 to bit 7 */
+    #define IOCON_DIGITAL_EN        (0x1 << 8)      /*!< Enables digital function by setting 1 to bit 7(default) */
+    #define IOCON_STDI2C_EN         (0x1 << 9)      /*!< I2C standard mode/fast-mode */
+    #define IOCON_FASTI2C_EN        (0x3 << 9)      /*!< I2C Fast-mode Plus and high-speed slave */
+    #define IOCON_INPFILT_OFF       (0x1 << 9)      /*!< Input filter Off for GPIO pins */
+    #define IOCON_INPFILT_ON        (0x0 << 9)      /*!< Input filter On for GPIO pins */
+    #define IOCON_OPENDRAIN_EN      (0x1 << 11)      /*!< Enables open-drain function */
+    #define IOCON_S_MODE_0CLK       (0x0 << 12)      /*!< Bypass input filter */
+    #define IOCON_S_MODE_1CLK       (0x1 << 12)      /*!< Input pulses shorter than 1 filter clock are rejected */
+    #define IOCON_S_MODE_2CLK       (0x2 << 12)      /*!< Input pulses shorter than 2 filter clock2 are rejected */
+    #define IOCON_S_MODE_3CLK       (0x3 << 12)      /*!< Input pulses shorter than 3 filter clock2 are rejected */
+    #define IOCON_S_MODE(clks)      ((clks) << 12)   /*!< Select clocks for digital input filter mode */
+    #define IOCON_CLKDIV(div)       ((div) << 14)    /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#else
+    #define IOCON_FUNC0 0x0                   /*!< Selects pin function 0 */
+    #define IOCON_FUNC1 0x1                   /*!< Selects pin function 1 */
+    #define IOCON_FUNC2 0x2                   /*!< Selects pin function 2 */
+    #define IOCON_FUNC3 0x3                   /*!< Selects pin function 3 */
+    #define IOCON_FUNC4 0x4                   /*!< Selects pin function 4 */
+    #define IOCON_FUNC5 0x5                   /*!< Selects pin function 5 */
+    #define IOCON_FUNC6 0x6                   /*!< Selects pin function 6 */
+    #define IOCON_FUNC7 0x7                   /*!< Selects pin function 7 */
+    #define IOCON_MODE_INACT (0x0 << 3)       /*!< No addition pin function */
+    #define IOCON_MODE_PULLDOWN (0x1 << 3)    /*!< Selects pull-down function */
+    #define IOCON_MODE_PULLUP (0x2 << 3)      /*!< Selects pull-up function */
+    #define IOCON_MODE_REPEATER (0x3 << 3)    /*!< Selects pin repeater function */
+    #define IOCON_HYS_EN (0x1 << 5)           /*!< Enables hysteresis */
+    #define IOCON_GPIO_MODE (0x1 << 5)        /*!< GPIO Mode */
+    #define IOCON_I2C_SLEW (0x1 << 5)         /*!< I2C Slew Rate Control */
+    #define IOCON_INV_EN (0x1 << 6)           /*!< Enables invert function on input */
+    #define IOCON_ANALOG_EN (0x0 << 7)        /*!< Enables analog function by setting 0 to bit 7 */
+    #define IOCON_DIGITAL_EN (0x1 << 7)       /*!< Enables digital function by setting 1 to bit 7(default) */
+    #define IOCON_STDI2C_EN (0x1 << 8)        /*!< I2C standard mode/fast-mode */
+    #define IOCON_FASTI2C_EN (0x3 << 8)       /*!< I2C Fast-mode Plus and high-speed slave */
+    #define IOCON_INPFILT_OFF (0x1 << 8)      /*!< Input filter Off for GPIO pins */
+    #define IOCON_INPFILT_ON (0x0 << 8)       /*!< Input filter On for GPIO pins */
+    #define IOCON_OPENDRAIN_EN (0x1 << 10)    /*!< Enables open-drain function */
+    #define IOCON_S_MODE_0CLK (0x0 << 11)     /*!< Bypass input filter */
+    #define IOCON_S_MODE_1CLK (0x1 << 11)     /*!< Input pulses shorter than 1 filter clock are rejected */
+    #define IOCON_S_MODE_2CLK (0x2 << 11)     /*!< Input pulses shorter than 2 filter clock2 are rejected */
+    #define IOCON_S_MODE_3CLK (0x3 << 11)     /*!< Input pulses shorter than 3 filter clock2 are rejected */
+    #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
+    #define IOCON_CLKDIV(div) \
+        ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+    base->PIO[port][pin] = modefunc;
+}
+
+/**
+ * @brief   Set all I/O Control pin muxing
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   pinArray    : Pointer to array of pin mux selections
+ * @param   arrayLength : Number of entries in pinArray
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+    uint32_t i;
+
+    for (i = 0; i < arrayLength; i++)
+    {
+        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lcdc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Max value of LCD_POL[PCD]. */
+#define LCD_PCD_MAX                                  \
+    ((LCD_POL_PCD_LO_MASK >> LCD_POL_PCD_LO_SHIFT) | \
+     (LCD_POL_PCD_HI_MASK >> (LCD_POL_PCD_HI_SHIFT - LCD_POL_PCD_LO_SHIFT)))
+
+/* Macro to contruct the LCD_POL[PCD]. */
+#if (LCD_POL_PCD_LO_MASK != 0x1F)
+#error LCD_POL_PCD_LO is not 5-bit. The macro LCD_POL_PCD_LO_WIDTH should be updated.
+#endif
+#define LCD_POL_PCD_LO_WIDTH 5U
+#define LCD_POL_PCD(pcd) (LCD_POL_PCD_LO(pcd) | LCD_POL_PCD_HI((pcd) >> LCD_POL_PCD_LO_WIDTH))
+
+/* Cursor interrupt. */
+#define LCDC_CURSOR_INT_MASK LCD_CRSR_INTMSK_CRSRIM_MASK
+
+/* Interrupts except cursor interrupt. */
+#define LCDC_NORMAL_INT_MASK \
+    (LCD_INTMSK_FUFIM_MASK | LCD_INTMSK_LNBUIM_MASK | LCD_INTMSK_VCOMPIM_MASK | LCD_INTMSK_BERIM_MASK)
+
+/* Detect the cursor interrupt and normal interrupt bits overlap. */
+#if (LCDC_CURSOR_INT_MASK & LCDC_NORMAL_INT_MASK)
+#error Cursor interrupt and normal interrupt overlap. The driver should be updated.
+#endif
+
+/* The max cursor clip value. */
+#define LCDC_CLIP_MAX (LCD_CRSR_CLIP_CRSRCLIPX_MASK >> LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static LCD_Type *const s_lcdBases[] = LCD_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static const clock_ip_name_t s_lcdClocks[] = LCD_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+static const reset_ip_name_t s_lcdResets[] = LCD_RSTS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+ * @brief Gets the LCD instance according to the LCD base
+ *
+ * @param base LCD peripheral base address.
+ * @return LCD instance.
+ */
+static uint32_t LCDC_GetInstance(LCD_Type *base);
+
+/*!
+ * @brief Calculate the clock divider to generate desired panel clock.
+ *
+ * @param config Pointer to the LCD configuration.
+ * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
+ * @param divider The divider result.
+ * @return Return false if no divider available to generate the desired clock,
+ * otherwise return true;
+ */
+static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t LCDC_GetInstance(LCD_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_lcdBases); instance++)
+    {
+        if (s_lcdBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_lcdBases));
+
+    return instance;
+}
+
+static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider)
+{
+    uint16_t cpl;
+    uint32_t pcd;
+
+    *divider = 0U;
+
+    /* Find the PCD. */
+    pcd = (srcClock_Hz + (config->panelClock_Hz / 2U)) / config->panelClock_Hz;
+
+    if (pcd <= 1U)
+    {
+        if (kLCDC_DisplayTFT == config->display)
+        {
+            pcd = 0U;
+            *divider = LCD_POL_BCD_MASK;
+        }
+        else
+        {
+            return false;
+        }
+    }
+    else
+    {
+        pcd -= 2U;
+
+        /* Verify the PCD value. */
+        if (pcd > LCD_PCD_MAX)
+        {
+            return false;
+        }
+
+        if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) ||
+            ((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) ||
+            ((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) ||
+            ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) ||
+            ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) ||
+            ((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U)))
+        {
+            return false;
+        }
+    }
+
+    if (config->display & LCD_CTRL_LCDTFT_MASK)
+    {
+        /* TFT panel. */
+        cpl = config->ppl - 1U;
+    }
+    else
+    {
+        if (config->display & LCD_CTRL_LCDBW_MASK)
+        {
+            if (config->display & LCD_CTRL_LCDMONO8_MASK)
+            {
+                /* 8-bit monochrome STN panel. */
+                cpl = (config->ppl / 8U) - 1U;
+            }
+            else
+            {
+                /* 4-bit monochrome STN panel. */
+                cpl = (config->ppl / 4U) - 1U;
+            }
+        }
+        else
+        {
+            /* Color STN panel. */
+            cpl = ((config->ppl * 3U) / 8U) - 1U;
+        }
+    }
+
+    *divider |= (LCD_POL_CPL(cpl) | LCD_POL_PCD(pcd));
+
+    return true;
+}
+
+status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config);
+    assert(srcClock_Hz);
+    assert((config->ppl & 0xFU) == 0U);
+    assert((config->upperPanelAddr & 0x07U) == 0U);
+    assert((config->lowerPanelAddr & 0x07U) == 0U);
+
+    uint32_t reg;
+    uint32_t divider;
+    uint32_t instance;
+
+    /* Verify the clock here. */
+    if (!LCDC_GetClockDivider(config, srcClock_Hz, &divider))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = LCDC_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_lcdClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_lcdResets[instance]);
+
+    /* Set register CTRL. */
+    reg = base->CTRL & (LCD_CTRL_LCDVCOMP_MASK | LCD_CTRL_WATERMARK_MASK);
+    reg |= (uint32_t)(config->dataFormat) | (uint32_t)(config->display) | LCD_CTRL_LCDBPP(config->bpp);
+
+    if (config->swapRedBlue)
+    {
+        reg |= LCD_CTRL_BGR_MASK;
+    }
+
+    base->CTRL = reg;
+
+    /* Clean pending interrupts and disable all interrupts. */
+    base->INTCLR = LCDC_NORMAL_INT_MASK;
+    base->CRSR_INTCLR = LCDC_CURSOR_INT_MASK;
+    base->INTMSK = 0U;
+    base->CRSR_INTMSK = 0U;
+
+    /* Configure timing. */
+    base->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) |
+                 LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U);
+
+    base->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) |
+                 LCD_TIMV_VBP(config->vbp - 1U);
+
+    base->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | divider;
+
+    /* Line end configuration. */
+    if (config->enableLineEnd)
+    {
+        base->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK;
+    }
+    else
+    {
+        base->LE = 0U;
+    }
+
+    /* Set panel frame base address. */
+    base->UPBASE = config->upperPanelAddr;
+    base->LPBASE = config->lowerPanelAddr;
+
+    return kStatus_Success;
+}
+
+void LCDC_Deinit(LCD_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_lcdClocks[LCDC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void LCDC_GetDefaultConfig(lcdc_config_t *config)
+{
+    config->panelClock_Hz = 0U;
+    config->ppl = 0U;
+    config->hsw = 0U;
+    config->hfp = 0U;
+    config->hbp = 0U;
+    config->lpp = 0U;
+    config->vsw = 0U;
+    config->vfp = 0U;
+    config->vbp = 0U;
+    config->acBiasFreq = 1U;
+    config->polarityFlags = 0U;
+    config->enableLineEnd = false;
+    config->lineEndDelay = 0U;
+    config->upperPanelAddr = 0U;
+    config->lowerPanelAddr = 0U;
+    config->bpp = kLCDC_1BPP;
+    config->dataFormat = kLCDC_LittleEndian;
+    config->swapRedBlue = false;
+    config->display = kLCDC_DisplayTFT;
+}
+
+void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr)
+{
+    /* The base address must be doubleword aligned. */
+    assert((addr & 0x07U) == 0U);
+
+    if (kLCDC_UpperPanel == panel)
+    {
+        base->UPBASE = addr;
+    }
+    else
+    {
+        base->LPBASE = addr;
+    }
+}
+
+void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words)
+{
+    assert(count_words <= ARRAY_SIZE(base->PAL));
+
+    uint32_t i;
+
+    for (i = 0; i < count_words; i++)
+    {
+        base->PAL[i] = palette[i];
+    }
+}
+
+void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTMSK |= reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTMSK |= reg;
+    }
+}
+
+void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTMSK &= ~reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTMSK &= ~reg;
+    }
+}
+
+uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->CRSR_INTRAW;
+    reg |= base->INTRAW;
+
+    return reg;
+}
+
+uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->CRSR_INTSTAT;
+    reg |= base->INTSTAT;
+
+    return reg;
+}
+
+void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTCLR = reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTCLR = reg;
+    }
+}
+
+void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config)
+{
+    assert(config);
+
+    uint32_t i;
+
+    base->CRSR_CFG = LCD_CRSR_CFG_CRSRSIZE(config->size) | LCD_CRSR_CFG_FRAMESYNC(config->syncMode);
+
+    /* Set position. */
+    LCDC_SetCursorPosition(base, 0, 0);
+
+    /* Palette. */
+    base->CRSR_PAL0 = ((uint32_t)config->palette0.red << LCD_CRSR_PAL0_RED_SHIFT) |
+                      ((uint32_t)config->palette0.blue << LCD_CRSR_PAL0_BLUE_SHIFT) |
+                      ((uint32_t)config->palette0.green << LCD_CRSR_PAL0_GREEN_SHIFT);
+    base->CRSR_PAL1 = ((uint32_t)config->palette1.red << LCD_CRSR_PAL1_RED_SHIFT) |
+                      ((uint32_t)config->palette1.blue << LCD_CRSR_PAL1_BLUE_SHIFT) |
+                      ((uint32_t)config->palette1.green << LCD_CRSR_PAL1_GREEN_SHIFT);
+
+    /* Image of cursors. */
+    if (kLCDC_CursorSize64 == config->size)
+    {
+        assert(config->image[0]);
+        LCDC_SetCursorImage(base, config->size, 0, config->image[0]);
+    }
+    else
+    {
+        for (i = 0; i < LCDC_CURSOR_COUNT; i++)
+        {
+            if (config->image[i])
+            {
+                LCDC_SetCursorImage(base, config->size, i, config->image[i]);
+            }
+        }
+    }
+}
+
+void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config)
+{
+    uint32_t i;
+
+    config->size = kLCDC_CursorSize32;
+    config->syncMode = kLCDC_CursorAsync;
+    config->palette0.red = 0U;
+    config->palette0.green = 0U;
+    config->palette0.blue = 0U;
+    config->palette1.red = 255U;
+    config->palette1.green = 255U;
+    config->palette1.blue = 255U;
+
+    for (i = 0; i < LCDC_CURSOR_COUNT; i++)
+    {
+        config->image[i] = (uint32_t *)0;
+    }
+}
+
+void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY)
+{
+    uint32_t clipX;
+    uint32_t clipY;
+
+    if (positionX < 0)
+    {
+        clipX = -positionX;
+        positionX = 0U;
+
+        /* If clip value too large, set to the max value. */
+        if (clipX > LCDC_CLIP_MAX)
+        {
+            clipX = LCDC_CLIP_MAX;
+        }
+    }
+    else
+    {
+        clipX = 0U;
+    }
+
+    if (positionY < 0)
+    {
+        clipY = -positionY;
+        positionY = 0U;
+
+        /* If clip value too large, set to the max value. */
+        if (clipY > LCDC_CLIP_MAX)
+        {
+            clipY = LCDC_CLIP_MAX;
+        }
+    }
+    else
+    {
+        clipY = 0U;
+    }
+
+    base->CRSR_CLIP = LCD_CRSR_CLIP_CRSRCLIPX(clipX) | LCD_CRSR_CLIP_CRSRCLIPY(clipY);
+    base->CRSR_XY = LCD_CRSR_XY_CRSRX(positionX) | LCD_CRSR_XY_CRSRY(positionY);
+}
+
+void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image)
+{
+    uint32_t regStart;
+    uint32_t i;
+    uint32_t len;
+
+    if (kLCDC_CursorSize64 == size)
+    {
+        regStart = 0U;
+        len = LCDC_CURSOR_IMG_64X64_WORDS;
+    }
+    else
+    {
+        regStart = index * LCDC_CURSOR_IMG_32X32_WORDS;
+        len = LCDC_CURSOR_IMG_32X32_WORDS;
+    }
+
+    for (i = 0U; i < len; i++)
+    {
+        base->CRSR_IMG[regStart + i] = image[i];
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,608 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LCDC_H__
+#define __FSL_LCDC_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_lcdc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LCDC driver version 2.0.0. */
+#define LPC_LCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!@brief How many hardware cursors supports. */
+#define LCDC_CURSOR_COUNT 4
+
+/*!@brief LCD cursor image bits per pixel. */
+#define LCDC_CURSOR_IMG_BPP 2
+
+/*!@brief LCD 32x32 cursor image size in word(32-bit). */
+#define LCDC_CURSOR_IMG_32X32_WORDS (32 * 32 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
+
+/*!@brief LCD 64x64 cursor image size in word(32-bit). */
+#define LCDC_CURSOR_IMG_64X64_WORDS (64 * 64 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
+
+/*!@brief LCD palette size in words(32-bit). */
+#define LCDC_PALETTE_SIZE_WORDS (ARRAY_SIZE(((LCD_Type *)0)->PAL))
+
+/*!
+ * @brief LCD sigal polarity flags.
+ */
+enum _lcdc_polarity_flags
+{
+    kLCDC_InvertVsyncPolarity = LCD_POL_IVS_MASK, /*!< Invert the VSYNC polarity, set to active low. */
+    kLCDC_InvertHsyncPolarity = LCD_POL_IHS_MASK, /*!< Invert the HSYNC polarity, set to active low. */
+    kLCDC_InvertClkPolarity = LCD_POL_IPC_MASK,   /*!< Invert the panel clock polarity, set to
+                                                      drive data on falling edge. */
+    kLCDC_InvertDePolarity = LCD_POL_IOE_MASK,    /*!< Invert the data enable (DE) polarity, set to active low. */
+};
+
+/*!
+ * @brief LCD bits per pixel.
+ */
+typedef enum _lcdc_bpp
+{
+    kLCDC_1BPP = 0U,     /*!< 1 bpp. */
+    kLCDC_2BPP = 1U,     /*!< 2 bpp. */
+    kLCDC_4BPP = 2U,     /*!< 4 bpp. */
+    kLCDC_8BPP = 3U,     /*!< 8 bpp. */
+    kLCDC_16BPP = 4U,    /*!< 16 bpp. */
+    kLCDC_24BPP = 5U,    /*!< 24 bpp, TFT panel only. */
+    kLCDC_16BPP565 = 6U, /*!< 16 bpp, 5:6:5 mode. */
+    kLCDC_12BPP = 7U,    /*!< 12 bpp, 4:4:4 mode. */
+} lcdc_bpp_t;
+
+/*!
+ * @brief The types of display panel.
+ */
+typedef enum _lcdc_display
+{
+    kLCDC_DisplayTFT = LCD_CTRL_LCDTFT_MASK, /*!< Active matrix TFT panels with up to 24-bit bus interface. */
+    kLCDC_DisplaySingleMonoSTN4Bit = LCD_CTRL_LCDBW_MASK, /*!< Single-panel monochrome STN (4-bit bus interface). */
+    kLCDC_DisplaySingleMonoSTN8Bit =
+        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK, /*!< Single-panel monochrome STN (8-bit bus interface). */
+    kLCDC_DisplayDualMonoSTN4Bit =
+        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */
+    kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK |
+                                  LCD_CTRL_LCDDUAL_MASK,  /*!< Dual-panel monochrome STN (8-bit bus interface). */
+    kLCDC_DisplaySingleColorSTN8Bit = 0U,                  /*!< Single-panel color STN (8-bit bus interface). */
+    kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */
+} lcdc_display_t;
+
+/*!
+ * @brief LCD panel buffer data format.
+ */
+typedef enum _lcdc_data_format
+{
+    kLCDC_LittleEndian = 0U,                                   /*!< Little endian byte, little endian pixel. */
+    kLCDC_BigEndian = LCD_CTRL_BEPO_MASK | LCD_CTRL_BEBO_MASK, /*!< Big endian byte, big endian pixel. */
+    kLCDC_WinCeMode = LCD_CTRL_BEPO_MASK, /*!< little-endian byte, big-endian pixel for Windows CE mode. */
+} lcdc_data_format_t;
+
+/*!
+ * @brief LCD configuration structure.
+ */
+typedef struct _lcdc_config
+{
+    uint32_t panelClock_Hz;  /*!< Panel clock in Hz. */
+    uint16_t ppl;            /*!< Pixels per line, it must could be divided by 16. */
+    uint8_t hsw;             /*!< HSYNC pulse width. */
+    uint8_t hfp;             /*!< Horizontal front porch. */
+    uint8_t hbp;             /*!< Horizontal back porch. */
+    uint16_t lpp;            /*!< Lines per panal. */
+    uint8_t vsw;             /*!< VSYNC pulse width. */
+    uint8_t vfp;             /*!< Vrtical front porch. */
+    uint8_t vbp;             /*!< Vertical back porch. */
+    uint8_t acBiasFreq;      /*!< The number of line clocks between AC bias pin toggling. Only used for STN display. */
+    uint16_t polarityFlags;  /*!< OR'ed value of @ref _lcdc_polarity_flags, used to contol the signal polarity. */
+    bool enableLineEnd;      /*!< Enable line end or not, the line end is a positive pulse with 4 panel clock. */
+    uint8_t lineEndDelay;    /*!< The panel clocks between the last pixel of line and the start of line end. */
+    uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */
+    uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */
+    lcdc_bpp_t bpp;           /*!< LCD bits per pixel. */
+    lcdc_data_format_t dataFormat; /*!< Data format. */
+    bool swapRedBlue;             /*!< Set true to use BGR format, set false to choose RGB format. */
+    lcdc_display_t display;        /*!< The display type. */
+} lcdc_config_t;
+
+/*!
+ * @brief LCD vertical compare interrupt mode.
+ */
+typedef enum _lcdc_vertical_compare_interrupt_mode
+{
+    kLCDC_StartOfVsync,       /*!< Generate vertical compare interrupt at start of VSYNC. */
+    kLCDC_StartOfBackPorch,   /*!< Generate vertical compare interrupt at start of back porch. */
+    kLCDC_StartOfActiveVideo, /*!< Generate vertical compare interrupt at start of active video. */
+    kLCDC_StartOfFrontPorch,  /*!< Generate vertical compare interrupt at start of front porch. */
+} lcdc_vertical_compare_interrupt_mode_t;
+
+/*!
+ * @brief LCD interrupts.
+ */
+enum _lcdc_interrupts
+{
+    kLCDC_CursorInterrupt = LCD_CRSR_INTMSK_CRSRIM_MASK,      /*!< Cursor image read finished interrupt. */
+    kLCDC_FifoUnderflowInterrupt = LCD_INTMSK_FUFIM_MASK,     /*!< FIFO underflow interrupt. */
+    kLCDC_BaseAddrUpdateInterrupt = LCD_INTMSK_LNBUIM_MASK,   /*!< Panel frame base address update interrupt. */
+    kLCDC_VerticalCompareInterrupt = LCD_INTMSK_VCOMPIM_MASK, /*!< Vertical compare interrupt. */
+    kLCDC_AhbErrorInterrupt = LCD_INTMSK_BERIM_MASK,          /*!< AHB master error interrupt. */
+};
+
+/*!
+ * @brief LCD panel frame.
+ */
+typedef enum _lcdc_panel
+{
+    kLCDC_UpperPanel, /*!< Upper panel frame. */
+    kLCDC_LowerPanel  /*!< Lower panel frame. */
+} lcdc_panel_t;
+
+/*!
+ * @brief LCD hardware cursor size
+ */
+typedef enum _lcdc_cursor_size
+{
+    kLCDC_CursorSize32, /*!< 32x32 pixel cursor. */
+    kLCDC_CursorSize64, /*!< 64x64 pixel cursor. */
+} lcdc_cursor_size_t;
+
+/*!
+ * @brief LCD hardware cursor palette
+ */
+typedef struct _lcdc_cursor_palette
+{
+    uint8_t red;   /*!< Red color component. */
+    uint8_t green; /*!< Red color component. */
+    uint8_t blue;  /*!< Red color component. */
+} lcdc_cursor_palette_t;
+
+/*!
+ * @brief LCD hardware cursor frame synchronization mode.
+ */
+typedef enum _lcdc_cursor_sync_mode
+{
+    kLCDC_CursorAsync, /*!< Cursor change will be displayed immediately. */
+    kLCDC_CursorSync,  /*!< Cursor change will be displayed in next frame. */
+} lcdc_cursor_sync_mode_t;
+
+/*!
+ * @brief LCD hardware cursor configuration structure.
+ */
+typedef struct _lcdc_cursor_config
+{
+    lcdc_cursor_size_t size;            /*!< Cursor size. */
+    lcdc_cursor_sync_mode_t syncMode;   /*!< Cursor synchronization mode. */
+    lcdc_cursor_palette_t palette0;     /*!< Cursor palette 0. */
+    lcdc_cursor_palette_t palette1;     /*!< Cursor palette 1. */
+    uint32_t *image[LCDC_CURSOR_COUNT]; /*!< Pointer to cursor image data. */
+} lcdc_cursor_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization and Deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize the LCD module.
+ *
+ * @param base LCD peripheral base address.
+ * @param config Pointer to configuration structure, see to @ref lcdc_config_t.
+ * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
+ * @retval kStatus_Success LCD is initialized successfully.
+ * @retval kStatus_InvalidArgument Initlialize failed because of invalid argument.
+ */
+status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitialize the LCD module.
+ *
+ * @param base LCD peripheral base address.
+ */
+void LCDC_Deinit(LCD_Type *base);
+
+/*!
+ * @brief Gets default pre-defined settings for initial configuration.
+ *
+ * This function initializes the configuration structure. The default values are:
+ *
+   @code
+    config->panelClock_Hz = 0U;
+    config->ppl = 0U;
+    config->hsw = 0U;
+    config->hfp = 0U;
+    config->hbp = 0U;
+    config->lpp = 0U;
+    config->vsw = 0U;
+    config->vfp = 0U;
+    config->vbp = 0U;
+    config->acBiasFreq = 1U;
+    config->polarityFlags = 0U;
+    config->enableLineEnd = false;
+    config->lineEndDelay = 0U;
+    config->upperPanelAddr = 0U;
+    config->lowerPanelAddr = 0U;
+    config->bpp = kLCDC_1BPP;
+    config->dataFormat = kLCDC_LittleEndian;
+    config->swapRedBlue = false;
+    config->display = kLCDC_DisplayTFT;
+   @endcode
+ *
+ * @param config Pointer to configuration structure.
+ */
+void LCDC_GetDefaultConfig(lcdc_config_t *config);
+
+/* @} */
+
+/*!
+ * @name Start and stop
+ * @{
+ */
+
+/*!
+ * @brief Start to output LCD timing signal.
+ *
+ * The LCD power up sequence should be:
+ * 1. Apply power to LCD, here all output signals are held low.
+ * 2. When LCD power stablized, call @ref LCDC_Start to output the timing signals.
+ * 3. Apply contrast voltage to LCD panel. Delay if the display requires.
+ * 4. Call @ref LCDC_PowerUp.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_Start(LCD_Type *base)
+{
+    base->CTRL |= LCD_CTRL_LCDEN_MASK;
+}
+
+/*!
+ * @brief Stop the LCD timing signal.
+ *
+ * The LCD power down sequence should be:
+ * 1. Call @ref LCDC_PowerDown.
+ * 2. Delay if the display requires. Disable contrast voltage to LCD panel.
+ * 3. Call @ref LCDC_Stop to disable the timing signals.
+ * 4. Disable power to LCD.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_Stop(LCD_Type *base)
+{
+    base->CTRL &= ~LCD_CTRL_LCDEN_MASK;
+}
+
+/*!
+ * @brief Power up the LCD and output the pixel signal.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_PowerUp(LCD_Type *base)
+{
+    base->CTRL |= LCD_CTRL_LCDPWR_MASK;
+}
+
+/*!
+ * @brief Power down the LCD and disable the output pixel signal.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_PowerDown(LCD_Type *base)
+{
+    base->CTRL &= ~LCD_CTRL_LCDPWR_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name LCD control
+ * @{
+ */
+
+/*!
+ * @brief Sets panel frame base address
+ *
+ * @param base LCD peripheral base address.
+ * @param panel Which panel to set.
+ * @param addr Frame base address, must be doubleword(64-bit) aligned.
+ */
+void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr);
+
+/*!
+ * @brief Sets palette
+ *
+ * @param base LCD peripheral base address.
+ * @param palette Pointer to the palette array.
+ * @param count_words Length of the palette array to set (how many words), it should
+ * not be larger than LCDC_PALETTE_SIZE_WORDS.
+ */
+void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Sets the vertical compare interrupt mode.
+ *
+ * @param base LCD peripheral base address.
+ * @param mode The vertical compare interrupt mode.
+ */
+static inline void LCDC_SetVerticalInterruptMode(LCD_Type *base, lcdc_vertical_compare_interrupt_mode_t mode)
+{
+    base->CTRL = (base->CTRL & ~LCD_CTRL_LCDVCOMP_MASK) | LCD_CTRL_LCDVCOMP(mode);
+}
+
+/*!
+ * @brief Enable LCD interrupts.
+ *
+ * Example to enable LCD base address update interrupt and vertical compare
+ * interrupt:
+ *
+ * @code
+   LCDC_EnableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to enable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disable LCD interrupts.
+ *
+ * Example to disable LCD base address update interrupt and vertical compare
+ * interrupt:
+ *
+ * @code
+   LCDC_DisableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Get LCD interrupt pending status.
+ *
+ * Example:
+ *
+ * @code
+   uint32_t status;
+
+   status = LCDC_GetInterruptsPendingStatus(LCD);
+
+   if (kLCDC_BaseAddrUpdateInterrupt & status)
+   {
+       // LCD base address update interrupt occurred.
+   }
+
+   if (kLCDC_VerticalCompareInterrupt & status)
+   {
+       // LCD vertical compare interrupt occurred.
+   }
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base);
+
+/*!
+ * @brief Get LCD enabled interrupt pending status.
+ *
+ * This function is similar with @ref LCDC_GetInterruptsPendingStatus, the only
+ * difference is, this function only returns the pending status of the
+ * interrupts that have been enabled using @ref LCDC_EnableInterrupts.
+ *
+ * @param base LCD peripheral base address.
+ * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base);
+
+/*!
+ * @brief Clear LCD interrupts pending status.
+ *
+ * Example to clear LCD base address update interrupt and vertical compare
+ * interrupt pending status:
+ *
+ * @code
+   LCDC_ClearInterruptsStatus(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Hardware cursor
+ * @{
+ */
+
+/*!
+ * @brief Set the hardware cursor configuration
+ *
+ * This function should be called before enabling the hardware cursor.
+ * It supports initializing multiple cursor images at a time when using
+ * 32x32 pixels cursor.
+ *
+ * For example:
+ *
+ * @code
+   uint32_t cursor0Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
+   uint32_t cursor2Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
+
+   lcdc_cursor_config_t cursorConfig;
+
+   LCDC_CursorGetDefaultConfig(&cursorConfig);
+
+   cursorConfig.image[0] = cursor0Img;
+   cursorConfig.image[2] = cursor2Img;
+
+   LCDC_SetCursorConfig(LCD, &cursorConfig);
+
+   LCDC_ChooseCursor(LCD, 0);
+   LCDC_SetCursorPosition(LCD, 0, 0);
+
+   LCDC_EnableCursor(LCD);
+   @endcode
+ *
+ * In this example, cursor 0 and cursor 2 image data are initialized, but cursor 1
+ * and cursor 3 image data are not initialized because image[1] and image[2] are
+ * all NULL. With this, application could initializes all cursor images it will
+ * use at the beginning and call @ref LCDC_SetCursorImage directly to display the
+ * one which it needs.
+ *
+ * @param base LCD peripheral base address.
+ * @param config Pointer to the hardware cursor configuration structure.
+ */
+void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config);
+
+/*!
+ * @brief Get the hardware cursor default configuration
+ *
+ * The default configuration values are:
+ *
+ * @code
+    config->size = kLCDC_CursorSize32;
+    config->syncMode = kLCDC_CursorAsync;
+    config->palette0.red = 0U;
+    config->palette0.green = 0U;
+    config->palette0.blue = 0U;
+    config->palette1.red = 255U;
+    config->palette1.green = 255U;
+    config->palette1.blue = 255U;
+    config->image[0] = (uint32_t *)0;
+    config->image[1] = (uint32_t *)0;
+    config->image[2] = (uint32_t *)0;
+    config->image[3] = (uint32_t *)0;
+   @endcode
+ *
+ * @param config Pointer to the hardware cursor configuration structure.
+ */
+void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config);
+
+/*!
+ * @brief Enable or disable the cursor.
+ *
+ * @param base LCD peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LCDC_EnableCursor(LCD_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CRSR_CTRL |= LCD_CRSR_CTRL_CRSRON_MASK;
+    }
+    else
+    {
+        base->CRSR_CTRL &= ~LCD_CRSR_CTRL_CRSRON_MASK;
+    }
+}
+
+/*!
+ * @brief Choose which cursor to display.
+ *
+ * When using 32x32 cursor, the number of cursors supports is @ref LCDC_CURSOR_COUNT.
+ * When using 64x64 cursor, the LCD only supports one cursor.
+ * This function selects which cursor to display when using 32x32 cursor.
+ * When synchronization mode is @ref kLCDC_CursorSync, the change effects in the
+ * next frame. When synchronization mode is @ref * kLCDC_CursorAsync, change effects
+ * immediately.
+ *
+ * @param base LCD peripheral base address.
+ * @param index Index of the cursor to display.
+ * @note The function @ref LCDC_SetCursorPosition must be called after this function
+ * to show the new cursor.
+ */
+static inline void LCDC_ChooseCursor(LCD_Type *base, uint8_t index)
+{
+    base->CRSR_CTRL = (base->CRSR_CTRL & ~LCD_CRSR_CTRL_CRSRNUM1_0_MASK) | LCD_CRSR_CTRL_CRSRNUM1_0(index);
+}
+
+/*!
+ * @brief Set the position of cursor
+ *
+ * When synchronization mode is @ref kLCDC_CursorSync, position change effects
+ * in the next frame. When synchronization mode is @ref kLCDC_CursorAsync,
+ * position change effects immediately.
+ *
+ * @param base LCD peripheral base address.
+ * @param positionX X ordinate of the cursor top-left measured in pixels
+ * @param positionY Y ordinate of the cursor top-left measured in pixels
+ */
+void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY);
+
+/*!
+ * @brief Set the cursor image.
+ *
+ * The interrupt @ref kLCDC_CursorInterrupt indicates that last cursor pixel is
+ * displayed. When the hardware cursor is enabled,
+ *
+ * @param base LCD peripheral base address.
+ * @param size The cursor size.
+ * @param index Index of the cursor to set when using 32x32 cursor.
+ * @param image Pointer to the cursor image. When using 32x32 cursor, the image
+ * size should be LCDC_CURSOR_IMG_32X32_WORDS. When using 64x64 cursor, the image
+ * size should be LCDC_CURSOR_IMG_64X64_WORDS.
+ */
+void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __FSL_LCDC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,862 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcan.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+
+#define MCAN_TIME_QUANTA_NUM (16U)
+
+/*! @brief MCAN Internal State. */
+enum _mcan_state
+{
+    kMCAN_StateIdle = 0x0,     /*!< MB/RxFIFO idle.*/
+    kMCAN_StateRxData = 0x1,   /*!< MB receiving.*/
+    kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
+    kMCAN_StateTxData = 0x3,   /*!< MB transmitting.*/
+    kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
+    kMCAN_StateRxFifo = 0x5,   /*!< RxFIFO receiving.*/
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the MCAN instance from peripheral base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @return MCAN instance.
+ */
+uint32_t MCAN_GetInstance(CAN_Type *base);
+
+/*!
+ * @brief Reset the MCAN instance.
+ *
+ * @param base MCAN peripheral base address.
+ */
+static void MCAN_Reset(CAN_Type *base);
+
+/*!
+ * @brief Set Baud Rate of MCAN.
+ *
+ * This function set the baud rate of MCAN.
+ *
+ * @param base MCAN peripheral base address.
+ * @param sourceClock_Hz Source Clock in Hz.
+ * @param baudRate_Bps Baud Rate in Bps.
+ */
+static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps);
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+/*!
+ * @brief Set Baud Rate of MCAN FD.
+ *
+ * This function set the baud rate of MCAN FD.
+ *
+ * @param base MCAN peripheral base address.
+ * @param sourceClock_Hz Source Clock in Hz.
+ * @param baudRateD_Bps Baud Rate in Bps.
+ */
+static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps);
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+/*!
+ * @brief Get the element's address when read receive fifo 0.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Address of the element in receive fifo 0.
+ */
+static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base);
+
+/*!
+ * @brief Get the element's address when read receive fifo 1.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Address of the element in receive fifo 1.
+ */
+static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base);
+
+/*!
+ * @brief Get the element's address when read receive buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Number of the erceive buffer element.
+ * @return Address of the element in receive buffer.
+ */
+static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx);
+
+/*!
+ * @brief Get the element's address when read transmit buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Number of the transmit buffer element.
+ * @return Address of the element in transmit buffer.
+ */
+static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of MCAN handle. */
+static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT];
+
+/* Array of MCAN peripheral base address. */
+static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS;
+
+/* Array of MCAN IRQ number. */
+static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of MCAN clock name. */
+static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* MCAN ISR for transactional APIs. */
+static mcan_isr_t s_mcanIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t MCAN_GetInstance(CAN_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++)
+    {
+        if (s_mcanBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_mcanBases));
+
+    return instance;
+}
+
+static void MCAN_Reset(CAN_Type *base)
+{
+    /* Set INIT bit. */
+    base->CCCR |= CAN_CCCR_INIT_MASK;
+    /* Confirm the value has been accepted. */
+    while (!((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
+    {
+    }
+
+    /* Set CCE bit to have access to the protected configuration registers,
+       and clear some status registers. */
+    base->CCCR |= CAN_CCCR_CCE_MASK;
+}
+
+static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps)
+{
+    mcan_timing_config_t timingConfigA;
+    uint32_t preDivA = baudRateA_Bps * MCAN_TIME_QUANTA_NUM;
+
+    if (0 == preDivA)
+    {
+        preDivA = 1U;
+    }
+
+    preDivA = (sourceClock_Hz / preDivA) - 1U;
+
+    /* Desired baud rate is too low. */
+    if (preDivA > 0x1FFU)
+    {
+        preDivA = 0x1FFU;
+    }
+
+    /* MCAN timing setting formula:
+     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
+     */
+    timingConfigA.preDivider = preDivA;
+    timingConfigA.seg1 = 0xAU;
+    timingConfigA.seg2 = 0x3U;
+    timingConfigA.rJumpwidth = 0x3U;
+
+    /* Update actual timing characteristic. */
+    MCAN_SetArbitrationTimingConfig(base, &timingConfigA);
+}
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps)
+{
+    mcan_timing_config_t timingConfigD;
+    uint32_t preDivD = baudRateD_Bps * MCAN_TIME_QUANTA_NUM;
+
+    if (0 == preDivD)
+    {
+        preDivD = 1U;
+    }
+
+    preDivD = (sourceClock_Hz / preDivD) - 1U;
+
+    /* Desired baud rate is too low. */
+    if (preDivD > 0x1FU)
+    {
+        preDivD = 0x1FU;
+    }
+
+    /* MCAN timing setting formula:
+     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
+     */
+    timingConfigD.preDivider = preDivD;
+    timingConfigD.seg1 = 0xAU;
+    timingConfigD.seg2 = 0x3U;
+    timingConfigD.rJumpwidth = 0x3U;
+
+    /* Update actual timing characteristic. */
+    MCAN_SetDataTimingConfig(base, &timingConfigD);
+}
+#endif
+
+void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable MCAN clock. */
+    CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    MCAN_Reset(base);
+
+    if (config->enableLoopBackInt)
+    {
+        base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK;
+        base->TEST |= CAN_TEST_LBCK_MASK;
+    }
+    if (config->enableLoopBackExt)
+    {
+        base->CCCR |= CAN_CCCR_TEST_MASK;
+        base->TEST |= CAN_TEST_LBCK_MASK;
+    }
+    if (config->enableBusMon)
+    {
+        base->CCCR |= CAN_CCCR_MON_MASK;
+    }
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+    if (config->enableCanfdNormal)
+    {
+        base->CCCR |= CAN_CCCR_FDOE_MASK;
+    }
+    if (config->enableCanfdSwitch)
+    {
+        base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK;
+    }
+#endif
+
+    /* Set baud rate of arbitration and data phase. */
+    MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA);
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+    MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD);
+#endif
+}
+
+void MCAN_Deinit(CAN_Type *base)
+{
+    /* Reset all Register Contents. */
+    MCAN_Reset(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable MCAN clock. */
+    CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void MCAN_EnterNormalMode(CAN_Type *base)
+{
+    /* Reset INIT bit to enter normal mode. */
+    base->CCCR &= ~CAN_CCCR_INIT_MASK;
+    while (((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
+    {
+    }
+}
+
+void MCAN_GetDefaultConfig(mcan_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Initialize MCAN Module config struct with default value. */
+    config->baudRateA = 500000U;
+    config->baudRateD = 500000U;
+    config->enableCanfdNormal = false;
+    config->enableCanfdSwitch = false;
+    config->enableLoopBackInt = false;
+    config->enableLoopBackExt = false;
+    config->enableBusMon = false;
+}
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Cleaning previous Timing Setting. */
+    base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK);
+
+    /* Updating Timing Setting according to configuration structure. */
+    base->DBTP |= (CAN_DBTP_DBRP(config->preDivider) | CAN_DBTP_DSJW(config->rJumpwidth) |
+                   CAN_DBTP_DTSEG1(config->seg1) | CAN_DBTP_DTSEG2(config->seg2));
+}
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Cleaning previous Timing Setting. */
+    base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK);
+
+    /* Updating Timing Setting according to configuration structure. */
+    base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) |
+                   CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2));
+}
+
+void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config)
+{
+    /* Set global configuration of remote/nonmasking frames, set filter address and list size. */
+    if (config->idFormat == kMCAN_FrameIDStandard)
+    {
+        base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame);
+        base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize);
+    }
+    else
+    {
+        base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame);
+        base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize);
+    }
+}
+
+void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
+{
+    /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */
+    base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) |
+                   CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode);
+    /* Set Rx FIFO 0 data field size */
+    base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize);
+}
+
+void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
+{
+    /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */
+    base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) |
+                   CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode);
+    /* Set Rx FIFO 1 data field size */
+    base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize);
+}
+
+void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config)
+{
+    /* Set Rx Buffer start address. */
+    base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT);
+    /* Set Rx Buffer data field size */
+    base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize);
+}
+
+void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config)
+{
+    /* Set TX Event FIFO start address, element size, watermark. */
+    base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) |
+                   CAN_TXEFC_EFWM(config->watermark);
+}
+
+void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config)
+{
+    assert((config->dedicatedSize + config->fqSize) <= 32U);
+
+    /* Set Tx Buffer start address, size, fifo/queue mode. */
+    base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) |
+                  CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode);
+    /* Set Tx Buffer data field size */
+    base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize);
+}
+
+void MCAN_SetSTDFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_std_filter_element_config_t *filter,
+                              uint8_t idx)
+{
+    uint8_t *elementAddress = 0;
+    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U);
+    memcpy(elementAddress, filter, sizeof(filter));
+}
+
+void MCAN_SetEXTFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_ext_filter_element_config_t *filter,
+                              uint8_t idx)
+{
+    uint8_t *elementAddress = 0;
+    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U);
+    memcpy(elementAddress, filter, sizeof(filter));
+}
+
+static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base)
+{
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXF0C & CAN_RXF0C_F0SA_MASK) +
+           ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U;
+}
+
+static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base)
+{
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXF1C & CAN_RXF1C_F1SA_MASK) +
+           ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U;
+}
+
+static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U;
+}
+
+static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 31U);
+    uint32_t eSize;
+    eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U;
+}
+
+uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx)
+{
+    return (base->TXBRP & (uint32_t)(1U << idx)) >> (uint32_t)idx;
+}
+
+uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx)
+{
+    return (base->TXBTO & (uint32_t)(1U << idx)) >> (uint32_t)idx;
+}
+
+status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame)
+{
+    if (!MCAN_IsTransmitRequestPending(base, idx))
+    {
+        uint8_t *elementAddress = 0;
+        elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx));
+
+        /* Write 2 words configuration field. */
+        memcpy(elementAddress, (uint8_t *)txFrame, 8U);
+        /* Write data field. */
+        memcpy(elementAddress + 8U, txFrame->data, txFrame->size);
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *rxFrame)
+{
+    mcan_rx_buffer_frame_t *elementAddress = 0;
+    elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx));
+    memcpy(rxFrame, elementAddress, (rxFrame->size + 8U) * 4U);
+    return kStatus_Success;
+}
+
+status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    mcan_rx_buffer_frame_t *elementAddress = 0;
+    if (0 == fifoBlock)
+    {
+        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base));
+    }
+    else
+    {
+        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base));
+    }
+    memcpy(rxFrame, elementAddress, 8U);
+    rxFrame->data = (uint8_t *)elementAddress + 8U;
+    /* Acknowledge the read. */
+    if (0 == fifoBlock)
+    {
+        base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT;
+    }
+    else
+    {
+        base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT;
+    }
+    return kStatus_Success;
+}
+
+status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame)
+{
+    if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, txFrame))
+    {
+        MCAN_TransmitAddRequest(base, idx);
+
+        /* Wait until message sent out. */
+        while (!MCAN_IsTransmitOccurred(base, idx))
+        {
+        }
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t bufferIdx, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert(bufferIdx <= 63U);
+
+    while (!MCAN_GetRxBufferStatusFlag(base, bufferIdx))
+    {
+    }
+    MCAN_ClearRxBufferStatusFlag(base, bufferIdx);
+    return MCAN_ReadRxBuffer(base, bufferIdx, rxFrame);
+}
+
+status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    if (0 == fifoBlock)
+    {
+        while (!MCAN_GetStatusFlag(base, CAN_IR_RF0N_MASK))
+        {
+        }
+        MCAN_ClearStatusFlag(base, CAN_IR_RF0N_MASK);
+    }
+    else
+    {
+        while (!MCAN_GetStatusFlag(base, CAN_IR_RF1N_MASK))
+        {
+        }
+        MCAN_ClearStatusFlag(base, CAN_IR_RF1N_MASK);
+    }
+    return MCAN_ReadRxFifo(base, fifoBlock, rxFrame);
+}
+
+void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    uint8_t instance;
+
+    /* Clean MCAN transfer handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Get instance from peripheral base address. */
+    instance = MCAN_GetInstance(base);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_mcanHandle[instance] = handle;
+
+    /* Register Callback function. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    s_mcanIsr = MCAN_TransferHandleIRQ;
+
+    /* We Enable Error & Status interrupt here, because this interrupt just
+     * report current status of MCAN module through Callback function.
+     * It is insignificance without a available callback function.
+     */
+    if (handle->callback != NULL)
+    {
+        MCAN_EnableInterrupts(base, 0,
+                              kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
+    }
+    else
+    {
+        MCAN_DisableInterrupts(base,
+                               kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
+    }
+
+    /* Enable interrupts in NVIC. */
+    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0]));
+    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1]));
+}
+
+status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer)
+{
+    /* Assertion. */
+    assert(handle);
+    assert(xfer);
+    assert(xfer->bufferIdx <= 63U);
+
+    /* Check if Tx Buffer is idle. */
+    if (kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx])
+    {
+        handle->txbufferIdx = xfer->bufferIdx;
+        /* Distinguish transmit type. */
+        if (kMCAN_FrameTypeRemote == xfer->frame->xtd)
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxRemote;
+
+            /* Register user Frame buffer to receive remote Frame. */
+            handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame;
+        }
+        else
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxData;
+        }
+
+        if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame))
+        {
+            /* Enable Buffer Interrupt. */
+            MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx);
+            MCAN_EnableInterrupts(base, 0, CAN_IE_TCE_MASK);
+
+            MCAN_TransmitAddRequest(base, xfer->bufferIdx);
+
+            return kStatus_Success;
+        }
+        else
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateIdle;
+            return kStatus_Fail;
+        }
+    }
+    else
+    {
+        return kStatus_MCAN_TxBusy;
+    }
+}
+
+status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
+                                             uint8_t fifoBlock,
+                                             mcan_handle_t *handle,
+                                             mcan_fifo_transfer_t *xfer)
+{
+    /* Assertion. */
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    assert(handle);
+    assert(xfer);
+
+    /* Check if Message Buffer is idle. */
+    if (kMCAN_StateIdle == handle->rxFifoState)
+    {
+        handle->rxFifoState = kMCAN_StateRxFifo;
+
+        /* Register Message Buffer. */
+        handle->rxFifoFrameBuf = xfer->frame;
+
+        /* Enable FIFO Interrupt. */
+        if (fifoBlock)
+        {
+            MCAN_EnableInterrupts(base, 0, CAN_IE_RF1NE_MASK);
+        }
+        else
+        {
+            MCAN_EnableInterrupts(base, 0, CAN_IE_RF0NE_MASK);
+        }
+        return kStatus_Success;
+    }
+    else
+    {
+        return fifoBlock ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy;
+    }
+}
+
+void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx)
+{
+    /* Assertion. */
+    assert(handle);
+    assert(bufferIdx <= 63U);
+
+    /* Disable Buffer Interrupt. */
+    MCAN_DisableTransmitBufferInterrupts(base, bufferIdx);
+    MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK);
+
+    /* Cancel send request. */
+    MCAN_TransmitCancelRequest(base, bufferIdx);
+
+    /* Un-register handle. */
+    handle->bufferFrameBuf[bufferIdx] = 0x0;
+
+    handle->bufferState[bufferIdx] = kMCAN_StateIdle;
+}
+
+void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle)
+{
+    /* Assertion. */
+    assert(handle);
+    assert((fifoBlock == 0) || (fifoBlock == 1));
+
+    /* Check if Rx FIFO is enabled. */
+    if (fifoBlock)
+    {
+        /* Disable Rx Message FIFO Interrupts. */
+        MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK);
+    }
+    else
+    {
+        MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK);
+    }
+    /* Un-register handle. */
+    handle->rxFifoFrameBuf = 0x0;
+
+    handle->rxFifoState = kMCAN_StateIdle;
+}
+
+void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle)
+{
+    /* Assertion. */
+    assert(handle);
+
+    status_t status = kStatus_MCAN_UnHandled;
+    uint32_t result;
+
+    /* Store Current MCAN Module Error and Status. */
+    result = base->IR;
+
+    do
+    {
+        /* Solve Rx FIFO, Tx interrupt. */
+        if (result & kMCAN_TxTransmitCompleteFlag)
+        {
+            status = kStatus_MCAN_TxIdle;
+            MCAN_TransferAbortSend(base, handle, handle->txbufferIdx);
+        }
+        else if (result & kMCAN_RxFifo0NewFlag)
+        {
+            MCAN_ReadRxFifo(base, 0, handle->rxFifoFrameBuf);
+            status = kStatus_MCAN_RxFifo0Idle;
+            MCAN_TransferAbortReceiveFifo(base, 0, handle);
+        }
+        else if (result & kMCAN_RxFifo0LostFlag)
+        {
+            status = kStatus_MCAN_RxFifo0Lost;
+        }
+        else if (result & kMCAN_RxFifo1NewFlag)
+        {
+            MCAN_ReadRxFifo(base, 1, handle->rxFifoFrameBuf);
+            status = kStatus_MCAN_RxFifo1Idle;
+            MCAN_TransferAbortReceiveFifo(base, 1, handle);
+        }
+        else if (result & kMCAN_RxFifo1LostFlag)
+        {
+            status = kStatus_MCAN_RxFifo0Lost;
+        }
+        else
+        {
+            ;
+        }
+
+        /* Clear resolved Rx FIFO, Tx Buffer IRQ. */
+        MCAN_ClearStatusFlag(base, result);
+
+        /* Calling Callback Function if has one. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, status, result, handle->userData);
+        }
+
+        /* Reset return status */
+        status = kStatus_MCAN_UnHandled;
+
+        /* Store Current MCAN Module Error and Status. */
+        result = base->IR;
+    } while ((0 != MCAN_GetStatusFlag(base, 0xFFFFFFFFU)) ||
+             (0 != (result & (kMCAN_ErrorWarningIntFlag | kMCAN_BusOffIntFlag | kMCAN_ErrorPassiveIntFlag))));
+}
+
+#if defined(CAN0)
+void CAN0_IRQ0_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[0]);
+
+    s_mcanIsr(CAN0, s_mcanHandle[0]);
+}
+
+void CAN0_IRQ1_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[0]);
+
+    s_mcanIsr(CAN0, s_mcanHandle[0]);
+}
+#endif
+
+#if defined(CAN1)
+void CAN1_IRQ0_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[1]);
+
+    s_mcanIsr(CAN1, s_mcanHandle[1]);
+}
+
+void CAN1_IRQ1_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[1]);
+
+    s_mcanIsr(CAN1, s_mcanHandle[1]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,966 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MCAN_H_
+#define _FSL_MCAN_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mcan
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MCAN driver version 2.0.0. */
+#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief MCAN transfer status. */
+enum _mcan_status
+{
+    kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0),            /*!< Tx Buffer is Busy. */
+    kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1),            /*!< Tx Buffer is Idle. */
+    kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2),            /*!< Rx Buffer is Busy. */
+    kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3),            /*!< Rx Buffer is Idle. */
+    kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4),        /*!< New message written to Rx FIFO 0. */
+    kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5),       /*!< Rx FIFO 0 is Idle. */
+    kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6),  /*!< Rx FIFO 0 fill level reached watermark. */
+    kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7),       /*!< Rx FIFO 0 full. */
+    kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8),       /*!< Rx FIFO 0 message lost. */
+    kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9),        /*!< New message written to Rx FIFO 1. */
+    kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10),      /*!< Rx FIFO 1 is Idle. */
+    kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */
+    kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12),      /*!< Rx FIFO 1 full. */
+    kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13),      /*!< Rx FIFO 1 message lost. */
+    kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14),      /*!< Rx FIFO 0 is busy. */
+    kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15),      /*!< Rx FIFO 1 is busy. */
+    kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16),      /*!< MCAN Module Error and Status. */
+    kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17),        /*!< UnHadled Interrupt asserted. */
+};
+
+/*!
+ * @brief MCAN status flags.
+ *
+ * This provides constants for the MCAN status flags for use in the MCAN functions.
+ * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to
+ * read MCAN_ErrorFlag and distinguish which error is occur using
+ * @ref _mcan_error_flags enumerations.
+ */
+enum _mcan_flags
+{
+    kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK,    /*!< CAN Synchronization Status. */
+    kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */
+    kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */
+    kMCAN_BusOffIntFlag = CAN_IR_BO_MASK,        /*!< Tx Error Warning Status. */
+    kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK,  /*!< Rx Error Warning Status. */
+    kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK,  /*!< Rx Error Warning Status. */
+};
+
+/*!
+ * @brief MCAN Rx FIFO status flags.
+ *
+ * The MCAN Rx FIFO Status enumerations are used to determine the status of the
+ * Rx FIFO.
+ */
+enum _mcan_rx_fifo_flags
+{
+    kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK,       /*!< Rx FIFO 0 new message flag. */
+    kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
+    kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK,      /*!< Rx FIFO 0 full flag. */
+    kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK,      /*!< Rx FIFO 0 message lost flag. */
+    kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK,       /*!< Rx FIFO 0 new message flag. */
+    kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
+    kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK,      /*!< Rx FIFO 0 full flag. */
+    kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK,      /*!< Rx FIFO 0 message lost flag. */
+};
+
+/*!
+ * @brief MCAN Tx status flags.
+ *
+ * The MCAN Tx Status enumerations are used to determine the status of the
+ * Tx Buffer/Event FIFO.
+ */
+enum _mcan_tx_flags
+{
+    kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK,      /*!< Transmission completed flag. */
+    kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */
+    kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK,       /*!< Tx Event FIFO element lost. */
+    kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK,       /*!< Tx Event FIFO full. */
+    kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK,  /*!< Tx Event FIFO fill level reached watermark. */
+    kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK,        /*!< Tx Handler wrote Tx Event FIFO element flag. */
+    kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK,       /*!< Tx FIFO empty flag. */
+};
+
+/*!
+ * @brief MCAN interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the MCAN Module interrupt configurations.
+ */
+enum _mcan_interrupt_enable
+{
+    kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK,  /*!< Bus Off interrupt. */
+    kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK,   /*!< Error interrupt. */
+    kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */
+};
+
+/*! @brief MCAN frame format. */
+typedef enum _mcan_frame_idformat
+{
+    kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */
+    kMCAN_FrameIDExtend = 0x1U,   /*!< Extend frame format attribute. */
+} mcan_frame_idformat_t;
+
+/*! @brief MCAN frame type. */
+typedef enum _mcan_frame_type
+{
+    kMCAN_FrameTypeData = 0x0U,   /*!< Data frame type attribute. */
+    kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
+} mcan_frame_type_t;
+
+/*! @brief MCAN frame datafield size. */
+typedef enum _mcan_bytes_in_datafield
+{
+    kMCAN_8ByteDatafield = 0x0U,  /*!< 8 byte data field. */
+    kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */
+    kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */
+    kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */
+    kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */
+    kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */
+    kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */
+    kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */
+} mcan_bytes_in_datafield_t;
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/*! @brief MCAN Tx Buffer structure. */
+typedef struct _mcan_tx_buffer_frame
+{
+    struct
+    {
+        uint32_t id : 29; /*!< CAN Frame Identifier. */
+        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
+        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
+        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
+    };
+    struct
+    {
+        uint32_t : 16;
+        uint32_t dlc : 4; /*!< Data Length Code. */
+        uint32_t brs : 1; /*!< Bit Rate Switch. */
+        uint32_t fdf : 1; /*!< CAN FD format. */
+        uint32_t : 1;     /*!< Reserved. */
+        uint32_t efc : 1; /*!< Event FIFO control. */
+        uint32_t mm : 8;  /*!< Message Marker. */
+    };
+    uint8_t *data;
+    uint8_t size;
+} mcan_tx_buffer_frame_t;
+
+/*! @brief MCAN Rx FIFO/Buffer structure. */
+typedef struct _mcan_rx_buffer_frame
+{
+    struct
+    {
+        uint32_t id : 29; /*!< CAN Frame Identifier. */
+        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
+        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
+        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
+    };
+    struct
+    {
+        uint32_t rxts : 16; /*!< Rx Timestamp. */
+        uint32_t dlc : 4;   /*!< Data Length Code. */
+        uint32_t brs : 1;   /*!< Bit Rate Switch. */
+        uint32_t fdf : 1;   /*!< CAN FD format. */
+        uint32_t : 2;       /*!< Reserved. */
+        uint32_t fidx : 7;  /*!< Filter Index. */
+        uint32_t anmf : 1;  /*!< Accepted Non-matching Frame. */
+    };
+    uint8_t *data;
+    uint8_t size;
+} mcan_rx_buffer_frame_t;
+
+/*! @brief MCAN Rx FIFO block number. */
+typedef enum _mcan_fifo_type
+{
+    kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */
+    kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */
+} mcan_fifo_type_t;
+
+/*! @brief MCAN FIFO Operation Mode. */
+typedef enum _mcan_fifo_opmode_config
+{
+    kMCAN_FifoBlocking = 0,  /*!< FIFO blocking mode. */
+    kMCAN_FifoOverwrite = 1, /*!< FIFO overwrite mode. */
+} mcan_fifo_opmode_config_t;
+
+/*! @brief MCAN Tx FIFO/Queue Mode. */
+typedef enum _mcan_txmode_config
+{
+    kMCAN_txFifo = 0,  /*!< Tx FIFO operation. */
+    kMCAN_txQueue = 1, /*!< Tx Queue operation. */
+} mcan_txmode_config_t;
+
+/*! @brief MCAN remote frames treatment. */
+typedef enum _mcan_remote_frame_config
+{
+    kMCAN_filterFrame = 0, /*!< Filter remote frames. */
+    kMCAN_rejectFrame = 1, /*!< Reject all remote frames. */
+} mcan_remote_frame_config_t;
+
+/*! @brief MCAN non-masking frames treatment. */
+typedef enum _mcan_nonmasking_frame_config
+{
+    kMCAN_acceptinFifo0 = 0, /*!< Accept non-masking frames in Rx FIFO 0. */
+    kMCAN_acceptinFifo1 = 1, /*!< Accept non-masking frames in Rx FIFO 1. */
+    kMCAN_reject0 = 2,       /*!< Reject non-masking frames. */
+    kMCAN_reject1 = 3,       /*!< Reject non-masking frames. */
+} mcan_nonmasking_frame_config_t;
+
+/*! @brief MCAN Filter Element Configuration. */
+typedef enum _mcan_fec_config
+{
+    kMCAN_disable = 0,       /*!< Disable filter element. */
+    kMCAN_storeinFifo0 = 1,  /*!< Store in Rx FIFO 0 if filter matches. */
+    kMCAN_storeinFifo1 = 2,  /*!< Store in Rx FIFO 1 if filter matches. */
+    kMCAN_reject = 3,        /*!< Reject ID if filter matches. */
+    kMCAN_setprio = 4,       /*!< Set priority if filter matches. */
+    kMCAN_setpriofifo0 = 5,  /*!< Set priority and store in FIFO 0 if filter matches. */
+    kMCAN_setpriofifo1 = 6,  /*!< Set priority and store in FIFO 1 if filter matches. */
+    kMCAN_storeinbuffer = 7, /*!< Store into Rx Buffer or as debug message. */
+} mcan_fec_config_t;
+
+/*! @brief MCAN Rx FIFO configuration. */
+typedef struct _mcan_rx_fifo_config
+{
+    uint32_t address;                        /*!< FIFOn start address. */
+    uint32_t elementSize;                    /*!< FIFOn element number. */
+    uint32_t watermark;                      /*!< FIFOn watermark level. */
+    mcan_fifo_opmode_config_t opmode;        /*!< FIFOn blocking/overwrite mode. */
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_rx_fifo_config_t;
+
+/*! @brief MCAN Rx Buffer configuration. */
+typedef struct _mcan_rx_buffer_config
+{
+    uint32_t address;                        /*!< Rx Buffer start address. */
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_rx_buffer_config_t;
+
+/*! @brief MCAN Tx Event FIFO configuration. */
+typedef struct _mcan_tx_fifo_config
+{
+    uint32_t address;     /*!< Event fifo start address. */
+    uint32_t elementSize; /*!< FIFOn element number. */
+    uint32_t watermark;   /*!< FIFOn watermark level. */
+} mcan_tx_fifo_config_t;
+
+/*! @brief MCAN Tx Buffer configuration. */
+typedef struct _mcan_tx_buffer_config
+{
+    uint32_t address;                        /*!< Tx Buffers Start Address. */
+    uint32_t dedicatedSize;                  /*!< Number of Dedicated Transmit Buffers. */
+    uint32_t fqSize;                         /*!< Transmit FIFO/Queue Size. */
+    mcan_txmode_config_t mode;               /*!< Tx FIFO/Queue Mode.*/
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_tx_buffer_config_t;
+
+/*! @brief MCAN Filter Type. */
+typedef enum _mcan_std_filter_type
+{
+    kMCAN_range = 0,           /*!< Range filter from SFID1 to SFID2. */
+    kMCAN_dual = 1,            /*!< Dual ID filter for SFID1 or SFID2. */
+    kMCAN_classic = 2,         /*!< Classic filter: SFID1 = filter, SFID2 = mask. */
+    kMCAN_disableORrange2 = 3, /*!< Filter element disabled for standard filter
+                                    or Range filter, XIDAM mask not applied for extended filter. */
+} mcan_filter_type_t;
+
+/*! @brief MCAN Standard Message ID Filter Element. */
+typedef struct _mcan_std_filter_element_config
+{
+    uint32_t sfid2 : 11;        /*!< Standard Filter ID 2. */
+    uint32_t : 5;               /*!< Reserved. */
+    uint32_t sfid1 : 11;        /*!< Standard Filter ID 1. */
+    mcan_fec_config_t sfec : 3; /*!< Standard Filter Element Configuration. */
+    mcan_filter_type_t sft : 2; /*!<  Standard Filter Type/ */
+} mcan_std_filter_element_config_t;
+
+/*! @brief MCAN Extended Message ID Filter Element. */
+typedef struct _mcan_ext_filter_element_config
+{
+    uint32_t efid1 : 29;        /*!< Extended Filter ID 1. */
+    mcan_fec_config_t efec : 3; /*!< Extended Filter Element Configuration. */
+    uint32_t efid2 : 29;        /*!< Extended Filter ID 2. */
+    uint32_t : 1;               /*!< Reserved. */
+    mcan_filter_type_t eft : 2; /*!< Extended Filter Type. */
+} mcan_ext_filter_element_config_t;
+
+/*! @brief MCAN Rx filter configuration. */
+typedef struct _mcan_frame_filter_config
+{
+    uint32_t address;                       /*!< Filter start address. */
+    uint32_t listSize;                      /*!< Filter list size. */
+    mcan_frame_idformat_t idFormat;         /*!< Frame format. */
+    mcan_remote_frame_config_t remFrame;    /*!< Remote frame treatment. */
+    mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */
+} mcan_frame_filter_config_t;
+
+/*! @brief MCAN module configuration structure. */
+typedef struct _mcan_config
+{
+    uint32_t baudRateA;     /*!< Baud rate of Arbitration phase in bps. */
+    uint32_t baudRateD;     /*!< Baud rate of Data phase in bps. */
+    bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */
+    bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */
+    bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */
+    bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */
+    bool enableBusMon;      /*!< Enable or Disable Bus Monitoring Mode. */
+} mcan_config_t;
+
+/*! @brief MCAN protocol timing characteristic configuration structure. */
+typedef struct _mcan_timing_config
+{
+    uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
+    uint8_t rJumpwidth;  /*!< Re-sync Jump Width. */
+    uint8_t seg1;        /*!< Data Time Segment 1. */
+    uint8_t seg2;        /*!< Data Time Segment 2. */
+} mcan_timing_config_t;
+
+/*! @brief MCAN Buffer transfer. */
+typedef struct _mcan_buffer_transfer
+{
+    mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
+    uint8_t bufferIdx;             /*!< The index of Message buffer used to transfer Message. */
+} mcan_buffer_transfer_t;
+
+/*! @brief MCAN Rx FIFO transfer. */
+typedef struct _mcan_fifo_transfer
+{
+    mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */
+} mcan_fifo_transfer_t;
+
+/*! @brief MCAN handle structure definition. */
+typedef struct _mcan_handle mcan_handle_t;
+
+/*! @brief MCAN transfer callback function.
+ *
+ *  The MCAN transfer callback returns a value from the underlying layer.
+ *  If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of
+ *  MCAN status register which can be used to get the working status(or error status) of MCAN module.
+ *  If the status equals to other MCAN Message Buffer transfer status, the result is the index of
+ *  Message Buffer that generate transfer event.
+ *  If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be
+ *  Ignored.
+ */
+typedef void (*mcan_transfer_callback_t)(
+    CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData);
+
+/*! @brief MCAN handle structure. */
+struct _mcan_handle
+{
+    mcan_transfer_callback_t callback;                   /*!< Callback function. */
+    void *userData;                                      /*!< MCAN callback function parameter.*/
+    mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */
+    mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf;     /*!< The buffer for received data from Rx FIFO. */
+    volatile uint8_t txbufferIdx;                        /*!< Message Buffer transfer state. */
+    volatile uint8_t bufferState[64];                    /*!< Message Buffer transfer state. */
+    volatile uint8_t rxFifoState;                        /*!< Rx FIFO transfer state. */
+};
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an MCAN instance.
+ *
+ * This function initializes the MCAN module with user-defined settings.
+ * This example shows how to set up the mcan_config_t parameters and how
+ * to call the MCAN_Init function by passing in these parameters.
+ *  @code
+ *   mcan_config_t config;
+ *   config->baudRateA = 500000U;
+ *   config->baudRateD = 500000U;
+ *   config->enableCanfdNormal = false;
+ *   config->enableCanfdSwitch = false;
+ *   config->enableLoopBackInt = false;
+ *   config->enableLoopBackExt = false;
+ *   config->enableBusMon = false;
+ *   MCAN_Init(CANFD0, &config, 8000000UL);
+ *   @endcode
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the user-defined configuration structure.
+ * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz.
+ */
+void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz);
+
+/*!
+ * @brief Deinitializes an MCAN instance.
+ *
+ * This function deinitializes the MCAN module.
+ *
+ * @param base MCAN peripheral base address.
+ */
+void MCAN_Deinit(CAN_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the MCAN configuration structure to default values. The default
+ * values are as follows.
+ *   config->baudRateA = 500000U;
+ *   config->baudRateD = 500000U;
+ *   config->enableCanfdNormal = false;
+ *   config->enableCanfdSwitch = false;
+ *   config->enableLoopBackInt = false;
+ *   config->enableLoopBackExt = false;
+ *   config->enableBusMon = false;
+ *
+ * @param config Pointer to the MCAN configuration structure.
+ */
+void MCAN_GetDefaultConfig(mcan_config_t *config);
+
+/*!
+ * @brief MCAN enters normal mode.
+ *
+ * After initialization, INIT bit in CCCR register must be cleared to enter
+ * normal mode thus synchronizes to the CAN bus and ready for communication.
+ *
+ * @param base MCAN peripheral base address.
+ */
+void MCAN_EnterNormalMode(CAN_Type *base);
+
+/*!
+ * @name Configuration.
+ * @{
+ */
+
+/*!
+ * @brief Sets the MCAN Message RAM base address.
+ *
+ * This function sets the Message RAM base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @param value Desired Message RAM base.
+ */
+static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value)
+{
+    assert((value >= 0x20000000U) && (value <= 0x20027FFFU));
+
+    base->MRBA = CAN_MRBA_BA(value);
+}
+
+/*!
+ * @brief Gets the MCAN Message RAM base address.
+ *
+ * This function gets the Message RAM base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Message RAM base address.
+ */
+static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base)
+{
+    return base->MRBA;
+}
+
+/*!
+ * @brief Sets the MCAN protocol arbitration phase timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the MCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default arbitration phase timing characteristics.
+ *
+ * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
+ * set in MCAN_Init().
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the timing configuration structure.
+ */
+void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+/*!
+ * @brief Sets the MCAN protocol data phase timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the MCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default data phase timing characteristics.
+ *
+ * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
+ * set in MCAN_Init().
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the timing configuration structure.
+ */
+void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+/*!
+ * @brief Configures an MCAN receive fifo 0 buffer.
+ *
+ * This function sets start address, element size, watermark, operation mode
+ * and datafield size of the recieve fifo 0.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive fifo 0 configuration structure.
+ */
+void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN receive fifo 1 buffer.
+ *
+ * This function sets start address, element size, watermark, operation mode
+ * and datafield size of the recieve fifo 1.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive fifo 1 configuration structure.
+ */
+void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN receive buffer.
+ *
+ * This function sets start address and datafield size of the recieve buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive buffer configuration structure.
+ */
+void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config);
+
+/*!
+ * @brief Configures an MCAN transmit event fifo.
+ *
+ * This function sets start address, element size, watermark of the transmit event fifo.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The transmit event fifo configuration structure.
+ */
+void MCAN_SetTxEventfifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN transmit buffer.
+ *
+ * This function sets start address, element size, fifo/queue mode and datafield
+ * size of the transmit buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The transmit buffer configuration structure.
+ */
+void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetSTDFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_std_filter_element_config_t *filter,
+                              uint8_t idx);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetEXTFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_ext_filter_element_config_t *filter,
+                              uint8_t idx);
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the MCAN module interrupt flags.
+ *
+ * This function gets all MCAN interrupt status flags.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The ORed MCAN interrupt mask.
+ * @return MCAN status flags which are ORed.
+ */
+static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask)
+{
+    return (bool)(base->IR & mask);
+}
+
+/*!
+ * @brief Clears the MCAN module interrupt flags.
+ *
+ * This function clears MCAN interrupt status flags.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The ORed MCAN interrupt mask.
+ */
+static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask)
+{
+    /* Write 1 to clear status flag. */
+    base->IR |= mask;
+}
+
+/*!
+ * @brief Gets the new data flag of specific Rx Buffer.
+ *
+ * This function gets new data flag of specific Rx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Rx Buffer index.
+ * @return Rx Buffer new data status flag.
+ */
+static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+
+    if (idx <= 31U)
+    {
+        return (bool)(base->NDAT1 & (1U << idx));
+    }
+    else
+    {
+        return (bool)(base->NDAT2 & (1U << (idx - 31U)));
+    }
+}
+
+/*!
+ * @brief Clears the new data flag of specific Rx Buffer.
+ *
+ * This function clears new data flag of specific Rx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Rx Buffer index.
+ */
+static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+
+    if (idx <= 31U)
+    {
+        base->NDAT1 &= ~(1U << idx);
+    }
+    else
+    {
+        base->NDAT2 &= ~(1U << (idx - 31U));
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables MCAN interrupts according to the provided interrupt line and mask.
+ *
+ * This function enables the MCAN interrupts according to the provided interrupt line and mask.
+ * The mask is a logical OR of enumeration members.
+ *
+ * @param base MCAN peripheral base address.
+ * @param line Interrupt line number, 0 or 1.
+ * @param mask The interrupts to enable.
+ */
+static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask)
+{
+    base->ILE |= (1U << line);
+    if (0 == line)
+    {
+        base->ILS &= ~mask;
+    }
+    else
+    {
+        base->ILS |= mask;
+    }
+    base->IE |= mask;
+}
+
+/*!
+ * @brief Enables MCAN Tx Buffer interrupts according to the provided index.
+ *
+ * This function enables the MCAN Tx Buffer interrupts.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
+{
+    base->TXBTIE |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Disables MCAN Tx Buffer interrupts according to the provided index.
+ *
+ * This function disables the MCAN Tx Buffer interrupts.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
+{
+    base->TXBTIE &= (uint32_t)(~(1U << idx));
+}
+
+/*!
+ * @brief Disables MCAN interrupts according to the provided mask.
+ *
+ * This function disables the MCAN interrupts according to the provided mask.
+ * The mask is a logical OR of enumeration members.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The interrupts to disable.
+ */
+static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
+{
+    base->IE &= ~mask;
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes an MCAN Message to the Transmit Buffer.
+ *
+ * This function writes a CAN Message to the specified Transmit Message Buffer
+ * and changes the Message Buffer state to start CAN Message transmit. After
+ * that the function returns immediately.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx The MCAN Tx Buffer index.
+ * @param txFrame Pointer to CAN message frame to be sent.
+ */
+status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame);
+
+/*!
+ * @brief Reads an MCAN Message from Rx FIFO.
+ *
+ * This function reads a CAN message from the Rx FIFO in the Message RAM.
+ *
+ * @param base MCAN peripheral base address.
+ * @param fifoBlock Rx FIFO block 0 or 1.
+ * @param rxFrame Pointer to CAN message frame structure for reception.
+ * @retval kStatus_Success - Read Message from Rx FIFO successfully.
+ */
+status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Tx Buffer add request to send message out.
+ *
+ * This function add sending request to corresponding Tx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx)
+{
+    base->TXBAR |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Tx Buffer cancel sending request.
+ *
+ * This function clears Tx buffer request pending bit.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx)
+{
+    base->TXBCR |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Performs a polling send transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created  before calling this API.
+ *
+ * @param base MCAN peripheral base pointer.
+ * @param idx The MCAN buffer index.
+ * @param txFrame Pointer to CAN message frame to be sent.
+ * @retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * @retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
+status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame);
+
+/*!
+ * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created before calling this API.
+ *
+ * @param base MCAN peripheral base pointer.
+ * @param fifoBlock Rx FIFO block, 0 or 1.
+ * @param rxFrame Pointer to CAN message frame structure for reception.
+ * @retval kStatus_Success - Read Message from Rx FIFO successfully.
+ * @retval kStatus_Fail    - No new message in Rx FIFO.
+ */
+status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
+
+/*!
+ * @brief Initializes the MCAN handle.
+ *
+ * This function initializes the MCAN handle, which can be used for other MCAN
+ * transactional APIs. Usually, for a specified MCAN instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+void MCAN_TransferCreateHandle(CAN_Type *base,
+                               mcan_handle_t *handle,
+                               mcan_transfer_callback_t callback,
+                               void *userData);
+
+/*!
+ * @brief Sends a message using IRQ.
+ *
+ * This function sends a message using IRQ. This is a non-blocking function, which returns
+ * right away. When messages have been sent out, the send callback function is called.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t.
+ * @retval kStatus_Success        Start Tx Buffer sending process successfully.
+ * @retval kStatus_Fail           Write Tx Buffer failed.
+ * @retval kStatus_MCAN_TxBusy Tx Buffer is in use.
+ */
+status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer);
+
+/*!
+ * @brief Receives a message from Rx FIFO using IRQ.
+ *
+ * This function receives a message using IRQ. This is a non-blocking function, which returns
+ * right away. When all messages have been received, the receive callback function is called.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param fifoBlock Rx FIFO block, 0 or 1.
+ * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t.
+ * @retval kStatus_Success            - Start Rx FIFO receiving process successfully.
+ * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use.
+ * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use.
+ */
+status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
+                                             uint8_t fifoBlock,
+                                             mcan_handle_t *handle,
+                                             mcan_fifo_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt driven message send process.
+ *
+ * This function aborts the interrupt driven message send process.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param bufferIdx The MCAN Buffer index.
+ */
+void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx);
+
+/*!
+ * @brief Aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * This function aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * @param base MCAN peripheral base address.
+ * @param fifoBlock MCAN Fifo block, 0 or 1.
+ * @param handle MCAN handle pointer.
+ */
+void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle);
+
+/*!
+ * @brief MCAN IRQ handle function.
+ *
+ * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ */
+void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MCAN_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mrt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Multi-Rate timer peripheral base address
+ *
+ * @return The MRT instance
+ */
+static uint32_t MRT_GetInstance(MRT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to MRT bases for each instance. */
+static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to MRT clocks for each instance. */
+static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to MRT resets for each instance. */
+static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t MRT_GetInstance(MRT_Type *base)
+{
+    uint32_t instance;
+    uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < mrtArrayCount; instance++)
+    {
+        if (s_mrtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < mrtArrayCount);
+
+    return instance;
+}
+
+void MRT_Init(MRT_Type *base, const mrt_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the MRT clock */
+    CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+
+    /* Set timer operating mode */
+    base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
+}
+
+void MRT_Deinit(MRT_Type *base)
+{
+    /* Stop all the timers */
+    MRT_StopTimer(base, kMRT_Channel_0);
+    MRT_StopTimer(base, kMRT_Channel_1);
+    MRT_StopTimer(base, kMRT_Channel_2);
+    MRT_StopTimer(base, kMRT_Channel_3);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the MRT clock*/
+    CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
+{
+    uint32_t newValue = count;
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
+    {
+        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
+        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
+    }
+
+    /* Update the timer interval value */
+    base->CHANNEL[channel].INTVAL = newValue;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MRT_H_
+#define _FSL_MRT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mrt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of MRT channels */
+typedef enum _mrt_chnl
+{
+    kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
+    kMRT_Channel_1,      /*!< MRT channel number 1 */
+    kMRT_Channel_2,      /*!< MRT channel number 2 */
+    kMRT_Channel_3       /*!< MRT channel number 3 */
+} mrt_chnl_t;
+
+/*! @brief List of MRT timer modes */
+typedef enum _mrt_timer_mode
+{
+    kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT),      /*!< Repeat Interrupt mode */
+    kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT),     /*!< One-shot Interrupt mode */
+    kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
+} mrt_timer_mode_t;
+
+/*! @brief List of MRT interrupts */
+typedef enum _mrt_interrupt_enable
+{
+    kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
+} mrt_interrupt_enable_t;
+
+/*! @brief List of MRT status flags */
+typedef enum _mrt_status_flags
+{
+    kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
+    kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK,           /*!< Indicates state of the timer */
+} mrt_status_flags_t;
+
+/*!
+ * @brief MRT configuration structure
+ *
+ * This structure holds the configuration settings for the MRT peripheral. To initialize this
+ * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _mrt_config
+{
+    bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
+} mrt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the MRT clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the MRT driver.
+ *
+ * @param base   Multi-Rate timer peripheral base address
+ * @param config Pointer to user's MRT config structure
+ */
+void MRT_Init(MRT_Type *base, const mrt_config_t *config);
+
+/*!
+ * @brief Gate the MRT clock
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+void MRT_Deinit(MRT_Type *base);
+
+/*!
+ * @brief Fill in the MRT config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->enableMultiTask = false;
+ * @endcode
+ * @param config Pointer to user's MRT config structure.
+ */
+static inline void MRT_GetDefaultConfig(mrt_config_t *config)
+{
+    assert(config);
+
+    /* Use hardware status operating mode */
+    config->enableMultiTask = false;
+}
+
+/*!
+ * @brief Sets up an MRT channel mode.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Channel that is being configured.
+ * @param mode    Timer mode to use for the channel.
+ */
+static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
+{
+    uint32_t reg = base->CHANNEL[channel].CTRL;
+
+    /* Clear old value */
+    reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
+    /* Add the new mode */
+    reg |= mode;
+
+    base->CHANNEL[channel].CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to enable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL |= mask;
+}
+
+/*!
+ * @brief Disables the selected MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to disable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled MRT interrupts.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::mrt_interrupt_enable_t
+ */
+static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the MRT status flags
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::mrt_status_flags_t
+ */
+static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
+}
+
+/*!
+ * @brief Clears the MRT status flags.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::mrt_status_flags_t
+ */
+static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Used to update the timer period in units of count.
+ *
+ * The new value will be immediately loaded or will be loaded at the end of the current time
+ * interval. For one-shot interrupt mode the new value will be immediately loaded.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base          Multi-Rate timer peripheral base address
+ * @param channel       Timer channel number
+ * @param count         Timer period in units of ticks
+ * @param immediateLoad true: Load the new value immediately into the TIMER register;
+ *                      false: Load the new value at the end of current timer interval
+ */
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return Current timer counting value in ticks
+ */
+static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
+{
+    return base->CHANNEL[channel].TIMER;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, counts down to 0 and
+ * depending on the timer mode it will either load the respective start value again or stop.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ * @param count   Timer period in units of ticks
+ */
+static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
+{
+    /* Write the timer interval value */
+    base->CHANNEL[channel].INTVAL = count;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops the timer from counting.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
+{
+    /* Stop the timer immediately */
+    base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @name Get & release channel
+ * @{
+ */
+
+/*!
+ * @brief Find the available channel.
+ *
+ * This function returns the lowest available channel number.
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
+{
+    return base->IDLE_CH;
+}
+
+/*!
+ * @brief Release the channel when the timer is using the multi-task mode.
+ *
+ * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
+ * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
+ * long as it is needed and release it by calling this function. This removes the need to ask for
+ * an available channel for every use.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
+{
+    uint32_t reg = base->CHANNEL[channel].STAT;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
+    reg |= MRT_CHANNEL_STAT_INUSE_MASK;
+
+    base->CHANNEL[channel].STAT = reg;
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MRT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_OTP_H_
+#define _FSL_OTP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup otp
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief OTP driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version.
+ */
+#define FSL_OTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Bank bit flags. */
+typedef enum _otp_bank
+{
+    kOTP_Bank0 = 0x1U, /*!< Bank 0. */
+    kOTP_Bank1 = 0x2U, /*!< Bank 1. */
+    kOTP_Bank2 = 0x4U, /*!< Bank 2. */
+    kOTP_Bank3 = 0x8U  /*!< Bank 3. */
+} otp_bank_t;
+
+/*! @brief Bank word bit flags. */
+typedef enum _otp_word
+{
+    kOTP_Word0 = 0x1U, /*!< Word 0. */
+    kOTP_Word1 = 0x2U, /*!< Word 1. */
+    kOTP_Word2 = 0x4U, /*!< Word 2. */
+    kOTP_Word3 = 0x8U  /*!< Word 3. */
+} otp_word_t;
+
+/*! @brief Lock modifications of a read or write access to a bank register. */
+typedef enum _otp_lock
+{
+    kOTP_LockDontLock = 0U, /*!< Do not lock. */
+    kOTP_LockLock = 1U      /*!< Lock till reset. */
+} otp_lock_t;
+
+/*! @brief OTP error codes. */
+enum _otp_status
+{
+    kStatus_OTP_WrEnableInvalid = MAKE_STATUS(kStatusGroup_OTP, 0x1U),           /*!< Write enable invalid. */
+    kStatus_OTP_SomeBitsAlreadyProgrammed = MAKE_STATUS(kStatusGroup_OTP, 0x2U), /*!< Some bits already programmed. */
+    kStatus_OTP_AllDataOrMaskZero = MAKE_STATUS(kStatusGroup_OTP, 0x3U),         /*!< All data or mask zero. */
+    kStatus_OTP_WriteAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0x4U),         /*!< Write access locked. */
+    kStatus_OTP_ReadDataMismatch = MAKE_STATUS(kStatusGroup_OTP, 0x5U),          /*!< Read data mismatch. */
+    kStatus_OTP_UsbIdEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x6U),              /*!< USB ID enabled. */
+    kStatus_OTP_EthMacEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x7U),             /*!< Ethernet MAC enabled. */
+    kStatus_OTP_AesKeysEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x8U),            /*!< AES keys enabled. */
+    kStatus_OTP_IllegalBank = MAKE_STATUS(kStatusGroup_OTP, 0x9U),               /*!< Illegal bank. */
+    kStatus_OTP_ShufflerConfigNotValid = MAKE_STATUS(kStatusGroup_OTP, 0xAU),    /*!< Shuffler config not valid. */
+    kStatus_OTP_ShufflerNotEnabled = MAKE_STATUS(kStatusGroup_OTP, 0xBU),        /*!< Shuffler not enabled. */
+    kStatus_OTP_ShufflerCanOnlyProgSingleKey =
+        MAKE_STATUS(kStatusGroup_OTP, 0xBU),                              /*!< Shuffler can only program single key. */
+    kStatus_OTP_IllegalProgramData = MAKE_STATUS(kStatusGroup_OTP, 0xCU), /*!< Illegal program data. */
+    kStatus_OTP_ReadAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0xDU),   /*!< Read access locked. */
+};
+
+#define _OTP_ERR_BASE (0x70000U)
+#define _OTP_MAKE_STATUS(errorCode) \
+    ((errorCode == 0U) ? kStatus_Success : MAKE_STATUS(kStatusGroup_OTP, ((errorCode)-_OTP_ERR_BASE)))
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes OTP controller.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_Init(void)
+{
+    uint32_t status = OTP_API->otpInit();
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Unlock one or more OTP banks for write access.
+ *
+ * @param bankMask bit flag that specifies which banks to unlock.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankWriteMask(otp_bank_t bankMask)
+{
+    uint32_t status = OTP_API->otpEnableBankWriteMask(bankMask);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Lock one or more OTP banks for write access.
+ *
+ * @param bankMask bit flag that specifies which banks to lock.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_DisableBankWriteMask(otp_bank_t bankMask)
+{
+    uint32_t status = OTP_API->otpDisableBankWriteMask(bankMask);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Locks or unlocks write access to a register of an OTP bank and possibly lock un/locking of it.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regEnableMask bit flag that specifies for which words to enable writing.
+ * @param regDisableMask bit flag that specifies for which words to disable writing.
+ * @param lockWrite specifies if access set can be modified or is locked till reset.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankWriteLock(uint32_t bankIndex,
+                                               otp_word_t regEnableMask,
+                                               otp_word_t regDisableMask,
+                                               otp_lock_t lockWrite)
+{
+    uint32_t status = OTP_API->otpEnableBankWriteLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Locks or unlocks read access to a register of an OTP bank and possibly lock un/locking of it.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regEnableMask bit flag that specifies for which words to enable reading.
+ * @param regDisableMask bit flag that specifies for which words to disable reading.
+ * @param lockWrite specifies if access set can be modified or is locked till reset.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankReadLock(uint32_t bankIndex,
+                                              otp_word_t regEnableMask,
+                                              otp_word_t regDisableMask,
+                                              otp_lock_t lockWrite)
+{
+    uint32_t status = OTP_API->otpEnableBankReadLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Program a single register in an OTP bank.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regIndex OTP register index.
+ * @param value value to write.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_ProgramRegister(uint32_t bankIndex, uint32_t regIndex, uint32_t value)
+{
+    uint32_t status = OTP_API->otpProgramReg(bankIndex, regIndex, value);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Returns the version of the OTP driver in ROM.
+ *
+ * @return version.
+ */
+static inline uint32_t OTP_GetDriverVersion(void)
+{
+    return OTP_API->otpGetDriverVersion();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_OTP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Irq number array */
+static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
+
+/*! @brief Callback function array for PINT(s). */
+static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void PINT_Init(PINT_Type *base)
+{
+    uint32_t i;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    pmcfg = 0;
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Disable all bit slices */
+    for (i = 0; i < PINT_PIN_INT_COUNT; i++)
+    {
+        pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
+    }
+
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Pint);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable all pattern match bit slices */
+    base->PMCFG = pmcfg;
+}
+
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
+{
+    assert(base);
+
+    /* Clear Rise and Fall flags first */
+    PINT_PinInterruptClrRiseFlag(base, intr);
+    PINT_PinInterruptClrFallFlag(base, intr);
+
+    /* select level or edge sensitive */
+    base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
+
+    /* enable rising or level interrupt */
+    if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
+    {
+        base->SIENR = 1U << intr;
+    }
+    else
+    {
+        base->CIENR = 1U << intr;
+    }
+
+    /* Enable falling or select high level */
+    if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+    {
+        base->SIENF = 1U << intr;
+    }
+    else
+    {
+        base->CIENF = 1U << intr;
+    }
+
+    s_pintCallback[intr] = callback;
+}
+
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
+{
+    uint32_t mask;
+    bool level;
+
+    assert(base);
+
+    *enable = kPINT_PinIntEnableNone;
+    level = false;
+
+    mask = 1U << pintr;
+    if (base->ISEL & mask)
+    {
+        /* Pin interrupt is level sensitive */
+        level = true;
+    }
+
+    if (base->IENR & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is enabled */
+            *enable = kPINT_PinIntEnableLowLevel;
+        }
+        else
+        {
+            /* Rising edge interrupt */
+            *enable = kPINT_PinIntEnableRiseEdge;
+        }
+    }
+
+    if (base->IENF & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is active high */
+            *enable = kPINT_PinIntEnableHighLevel;
+        }
+        else
+        {
+            /* Either falling or both edge */
+            if (*enable == kPINT_PinIntEnableRiseEdge)
+            {
+                /* Rising and faling edge */
+                *enable = kPINT_PinIntEnableBothEdges;
+            }
+            else
+            {
+                /* Falling edge */
+                *enable = kPINT_PinIntEnableFallEdge;
+            }
+        }
+    }
+
+    *callback = s_pintCallback[pintr];
+}
+
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    /* Input source selection for selected bit slice */
+    base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
+
+    /* Bit slice configuration */
+    pmcfg = base->PMCFG;
+    pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
+
+    /* If end point is true, enable the bits */
+    if (bslice != 7U)
+    {
+        if (cfg->end_point)
+        {
+            pmcfg |= (0x1U << bslice);
+        }
+        else
+        {
+            pmcfg &= ~(0x1U << bslice);
+        }
+    }
+
+    base->PMCFG = pmcfg;
+
+    /* Save callback pointer */
+    s_pintCallback[bslice] = cfg->callback;
+}
+
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
+    cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
+
+    if (bslice == 7U)
+    {
+        cfg->end_point = true;
+    }
+    else
+    {
+        cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
+    }
+    cfg->callback = s_pintCallback[bslice];
+}
+
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
+{
+    uint32_t pmctrl;
+    uint32_t pmstatus;
+    uint32_t pmsrc;
+
+    pmctrl = PINT->PMCTRL;
+    pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
+    if (pmstatus)
+    {
+        /* Reset Pattern match engine detection logic */
+        pmsrc = base->PMSRC;
+        base->PMSRC = pmsrc;
+    }
+    return (pmstatus);
+}
+
+void PINT_EnableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    PINT_PinInterruptClrStatusAll(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        EnableIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_DisableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        DisableIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_Deinit(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    /* Cleanup */
+    PINT_DisableCallback(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(kCLOCK_Pint);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+void PIN_INT0_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt0] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
+    }
+}
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+void PIN_INT1_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt1] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+void PIN_INT2_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt2] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+void PIN_INT3_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt3] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+void PIN_INT4_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt4] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+void PIN_INT5_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt5] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+void PIN_INT6_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt6] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+void PIN_INT7_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt7] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_PINT_H_
+#define _FSL_PINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/* Number of interrupt line supported by PINT */
+#define PINT_PIN_INT_COUNT 8U
+
+/* Number of input sources supported by PINT */
+#define PINT_INPUT_COUNT 8U
+
+/* PININT Bit slice source register bits */
+#define PININT_BITSLICE_SRC_START 8U
+#define PININT_BITSLICE_SRC_MASK 7U
+
+/* PININT Bit slice configuration register bits */
+#define PININT_BITSLICE_CFG_START 8U
+#define PININT_BITSLICE_CFG_MASK 7U
+#define PININT_BITSLICE_ENDP_MASK 7U
+
+#define PINT_PIN_INT_LEVEL 0x10U
+#define PINT_PIN_INT_EDGE 0x00U
+#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U
+#define PINT_PIN_INT_RISE 0x01U
+#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE)
+#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL)
+#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+
+/*! @brief PINT Pin Interrupt enable type */
+typedef enum _pint_pin_enable
+{
+    kPINT_PinIntEnableNone = 0U,                      /*!< Do not generate Pin Interrupt */
+    kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE,  /*!< Generate Pin Interrupt on rising edge */
+    kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE,  /*!< Generate Pin Interrupt on falling edge */
+    kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */
+    kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL,  /*!< Generate Pin Interrupt on low level */
+    kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */
+} pint_pin_enable_t;
+
+/*! @brief PINT Pin Interrupt type */
+typedef enum _pint_int
+{
+    kPINT_PinInt0 = 0U, /*!< Pin Interrupt  0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PinInt1 = 1U, /*!< Pin Interrupt  1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PinInt2 = 2U, /*!< Pin Interrupt  2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PinInt3 = 3U, /*!< Pin Interrupt  3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PinInt4 = 4U, /*!< Pin Interrupt  4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PinInt5 = 5U, /*!< Pin Interrupt  5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PinInt6 = 6U, /*!< Pin Interrupt  6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PinInt7 = 7U, /*!< Pin Interrupt  7 */
+#endif
+} pint_pin_int_t;
+
+/*! @brief PINT Pattern Match bit slice input source type */
+typedef enum _pint_pmatch_input_src
+{
+    kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */
+    kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */
+    kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */
+    kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */
+    kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */
+    kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */
+    kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */
+    kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */
+} pint_pmatch_input_src_t;
+
+/*! @brief PINT Pattern Match bit slice type */
+typedef enum _pint_pmatch_bslice
+{
+    kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
+#endif
+} pint_pmatch_bslice_t;
+
+/*! @brief PINT Pattern Match configuration type */
+typedef enum _pint_pmatch_bslice_cfg
+{
+    kPINT_PatternMatchAlways = 0U,          /*!< Always Contributes to product term match */
+    kPINT_PatternMatchStickyRise = 1U,      /*!< Sticky Rising edge */
+    kPINT_PatternMatchStickyFall = 2U,      /*!< Sticky Falling edge */
+    kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */
+    kPINT_PatternMatchHigh = 4U,            /*!< High level */
+    kPINT_PatternMatchLow = 5U,             /*!< Low level */
+    kPINT_PatternMatchNever = 6U,           /*!< Never contributes to product term match */
+    kPINT_PatternMatchBothEdges = 7U,       /*!< Either rising or falling edge */
+} pint_pmatch_bslice_cfg_t;
+
+/*! @brief PINT Callback function. */
+typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status);
+
+typedef struct _pint_pmatch_cfg
+{
+    pint_pmatch_input_src_t bs_src;
+    pint_pmatch_bslice_cfg_t bs_cfg;
+    bool end_point;
+    pint_cb_t callback;
+} pint_pmatch_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize PINT peripheral.
+
+ * This function initializes the PINT peripheral and enables the clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Init(PINT_Type *base);
+
+/*!
+ * @brief	Configure PINT peripheral pin interrupt.
+
+ * This function configures a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param intr Pin interrupt.
+ * @param enable Selects detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback);
+
+/*!
+ * @brief	Get PINT peripheral pin interrupt configuration.
+
+ * This function returns the configuration of a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ * @param enable Pointer to store the detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback);
+
+/*!
+ * @brief	Clear Selected pin interrupt status.
+
+ * This function clears the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->IST = (1U << pintr);
+}
+
+/*!
+ * @brief	Get Selected pin interrupt status.
+
+ * This function returns the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval status = 0 No pin interrupt request.  = 1 Selected Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->IST & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupts status.
+
+ * This function clears the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base)
+{
+    base->IST = PINT_IST_PSTAT_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupts status.
+
+ * This function returns the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the status of corresponding pin interrupt.
+ * = 0 No pin interrupt request. = 1 Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base)
+{
+    return (base->IST);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt fall flag.
+
+ * This function clears the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->FALL = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt fall flag.
+
+ * This function returns the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->FALL & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt fall flags.
+
+ * This function clears the fall flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base)
+{
+    base->FALL = PINT_FALL_FDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt fall flags.
+
+ * This function returns the fall flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt.
+ * 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base)
+{
+    return (base->FALL);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt rise flag.
+
+ * This function clears the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->RISE = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt rise flag.
+
+ * This function returns the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->RISE & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt rise flags.
+
+ * This function clears the rise flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base)
+{
+    base->RISE = PINT_RISE_RDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt rise flags.
+
+ * This function returns the rise flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt.
+ * 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base)
+{
+    return (base->RISE);
+}
+
+/*!
+ * @brief	Configure PINT pattern match.
+
+ * This function configures a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get PINT pattern match configuration.
+
+ * This function returns the configuration of a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get pattern match bit slice status.
+
+ * This function returns the status of selected bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ *
+ * @retval status = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice)
+{
+    return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice;
+}
+
+/*!
+ * @brief	Get status of all pattern match bit slices.
+
+ * This function returns the status of all bit slices.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base)
+{
+    return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT;
+}
+
+/*!
+ * @brief	Reset pattern match detection logic.
+
+ * This function resets the pattern match detection logic if any of the product term is matching.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval pmstatus Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match was detected.  = 1 Match was not detected.
+ */
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base);
+
+/*!
+ * @brief	Enable pattern match function.
+
+ * This function enables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Disable pattern match function.
+
+ * This function disables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Enable RXEV output.
+
+ * This function enables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Disable RXEV output.
+
+ * This function disables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_EnableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void PINT_DisableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Deinitialize PINT peripheral.
+
+ * This function disables the PINT clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Deinit(PINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_PINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+    kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
+    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+    kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
+    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+    kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
+    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+    kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
+    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+    kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
+    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+    kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
+    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+    kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
+    kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
+    kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
+    kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
+    kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
+    kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
+
+    kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
+    kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
+    kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
+    kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
+    kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
+    kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
+
+    kPDRUNCFG_ForceUnsigned = 0x80000000U,
+} pd_bit_t;
+
+/* Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+    kPmu_Sleep = 0U,
+    kPmu_Deep_Sleep = 1U,
+    kPmu_Deep_PowerDown = 2U,
+} power_mode_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to power down flash controller.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_PowerDownFlash(void)
+{
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_DisableClock(kCLOCK_Flash);
+
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_DisableClock(kCLOCK_Fmc);
+}
+
+/*!
+ * @brief API to power up flash controller.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_PowerUpFlash(void)
+{
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_EnableClock(kCLOCK_Fmc);
+}
+
+/*!
+ * @brief Power Library API to power the PLLs.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetPLL(void);
+
+/*!
+ * @brief Power Library API to power the USB PHY.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetUsbPhy(void);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during power mode selected.
+ * @return none
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter sleep mode.
+ *
+ * @return none
+ */
+void POWER_EnterSleep(void);
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd   Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during deep power 
+ *                          down mode, but this is has no effect as the voltages are cut off.
+ 
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate, 
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSL_POWER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kFLASH_RST_SHIFT_RSTn = 0 | 7U,          /**< Flash controller reset control */
+    kFMC_RST_SHIFT_RSTn = 0 | 8U,            /**< Flash accelerator reset control */
+    kEEPROM_RST_SHIFT_RSTn = 0 | 9U,         /**< EEPROM reset control */
+    kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
+    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
+    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
+    kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
+    kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
+    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
+    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
+    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
+    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
+    
+    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
+    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
+    kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
+    kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
+    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
+    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
+    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
+    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
+    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
+    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
+    kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
+    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
+    
+    kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
+    kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
+    kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
+    kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */    
+    kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
+    kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
+    kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
+    kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */ 
+    kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
+    kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
+    kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
+    kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */ 
+    kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
+    kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
+    kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
+    kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
+    kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
+    kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
+    kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
+    
+    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define AES_RSTS             \
+    {                        \
+        kAES_RST_SHIFT_RSTn  \
+    } /* Reset bits for AES peripheral */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS                                                                                     \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for CTIMER peripheral */
+#define DMA_RSTS            \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for DMIC peripheral */
+#define EMC_RSTS             \
+    {                        \
+        kEMC_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define ETH_RST              \
+    {                        \
+        kETH_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn                                       \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS                                  \
+    {                                              \
+        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS                                    \
+    {                                                \
+        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
+        kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS                                 \
+    {                                              \
+        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+    } /* Reset bits for Flash peripheral */
+#define LCD_RSTS                                 \
+    {                                            \
+        kLCD_RST_SHIFT_RSTn                      \
+    } /* Reset bits for LCD peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define MCAN_RSTS                                   \
+    {                                               \
+        kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
+    } /* Reset bits for MCAN0&MACN1 peripheral */
+#define OTP_RSTS            \
+    {                       \
+        kOTP_RST_SHIFT_RSTn \
+    } /* Reset bits for OTP peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define RNG_RSTS             \
+    {                        \
+        kRNG_RST_SHIFT_RSTn  \
+    } /* Reset bits for RNG peripheral */
+#define SDIO_RST             \
+    {                        \
+        kSDIO_RST_SHIFT_RSTn \
+    } /* Reset bits for SDIO peripheral */
+#define SCT_RSTS             \
+    {                        \
+        kSCT0_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define SHA_RST              \
+    {                        \
+        kSHA_RST_SHIFT_RSTn  \
+    } /* Reset bits for SHA peripheral */
+#define USB0D_RST             \
+    {                         \
+        kUSB0D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0D peripheral */
+#define USB0HMR_RST             \
+    {                           \
+        kUSB0HMR_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HMR peripheral */
+#define USB0HSL_RST             \
+    {                           \
+        kUSB0HSL_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HSL peripheral */
+#define USB1H_RST             \
+    {                         \
+        kUSB1H_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1H peripheral */
+#define USB1D_RST             \
+    {                         \
+        kUSB1D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1D peripheral */
+#define USB1RAM_RST             \
+    {                           \
+        kUSB1RAM_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1RAM peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rit.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base RIT peripheral base address
+ *
+ * @return The RIT instance
+ */
+static uint32_t RIT_GetInstance(RIT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to RIT bases for each instance. */
+static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to PIT clocks for each instance. */
+static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t RIT_GetInstance(RIT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++)
+    {
+        if (s_ritBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_ritBases));
+
+    return instance;
+}
+
+void RIT_GetDefaultConfig(rit_config_t *config)
+{
+    assert(config);
+    /* Timer operation are no effect in Debug mode */
+    config->enableRunInDebug = false;
+}
+
+void RIT_Init(RIT_Type *base, const rit_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the RIT clock*/
+    CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Enable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+
+    /* Config timer operation is no effect in debug mode */
+    if (!config->enableRunInDebug)
+    {
+        base->CTRL &= ~RIT_CTRL_RITENBR_MASK;
+    }
+    else
+    {
+        base->CTRL |= RIT_CTRL_RITENBR_MASK;
+    }
+}
+
+void RIT_Deinit(RIT_Type *base)
+{
+    /* Disable RIT timers */
+    base->CTRL |= ~RIT_CTRL_RITEN_MASK;
+#ifdef FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+    /* Gate the RIT clock*/
+    CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void RIT_SetTimerCompare(RIT_Type *base, uint64_t count)
+{
+    /* Disable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+    base->COMPVAL = (uint32_t)count;
+    base->COMPVAL_H = (uint16_t)(count >> 32U);
+}
+
+void RIT_SetMaskBit(RIT_Type *base, uint64_t count)
+{
+    base->MASK = (uint32_t)count;
+    base->MASK_H = (uint16_t)(count >> 32U);
+}
+
+uint64_t RIT_GetCompareTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* COMPVAL_H should be read before COMPVAL */
+    valueH = base->COMPVAL_H;
+    valueL = base->COMPVAL;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+uint64_t RIT_GetCounterTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* COUNTER_H should be read before COUNTER */
+    valueH = base->COUNTER_H;
+    valueL = base->COUNTER;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+uint64_t RIT_GetMaskTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* MASK_H should be read before MASK */
+    valueH = base->MASK_H;
+    valueL = base->MASK;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RIT_H_
+#define _FSL_RIT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rit
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RIT status flags */
+typedef enum _rit_status_flags
+{
+    kRIT_TimerFlag = RIT_CTRL_RITINT_MASK, /*!< Timer flag */
+} rit_status_flags_t;
+
+/*!
+ * @brief RIT config structure
+ *
+ * This structure holds the configuration settings for the RIT peripheral. To initialize this
+ * structure to reasonable defaults, call the RIT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rit_config
+{
+    bool enableRunInDebug; /*!< true: The timer is halted when the processor is halted for debugging.; false: Debug has
+                              no effect on the timer operation. */
+} rit_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations.
+ *
+ * @note This API should be called at the beginning of the application using the RIT driver.
+ *
+ * @param base   RIT peripheral base address
+ * @param config Pointer to the user's RIT config structure
+ */
+void RIT_Init(RIT_Type *base, const rit_config_t *config);
+
+/*!
+ * @brief Gates the RIT clock and disables the RIT module.
+ *
+ * @param base RIT peripheral base address
+ */
+void RIT_Deinit(RIT_Type *base);
+
+/*!
+ * @brief Fills in the RIT configuration structure with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ *     config->enableRunInDebug = false;
+ * @endcode
+ * @param config Pointer to the onfiguration structure.
+ */
+void RIT_GetDefaultConfig(rit_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RIT status flags.
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rit_status_flags_t
+ */
+static inline uint32_t RIT_GetStatusFlags(RIT_Type *base)
+{
+    return (base->CTRL);
+}
+
+/*!
+ * @brief  Clears the RIT status flags.
+ *
+ * @param base    RIT peripheral base address
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::rit_status_flags_t
+ */
+static inline void RIT_ClearStatusFlags(RIT_Type *base, uint32_t mask)
+{
+    base->CTRL |= mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function until it XXXXXXX,
+ * then it counting the value again.
+ * Software must stop the counter before reloading it with a new value..
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    RIT peripheral base address
+ * @param count   Timer period in units of ticks
+ */
+void RIT_SetTimerCompare(RIT_Type *base, uint64_t count);
+
+/*!
+ * @brief Sets the mask bit of count compare.
+ *
+ * Timers begin counting from the value set by this function until it XXXXXXX,
+ * then it counting the value again.
+ * Software must stop the counter before reloading it with a new value..
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    RIT peripheral base address
+ * @param count   Timer period in units of ticks
+ */
+void RIT_SetMaskBit(RIT_Type *base, uint64_t count);
+
+/*!
+ * @brief Reads the current timer counting value of compare register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetCompareTimerCount(RIT_Type *base);
+
+/*!
+ * @brief Reads the current timer counting value of counter register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetCounterTimerCount(RIT_Type *base);
+
+/*!
+ * @brief Reads the current timer counting value of mask register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetMaskTimerCount(RIT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load initial value(0U), count up to desired value or over-flow
+ * then the counter will count up again. Each time a timer reaches desired value,
+ * it generates a XXXXXXX and sets XXXXXXX.
+ *
+ * @param base    RIT peripheral base address
+ */
+static inline void RIT_StartTimer(RIT_Type *base)
+{
+    base->CTRL |= RIT_CTRL_RITEN_MASK;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stop timer counting. Timer reload their new value
+ * after the next time they call the RIT_StartTimer.
+ *
+ * @param base    RIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void RIT_StopTimer(RIT_Type *base)
+{
+    /* Disable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+}
+
+/*! @}*/
+
+static inline void RIT_ClearCounter(RIT_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= RIT_CTRL_RITENCLR_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~RIT_CTRL_RITENCLR_MASK;
+    }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RIT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RNG_DRIVER_H_
+#define _FSL_RNG_DRIVER_H_
+
+#include "fsl_common.h"
+
+#if defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && FSL_FEATURE_SOC_LPC_RNG_COUNT
+
+/*!
+ * @addtogroup rng
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RNG driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version.
+ */
+#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function returns single 32 bit random number.
+ *
+ * @return random data
+ */
+static inline uint32_t RNG_GetRandomData(void)
+{
+    return OTP_API->rngRead();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_LPC_RNG_COUNT */
+#endif /*_FSL_TRNG_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR (365U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds  Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Check year, month, hour, minute, seconds */
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+    {
+        /* If not correct then error*/
+        return false;
+    }
+
+    /* Adjust the days in February for a leap year */
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /* Check the validity of the day */
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
+    {
+        return false;
+    }
+
+    return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
+    /* Number of days from begin of the non Leap-year*/
+    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+    uint32_t seconds;
+
+    /* Compute number of days from 1970 till given year*/
+    seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    seconds += ((datetime->year / 4) - (1970U / 4));
+    /* Add number of days till given month*/
+    seconds += monthDays[datetime->month];
+    /* Add days in given month. We subtract the current day as it is
+     * represented in the hours, minutes and seconds field*/
+    seconds += (datetime->day - 1);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        seconds--;
+    }
+
+    seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+              (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+    return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t x;
+    uint32_t secondsRemaining, days;
+    uint16_t daysInYear;
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Start with the seconds value that is passed in to be converted to date time format */
+    secondsRemaining = seconds;
+
+    /* Calcuate the number of days, we add 1 for the current day which is represented in the
+     * hours and seconds field
+     */
+    days = secondsRemaining / SECONDS_IN_A_DAY + 1;
+
+    /* Update seconds left*/
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+    /* Calculate the datetime hour, minute and second fields */
+    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+    datetime->minute = secondsRemaining / 60U;
+    datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
+
+    /* Calculate year */
+    daysInYear = DAYS_IN_A_YEAR;
+    datetime->year = YEAR_RANGE_START;
+    while (days > daysInYear)
+    {
+        /* Decrease day count by a year and increment year by 1 */
+        days -= daysInYear;
+        datetime->year++;
+
+        /* Adjust the number of days for a leap year */
+        if (datetime->year & 3U)
+        {
+            daysInYear = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            daysInYear = DAYS_IN_A_YEAR + 1;
+        }
+    }
+
+    /* Adjust the days in February for a leap year */
+    if (!(datetime->year & 3U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (days <= daysPerMonth[x])
+        {
+            datetime->month = x;
+            break;
+        }
+        else
+        {
+            days -= daysPerMonth[x];
+        }
+    }
+
+    datetime->day = days;
+}
+
+void RTC_Init(RTC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the RTC peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Make sure the reset bit is cleared */
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+
+    /* Make sure the RTC OSC is powered up */
+    base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
+}
+
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(datetime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set time in seconds */
+    base->COUNT = RTC_ConvertDatetimeToSeconds(datetime);
+
+    return kStatus_Success;
+}
+
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t seconds = 0;
+
+    seconds = base->COUNT;
+    RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+    assert(alarmTime);
+
+    uint32_t alarmSeconds = 0;
+    uint32_t currSeconds = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(alarmTime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+    /* Get the current time */
+    currSeconds = base->COUNT;
+
+    /* Return error if the alarm time has passed */
+    if (alarmSeconds < currSeconds)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set alarm in seconds*/
+    base->MATCH = alarmSeconds;
+
+    return kStatus_Success;
+}
+
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t alarmSeconds = 0;
+
+    /* Get alarm in seconds  */
+    alarmSeconds = base->MATCH;
+
+    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+    kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/
+    kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK  /*!< Wake-up interrupt.*/
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+    kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/
+    kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/
+} rtc_status_flags_t;
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+    uint16_t year;  /*!< Range from 1970 to 2099.*/
+    uint8_t month;  /*!< Range from 1 to 12.*/
+    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
+    uint8_t hour;   /*!< Range from 0 to 23.*/
+    uint8_t minute; /*!< Range from 0 to 59.*/
+    uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and enables the RTC oscillator.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_Init(RTC_Type *base);
+
+/*!
+ * @brief Stop the timer and gate the RTC clock
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+    /* Stop the RTC timer */
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the module clock */
+    CLOCK_DisableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function as writes to the RTC
+ * seconds register will fail if the RTC counter is running.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details to set are stored
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base      RTC peripheral base address
+ * @param alarmTime Pointer to structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @brief Enable the RTC high resolution timer and set the wake-up time.
+ *
+ * @param base        RTC peripheral base address
+ * @param wakeupValue The value to be loaded into the RTC WAKE register
+ */
+static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue)
+{
+    /* Enable the 1kHz RTC timer */
+    base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK;
+
+    /* Set the start count value into the wake-up timer */
+    base->WAKE = wakeupValue;
+}
+
+/*!
+ * @brief Read actual RTC counter value.
+ *
+ * @param base        RTC peripheral base address
+ */
+static inline uint16_t RTC_GetWakeupCount(RTC_Type *base)
+{
+    /* Read wake-up counter */
+    return RTC_WAKE_VAL(base->WAKE);
+}
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask);
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK));
+}
+
+/*!
+ * @brief  Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+
+    /* Write 1 to the flags we wish to clear */
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_RTC_EN_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_SWRESET_MASK;
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sctimer.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Typedef for interrupt handler. */
+typedef void (*sctimer_isr_t)(SCT_Type *base);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The SCTimer instance
+ */
+static uint32_t SCTIMER_GetInstance(SCT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to SCT bases for each instance. */
+static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to SCT clocks for each instance. */
+static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to SCT resets for each instance. */
+static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
+
+/*!< @brief SCTimer event Callback function. */
+static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
+
+/*!< @brief Keep track of SCTimer event number */
+static uint32_t s_currentEvent;
+
+/*!< @brief Keep track of SCTimer state number */
+static uint32_t s_currentState;
+
+/*!< @brief Keep track of SCTimer match/capture register number */
+static uint32_t s_currentMatch;
+
+/*! @brief Pointer to SCTimer IRQ handler */
+static sctimer_isr_t s_sctimerIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SCTIMER_GetInstance(SCT_Type *base)
+{
+    uint32_t instance;
+    uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < sctArrayCount; instance++)
+    {
+        if (s_sctBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < sctArrayCount);
+
+    return instance;
+}
+
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
+{
+    assert(config);
+    uint32_t i;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SCTimer clock*/
+    CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
+
+    /* Setup the counter operation */
+    base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
+                   SCT_CONFIG_UNIFY(config->enableCounterUnify);
+
+    /* Write to the control register, clear the counter and keep the counters halted */
+    base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
+                 SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
+
+    if (!(config->enableCounterUnify))
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
+                      SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
+    }
+
+    /* Initial state of channel output */
+    base->OUTPUT = config->outInitState;
+
+    /* Clear the global variables */
+    s_currentEvent = 0;
+    s_currentState = 0;
+    s_currentMatch = 0;
+
+    /* Clear the callback array */
+    for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
+    {
+        s_eventCallback[i] = NULL;
+    }
+
+    /* Save interrupt handler */
+    s_sctimerIsr = SCTIMER_EventHandleIRQ;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_Deinit(SCT_Type *base)
+{
+    /* Halt the counters */
+    base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the SCTimer clock*/
+    CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
+{
+    assert(config);
+
+    /* SCT operates as a unified 32-bit counter */
+    config->enableCounterUnify = true;
+    /* System clock clocks the entire SCT module */
+    config->clockMode = kSCTIMER_System_ClockMode;
+    /* This is used only by certain clock modes */
+    config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+    /* Up count mode only for the unified counter */
+    config->enableBidirection_l = false;
+    /* Up count mode only for Counte_H */
+    config->enableBidirection_h = false;
+    /* Prescale factor of 1 */
+    config->prescale_l = 0;
+    /* Prescale factor of 1 for Counter_H*/
+    config->prescale_h = 0;
+    /* Clear outputs */
+    config->outInitState = 0;
+}
+
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event)
+{
+    assert(pwmParams);
+    assert(srcClock_Hz);
+    assert(pwmFreq_Hz);
+
+    uint32_t period, pulsePeriod = 0;
+    uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
+    uint32_t periodEvent, pulseEvent;
+    uint32_t reg;
+
+    /* This function will create 2 events, return an error if we do not have enough events available */
+    if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    if (pwmParams->dutyCyclePercent == 0)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set unify bit to operate in 32-bit counter mode */
+    base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
+
+    /* Use bi-directional mode for center-aligned PWM */
+    if (mode == kSCTIMER_CenterAlignedPwm)
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
+    }
+
+    /* Calculate PWM period match value */
+    if (mode == kSCTIMER_EdgeAlignedPwm)
+    {
+        period = (sctClock / pwmFreq_Hz) - 1;
+    }
+    else
+    {
+        period = sctClock / (pwmFreq_Hz * 2);
+    }
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (pwmParams->dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Schedule an event when we reach the PWM period */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
+
+    /* Schedule an event when we reach the pulse width */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
+
+    /* Reset the counter when we reach the PWM period */
+    SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
+
+    /* Return the period event to the user */
+    *event = periodEvent;
+
+    /* For high-true level */
+    if (pwmParams->level == kSCTIMER_HighTrue)
+    {
+        /* Set the initial output level to low which is the inactive state */
+        base->OUTPUT &= ~(1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Set the output when we reach the PWM period */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
+            /* Clear the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Clear the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+    /* For low-true level */
+    else
+    {
+        /* Set the initial output level to high which is the inactive state */
+        base->OUTPUT |= (1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Clear the output when we reach the PWM period */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
+            /* Set the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Set the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
+
+{
+    assert(dutyCyclePercent > 0);
+
+    uint32_t periodMatchReg, pulseMatchReg;
+    uint32_t pulsePeriod = 0, period;
+
+    /* Retrieve the match register number for the PWM period */
+    periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    /* Retrieve the match register number for the PWM pulse period */
+    pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    period = base->SCTMATCH[periodMatchReg];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Stop the counter before updating match register */
+    SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
+
+    /* Update dutycycle */
+    base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
+    base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
+
+    /* Restart the counter */
+    SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
+}
+
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event)
+{
+    uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
+    uint32_t currentCtrlVal = howToMonitor;
+
+    /* Return an error if we have hit the limit in terms of number of events created */
+    if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    /* IO only mode */
+    if (combMode == 0x2U)
+    {
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
+    }
+    /* Match mode only */
+    else if (combMode == 0x1U)
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+    /* Use both Match & IO */
+    else
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+
+    /* Enable the event in the current state */
+    base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
+
+    /* Return the event number */
+    *event = s_currentEvent;
+
+    /* Increment the event number */
+    s_currentEvent++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
+{
+    /* Enable event in the current state */
+    base->EVENT[event].STATE |= (1U << s_currentState);
+}
+
+status_t SCTIMER_IncreaseState(SCT_Type *base)
+{
+    /* Return an error if we have hit the limit in terms of states used */
+    if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
+    {
+        return kStatus_Fail;
+    }
+
+    s_currentState++;
+
+    return kStatus_Success;
+}
+
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
+{
+    return s_currentState;
+}
+
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    uint32_t reg;
+
+    /* Set the same event to set and clear the output */
+    base->OUT[whichIO].CLR |= (1U << event);
+    base->OUT[whichIO].SET |= (1U << event);
+
+    /* Set the conflict resolution to toggle output */
+    reg = base->RES;
+    reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
+    reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
+    base->RES = reg;
+}
+
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event)
+{
+    /* Return an error if we have hit the limit in terms of number of capture/match registers used */
+    if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        /* Set the bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
+    }
+    else
+    {
+        /* Set bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
+    }
+
+    /* Return the match register number */
+    *captureRegister = s_currentMatch;
+
+    /* Increase the match register number */
+    s_currentMatch++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
+{
+    s_eventCallback[event] = callback;
+}
+
+void SCTIMER_EventHandleIRQ(SCT_Type *base)
+{
+    uint32_t eventFlag = SCT0->EVFLAG;
+    /* Only clear the flags whose interrupt field is enabled */
+    uint32_t clearFlag = (eventFlag & SCT0->EVEN);
+    uint32_t mask = eventFlag;
+    int i = 0;
+
+    /* Invoke the callback for certain events */
+    for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
+    {
+        if (mask & 0x1)
+        {
+            if (s_eventCallback[i] != NULL)
+            {
+                s_eventCallback[i]();
+            }
+        }
+        mask >>= 1;
+    }
+
+    /* Clear event interrupt flag */
+    SCT0->EVFLAG = clearFlag;
+}
+
+void SCT0_IRQHandler(void)
+{
+    s_sctimerIsr(SCT0);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,822 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SCTIMER_H_
+#define _FSL_SCTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief SCTimer PWM operation modes */
+typedef enum _sctimer_pwm_mode
+{
+    kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
+    kSCTIMER_CenterAlignedPwm     /*!< Center-aligned PWM */
+} sctimer_pwm_mode_t;
+
+/*! @brief SCTimer counters when working as two independent 16-bit counters */
+typedef enum _sctimer_counter
+{
+    kSCTIMER_Counter_L = 0U, /*!< Counter L */
+    kSCTIMER_Counter_H       /*!< Counter H */
+} sctimer_counter_t;
+
+/*! @brief List of SCTimer input pins */
+typedef enum _sctimer_input
+{
+    kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */
+    kSCTIMER_Input_1,      /*!< SCTIMER input 1 */
+    kSCTIMER_Input_2,      /*!< SCTIMER input 2 */
+    kSCTIMER_Input_3,      /*!< SCTIMER input 3 */
+    kSCTIMER_Input_4,      /*!< SCTIMER input 4 */
+    kSCTIMER_Input_5,      /*!< SCTIMER input 5 */
+    kSCTIMER_Input_6,      /*!< SCTIMER input 6 */
+    kSCTIMER_Input_7       /*!< SCTIMER input 7 */
+} sctimer_input_t;
+
+/*! @brief List of SCTimer output pins */
+typedef enum _sctimer_out
+{
+    kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/
+    kSCTIMER_Out_1,      /*!< SCTIMER output 1 */
+    kSCTIMER_Out_2,      /*!< SCTIMER output 2 */
+    kSCTIMER_Out_3,      /*!< SCTIMER output 3 */
+    kSCTIMER_Out_4,      /*!< SCTIMER output 4 */
+    kSCTIMER_Out_5,      /*!< SCTIMER output 5 */
+    kSCTIMER_Out_6,      /*!< SCTIMER output 6 */
+    kSCTIMER_Out_7       /*!< SCTIMER output 7 */
+} sctimer_out_t;
+
+/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */
+typedef enum _sctimer_pwm_level_select
+{
+    kSCTIMER_LowTrue = 0U, /*!< Low true pulses */
+    kSCTIMER_HighTrue      /*!< High true pulses */
+} sctimer_pwm_level_select_t;
+
+/*! @brief Options to configure a SCTimer PWM signal */
+typedef struct _sctimer_pwm_signal_param
+{
+    sctimer_out_t output;             /*!< The output pin to use to generate the PWM signal */
+    sctimer_pwm_level_select_t level; /*!< PWM output active level select. */
+    uint8_t dutyCyclePercent;         /*!< PWM pulse width, value should be between 1 to 100
+                                           100 = always active signal (100% duty cycle).*/
+} sctimer_pwm_signal_param_t;
+
+/*! @brief SCTimer clock mode options */
+typedef enum _sctimer_clock_mode
+{
+    kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */
+    kSCTIMER_Sampled_ClockMode,     /*!< Sampled System Clock Mode */
+    kSCTIMER_Input_ClockMode,       /*!< SCT Input Clock Mode */
+    kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */
+} sctimer_clock_mode_t;
+
+/*! @brief SCTimer clock select options */
+typedef enum _sctimer_clock_select
+{
+    kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */
+    kSCTIMER_Clock_On_Fall_Input_0,      /*!< Falling edges on input 0 */
+    kSCTIMER_Clock_On_Rise_Input_1,      /*!< Rising edges on input 1 */
+    kSCTIMER_Clock_On_Fall_Input_1,      /*!< Falling edges on input 1 */
+    kSCTIMER_Clock_On_Rise_Input_2,      /*!< Rising edges on input 2 */
+    kSCTIMER_Clock_On_Fall_Input_2,      /*!< Falling edges on input 2 */
+    kSCTIMER_Clock_On_Rise_Input_3,      /*!< Rising edges on input 3 */
+    kSCTIMER_Clock_On_Fall_Input_3,      /*!< Falling edges on input 3 */
+    kSCTIMER_Clock_On_Rise_Input_4,      /*!< Rising edges on input 4 */
+    kSCTIMER_Clock_On_Fall_Input_4,      /*!< Falling edges on input 4 */
+    kSCTIMER_Clock_On_Rise_Input_5,      /*!< Rising edges on input 5 */
+    kSCTIMER_Clock_On_Fall_Input_5,      /*!< Falling edges on input 5 */
+    kSCTIMER_Clock_On_Rise_Input_6,      /*!< Rising edges on input 6 */
+    kSCTIMER_Clock_On_Fall_Input_6,      /*!< Falling edges on input 6 */
+    kSCTIMER_Clock_On_Rise_Input_7,      /*!< Rising edges on input 7 */
+    kSCTIMER_Clock_On_Fall_Input_7       /*!< Falling edges on input 7 */
+} sctimer_clock_select_t;
+
+/*!
+ * @brief SCTimer output conflict resolution options.
+ *
+ * Specifies what action should be taken if multiple events dictate that a given output should be
+ * both set and cleared at the same time
+ */
+typedef enum _sctimer_conflict_resolution
+{
+    kSCTIMER_ResolveNone = 0U, /*!< No change */
+    kSCTIMER_ResolveSet,       /*!< Set output */
+    kSCTIMER_ResolveClear,     /*!< Clear output */
+    kSCTIMER_ResolveToggle     /*!< Toggle output */
+} sctimer_conflict_resolution_t;
+
+/*! @brief List of SCTimer event types */
+typedef enum _sctimer_event
+{
+    kSCTIMER_InputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_MatchEventOnly =
+        (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT)
+} sctimer_event_t;
+
+/*! @brief SCTimer callback typedef. */
+typedef void (*sctimer_event_callback_t)(void);
+
+/*! @brief List of SCTimer interrupts */
+typedef enum _sctimer_interrupt_enable
+{
+    kSCTIMER_Event0InterruptEnable = (1U << 0),   /*!< Event 0 interrupt */
+    kSCTIMER_Event1InterruptEnable = (1U << 1),   /*!< Event 1 interrupt */
+    kSCTIMER_Event2InterruptEnable = (1U << 2),   /*!< Event 2 interrupt */
+    kSCTIMER_Event3InterruptEnable = (1U << 3),   /*!< Event 3 interrupt */
+    kSCTIMER_Event4InterruptEnable = (1U << 4),   /*!< Event 4 interrupt */
+    kSCTIMER_Event5InterruptEnable = (1U << 5),   /*!< Event 5 interrupt */
+    kSCTIMER_Event6InterruptEnable = (1U << 6),   /*!< Event 6 interrupt */
+    kSCTIMER_Event7InterruptEnable = (1U << 7),   /*!< Event 7 interrupt */
+    kSCTIMER_Event8InterruptEnable = (1U << 8),   /*!< Event 8 interrupt */
+    kSCTIMER_Event9InterruptEnable = (1U << 9),   /*!< Event 9 interrupt */
+    kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */
+    kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */
+    kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */
+} sctimer_interrupt_enable_t;
+
+/*! @brief List of SCTimer flags */
+typedef enum _sctimer_status_flags
+{
+    kSCTIMER_Event0Flag = (1U << 0),   /*!< Event 0 Flag */
+    kSCTIMER_Event1Flag = (1U << 1),   /*!< Event 1 Flag */
+    kSCTIMER_Event2Flag = (1U << 2),   /*!< Event 2 Flag */
+    kSCTIMER_Event3Flag = (1U << 3),   /*!< Event 3 Flag */
+    kSCTIMER_Event4Flag = (1U << 4),   /*!< Event 4 Flag */
+    kSCTIMER_Event5Flag = (1U << 5),   /*!< Event 5 Flag */
+    kSCTIMER_Event6Flag = (1U << 6),   /*!< Event 6 Flag */
+    kSCTIMER_Event7Flag = (1U << 7),   /*!< Event 7 Flag */
+    kSCTIMER_Event8Flag = (1U << 8),   /*!< Event 8 Flag */
+    kSCTIMER_Event9Flag = (1U << 9),   /*!< Event 9 Flag */
+    kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */
+    kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */
+    kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */
+    kSCTIMER_BusErrorLFlag =
+        (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */
+    kSCTIMER_BusErrorHFlag =
+        (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */
+} sctimer_status_flags_t;
+
+/*!
+ * @brief SCTimer configuration structure
+ *
+ * This structure holds the configuration settings for the SCTimer peripheral. To initialize this
+ * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _sctimer_config
+{
+    bool enableCounterUnify;            /*!< true: SCT operates as a unified 32-bit counter;
+                                             false: SCT operates as two 16-bit counters */
+    sctimer_clock_mode_t clockMode;     /*!< SCT clock mode value */
+    sctimer_clock_select_t clockSelect; /*!< SCT clock select value */
+    bool enableBidirection_l;           /*!< true: Up-down count mode for the L or unified counter
+                                             false: Up count mode only for the L or unified counter */
+    bool enableBidirection_h;           /*!< true: Up-down count mode for the H or unified counter
+                                             false: Up count mode only for the H or unified counter.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t prescale_l;                 /*!< Prescale value to produce the L or unified counter clock */
+    uint8_t prescale_h;                 /*!< Prescale value to produce the H counter clock.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t outInitState;               /*!< Defines the initial output value */
+} sctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the SCTimer clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the SCTimer driver.
+ *
+ * @param base   SCTimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ *
+ * @return kStatus_Success indicates success; Else indicates failure.
+ */
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config);
+
+/*!
+ * @brief Gates the SCTimer clock.
+ *
+ * @param base SCTimer peripheral base address
+ */
+void SCTIMER_Deinit(SCT_Type *base);
+
+/*!
+ * @brief  Fills in the SCTimer configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *  config->enableCounterUnify = true;
+ *  config->clockMode = kSCTIMER_System_ClockMode;
+ *  config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+ *  config->enableBidirection_l = false;
+ *  config->enableBidirection_h = false;
+ *  config->prescale_l = 0;
+ *  config->prescale_h = 0;
+ *  config->outInitState = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
+ * function will create 2 events; one of the events will trigger on match with the pulse value
+ * and the other will trigger when the counter matches the PWM period. The PWM period event is
+ * also used as a limit event to reset the counter or change direction. Both events are enabled
+ * for the same state. The state number can be retrieved by calling the function
+ * SCTIMER_GetCurrentStateNumber().
+ * The counter is set to operate as one 32-bit counter (unify bit is set to 1).
+ * The counter operates in bi-directional mode when generating a center-aligned PWM.
+ *
+ * @note When setting PWM output from multiple output pins, they all should use the same PWM mode
+ * i.e all PWM's should be either edge-aligned or center-aligned.
+ * When using this API, the PWM signal frequency of all the initialized channels must be the same.
+ * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the 
+ * API's pwmFreq_Hz.
+ *
+ * @param base        SCTimer peripheral base address
+ * @param pwmParams   PWM parameters to configure the output
+ * @param mode        PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
+ * @param pwmFreq_Hz  PWM signal frequency in Hz
+ * @param srcClock_Hz SCTimer counter clock in Hz
+ * @param event       Pointer to a variable where the PWM period event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If we have hit the limit in terms of number of events created or if
+ *                      an incorrect PWM dutycylce is passed in.
+ */
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base              SCTimer peripheral base address
+ * @param output            The output to configure
+ * @param dutyCyclePercent  New PWM pulse width; the value should be between 1 to 100
+ * @param event             Event number associated with this PWM signal. This was returned to the user by the
+ *                          function SCTIMER_SetupPwm().
+ */
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN |= mask;
+}
+
+/*!
+ * @brief Disables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::sctimer_interrupt_enable_t
+ */
+static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base)
+{
+    return (base->EVEN & 0xFFFFU);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::sctimer_status_flags_t
+ */
+static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base)
+{
+    uint32_t statusFlags = 0;
+
+    /* Add the recorded events */
+    statusFlags = (base->EVFLAG & 0xFFFFU);
+
+    /* Add bus error flags */
+    statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+
+    return statusFlags;
+}
+
+/*!
+ * @brief Clears the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::sctimer_status_flags_t
+ */
+static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask)
+{
+    /* Write to the flag registers */
+    base->EVFLAG = (mask & 0xFFFFU);
+    base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the SCTimer counter.
+ *
+ * @param base           SCTimer peripheral base address
+ * @param countertoStart SCTimer counter to start; if unify mode is set then function always
+ *                       writes to HALT_L bit
+ */
+static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart)
+{
+    /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L))
+    {
+        base->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Start H counter */
+        base->CTRL &= ~(SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*!
+ * @brief Halts the SCTimer counter.
+ *
+ * @param base          SCTimer peripheral base address
+ * @param countertoStop SCTimer counter to stop; if unify mode is set then function always
+ *                      writes to HALT_L bit
+ */
+static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop)
+{
+    /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L))
+    {
+        base->CTRL |= (SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Stop H counter */
+        base->CTRL |= (SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*! @}*/
+
+/*!
+ * @name Functions to create a new event and manage the state logic
+ * @{
+ */
+
+/*!
+ * @brief Create an event that is triggered on a match or IO and schedule in current state.
+ *
+ * This function will configure an event using the options provided by the user. If the event type uses
+ * the counter match, then the function will set the user provided match value into a match register
+ * and put this match register number into the event control register.
+ * The event is enabled for the current state and the event number is increased by one at the end.
+ * The function returns the event number; this event number can be used to configure actions to be
+ * done when this event is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
+ * @param matchValue   The match value that will be programmed to a match register
+ * @param whichIO      The input or output that will be involved in event triggering. This field
+ *                     is ignored if the event type is "match only"
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as we have only 1 unified counter; hence ignored.
+ * @param event        Pointer to a variable where the new event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of events created or
+                         if we have reached the limit in terms of number of match registers
+ */
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event);
+
+/*!
+ * @brief Enable an event in the current state.
+ *
+ * This function will allow the event passed in to trigger in the current state. The event must
+ * be created earlier by either calling the function SCTIMER_SetupPwm() or function
+ * SCTIMER_CreateAndScheduleEvent() .
+ *
+ * @param base  SCTimer peripheral base address
+ * @param event Event number to enable in the current state
+ *
+ */
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event);
+
+/*!
+ * @brief Increase the state by 1
+ *
+ * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
+ * state.
+ *
+ * @param base  SCTimer peripheral base address
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of states used
+
+ */
+status_t SCTIMER_IncreaseState(SCT_Type *base);
+
+/*!
+ * @brief Provides the current state
+ *
+ * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The current state
+ */
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Actions to take in response to an event
+ * @{
+ */
+
+/*!
+ * @brief Setup capture of the counter value on trigger of a selected event
+ *
+ * @param base            SCTimer peripheral base address
+ * @param whichCounter    SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                        field has no meaning as only the Counter_L bits are used.
+ * @param captureRegister Pointer to a variable where the capture register number will be returned. User
+ *                        can read the captured value from this register when the specified event is triggered.
+ * @param event           Event number that will trigger the capture
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of match/capture registers available
+ */
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event);
+
+/*!
+ * @brief Receive noticification when the event trigger an interrupt.
+ *
+ * If the interrupt for the event is enabled by the user, then a callback can be registered
+ * which will be invoked when the event is triggered
+ *
+ * @param base     SCTimer peripheral base address
+ * @param event    Event number that will trigger the interrupt
+ * @param callback Function to invoke when the event is triggered
+ */
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event);
+
+/*!
+ * @brief Transition to the specified state.
+ *
+ * This transition will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param nextState The next state SCTimer will transition to
+ * @param event     Event number that will trigger the state transition
+ */
+static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event)
+{
+    uint32_t reg = base->EVENT[event].CTRL;
+
+    reg &= ~(SCT_EVENT_CTRL_STATEV_MASK);
+    /* Load the STATEV value when the event occurs to be the next state */
+    reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK;
+
+    base->EVENT[event].CTRL = reg;
+}
+
+/*!
+ * @brief Set the Output.
+ *
+ * This output will be set when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to set
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].SET |= (1U << event);
+}
+
+/*!
+ * @brief Clear the Output.
+ *
+ * This output will be cleared when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to clear
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].CLR |= (1U << event);
+}
+
+/*!
+ * @brief Toggle the output level.
+ *
+ * This change in the output level is triggered by the event number that is passed in by the user.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to toggle
+ * @param event   Event number that will trigger the output change
+ */
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event);
+
+/*!
+ * @brief Limit the running counter.
+ *
+ * The counter is limited when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be limited
+ */
+static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event);
+    }
+    else
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Stop the running counter.
+ *
+ * The counter is stopped when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be stopped
+ */
+static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->STOP |= SCT_STOP_STOPMSK_L(1U << event);
+    }
+    else
+    {
+        base->STOP |= SCT_STOP_STOPMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Re-start the stopped counter.
+ *
+ * The counter will re-start when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to re-start
+ */
+static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->START |= SCT_START_STARTMSK_L(1U << event);
+    }
+    else
+    {
+        base->START |= SCT_START_STARTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Halt the running counter.
+ *
+ * The counter is disabled (halted) when the event number that is passed in by the user is
+ * triggered. When the counter is halted, all further events are disabled. The HALT condition
+ * can only be removed by calling the SCTIMER_StartTimer() function.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be halted
+ */
+static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->HALT |= SCT_HALT_HALTMSK_L(1U << event);
+    }
+    else
+    {
+        base->HALT |= SCT_HALT_HALTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Generate a DMA request.
+ *
+ * DMA request will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param dmaNumber The DMA request to generate
+ * @param event     Event number that will trigger the DMA request
+ */
+static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event)
+{
+    if (dmaNumber == 0)
+    {
+        base->DMA0REQUEST |= (1U << event);
+    }
+    else
+    {
+        base->DMA1REQUEST |= (1U << event);
+    }
+}
+
+/*!
+ * @brief SCTimer interrupt handler.
+ *
+ * @param base SCTimer peripheral base address.
+ */
+void SCTIMER_EventHandleIRQ(SCT_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SCTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,1293 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sdif.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Typedef for interrupt handler. */
+typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the instance.
+ *
+ * @param base SDIF peripheral base address.
+ * @return Instance number.
+ */
+static uint32_t SDIF_GetInstance(SDIF_Type *base);
+
+/*
+* @brief config the SDIF interface before transfer between the card and host
+* @param SDIF base address
+* @param transfer config structure
+*/
+static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer);
+
+/*
+* @brief wait the command done function and check error status
+* @param SDIF base address
+* @param command config structure
+*/
+static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command);
+
+/*
+* @brief transfer data in a blocking way
+* @param SDIF base address
+* @param data config structure
+* @param indicate current transfer mode:DMA or polling
+*/
+static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA);
+
+/*
+* @brief read the command response
+* @param SDIF base address
+* @param sdif command pointer
+*/
+static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command);
+
+/*
+* @brief handle transfer command interrupt
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flags
+*/
+static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief handle transfer data interrupt
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flags
+*/
+static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief handle DMA transfer
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flag
+*/
+static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief driver IRQ handler
+* @param SDIF base address
+* @param sdif handle
+*/
+static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle);
+
+/*
+* @brief read data port
+* @param SDIF base address
+* @param sdif data
+* @param the number of data been transferred
+*/
+static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
+
+/*
+* @brief write data port
+* @param SDIF base address
+* @param sdif data
+* @param the number of data been transferred
+*/
+static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
+
+/*
+* @brief read data by blocking way
+* @param SDIF base address
+* @param sdif data
+*/
+static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
+
+/*
+* @brief write data by blocking way
+* @param SDIF base address
+* @param sdif data
+*/
+static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
+
+/*
+* @brief handle sdio interrupt
+* This function will call the SDIO interrupt callback
+* @param SDIF handle
+*/
+static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief SDIF internal handle pointer array */
+static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT];
+
+/*! @brief SDIF base pointer array */
+static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS;
+
+/*! @brief SDIF IRQ name array */
+static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS;
+
+/* SDIF ISR for transactional APIs. */
+static sdif_isr_t s_sdifIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SDIF_GetInstance(SDIF_Type *base)
+{
+    uint8_t instance = 0U;
+
+    while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base))
+    {
+        instance++;
+    }
+
+    assert(instance < ARRAY_SIZE(s_sdifBase));
+
+    return instance;
+}
+
+static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer)
+{
+    sdif_command_t *command = transfer->command;
+    sdif_data_t *data = transfer->data;
+
+    if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK)))
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    if (data != NULL)
+    {
+        /* config the block size register ,the block size maybe smaller than FIFO
+         depth, will test on the board */
+        base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize);
+        /* config the byte count register */
+        base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount);
+
+        command->flags |= kSDIF_DataExpect; /* need transfer data flag */
+
+        if (data->txData != NULL)
+        {
+            command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */
+        }
+        else
+        {
+            /* config the card read threshold,enable the card read threshold */
+            if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t)))
+            {
+                base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize);
+            }
+            else
+            {
+                base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK;
+            }
+        }
+
+        if (data->streamTransfer)
+        {
+            command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer  */
+        }
+
+        if ((data->enableAutoCommand12) &&
+            (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */
+        {
+            command->flags |= kSDIF_DataTransferAutoStop;
+        }
+    }
+    /* R2 response length long */
+    if (command->responseType == kCARD_ResponseTypeR2)
+    {
+        command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect);
+    }
+    else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4))
+    {
+        command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */
+    }
+    else
+    {
+        if (command->responseType != kCARD_ResponseTypeNone)
+        {
+            command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect);
+        }
+    }
+
+    if (command->type == kCARD_CommandTypeAbort)
+    {
+        command->flags |= kSDIF_TransferStopAbort;
+    }
+
+    /* wait pre-transfer complete */
+    command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg;
+
+    return kStatus_Success;
+}
+
+static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command)
+{
+    /* check if command exsit,if not, do not read the response */
+    if (NULL != command)
+    {
+        /* read reponse */
+        command->response[0U] = base->RESP[0U];
+        if (command->responseType == kCARD_ResponseTypeR2)
+        {
+            command->response[1U] = base->RESP[1U];
+            command->response[2U] = base->RESP[2U];
+            command->response[3U] = base->RESP[3U];
+        }
+
+        if ((command->responseErrorFlags != 0U) &&
+            ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
+             (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5)))
+        {
+            if (((command->responseErrorFlags) & (command->response[0U])) != 0U)
+            {
+                return kStatus_SDIF_ResponseError;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command)
+{
+    uint32_t status = 0U;
+
+    do
+    {
+        status = SDIF_GetInterruptStatus(base);
+        if ((status &
+             (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u)
+        {
+            SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError |
+                                                      kSDIF_ResponseTimeout | kSDIF_HardwareLockError));
+            return kStatus_SDIF_SendCmdFail;
+        }
+    } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone);
+
+    /* clear the command done bit */
+    SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone);
+
+    return SDIF_ReadCommandResponse(base, command);
+}
+
+status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig)
+{
+    assert(NULL != dmaConfig);
+    assert(NULL != dmaConfig->dmaDesBufferStartAddr);
+
+    sdif_dma_descriptor_t *dmaDesAddr;
+    uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr;
+    uint32_t dmaDesBufferSize = 0U;
+
+    dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+
+    /* chain descriptor mode */
+    if (dmaConfig->mode == kSDIF_ChainDMAMode)
+    {
+        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorDataBufferEnd) != kSDIF_DMADescriptorDataBufferEnd) &&
+               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
+        {
+            /* set the OWN bit */
+            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+            dmaDesAddr++;
+            dmaDesBufferSize += sizeof(sdif_dma_descriptor_t);
+        }
+        /* if access dma des address overflow, return fail */
+        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
+        {
+            return kStatus_Fail;
+        }
+        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+    }
+    /* dual descriptor mode */
+    else
+    {
+        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorEnd) != kSDIF_DMADescriptorEnd) &&
+               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
+        {
+            dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+            tempDMADesBuffer += dmaConfig->dmaDesSkipLen;
+        }
+        /* if access dma des address overflow, return fail */
+        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
+        {
+            return kStatus_Fail;
+        }
+        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+    }
+    /* reload DMA descriptor */
+    base->PLDMND = SDIF_POLL_DEMAND_VALUE;
+
+    return kStatus_Success;
+}
+
+static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
+{
+    uint32_t i;
+    uint32_t totalWords;
+    uint32_t wordsCanBeRead; /* The words can be read at this time. */
+    uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT);
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
+    if (readWatermark >= totalWords)
+    {
+        wordsCanBeRead = totalWords;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark,
+    transfers watermark level words. */
+    else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark))
+    {
+        wordsCanBeRead = readWatermark;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left
+    words. */
+    else
+    {
+        wordsCanBeRead = (totalWords - transferredWords);
+    }
+
+    i = 0U;
+    while (i < wordsCanBeRead)
+    {
+        data->rxData[transferredWords++] = base->FIFO[i];
+        i++;
+    }
+
+    return transferredWords;
+}
+
+static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
+{
+    uint32_t i;
+    uint32_t totalWords;
+    uint32_t wordsCanBeWrite; /* The words can be read at this time. */
+    uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT);
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
+    if (writeWatermark >= totalWords)
+    {
+        wordsCanBeWrite = totalWords;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark,
+    transfers watermark level words. */
+    else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark))
+    {
+        wordsCanBeWrite = writeWatermark;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers left
+    words. */
+    else
+    {
+        wordsCanBeWrite = (totalWords - transferredWords);
+    }
+
+    i = 0U;
+    while (i < wordsCanBeWrite)
+    {
+        base->FIFO[i] = data->txData[transferredWords++];
+        i++;
+    }
+
+    return transferredWords;
+}
+
+static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
+{
+    uint32_t totalWords;
+    uint32_t transferredWords = 0U;
+    status_t error = kStatus_Success;
+    uint32_t status;
+    bool transferOver = false;
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    while ((transferredWords < totalWords) && (error == kStatus_Success))
+    {
+        /* wait data transfer complete or reach RX watermark */
+        do
+        {
+            status = SDIF_GetInterruptStatus(base);
+            if (status & kSDIF_DataTransferError)
+            {
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_Fail;
+                }
+            }
+        } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver));
+
+        if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver)
+        {
+            transferOver = true;
+        }
+
+        if (error == kStatus_Success)
+        {
+            transferredWords = SDIF_ReadDataPort(base, data, transferredWords);
+        }
+
+        /* clear interrupt status */
+        SDIF_ClearInterruptStatus(base, status);
+    }
+
+    return error;
+}
+
+static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
+{
+    uint32_t totalWords;
+    uint32_t transferredWords = 0U;
+    status_t error = kStatus_Success;
+    uint32_t status;
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    while ((transferredWords < totalWords) && (error == kStatus_Success))
+    {
+        /* wait data transfer complete or reach RX watermark */
+        do
+        {
+            status = SDIF_GetInterruptStatus(base);
+            if (status & kSDIF_DataTransferError)
+            {
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_Fail;
+                }
+            }
+        } while ((status & kSDIF_WriteFIFORequest) == 0U);
+
+        if (error == kStatus_Success)
+        {
+            transferredWords = SDIF_WriteDataPort(base, data, transferredWords);
+        }
+
+        /* clear interrupt status */
+        SDIF_ClearInterruptStatus(base, status);
+    }
+
+    while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver)
+    {
+    }
+
+    if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError)
+    {
+        if (!(data->enableIgnoreError))
+        {
+            error = kStatus_Fail;
+        }
+    }
+    SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError));
+
+    return error;
+}
+
+bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout)
+{
+    base->CTRL |= mask;
+
+    /* check software DMA reset here for DMA reset also need to check this bit */
+    while ((base->CTRL & mask) != 0U)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+
+    return timeout ? true : false;
+}
+
+static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA)
+{
+    assert(NULL != data);
+
+    uint32_t dmaStatus = 0U;
+    status_t error = kStatus_Success;
+
+    /* in DMA mode, only need to wait the complete flag and check error */
+    if (isDMA)
+    {
+        do
+        {
+            dmaStatus = SDIF_GetInternalDMAStatus(base);
+            if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError)
+            {
+                SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary);
+                error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */
+            }
+            /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */
+            if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary)
+            {
+                SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary);
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_SDIF_DataTransferFail;
+                }
+
+                /* if error occur, then return */
+                break;
+            }
+        } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U);
+
+        /* clear the corresponding status bit */
+        SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor |
+                                           kSDIF_NormalInterruptSummary));
+
+        SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base));
+    }
+    else
+    {
+        if (data->rxData != NULL)
+        {
+            error = SDIF_ReadDataPortBlocking(base, data);
+        }
+        else
+        {
+            error = SDIF_WriteDataPortBlocking(base, data);
+        }
+    }
+
+    return error;
+}
+
+status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout)
+{
+    assert(NULL != cmd);
+
+    base->CMDARG = cmd->argument;
+    base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK));
+
+    /* wait start_cmd bit auto clear within timeout */
+    while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+
+        --timeout;
+    }
+
+    return timeout ? kStatus_Success : kStatus_Fail;
+}
+
+bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout)
+{
+    bool enINT = false;
+    sdif_command_t command;
+
+    memset(&command, 0U, sizeof(sdif_command_t));
+
+    /* add for confict with interrupt mode,close the interrupt temporary */
+    if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK)
+    {
+        enINT = true;
+        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
+    }
+
+    command.flags = SDIF_CMD_SEND_INITIALIZATION_MASK;
+
+    if (SDIF_SendCommand(base, &command, timeout) == kStatus_Fail)
+    {
+        return false;
+    }
+
+    /* wait command done */
+    while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone)
+    {
+    }
+
+    /* clear status */
+    SDIF_ClearInterruptStatus(base, kSDIF_CommandDone);
+
+    /* add for confict with interrupt mode */
+    if (enINT)
+    {
+        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
+    }
+
+    return true;
+}
+
+void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider)
+{
+    /*config the clock delay and pharse shift
+     *should config the clk_in_drv,
+     *clk_in_sample to meet the min hold and
+     *setup time
+     */
+    if (target_HZ <= kSDIF_Freq400KHZ)
+    {
+        /*min hold time:5ns
+        * min setup time: 5ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY);
+    }
+    else if (target_HZ >= kSDIF_Freq50MHZ)
+    {
+        /*
+        * user need to pay attention to this parameter
+        * can be change the setting for you card and board
+        * min hold time:2ns
+        * min setup time: 6ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY);
+        /* means the input clock = 2 * card clock,
+        * can use clock pharse shift tech
+        */
+        if (divider == 1U)
+        {
+            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
+                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180);
+        }
+    }
+    else
+    {
+        /*
+        * user need to pay attention to this parameter
+        * can be change the setting for you card and board
+        * min hold time:5ns
+        * min setup time: 5ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY);
+        /* means the input clock = 2 * card clock,
+        * can use clock pharse shift tech
+        */
+        if (divider == 1U)
+        {
+            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
+                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90);
+        }
+    }
+}
+
+uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ)
+{
+    assert(srcClock_Hz <= FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK);
+
+    sdif_command_t cmd = {0U};
+    uint32_t divider = 0U, targetFreq = target_HZ;
+
+    /* if target freq bigger than the source clk, set the target_HZ to
+     src clk, this interface can run up to 52MHZ with card */
+    if (srcClock_Hz < targetFreq)
+    {
+        targetFreq = srcClock_Hz;
+    }
+
+    /* disable the clock first,need sync to CIU*/
+    SDIF_EnableCardClock(base, false);
+
+    /* update the clock register and wait the pre-transfer complete */
+    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /*calucate the divider*/
+    if (targetFreq != srcClock_Hz)
+    {
+        divider = (srcClock_Hz / targetFreq + 1U) / 2U;
+    }
+    /* load the clock divider */
+    base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider);
+
+    /* update the divider to CIU */
+    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /* enable the card clock and sync to CIU */
+    SDIF_EnableCardClock(base, true);
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /* config the clock delay to meet the hold time and setup time */
+    SDIF_ConfigClockDelay(target_HZ, divider);
+
+    /* return the actual card clock freq */
+
+    return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz;
+}
+
+bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout)
+{
+    /* assert this bit to reset the data machine to abort the read data */
+    base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK;
+    /* polling the bit self clear */
+    while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+
+    return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true;
+}
+
+status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize)
+{
+    assert(NULL != config);
+    assert(NULL != data);
+
+    uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U;
+    uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr;
+    const uint32_t *dataBuffer = data;
+    sdif_dma_descriptor_t *descriptorPoniter = NULL;
+    uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode);
+
+    /* check the dma descriptor buffer length , it is user's responsibility to make sure the DMA descriptor table
+    size is bigger enough to hold the transfer descriptor */
+    if (config->dmaDesBufferLen * sizeof(uint32_t) < sizeof(sdif_dma_descriptor_t))
+    {
+        return kStatus_SDIF_DescriptorBufferLenError;
+    }
+
+    /* check the read/write data size,must be a multiple of 4 */
+    if (dataSize % sizeof(uint32_t) != 0U)
+    {
+        dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t));
+    }
+
+    /*config the bus mode*/
+    if (config->enableFixBurstLen)
+    {
+        base->BMOD |= SDIF_BMOD_FB_MASK;
+    }
+
+    /* calucate the dma descriptor entry due to DMA buffer size limit */
+    /* if datasize smaller than one descriptor buffer size */
+    if (dataSize > maxDMABuffer)
+    {
+        dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U);
+    }
+    else /* need one dma descriptor */
+    {
+        dmaEntry = 1U;
+    }
+
+    /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor
+    table
+    size is bigger enough to hold the transfer descriptor */
+    if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen))
+    {
+        return kStatus_SDIF_DescriptorBufferLenError;
+    }
+
+    switch (config->mode)
+    {
+        case kSDIF_DualDMAMode:
+            base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */
+            for (i = 0U; i < dmaEntry; i++)
+            {
+                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
+                {
+                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                    dataSize -= dmaBufferSize;
+                    dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ?
+                                         FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE :
+                                         dataSize;
+                    dataSize -= dmaBuffer1Size;
+                }
+                else
+                {
+                    dmaBufferSize = dataSize;
+                    dmaBuffer1Size = 0U;
+                }
+
+                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+                if (i == 0U)
+                {
+                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
+                }
+                descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA | kSDIF_DisableCompleteInterrupt;
+                descriptorPoniter->dmaDataBufferSize =
+                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size);
+
+                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
+                descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t);
+                dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t);
+
+                /* descriptor skip length */
+                tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t);
+            }
+            /* enable the completion interrupt when reach the last descriptor */
+            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
+            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd | kSDIF_DMADescriptorEnd;
+            break;
+
+        case kSDIF_ChainDMAMode:
+            for (i = 0U; i < dmaEntry; i++)
+            {
+                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
+                {
+                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                    dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                }
+                else
+                {
+                    dmaBufferSize = dataSize;
+                }
+
+                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+                if (i == 0U)
+                {
+                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
+                }
+                descriptorPoniter->dmaDesAttribute |=
+                    kSDIF_DMADescriptorOwnByDMA | kSDIF_DMASecondAddrChained | kSDIF_DisableCompleteInterrupt;
+                descriptorPoniter->dmaDataBufferSize =
+                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/
+                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
+                dataBuffer += dmaBufferSize / sizeof(uint32_t);
+                tempDMADesBuffer +=
+                    sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calucate the next descriptor address */
+                /* this descriptor buffer2 pointer to the next descriptor address */
+                descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer;
+            }
+            /* enable the completion interrupt when reach the last descriptor */
+            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
+            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd;
+            break;
+
+        default:
+            break;
+    }
+
+    /* use internal DMA interface */
+    base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK;
+    /* enable the internal SD/MMC DMA */
+    base->BMOD |= SDIF_BMOD_DE_MASK;
+    /* enable DMA status check */
+    base->IDINTEN |= kSDIF_DMAAllStatus;
+    /* clear write/read FIFO request interrupt in DMA mode, DMA will handle the data transfer*/
+    SDIF_DisableInterrupt(base, kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | kSDIF_DataTransferOver);
+    /* load DMA descriptor buffer address */
+    base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr;
+
+    return kStatus_Success;
+}
+
+void SDIF_Init(SDIF_Type *base, sdif_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t timeout;
+
+    /* enable SDIF clock */
+    CLOCK_EnableClock(kCLOCK_Sdio);
+
+    /* do software reset */
+    base->BMOD |= SDIF_BMOD_SWR_MASK;
+
+    /* reset all */
+    SDIF_Reset(base, kSDIF_ResetAll, SDIF_TIMEOUT_VALUE);
+
+    /*config timeout register */
+    timeout = base->TMOUT;
+    timeout &= ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK);
+    timeout |= SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout);
+
+    base->TMOUT = timeout;
+
+    /* config the card detect debounce clock count */
+    base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock);
+
+    /*config the watermark/burst transfer value */
+    base->FIFOTH =
+        SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U);
+
+    /* enable the interrupt status  */
+    SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus);
+
+    /* clear all interrupt/DMA status */
+    SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus);
+    SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus);
+}
+
+status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer)
+{
+    assert(NULL != transfer);
+
+    bool isDMA = false;
+    sdif_data_t *data = transfer->data;
+
+    /* config the transfer parameter */
+    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    /* if need transfer data in dma mode, config the DMA descriptor first */
+    if ((data != NULL) && (dmaConfig != NULL))
+    {
+        /* use internal DMA mode to transfer between the card and host*/
+        isDMA = true;
+
+        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
+                                   data->blockSize * data->blockCount) != kStatus_Success)
+        {
+            return kStatus_SDIF_DescriptorBufferLenError;
+        }
+    }
+
+    /* send command first */
+    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
+    {
+        return kStatus_SDIF_SyncCmdTimeout;
+    }
+
+    /* wait the command transfer done and check if error occurs */
+    if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success)
+    {
+        return kStatus_SDIF_SendCmdFail;
+    }
+
+    /* if use DMA transfer mode ,check the corresponding status bit */
+    if (data != NULL)
+    {
+        /* check the if has DMA descriptor featch error */
+        if (isDMA &&
+            ((SDIF_GetInternalDMAStatus(base) & kSDIF_DMADescriptorUnavailable) == kSDIF_DMADescriptorUnavailable))
+        {
+            SDIF_ClearInternalDMAStatus(base, kSDIF_DMADescriptorUnavailable | kSDIF_AbnormalInterruptSummary);
+
+            /* release the DMA descriptor to DMA */
+            SDIF_ReleaseDMADescriptor(base, dmaConfig);
+        }
+        /* handle data transfer */
+        if (SDIF_TransferDataBlocking(base, data, isDMA) != kStatus_Success)
+        {
+            return kStatus_SDIF_DataTransferFail;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t SDIF_TransferNonBlocking(SDIF_Type *base,
+                                  sdif_handle_t *handle,
+                                  sdif_dma_config_t *dmaConfig,
+                                  sdif_transfer_t *transfer)
+{
+    assert(NULL != transfer);
+
+    sdif_data_t *data = transfer->data;
+
+    /* save the data and command before transfer */
+    handle->data = transfer->data;
+    handle->command = transfer->command;
+    handle->transferredWords = 0U;
+    handle->interruptFlags = 0U;
+    handle->dmaInterruptFlags = 0U;
+
+    /* config the transfer parameter */
+    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    if ((data != NULL) && (dmaConfig != NULL))
+    {
+        /* use internal DMA mode to transfer between the card and host*/
+        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
+                                   data->blockSize * data->blockCount) != kStatus_Success)
+        {
+            return kStatus_SDIF_DescriptorBufferLenError;
+        }
+    }
+
+    /* send command first */
+    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
+    {
+        return kStatus_SDIF_SyncCmdTimeout;
+    }
+
+    return kStatus_Success;
+}
+
+void SDIF_TransferCreateHandle(SDIF_Type *base,
+                               sdif_handle_t *handle,
+                               sdif_transfer_callback_t *callback,
+                               void *userData)
+{
+    assert(handle);
+    assert(callback);
+
+    /* reset the handle. */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Set the callback. */
+    handle->callback.SDIOInterrupt = callback->SDIOInterrupt;
+    handle->callback.DMADesUnavailable = callback->DMADesUnavailable;
+    handle->callback.CommandReload = callback->CommandReload;
+    handle->callback.TransferComplete = callback->TransferComplete;
+
+    handle->userData = userData;
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_sdifHandle[SDIF_GetInstance(base)] = handle;
+
+    /* save IRQ handler */
+    s_sdifIsr = SDIF_TransferHandleIRQ;
+
+    /* enable the global interrupt */
+    SDIF_EnableGlobalInterrupt(base, true);
+
+    EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]);
+}
+
+void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability)
+{
+    assert(NULL != capability);
+
+    capability->sdVersion = SDIF_SUPPORT_SD_VERSION;
+    capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION;
+    capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK;
+    /* set the max block count = max byte conut / max block size */
+    capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK;
+    capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag |
+                        kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag;
+}
+
+static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    assert(handle->command);
+
+    /* transfer error */
+    if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout))
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData);
+    }
+    /* cmd buffer full, in this condition user need re-send the command */
+    else if (interruptFlags & kSDIF_HardwareLockError)
+    {
+        if (handle->callback.CommandReload)
+        {
+            handle->callback.CommandReload();
+        }
+    }
+    /* transfer command success */
+    else
+    {
+        SDIF_ReadCommandResponse(base, handle->command);
+        if (((handle->data) == NULL) && (handle->callback.TransferComplete))
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+}
+
+static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    assert(handle->data);
+
+    /* data starvation by host time out, software should read/write FIFO*/
+    if (interruptFlags & kSDIF_DataStarvationByHostTimeout)
+    {
+        if (handle->data->rxData != NULL)
+        {
+            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+        }
+        else if (handle->data->txData != NULL)
+        {
+            handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
+        }
+        else
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+        }
+    }
+    /* data transfer fail */
+    else if (interruptFlags & kSDIF_DataTransferError)
+    {
+        if (!handle->data->enableIgnoreError)
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+        }
+    }
+    /* need fill data to FIFO */
+    else if (interruptFlags & kSDIF_WriteFIFORequest)
+    {
+        handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
+    }
+    /* need read data from FIFO */
+    else if (interruptFlags & kSDIF_ReadFIFORequest)
+    {
+        handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+    }
+    else
+    {
+    }
+
+    /* data transfer over */
+    if (interruptFlags & kSDIF_DataTransferOver)
+    {
+        while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U))
+        {
+            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+        }
+        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+    }
+}
+
+static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    if (interruptFlags & kSDIF_DMAFatalBusError)
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData);
+    }
+    else if (interruptFlags & kSDIF_DMADescriptorUnavailable)
+    {
+        if (handle->callback.DMADesUnavailable)
+        {
+            handle->callback.DMADesUnavailable();
+        }
+    }
+    else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) &&
+             (!handle->data->enableIgnoreError))
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+    }
+    /* card normal summary */
+    else
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+    }
+}
+
+static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle)
+{
+    if (handle->callback.SDIOInterrupt != NULL)
+    {
+        handle->callback.SDIOInterrupt();
+    }
+}
+
+static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle)
+{
+    assert(handle);
+
+    uint32_t interruptFlags, dmaInterruptFlags;
+
+    interruptFlags = SDIF_GetInterruptStatus(base);
+    dmaInterruptFlags = SDIF_GetInternalDMAStatus(base);
+
+    handle->interruptFlags = interruptFlags;
+    handle->dmaInterruptFlags = dmaInterruptFlags;
+
+    if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U)
+    {
+        SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus));
+    }
+    if ((interruptFlags & kSDIF_DataTransferStatus) != 0U)
+    {
+        SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus));
+    }
+    if (interruptFlags & kSDIF_SDIOInterrupt)
+    {
+        SDIF_TransferHandleSDIOInterrupt(handle);
+    }
+    if (dmaInterruptFlags & kSDIF_DMAAllStatus)
+    {
+        SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags);
+    }
+
+    SDIF_ClearInterruptStatus(base, interruptFlags);
+    SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags);
+}
+
+void SDIF_Deinit(SDIF_Type *base)
+{
+    /* disable clock here*/
+    CLOCK_DisableClock(kCLOCK_Sdio);
+    /* disable the SDIOCLKCTRL */
+    SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                             SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK);
+    RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn);
+}
+
+#if defined(SDIF)
+void SDIF_DriverIRQHandler(void)
+{
+    assert(s_sdifHandle[0]);
+
+    s_sdifIsr(SDIF, s_sdifHandle[0]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,824 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SDIF_H_
+#define _FSL_SDIF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sdif
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.1. */
+#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*@}*/
+
+#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */
+
+#define SDIF_SUPPORT_SD_VERSION (0x20)  /*!< define the controller support sd/sdio card version 2.0 */
+#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */
+
+#define SDIF_TIMEOUT_VALUE (65535U)    /*!< define the timeout counter */
+#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */
+
+#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU)          /*!< DMA descriptor buffer1 size */
+#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!<DMA descriptor buffer2 size */
+#define SDIF_RX_WATERMARK (15U)                                    /*!<RX water mark value */
+#define SDIF_TX_WATERMARK (16U)                                    /*!<TX water mark value */
+
+/*! @brief  SDIOCLKCTRL setting
+* below clock delay setting should meet you board layout
+* user can change it when you meet timing mismatch issue
+* such as: response error/CRC error and so on
+*/
+#define SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY (0X17U)
+#define SDIF_INDENTIFICATION_MODE_DRV_DELAY (0X17U)
+#define SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY (0x10U)
+#define SDIF_HIGHSPEED_25MHZ_DRV_DELAY (0x10U)
+#define SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY (0x1FU)
+#define SDIF_HIGHSPEED_50MHZ_DRV_DELAY (0x1FU)
+
+/*! @brief SDIF status */
+enum _sdif_status
+{
+    kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */
+    kStatue_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U),          /*!< invalid argument status */
+    kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */
+    kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U),    /* send command to card fail */
+    kStatus_SDIF_SendCmdErrorBufferFull =
+        MAKE_STATUS(kStatusGroup_SDIF, 4U), /* send command to card fail, due to command buffer full
+                                     user need to resend this command */
+    kStatus_SDIF_DMATransferFailWithFBE =
+        MAKE_STATUS(kStatusGroup_SDIF, 5U), /* DMA transfer data fail with fatal bus error ,
+                                     to do with this error :issue a hard reset/controller reset*/
+    kStatus_SDIF_DMATransferDescriptorUnavaliable = MAKE_STATUS(kStatusGroup_SDIF, 6U), /* DMA descriptor unavalible */
+    kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U),                 /* transfer data fail */
+    kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U),
+};
+
+/*! @brief Host controller capabilities flag mask */
+enum _sdif_capability_flag
+{
+    kSDIF_SupportHighSpeedFlag = 0x1U,     /*!< Support high-speed */
+    kSDIF_SupportDmaFlag = 0x2U,           /*!< Support DMA */
+    kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */
+    kSDIF_SupportV330Flag = 0x8U,          /*!< Support voltage 3.3V */
+    kSDIF_Support4BitFlag = 0x10U,         /*!< Support 4 bit mode */
+    kSDIF_Support8BitFlag = 0x20U,         /*!< Support 8 bit mode */
+};
+
+/*! @brief define the reset type */
+enum _sdif_reset_type
+{
+    kSDIF_ResetController =
+        SDIF_CTRL_CONTROLLER_RESET_MASK,                /*!< reset controller,will reset: BIU/CIU interface
+                                                          CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE
+                                                          and READ_WAIT bits of control register,START_CMD bit of the
+                                                          command register*/
+    kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK,        /*!< reset data FIFO*/
+    kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */
+
+    kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/
+                     kSDIF_ResetDMAInterface,
+};
+
+/*! @brief define the card bus width type */
+typedef enum _sdif_bus_width
+{
+    kSDIF_Bus1BitWidth = 0U,                          /*!< 1bit bus width, 1bit mode and 4bit mode
+                                                      share one register bit */
+    kSDIF_Bus4BitWidth = SDIF_CTYPE_CARD_WIDTH0_MASK, /*!< 4bit mode mask */
+    kSDIF_Bus8BitWidth = SDIF_CTYPE_CARD_WIDTH1_MASK, /*!< support 8 bit mode */
+} sdif_bus_width_t;
+
+/*! @brief define the command flags */
+enum _sdif_command_flags
+{
+    kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK,      /*!< command request response*/
+    kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK,  /*!< command response length long */
+    kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/
+    kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK,               /*!< request data transfer,ethier read/write*/
+    kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK,             /*!< data transfer direction */
+    kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK,    /*!< data transfer mode :stream/block transfer command */
+    kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */
+    kSDIF_WaitPreTransferComplete =
+        SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd  */
+    kSDIF_TransferStopAbort =
+        SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer
+                                       ,this bit should set so that cmd/data state-machines of CIU can return
+                                       to idle correctly*/
+    kSDIF_SendInitialization =
+        SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initaliztion  80 clocks for SD card after power on  */
+    kSDIF_CmdUpdateClockRegisterOnly =
+        SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK,                /*!< send cmd update the CIU clock register only */
+    kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */
+    kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK,         /*!< command expect command completion signal signal */
+    kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK,        /*!< this bit should only be set for mandatory boot mode */
+    kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */
+    kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK,      /*!< when software set this bit along with START_CMD, CIU
+                                                                terminates the boot operation*/
+    kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK,       /*!< select boot mode ,alternate or mandatory*/
+    kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK,      /*!< this bit set for CMD11 only */
+    kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK,    /*!< cmd and data send to card through the HOLD register*/
+};
+
+/*! @brief The command type */
+enum _sdif_command_type
+{
+    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
+    kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
+    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
+    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
+};
+
+/*!
+ * @brief The command response type.
+ *
+ * Define the command response type from card to host controller.
+ */
+enum _sdif_response_type
+{
+    kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
+    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
+    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
+    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
+    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
+    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
+    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
+    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
+    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
+    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
+};
+
+/*! @brief define the interrupt mask flags */
+enum _sdif_interrupt_mask
+{
+    kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK,                 /*!< mask for card detect */
+    kSDIF_ResponseError = SDIF_INTMASK_RE_MASK,                /*!< command response error */
+    kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK,               /*!< command transfer over*/
+    kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK,            /*!< data transfer over flag*/
+    kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK,           /*!< write FIFO request */
+    kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK,            /*!< read FIFO request */
+    kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK,           /*!< reponse CRC error */
+    kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK,               /*!< data CRC error */
+    kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK,             /*!< response timeout */
+    kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK,            /*!< read data timeout */
+    kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */
+    kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK,                  /*!< indicate the FIFO underrun or overrun error */
+    kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK,           /*!< hardware lock write error */
+    kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK,           /*!< start bit error */
+    kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK,                 /*!< indicate the auto command done */
+    kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK,             /*!< end bit error */
+    kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK,     /*!< interrupt from the SDIO card */
+
+    kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError |
+                                  kSDIF_ResponseTimeout |
+                                  kSDIF_HardwareLockError, /*!< command transfer status collection*/
+    kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest |
+                               kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout |
+                               kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError |
+                               kSDIF_AutoCmdDone, /*!< data transfer status collection */
+    kSDIF_DataTransferError =
+        kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout,
+    kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */
+
+};
+
+/*! @brief define the internal DMA status flags */
+enum _sdif_dma_status
+{
+    kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */
+    kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK,  /*!< DMA revieve finished for one DMA descriptor */
+    kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK,           /*!< DMA fatal bus error */
+    kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK,    /*!< DMA descriptor unavailable */
+    kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK,        /*!< card error summary */
+    kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK,     /*!< normal interrupt summary */
+    kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK,   /*!< abnormal interrupt summary*/
+
+    kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError |
+                         kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary |
+                         kSDIF_AbnormalInterruptSummary,
+
+};
+
+/*! @brief define the internal DMA descriptor flag */
+enum _sdif_dma_descriptor_flag
+{
+    kSDIF_DisableCompleteInterrupt = 0x2U,     /*!< disable the complete interrupt flag for the ends
+                                                in the buffer pointed to by this descriptor*/
+    kSDIF_DMADescriptorDataBufferEnd = 0x4U,   /*!< indicate this descriptor contain the last data buffer of data */
+    kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer
+                                                 of data,if first buffer size is 0,next descriptor contain
+                                                 the begaining of the data*/
+    kSDIF_DMASecondAddrChained = 0x10U,        /*!< indicate that the second addr in the descriptor is the
+                                               next descriptor addr not the data buffer */
+    kSDIF_DMADescriptorEnd = 0x20U,            /*!< indicate that the descriptor list reached its final descriptor*/
+    kSDIF_DMADescriptorOwnByDMA = 0x80000000U, /*!< indicate the descriptor is own by SD/MMC DMA */
+};
+
+/*! @brief define the internal DMA mode */
+typedef enum _sdif_dma_mode
+{
+    kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */
+    kSDIF_DualDMAMode = 0x02U,  /* dual mode is one descriptor with two buffer */
+} sdif_dma_mode_t;
+
+/*! @brief define the card work freq mode */
+enum _sdif_card_freq
+{
+    kSDIF_Freq50MHZ = 50000000U, /*!< 50MHZ mode*/
+    kSDIF_Freq400KHZ = 400000U,  /*!< identificatioin mode*/
+};
+
+/*! @brief define the clock pharse shift */
+enum _sdif_clock_pharse_shift
+{
+    kSDIF_ClcokPharseShift0,   /*!< clock pharse shift 0*/
+    kSDIF_ClcokPharseShift90,  /*!< clock pharse shift 90*/
+    kSDIF_ClcokPharseShift180, /*!< clock pharse shift 180*/
+    kSDIF_ClcokPharseShift270, /*!< clock pharse shift 270*/
+};
+
+/*! @brief define the internal DMA descriptor */
+typedef struct _sdif_dma_descriptor
+{
+    uint32_t dmaDesAttribute;           /*!< internal DMA attribute control and status */
+    uint32_t dmaDataBufferSize;         /*!< internal DMA transfer buffer size control */
+    const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */
+    const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */
+
+} sdif_dma_descriptor_t;
+
+/*! @brief Defines the internal DMA config structure. */
+typedef struct _sdif_dma_config
+{
+    bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will
+                             use only SINGLE, INCR4, INCR8 or INCR16 during start of
+                             normal burst transfers. When reset, the AHB will use SINGLE
+                             and INCR burst transfer operations */
+
+    sdif_dma_mode_t mode; /*!< define the DMA mode */
+
+    uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor
+                               this field is special for dual DMA mode */
+
+    uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/
+    uint32_t dmaDesBufferLen;        /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the
+                                        dma descriptor buffer length if it is bigger enough for your transfer */
+
+} sdif_dma_config_t;
+
+/*!
+ * @brief Card data descriptor
+ */
+typedef struct _sdif_data
+{
+    bool streamTransfer;      /*!< indicate this is a stream data transfer command */
+    bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */
+    bool enableIgnoreError;   /*!< indicate if enable ignore error when transfer data */
+
+    size_t blockSize;       /*!< Block size, take care when config this parameter */
+    uint32_t blockCount;    /*!< Block count */
+    uint32_t *rxData;       /*!< data buffer to recieve */
+    const uint32_t *txData; /*!< data buffer to transfer */
+} sdif_data_t;
+
+/*!
+ * @brief Card command descriptor
+ *
+ * Define card command-related attribute.
+ */
+typedef struct _sdif_command
+{
+    uint32_t index;              /*!< Command index */
+    uint32_t argument;           /*!< Command argument */
+    uint32_t response[4U];       /*!< Response for this command */
+    uint32_t type;               /*!< define the command type */
+    uint32_t responseType;       /*!< Command response type */
+    uint32_t flags;              /*!< Cmd flags */
+    uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when
+                                    recieve the cmd response */
+} sdif_command_t;
+
+/*! @brief Transfer state */
+typedef struct _sdif_transfer
+{
+    sdif_data_t *data;       /*!< Data to transfer */
+    sdif_command_t *command; /*!< Command to send */
+} sdif_transfer_t;
+
+/*! @brief Data structure to initialize the sdif */
+typedef struct _sdif_config
+{
+    uint8_t responseTimeout;        /*!< command reponse timeout value */
+    uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in
+                                        card detect logic,typical value is 5-25ms */
+    uint32_t endianMode;            /*!< define endian mode ,this field is not used in this
+                                    module actually, keep for compatible with middleware*/
+    uint32_t dataTimeout;           /*!< data timeout value  */
+} sdif_config_t;
+
+/*!
+ * @brief SDIF capability information.
+ * Defines a structure to get the capability information of SDIF.
+ */
+typedef struct _sdif_capability
+{
+    uint32_t sdVersion;      /*!< support SD card/sdio version */
+    uint32_t mmcVersion;     /*!< support emmc card version */
+    uint32_t maxBlockLength; /*!< Maximum block length united as byte */
+    uint32_t maxBlockCount;  /*!< Maximum byte count can be transfered */
+    uint32_t flags;          /*!< Capability flags to indicate the support information */
+} sdif_capability_t;
+
+/*! @brief sdif callback functions. */
+typedef struct _sdif_transfer_callback
+{
+    void (*SDIOInterrupt)(void);     /*!< SDIO card interrupt occurs */
+    void (*DMADesUnavailable)(void); /*!< DMA descriptor unavailable */
+    void (*CommandReload)(void);     /*!< command buffer full,need re-load */
+    void (*TransferComplete)(SDIF_Type *base,
+                             void *handle,
+                             status_t status,
+                             void *userData); /*!< Transfer complete callback */
+} sdif_transfer_callback_t;
+
+/*!
+ * @brief sdif handle
+ *
+ * Defines the structure to save the sdif state information and callback function. The detail interrupt status when
+ * send command or transfer data can be obtained from interruptFlags field by using mask defined in
+ * sdif_interrupt_flag_t;
+ * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
+ */
+typedef struct _sdif_handle
+{
+    /* Transfer parameter */
+    sdif_data_t *volatile data;       /*!< Data to transfer */
+    sdif_command_t *volatile command; /*!< Command to send */
+
+    /* Transfer status */
+    volatile uint32_t interruptFlags;    /*!< Interrupt flags of last transaction */
+    volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/
+    volatile uint32_t transferredWords;  /*!< Words transferred by polling way */
+
+    /* Callback functions */
+    sdif_transfer_callback_t callback; /*!< Callback function */
+    void *userData;                    /*!< Parameter for transfer complete callback */
+} sdif_handle_t;
+
+/*! @brief sdif transfer function. */
+typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content);
+
+/*! @brief sdif host descriptor */
+typedef struct _sdif_host
+{
+    SDIF_Type *base;                   /*!< sdif peripheral base address */
+    uint32_t sourceClock_Hz;           /*!< sdif source clock frequency united in Hz */
+    sdif_config_t config;              /*!< sdif configuration */
+    sdif_transfer_function_t transfer; /*!< sdif transfer function */
+    sdif_capability_t capability;      /*!< sdif capability information */
+} sdif_host_t;
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief SDIF module initialization function.
+ *
+ * Configures the SDIF according to the user configuration.
+ * @param base SDIF peripheral base address.
+ * @param config SDIF configuration information.
+ */
+void SDIF_Init(SDIF_Type *base, sdif_config_t *config);
+
+/*!
+ * @brief SDIF module deinit function.
+ * user should call this function follow with IP reset
+ * @param base SDIF peripheral base address.
+ */
+void SDIF_Deinit(SDIF_Type *base);
+
+/*!
+ * @brief SDIF send initialize 80 clocks for SD card after initilize
+ * @param base SDIF peripheral base address.
+ * @param timeout value
+ */
+bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout);
+
+/*!
+ * @brief SDIF module detect card insert status function.
+ * @param base SDIF peripheral base address.
+ * @param data3 indicate use data3 as card insert detect pin
+ * will return the data3 PIN status in this condition
+ */
+static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
+{
+    if (data3)
+    {
+        return base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK;
+    }
+    else
+    {
+        return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF module enable/disable card clock.
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK;
+    }
+    else
+    {
+        base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF module enable/disable module disable the card clock
+ * to enter low power mode when card is idle,for SDIF cards, if
+ * interrupts must be detected, clock should not be stopped
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK;
+    }
+    else
+    {
+        base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK;
+    }
+}
+
+/*!
+ * @brief Sets the card bus clock frequency.
+ *
+ * @param base SDIF peripheral base address.
+ * @param srcClock_Hz SDIF source clock frequency united in Hz.
+ * @param target_HZ card bus clock frequency united in Hz.
+ * @return The nearest frequency of busClock_Hz configured to SD bus.
+ */
+uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ);
+
+/*!
+ * @brief reset the different block of the interface.
+ * @param base SDIF peripheral base address.
+ * @param mask indicate which block to reset.
+ * @param timeout value,set to wait the bit self clear
+ * @return reset result.
+ */
+bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout);
+
+/*!
+ * @brief enable/disable the card power.
+ * once turn power on, software should wait for regulator/switch
+ * ramp-up time before trying to initialize card.
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag.
+ */
+static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK;
+    }
+    else
+    {
+        base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief get the card write protect status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base)
+{
+    return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK;
+}
+
+/*!
+ * @brief set card data bus width
+ * @param base SDIF peripheral base address.
+ * @param data bus width type
+ */
+static inline void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type)
+{
+    base->CTYPE = type;
+}
+
+/*!
+ * @brief toggle state on hardware reset PIN
+ * This is used which card has a reset PIN typically.
+ * @param base SDIF peripheral base address.
+ */
+static inline void SDIF_AssertHardwareReset(SDIF_Type *base)
+{
+    base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK;
+}
+
+/*!
+ * @brief send command to the card
+ * @param base SDIF peripheral base address.
+ * @param command configuration collection
+ * @param timeout value
+ * @return command excute status
+ */
+status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout);
+
+/*!
+ * @brief SDIF enable/disable global interrupt
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF enable interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask
+ */
+static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->INTMASK |= mask;
+}
+
+/*!
+ * @brief SDIF disable interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask
+ */
+static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->INTMASK &= ~mask;
+}
+
+/*!
+ * @brief SDIF get interrupt status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base)
+{
+    return base->MINTSTS;
+}
+
+/*!
+ * @brief SDIF clear interrupt status
+ * @param base SDIF peripheral base address.
+ * @param status mask to clear
+ */
+static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask)
+{
+    base->RINTSTS &= mask;
+}
+
+/*!
+ * @brief Creates the SDIF handle.
+ * register call back function for interrupt and enable the interrupt
+ * @param base SDIF peripheral base address.
+ * @param handle SDIF handle pointer.
+ * @param callback Structure pointer to contain all callback functions.
+ * @param userData Callback function parameter.
+ */
+void SDIF_TransferCreateHandle(SDIF_Type *base,
+                               sdif_handle_t *handle,
+                               sdif_transfer_callback_t *callback,
+                               void *userData);
+
+/*!
+ * @brief SDIF enable DMA interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask to set
+ */
+static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->IDINTEN |= mask;
+}
+
+/*!
+ * @brief SDIF disable DMA interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask to clear
+ */
+static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->IDINTEN &= ~mask;
+}
+
+/*!
+ * @brief SDIF get internal DMA status
+ * @param base SDIF peripheral base address.
+ * @return the internal DMA status register
+ */
+static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base)
+{
+    return base->IDSTS;
+}
+
+/*!
+ * @brief SDIF clear internal DMA status
+ * @param base SDIF peripheral base address.
+ * @param status mask to clear
+ */
+static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask)
+{
+    base->IDSTS &= mask;
+}
+
+/*!
+ * @brief SDIF internal DMA config function
+ * @param base SDIF peripheral base address.
+ * @param internal DMA configuration collection
+ * @param data buffer pointer
+ * @param data buffer size
+ */
+status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize);
+
+/*!
+ * @brief SDIF send read wait to SDIF card function
+ * @param base SDIF peripheral base address.
+ */
+static inline void SDIF_SendReadWait(SDIF_Type *base)
+{
+    base->CTRL |= SDIF_CTRL_READ_WAIT_MASK;
+}
+
+/*!
+ * @brief SDIF abort the read data when SDIF card is in suspend state
+ * Once assert this bit,data state machine will be reset which is waiting for the
+ * next blocking data,used in SDIO card suspend sequence,should call after suspend
+ * cmd send
+ * @param base SDIF peripheral base address.
+ * @param timeout value to wait this bit self clear which indicate the data machine
+ * reset to idle
+ */
+bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout);
+
+/*!
+ * @brief SDIF enable/disable CE-ATA card interrupt
+ * this bit should set together with the card register
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF transfer function data/cmd in a non-blocking way
+ * this API should be use in interrupt mode, when use this API user
+ * must call SDIF_TransferCreateHandle first, all status check through
+ * interrupt
+ * @param base SDIF peripheral base address.
+ * @param sdif handle
+ * @param DMA config structure
+ *  This parameter can be config as:
+ *      1. NULL
+            In this condition, polling transfer mode is selected
+        2. avaliable DMA config
+            In this condition, DMA transfer mode is selected
+ * @param sdif transfer configuration collection
+ */
+status_t SDIF_TransferNonBlocking(SDIF_Type *base,
+                                  sdif_handle_t *handle,
+                                  sdif_dma_config_t *dmaConfig,
+                                  sdif_transfer_t *transfer);
+
+/*!
+ * @brief SDIF transfer function data/cmd in a blocking way
+ * @param base SDIF peripheral base address.
+ * @param DMA config structure
+ *       1. NULL
+ *           In this condition, polling transfer mode is selected
+ *       2. avaliable DMA config
+ *           In this condition, DMA transfer mode is selected
+ * @param sdif transfer configuration collection
+ */
+status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer);
+
+/*!
+ * @brief SDIF release the DMA descriptor to DMA engine
+ * this function should be called when DMA descriptor unavailable status occurs
+ * @param base SDIF peripheral base address.
+ * @param sdif DMA config pointer
+ */
+status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig);
+
+/*!
+ * @brief SDIF return the controller capability
+ * @param base SDIF peripheral base address.
+ * @param sdif capability pointer
+ */
+void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability);
+
+/*!
+ * @brief SDIF return the controller status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base)
+{
+    return base->STATUS;
+}
+
+/*!
+ * @brief SDIF send command  complete signal disable to CE-ATA card
+ * @param base SDIF peripheral base address.
+ * @param send auto stop flag
+ */
+static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop)
+{
+    if (withAutoStop)
+    {
+        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK;
+    }
+    else
+    {
+        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF config the clock delay
+ * This function is used to config the cclk_in delay to
+ * sample and drvive the data ,should meet the min setup
+ * time and hold time, and user need to config this paramter
+ * according to your board setting
+ * @param target freq work mode
+ * @param clock divider which is used to decide if use pharse shift for delay
+ */
+void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif /* _FSL_sdif_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/* Note:  FIFOCFG[SIZE] has always value 1 = 8 items depth */
+#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3)
+
+/* Convert transfer count to transfer bytes. dataWidth is a
+ * range <0,15>. Range <8,15> represents 2B transfer */
+#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U))
+#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U))
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief internal SPI config array */
+static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0};
+
+/*! @brief Array to map SPI instance number to base address. */
+static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS;
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the FLEXCOMM */
+uint32_t SPI_GetInstance(SPI_Type *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++)
+    {
+        if ((uint32_t)base == s_spiBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+void *SPI_GetConfig(SPI_Type *base)
+{
+    int32_t instance;
+    instance = SPI_GetInstance(base);
+    if (instance < 0)
+    {
+        return NULL;
+    }
+    return &g_configs[instance];
+}
+
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableLoopback = false;
+    config->enableMaster = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->baudRate_Bps = 500000U;
+    config->dataWidth = kSPI_Data8Bits;
+    config->sselNum = kSPI_Ssel0;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
+{
+    int32_t result = 0, instance = 0;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to SPI mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* set divider */
+    result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+    /* get instance number */
+    instance = SPI_GetInstance(base);
+    assert(instance >= 0);
+
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    /* master mode */
+    tmp |= SPI_CFG_MASTER(1);
+    /* loopback */
+    tmp |= SPI_CFG_LOOP(config->enableLoopback);
+    base->CFG = tmp;
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    g_configs[instance].sselNum = config->sselNum;
+    /* enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+
+    SPI_Enable(base, config->enableMaster);
+    return kStatus_Success;
+}
+
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableSlave = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->dataWidth = kSPI_Data8Bits;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
+{
+    int32_t result = 0, instance;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config)));
+    if ((NULL == base) || (NULL == config))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* configure flexcomm to SPI, enable clock gate */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    instance = SPI_GetInstance(base);
+
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    base->CFG = tmp;
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    /* empty and enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+
+    SPI_Enable(base, config->enableSlave);
+    return kStatus_Success;
+}
+
+void SPI_Deinit(SPI_Type *base)
+{
+    /* Assert arguments */
+    assert(NULL != base);
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK |
+                         SPI_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(SPI_CFG_ENABLE_MASK);
+}
+
+void SPI_EnableTxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK;
+    }
+}
+
+void SPI_EnableRxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK;
+    }
+}
+
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* calculate baudrate */
+    tmp = (srcClock_Hz / baudrate_Bps) - 1;
+    if (tmp > 0xFFFF)
+    {
+        return kStatus_SPI_BaudrateNotSupport;
+    }
+    base->DIV &= ~SPI_DIV_DIVVAL_MASK;
+    base->DIV |= SPI_DIV_DIVVAL(tmp);
+    return kStatus_Success;
+}
+
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags)
+{
+    uint32_t control = 0;
+    int32_t instance;
+
+    /* check params */
+    assert(NULL != base);
+    /* get and check instance */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return;
+    }
+
+    /* set data width */
+    control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth);
+    /* set sssel */
+    control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* mask configFlags */
+    control |= (configFlags & SPI_FIFOWR_FLAGS_MASK);
+    /* control should not affect lower 16 bits */
+    assert(!(control & 0xFFFF));
+    base->FIFOWR = data | control;
+}
+
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* get flexcomm instance by 'base' param */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* Initialize the handle */
+    if (base->CFG & SPI_CFG_MASTER_MASK)
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle);
+    }
+    else
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle);
+    }
+
+    handle->dataWidth = g_configs[instance].dataWidth;
+    /* in slave mode, the sselNum is not important */
+    handle->sselNum = g_configs[instance].sselNum;
+    handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base);
+    handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base);
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable SPI NVIC */
+    EnableIRQ(s_spiIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    uint32_t tx_ctrl = 0, last_ctrl = 0;
+    uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth;
+    uint32_t toReceiveCount = 0;
+    uint8_t *txData, *rxData;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    txData = xfer->txData;
+    rxData = xfer->rxData;
+    txRemainingBytes = txData ? xfer->dataSize : 0;
+    rxRemainingBytes = rxData ? xfer->dataSize : 0;
+
+    instance = SPI_GetInstance(base);
+    assert(instance >= 0);
+    dataWidth = g_configs[instance].dataWidth;
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* clear tx/rx errors and empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* set width of data - range asserted at entry */
+    tx_ctrl |= SPI_FIFOWR_LEN(dataWidth);
+    /* end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    /* last index of loop */
+    while (txRemainingBytes || rxRemainingBytes || toReceiveCount)
+    {
+        /* if rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (rxRemainingBytes)
+            {
+                *(rxData++) = tmp32;
+                rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (dataWidth > 8)
+                {
+                    *(rxData++) = tmp32 >> 8;
+                    rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            toReceiveCount -= 1;
+        }
+        /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) &&
+            ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (txRemainingBytes)
+            {
+                tmp32 = *(txData++);
+                txRemainingBytes--;
+                /* write 16 bit at once */
+                if (dataWidth > 8)
+                {
+                    tmp32 |= ((uint32_t)(*(txData++))) << 8U;
+                    txRemainingBytes--;
+                }
+                if (!txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            toReceiveCount += 1;
+        }
+    }
+    /* wait if TX FIFO of previous transfer is not empty */
+    while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK))
+    {
+    }
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
+{
+    /* check params */
+    assert(
+        !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if SPI is busy */
+    if (handle->state == kStatus_SPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+
+    /* Set the handle information */
+    handle->txData = xfer->txData;
+    handle->rxData = xfer->rxData;
+    /* set count */
+    handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0;
+    handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0;
+    handle->totalByteCount = xfer->dataSize;
+    /* other options */
+    handle->toReceiveCount = 0;
+    handle->configFlags = xfer->configFlags;
+    /* Set the SPI state to busy */
+    handle->state = kStatus_SPI_Busy;
+    /* clear FIFOs when transfer starts */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */
+    base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK;
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kStatus_SPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->totalByteCount - handle->rxRemainingBytes;
+    return kStatus_Success;
+}
+
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupt requests*/
+    base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK);
+    /* Empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+
+    handle->state = kStatus_SPI_Idle;
+    handle->txRemainingBytes = 0;
+    handle->rxRemainingBytes = 0;
+}
+
+static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32;
+    bool loopContinue;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData)));
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum));
+    /* set width of data */
+    tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth);
+    /* end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    do
+    {
+        loopContinue = false;
+
+        /* rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (handle->rxRemainingBytes)
+            {
+                /* low byte must go first */
+                *(handle->rxData++) = tmp32;
+                handle->rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    *(handle->rxData++) = tmp32 >> 8;
+                    handle->rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            handle->toReceiveCount -= 1;
+            loopContinue = true;
+        }
+
+        /* - txFIFO is not full
+         * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO
+         * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer
+         */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) &&
+            ((handle->txRemainingBytes) ||
+             (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (handle->txRemainingBytes)
+            {
+                /* low byte must go first */
+                tmp32 = *(handle->txData++);
+                handle->txRemainingBytes--;
+                /* write 16 bit at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U;
+                    handle->txRemainingBytes--;
+                }
+                /* last transfer */
+                if (!handle->txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            /* increase number of expected data to receive */
+            handle->toReceiveCount += 1;
+            loopContinue = true;
+        }
+    } while (loopContinue);
+}
+
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert((NULL != base) && (NULL != handle));
+
+    /* IRQ behaviour:
+     * - first interrupt is triggered by empty txFIFO. The transfer function
+     *   then tries empty rxFIFO and fill txFIFO interleaved that results to
+     *   strategy to process as many items as possible.
+     * - the next IRQs can be:
+     *      rxIRQ from nonempty rxFIFO which requires to empty rxFIFO.
+     *      txIRQ from empty txFIFO which requires to refill txFIFO.
+     * - last interrupt is triggered by empty txFIFO. The last state is
+     *   known by empty rxBuffer and txBuffer. If there is nothing to receive
+     *   or send - both operations have been finished and interrupts can be
+     *   disabled.
+     */
+
+    /* Data to send or read or expected to receive */
+    if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount))
+    {
+        /* Transmit or receive data */
+        SPI_TransferHandleIRQInternal(base, handle);
+        /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and
+         * enable txIRQ to confirm when txFIFO becomes empty */
+        if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount))
+        {
+            base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK);
+            base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK;
+        }
+        else
+        {
+            uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes);
+            /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data,
+             * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */
+            if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount))
+            {
+                base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK;
+            }
+            /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel.
+             * Cannot clear rxFIFO, txFIFO might be still active */
+            if (rxRemainingCount == 0)
+            {
+                if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) &&
+                    (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1);
+                }
+            }
+            /* Expected to receive less data than rxLevel value, we have to update rxLevel */
+            else
+            {
+                if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */
+        base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK;
+        base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) |
+                         SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark);
+        /* set idle state and call user callback */
+        handle->state = kStatus_SPI_Idle;
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, handle->state, handle->userData);
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_H_
+#define _FSL_SPI_H_
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*!
+ * @addtogroup spi_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define SPI_DUMMYDATA (0xFFFF)
+#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
+#define SPI_CTRLMASK (0xFFFF0000)
+
+#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
+#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
+#define SPI_DEASSERT_ALL (0xF0000)
+
+#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
+
+#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
+#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief SPI transfer option.*/
+typedef enum _spi_xfer_option {
+    kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK),  /*!< Delay chip select */
+    kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
+} spi_xfer_option_t;
+
+/*! @brief SPI data shifter direction options.*/
+typedef enum _spi_shift_direction {
+    kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
+    kSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit. */
+} spi_shift_direction_t;
+
+/*! @brief SPI clock polarity configuration.*/
+typedef enum _spi_clock_polarity {
+    kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
+    kSPI_ClockPolarityActiveLow          /*!< Active-low SPI clock (idles high). */
+} spi_clock_polarity_t;
+
+/*! @brief SPI clock phase configuration.*/
+typedef enum _spi_clock_phase {
+    kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
+                                         *   cycle of a data transfer. */
+    kSPI_ClockPhaseSecondEdge        /*!< First edge on SCK occurs at the start of the
+                                         *   first cycle of a data transfer. */
+} spi_clock_phase_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _spi_txfifo_watermark {
+    kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
+    kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
+    kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
+    kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
+    kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
+    kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
+    kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
+    kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
+} spi_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _spi_rxfifo_watermark {
+    kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
+    kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
+    kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
+    kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
+    kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
+    kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
+    kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
+    kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
+} spi_rxfifo_watermark_t;
+
+/*! @brief Transfer data width */
+typedef enum _spi_data_width {
+    kSPI_Data4Bits = 3,   /*!< 4 bits data width */
+    kSPI_Data5Bits = 4,   /*!< 5 bits data width */
+    kSPI_Data6Bits = 5,   /*!< 6 bits data width */
+    kSPI_Data7Bits = 6,   /*!< 7 bits data width */
+    kSPI_Data8Bits = 7,   /*!< 8 bits data width */
+    kSPI_Data9Bits = 8,   /*!< 9 bits data width */
+    kSPI_Data10Bits = 9,  /*!< 10 bits data width */
+    kSPI_Data11Bits = 10, /*!< 11 bits data width */
+    kSPI_Data12Bits = 11, /*!< 12 bits data width */
+    kSPI_Data13Bits = 12, /*!< 13 bits data width */
+    kSPI_Data14Bits = 13, /*!< 14 bits data width */
+    kSPI_Data15Bits = 14, /*!< 15 bits data width */
+    kSPI_Data16Bits = 15, /*!< 16 bits data width */
+} spi_data_width_t;
+
+/*! @brief Slave select */
+typedef enum _spi_ssel {
+    kSPI_Ssel0 = 0, /*!< Slave select 0 */
+    kSPI_Ssel1 = 1, /*!< Slave select 1 */
+    kSPI_Ssel2 = 2, /*!< Slave select 2 */
+    kSPI_Ssel3 = 3, /*!< Slave select 3 */
+} spi_ssel_t;
+
+/*! @brief SPI master user configure structure.*/
+typedef struct _spi_master_config
+{
+    bool enableLoopback;                /*!< Enable loopback for test purpose */
+    bool enableMaster;                  /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    uint32_t baudRate_Bps;              /*!< Baud Rate for SPI in Hz */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_ssel_t sselNum;                 /*!< Slave select number */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_master_config_t;
+
+/*! @brief SPI slave user configure structure.*/
+typedef struct _spi_slave_config
+{
+    bool enableSlave;                   /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_slave_config_t;
+
+/*! @brief SPI transfer status.*/
+enum _spi_status
+{
+    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0),  /*!< SPI bus is busy */
+    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1),  /*!< SPI is idle */
+    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI  error */
+    kStatus_SPI_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief SPI interrupt sources.*/
+enum _spi_interrupt_enable
+{
+    kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
+    kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
+};
+
+/*! @brief SPI status flags.*/
+enum _spi_statusflags
+{
+    kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK,       /*!< txFifo is empty */
+    kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK,   /*!< txFifo is not full */
+    kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
+    kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK,         /*!< rxFIFO is full */
+};
+
+/*! @brief SPI transfer structure */
+typedef struct _spi_transfer
+{
+    uint8_t *txData;      /*!< Send buffer */
+    uint8_t *rxData;      /*!< Receive buffer */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    size_t dataSize;      /*!< Transfer bytes */
+} spi_transfer_t;
+
+/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
+typedef struct _spi_config
+{
+    spi_data_width_t dataWidth;
+    spi_ssel_t sselNum;
+} spi_config_t;
+
+/*! @brief  Master handle type */
+typedef struct _spi_master_handle spi_master_handle_t;
+
+/*! @brief  Slave handle type */
+typedef spi_master_handle_t spi_slave_handle_t;
+
+/*! @brief SPI master callback for finished transmit */
+typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI slave callback for finished transmit */
+typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI transfer handle structure */
+struct _spi_master_handle
+{
+    uint8_t *volatile txData;         /*!< Transfer buffer */
+    uint8_t *volatile rxData;         /*!< Receive buffer */
+    volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
+    volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
+    volatile size_t toReceiveCount;   /*!< Receive data remaining in bytes */
+    size_t totalByteCount;            /*!< A number of transfer bytes */
+    volatile uint32_t state;          /*!< SPI internal state */
+    spi_master_callback_t callback;   /*!< SPI callback */
+    void *userData;                   /*!< Callback parameter */
+    uint8_t dataWidth;                /*!< Width of the data [Valid values: 1 to 16] */
+    uint8_t sselNum;      /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @brief Returns instance number for SPI peripheral base address. */
+uint32_t SPI_GetInstance(SPI_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief  Sets the SPI master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
+ * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
+ * some fields of the structure before calling SPI_MasterInit(). After calling this API,
+ * the master is ready to transfer.
+ * Example:
+   @code
+   spi_master_config_t config;
+   SPI_MasterGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to master config structure
+ */
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with master configuration.
+ *
+ * The configuration structure can be filled by user from scratch, or be set with default
+ * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+   spi_master_config_t config = {
+   .baudRate_Bps = 400000,
+   ...
+   };
+   SPI_MasterInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to master configuration structure
+ * @param srcClock_Hz Source clock frequency.
+ */
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief  Sets the SPI slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
+ * Modify some fields of the structure before calling SPI_SlaveInit().
+ * Example:
+   @code
+   spi_slave_config_t config;
+   SPI_SlaveGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to slave configuration structure
+ */
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with slave configuration.
+ *
+ * The configuration structure can be filled by user from scratch or be set with
+ * default values by SPI_SlaveGetDefaultConfig().
+ * After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+    spi_slave_config_t config = {
+    .polarity = flexSPIClockPolarity_ActiveHigh;
+    .phase = flexSPIClockPhase_FirstEdge;
+    .direction = flexSPIMsbFirst;
+    ...
+    };
+    SPI_SlaveInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to slave configuration structure
+ */
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
+
+/*!
+ * @brief De-initializes the SPI.
+ *
+ * Calling this API resets the SPI module, gates the SPI clock.
+ * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
+ *
+ * @param base SPI base pointer
+ */
+void SPI_Deinit(SPI_Type *base);
+
+/*!
+ * @brief Enable or disable the SPI Master or Slave
+ * @param base SPI base pointer
+ * @param enable or disable ( true = enable, false = disable)
+ */
+static inline void SPI_Enable(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= SPI_CFG_ENABLE_MASK;
+    }
+    else
+    {
+        base->CFG &= ~SPI_CFG_ENABLE_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the status flag.
+ *
+ * @param base SPI base pointer
+ * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
+ */
+static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFOSTAT;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENSET = irqs;
+}
+
+/*!
+ * @brief Disables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENCLR = irqs;
+}
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMA request from SPI txFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableTxDMA(SPI_Type *base, bool enable);
+
+/*!
+ * @brief Enables the DMA request from SPI rxFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableRxDMA(SPI_Type *base, bool enable);
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the baud rate for SPI transfer. This is only used in master.
+ *
+ * @param base SPI base pointer
+ * @param baudrate_Bps baud rate needed in Hz.
+ * @param srcClock_Hz SPI source clock frequency in Hz.
+ */
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Writes a data into the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @param data needs to be write.
+ * @param configFlags transfer configuration options @ref spi_xfer_option_t
+ */
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
+
+/*!
+ * @brief Gets a data from the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @return Data in the register.
+ */
+static inline uint32_t SPI_ReadData(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFORD;
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPI master handle.
+ *
+ * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData);
+
+/*!
+ * @brief Transfers a block of data using a polling method.
+ *
+ * @param base SPI base pointer
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer count.
+ *
+ * This function gets the master transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief SPI master aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Interrupts the handler for the SPI.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Initializes the SPI slave handle.
+ *
+ * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                                     spi_slave_handle_t *handle,
+                                                     spi_slave_callback_t callback,
+                                                     void *userData)
+{
+    return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
+}
+
+/*!
+ * @brief Performs a non-blocking SPI slave interrupt transfer.
+ *
+ * @note The API returns immediately after the transfer initialization is finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferNonBlocking(base, handle, xfer);
+}
+
+/*!
+ * @brief Gets the slave transfer count.
+ *
+ * This function gets the slave transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count);
+}
+
+/*!
+ * @brief SPI slave aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
+ */
+static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle);
+}
+
+/*!
+ * @brief Interrupts a handler for the SPI slave.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ */
+static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferHandleIRQ(base, handle);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi_dma.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
+typedef struct _spi_dma_private_handle
+{
+    SPI_Type *base;
+    spi_dma_handle_t *handle;
+} spi_dma_private_handle_t;
+
+/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _spi_dma_states_t
+{
+    kSPI_Idle = 0x0, /*!< SPI is idle state */
+    kSPI_Busy        /*!< SPI is busy tranferring data. */
+};
+
+typedef struct _spi_dma_txdummy
+{
+    uint32_t lastWord;
+    uint32_t word;
+} spi_dma_txdummy_t;
+
+/*<! Private handle only used for internally. */
+static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+* @brief SPI private function to return SPI configuration
+*
+* @param base SPI base address.
+*/
+void *SPI_GetConfig(SPI_Type *base);
+
+/*!
+ * @brief DMA callback function for SPI send transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief DMA callback function for SPI receive transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#endif
+
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint16_t s_rxDummy;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint16_t s_rxDummy;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint16_t s_rxDummy;
+#endif
+
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
+{
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0;
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0;
+}
+
+static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
+{
+    *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum)));
+    /* set width of data - range asserted at entry */
+    *fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
+}
+
+static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl)
+{
+    assert(!(fifo == NULL));
+    if (fifo == NULL)
+    {
+        return;
+    }
+    /* CS deassert and CS delay are relevant only for last word */
+    uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK));
+    uint32_t i = 0;
+    for (; i + 1 < count; i++)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U);
+    }
+    if (i < count)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U);
+    }
+}
+
+static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
+{
+    *dummy = SPI_DUMMYDATA;
+    XferToFifoWR(xfer, dummy);
+    SpiConfigToFifoWR(spi_config_p, dummy);
+}
+
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = SPI_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set spi base to handle */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle */
+    handle->state = kSPI_Idle;
+
+    /* Set handle to global state */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
+    DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    status_t result = kStatus_Success;
+    spi_config_t *spi_config_p;
+
+    assert(!((NULL == handle) || (NULL == xfer)));
+    if ((NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* txData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))));
+    if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* rxData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))));
+    if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* byte size is zero or not aligned to sizeof(uint32_t) */
+    assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))));
+    if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* cannot get instance from base address */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if the device is busy */
+    if (handle->state == kSPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+    else
+    {
+        uint32_t tmp;
+        dma_transfer_config_t xferConfig = {0};
+        spi_config_p = (spi_config_t *)SPI_GetConfig(base);
+
+        handle->state = kStatus_SPI_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* receive */
+        SPI_EnableRxDMA(base, true);
+        if (xfer->rxData)
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_PeripheralToMemory, NULL);
+        }
+        else
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_StaticToStatic, NULL);
+        }
+        DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
+        handle->rxInProgress = true;
+        DMA_StartTransfer(handle->rxHandle);
+
+        /* transmit */
+        SPI_EnableTxDMA(base, true);
+        if (xfer->txData)
+        {
+            tmp = 0;
+            XferToFifoWR(xfer, &tmp);
+            SpiConfigToFifoWR(spi_config_p, &tmp);
+            PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp);
+            DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+        }
+        else
+        {
+            if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t)))
+            {
+                dma_xfercfg_t tmp_xfercfg = { 0 };
+                tmp_xfercfg.valid = true;
+                tmp_xfercfg.swtrig = true;
+                tmp_xfercfg.intA = true;
+                tmp_xfercfg.byteWidth = sizeof(uint32_t);
+                tmp_xfercfg.srcInc = 0;
+                tmp_xfercfg.dstInc = 0;
+                tmp_xfercfg.transferCount = 1;
+                /* create chained descriptor to transmit last word */
+                SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p);
+                DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
+                                     (uint32_t *)&base->FIFOWR, NULL);
+                /* use common API to setup first descriptor */
+                SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic,
+                                    &s_spi_descriptor_table[instance]);
+                /* disable interrupts for first descriptor
+                 * to avoid calling callback twice */
+                xferConfig.xfercfg.intA = false;
+                xferConfig.xfercfg.intB = false;
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+            else
+            {
+                SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize, kDMA_StaticToStatic, NULL);
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+        }
+        handle->txInProgress = true;
+        DMA_StartTransfer(handle->txHandle);
+    }
+
+    return result;
+}
+
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->rxInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->txInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Stop tx transfer first */
+    DMA_AbortTransfer(handle->txHandle);
+    /* Then rx transfer */
+    DMA_AbortTransfer(handle->rxHandle);
+
+    /* Set the handle state */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+    handle->state = kSPI_Idle;
+}
+
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    size_t bytes;
+
+    bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
+
+    *count = handle->transferSize - bytes;
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_DMA_H_
+#define _FSL_SPI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_spi.h"
+
+/*!
+ * @addtogroup spi_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _spi_dma_handle spi_dma_handle_t;
+
+/*! @brief SPI DMA callback called at the end of transfer. */
+typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spi_dma_handle
+{
+    volatile bool txInProgress;  /*!< Send transfer finished */
+    volatile bool rxInProgress;  /*!< Receive transfer finished */
+    dma_handle_t *txHandle;      /*!< DMA handler for SPI send */
+    dma_handle_t *rxHandle;      /*!< DMA handler for SPI receive */
+    uint8_t bytesPerFrame;       /*!< Bytes in a frame for SPI tranfer */
+    spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;              /*!< User Data for SPI DMA callback */
+    uint32_t state;              /*!< Internal state of SPI DMA transfer */
+    size_t transferSize;         /*!< Bytes need to be transfer */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initialize the SPI master DMA handle.
+ *
+ * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle);
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Initialize the SPI slave DMA handle.
+ *
+ * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
+                                                        spi_dma_handle_t *handle,
+                                                        spi_dma_callback_t callback,
+                                                        void *userData,
+                                                        dma_handle_t *txHandle,
+                                                        dma_handle_t *rxHandle)
+{
+    return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferDMA(base, handle, xfer);
+}
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the master DMA transfer remaining bytes.
+ *
+ * This function gets the master DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    SPI_MasterTransferAbortDMA(base, handle);
+}
+
+/*!
+ * @brief Gets the slave DMA transfer remaining bytes.
+ *
+ * This function gets the slave DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCountDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spifi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the SPIFI instance from peripheral base address.
+ *
+ * @param base SPIFI peripheral base address.
+ * @return SPIFI instance.
+ */
+uint32_t SPIFI_GetInstance(SPIFI_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of SPIFI peripheral base address. */
+static SPIFI_Type *const s_spifiBases[] = SPIFI_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of SPIFI clock name. */
+static const clock_ip_name_t s_spifiClock[] = SPIFI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t SPIFI_GetInstance(SPIFI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_spifiBases); instance++)
+    {
+        if (s_spifiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_spifiBases));
+
+    return instance;
+}
+
+void SPIFI_GetDefaultConfig(spifi_config_t *config)
+{
+    config->timeout = 0xFFFFU;
+    config->csHighTime = 0xFU;
+    config->disablePrefetch = false;
+    config->disableCachePrefech = false;
+    config->isFeedbackClock = true;
+    config->spiMode = kSPIFI_SPISckLow;
+    config->isReadFullClockCycle = false;
+    config->dualMode = kSPIFI_QuadMode;
+}
+
+void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_EnableClock(s_spifiClock[SPIFI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the Command register */
+    SPIFI_ResetCommand(base);
+
+    /* Set time delay parameter */
+    base->CTRL = SPIFI_CTRL_TIMEOUT(config->timeout) | SPIFI_CTRL_CSHIGH(config->csHighTime) |
+                 SPIFI_CTRL_D_PRFTCH_DIS(config->disablePrefetch) | SPIFI_CTRL_MODE3(config->spiMode) |
+                 SPIFI_CTRL_PRFTCH_DIS(config->disableCachePrefech) | SPIFI_CTRL_DUAL(config->dualMode) |
+                 SPIFI_CTRL_RFCLK(config->isReadFullClockCycle) | SPIFI_CTRL_FBCLK(config->isFeedbackClock);
+}
+
+void SPIFI_Deinit(SPIFI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_DisableClock(s_spifiClock[SPIFI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd)
+{
+    /* Wait for the CMD and MCINT flag all be 0 */
+    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
+    {
+    }
+    base->CMD = SPIFI_CMD_DATALEN(cmd->dataLen) | SPIFI_CMD_POLL(cmd->isPollMode) | SPIFI_CMD_DOUT(cmd->direction) |
+                SPIFI_CMD_INTLEN(cmd->intermediateBytes) | SPIFI_CMD_FIELDFORM(cmd->format) |
+                SPIFI_CMD_FRAMEFORM(cmd->type) | SPIFI_CMD_OPCODE(cmd->opcode);
+
+    /* Wait for the command written */
+    while ((base->STAT & SPIFI_STAT_CMD_MASK) == 0U)
+    {
+    }
+}
+
+void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd)
+{
+    /* Wait for the CMD and MCINT flag all be 0 */
+    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
+    {
+    }
+
+    base->MCMD = SPIFI_MCMD_POLL(0U) | SPIFI_MCMD_DOUT(0U) | SPIFI_MCMD_INTLEN(cmd->intermediateBytes) |
+                 SPIFI_MCMD_FIELDFORM(cmd->format) | SPIFI_MCMD_FRAMEFORM(cmd->type) | SPIFI_MCMD_OPCODE(cmd->opcode);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPIFI_H_
+#define _FSL_SPIFI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup spifi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SPIFI driver version 2.0.0. */
+#define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Status structure of SPIFI.*/
+enum _status_t
+{
+    kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0),  /*!< SPIFI is in idle state  */
+    kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1),  /*!< SPIFI is busy */
+    kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */
+};
+
+/*! @brief SPIFI interrupt source */
+typedef enum _spifi_interrupt_enable
+{
+    kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */
+} spifi_interrupt_enable_t;
+
+/*! @brief SPIFI SPI mode select */
+typedef enum _spifi_spi_mode
+{
+    kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */
+    kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */
+} spifi_spi_mode_t;
+
+/*! @brief SPIFI dual mode select */
+typedef enum _spifi_dual_mode
+{
+    kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */
+    kSPIFI_DualMode = 0x1U  /*!< SPIFI uses IO1:0 */
+} spifi_dual_mode_t;
+
+/*! @brief SPIFI data direction */
+typedef enum _spifi_data_direction
+{
+    kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
+    kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
+} spifi_data_direction_t;
+
+/*! @brief SPIFI command opcode format */
+typedef enum _spifi_command_format
+{
+    kSPIFI_CommandAllSerial = 0x0,     /*!< All fields of command are serial. */
+    kSPIFI_CommandDataQuad = 0x1U,     /*!< Only data field is dual/quad, others are serial. */
+    kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
+    kSPIFI_CommandAllQuad = 0x3U       /*!< All fields of command are dual/quad mode. */
+} spifi_command_format_t;
+
+/*! @brief SPIFI command type */
+typedef enum _spifi_command_type
+{
+    kSPIFI_CommandOpcodeOnly = 0x1U,             /*!< Command only have opcode, no address field */
+    kSPIFI_CommandOpcodeAddrOneByte = 0x2U,      /*!< Command have opcode and also one byte address field */
+    kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U,     /*!< Command have opcode and also two bytes address field */
+    kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U,   /*!< Command have opcode and also three bytes address field. */
+    kSPIFI_CommandOpcodeAddrFourBytes = 0x5U,    /*!< Command have opcode and also four bytes address field */
+    kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
+    kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U   /*!< Command have no opcode and four bytes address field */
+} spifi_command_type_t;
+
+/*! @brief SPIFI status flags */
+enum _spifi_status_flags
+{
+    kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */
+    kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK,          /*!< Command write finished */
+    kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */
+};
+
+/*! @brief SPIFI command structure */
+typedef struct _spifi_command
+{
+    uint16_t dataLen;                 /*!< How many data bytes are needed in this command. */
+    bool isPollMode;                  /*!< For command need to read data from serial flash */
+    spifi_data_direction_t direction; /*!< Data direction of this command. */
+    uint8_t intermediateBytes;        /*!< How many intermediate bytes needed */
+    spifi_command_format_t format;    /*!< Command format */
+    spifi_command_type_t type;        /*!< Command type */
+    uint8_t opcode;                   /*!< Command opcode value */
+} spifi_command_t;
+
+/*!
+ * @brief SPIFI region configuration structure.
+ */
+typedef struct _spifi_config
+{
+    uint16_t timeout;           /*!< SPI transfer timeout, the unit is SCK cycles */
+    uint8_t csHighTime;         /*!< CS high time cycles */
+    bool disablePrefetch;       /*!< True means SPIFI will not attempt a speculative prefetch. */
+    bool disableCachePrefech;   /*!< Disable prefetch of cache line */
+    bool isFeedbackClock;       /*!< Is data sample uses feedback clock. */
+    spifi_spi_mode_t spiMode;   /*!< SPIFI spi mode select */
+    bool isReadFullClockCycle;  /*!< If enable read full clock cycle. */
+    spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */
+} spifi_config_t;
+
+/*! @brief Transfer structure for SPIFI */
+typedef struct _spifi_transfer
+{
+    uint8_t *data;   /*!< Pointer to data to transmit */
+    size_t dataSize; /*!< Bytes to be transmit */
+} spifi_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPIFI with the user configuration structure.
+ *
+ * This function configures the SPIFI module with the user-defined configuration.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ */
+void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config);
+
+/*!
+ * @brief Get SPIFI default configure settings.
+ *
+ * @param config  SPIFI config structure pointer.
+ */
+void SPIFI_GetDefaultConfig(spifi_config_t *config);
+
+/*!
+ * @brief Deinitializes the SPIFI regions.
+ *
+ * @param base     SPIFI peripheral base address.
+ */
+void SPIFI_Deinit(SPIFI_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Set SPIFI flash command.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param cmd      SPIFI command structure pointer.
+ */
+void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd);
+
+/*!
+ * @brief Set SPIFI command address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param addr     Address value for the command.
+ */
+static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr)
+{
+    base->ADDR = addr;
+}
+
+/*!
+ * @brief Set SPIFI intermediate data.
+ *
+ * Before writing a command wihch needs specific intermediate value, users shall call this function to write it.
+ * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As
+ * dummy cycle do not care about the value, no need to call this function.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param val      Intermediate data.
+ */
+static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val)
+{
+    base->IDATA = val;
+}
+
+/*!
+ * @brief Set SPIFI Cache limit value.
+ *
+ * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this
+ * function, to prevent such caching at and above the address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param val     Zero-based upper limit of cacheable memory.
+ */
+static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val)
+{
+    base->CLIMIT = val;
+}
+
+/*!
+ * @brief Reset the command field of SPIFI.
+ *
+ * This function is used to abort the current command or memory mode.
+ *
+ * @param base     SPIFI peripheral base address.
+ */
+static inline void SPIFI_ResetCommand(SPIFI_Type *base)
+{
+    base->STAT = SPIFI_STAT_RESET_MASK;
+    /* Wait for the RESET flag cleared by HW */
+    while (base->STAT & SPIFI_STAT_RESET_MASK)
+    {
+    }
+}
+
+/*!
+ * @brief Set SPIFI flash AHB read command.
+ *
+ * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall
+ * be called.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param cmd      SPIFI command structure pointer.
+ */
+void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd);
+
+/*!
+ * @brief Enable SPIFI interrupt.
+ *
+ * The interrupt is triggered only in command mode, and it means the command now is finished.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: spifi_interrupt_enable_t
+ */
+static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask)
+{
+    base->CTRL |= mask;
+}
+
+/*!
+ * @brief Disable SPIFI interrupt.
+ *
+ * The interrupt is triggered only in command mode, and it means the command now is finished.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: spifi_interrupt_enable_t
+ */
+static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask)
+{
+    base->CTRL &= ~mask;
+}
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get the status of all interrupt flags for SPIFI.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @return SPIFI flag status
+ */
+static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base)
+{
+    return base->STAT;
+}
+
+/* @}*/
+
+/*!
+ * @brief Enable or disable DMA request for SPIFI.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param enable   True means enable DMA and false means disable DMA.
+ */
+static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SPIFI_CTRL_DMAEN_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK;
+    }
+}
+
+/*!
+ * @brief  Gets the SPIFI data register address.
+ *
+ * This API is used to provide a transfer address for the SPIFI DMA transfer configuration.
+ *
+ * @param base SPIFI base pointer
+ * @return data register address
+ */
+static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base)
+{
+    return (uint32_t)(&(base->DATA));
+}
+
+/*!
+ * @brief Write a word data in address of SPIFI.
+ *
+ * Users can write a page or at least a word data into SPIFI address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param data     Data need be write.
+ */
+static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Read data from serial flash.
+ *
+ * Users should notice before call this function, the data length field in command register shall larger
+ * than 4, otherwise a hardfault will happen.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @return Data input from flash.
+ */
+static inline uint32_t SPIFI_ReadData(SPIFI_Type *base)
+{
+    return base->DATA;
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SPIFI_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spifi_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for spifi_dma_private_handle_t. The structure is private. */
+typedef struct _spifi_dma_private_handle
+{
+    SPIFI_Type *base;
+    spifi_dma_handle_t *handle;
+} spifi_dma_private_handle_t;
+
+/* SPIFI DMA transfer handle. */
+enum _spifi_dma_tansfer_states
+{
+    kSPIFI_Idle,   /* TX idle. */
+    kSPIFI_BusBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static spifi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPIFI_COUNT][2];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief SPIFI DMA send finished callback function.
+ *
+ * This function is called when SPIFI DMA send finished. It disables the SPIFI
+ * TX DMA request and sends @ref kStatus_SPIFI_TxIdle to SPIFI callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief SPIFI DMA receive finished callback function.
+ *
+ * This function is called when SPIFI DMA receive finished. It disables the SPIFI
+ * RX DMA request and sends @ref kStatus_SPIFI_RxIdle to SPIFI callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief Get the SPIFI instance from peripheral base address.
+ *
+ * @param base SPIFI peripheral base address.
+ * @return SPIFI instance.
+ */
+extern uint32_t SPIFI_GetInstance(SPIFI_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    intmode = intmode;
+
+    if (transferDone)
+    {
+        SPIFI_TransferAbortSendDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
+
+        if (spifiPrivateHandle->handle->callback)
+        {
+            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
+                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
+
+    /* Avoid warning for unused parameters. */
+    handle = handle;
+    intmode = intmode;
+
+    if (transferDone)
+    {
+        /* Disable transfer. */
+        SPIFI_TransferAbortReceiveDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
+
+        if (spifiPrivateHandle->handle->callback)
+        {
+            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
+                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = SPIFI_GetInstance(base);
+
+    s_dmaPrivateHandle[instance][0].base = base;
+    s_dmaPrivateHandle[instance][0].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kSPIFI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure TX dma callback */
+    DMA_SetCallback(handle->dmaHandle, SPIFI_SendDMACallback, &s_dmaPrivateHandle[instance][0]);
+}
+
+void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = SPIFI_GetInstance(base);
+
+    s_dmaPrivateHandle[instance][1].base = base;
+    s_dmaPrivateHandle[instance][1].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kSPIFI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure RX dma callback */
+    DMA_SetCallback(handle->dmaHandle, SPIFI_ReceiveDMACallback, &s_dmaPrivateHandle[instance][1]);
+}
+
+status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kSPIFI_BusBusy == handle->state)
+    {
+        status = kStatus_SPIFI_Busy;
+    }
+    else
+    {
+        handle->state = kSPIFI_BusBusy;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)SPIFI_GetDataRegisterAddress(base), sizeof(uint32_t),
+                            xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable SPIFI TX DMA. */
+        SPIFI_EnableDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kSPIFI_BusBusy == handle->state)
+    {
+        status = kStatus_SPIFI_Busy;
+    }
+    else
+    {
+        handle->state = kSPIFI_BusBusy;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)SPIFI_GetDataRegisterAddress(base), xfer->data, sizeof(uint32_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable SPIFI TX DMA. */
+        SPIFI_EnableDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable SPIFI TX DMA. */
+    SPIFI_EnableDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kSPIFI_Idle;
+}
+
+void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable SPIFI RX DMA. */
+    SPIFI_EnableDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kSPIFI_Idle;
+}
+
+status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kSPIFI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
+
+status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kSPIFI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPIFI_DMA_H_
+#define _FSL_SPIFI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_spifi.h"
+
+/*!
+ * @addtogroup spifi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _spifi_dma_handle spifi_dma_handle_t;
+
+/*! @brief SPIFI DMA transfer callback function for finish and error */
+typedef void (*spifi_dma_callback_t)(SPIFI_Type *base, spifi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPIFI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spifi_dma_handle
+{
+    dma_handle_t *dmaHandle;       /*!< DMA handler for SPIFI send */
+    size_t transferSize;           /*!< Bytes need to transfer. */
+    uint32_t state;                /*!< Internal state for SPIFI DMA transfer */
+    spifi_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                /*!< User callback parameter */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPIFI handle for send which is used in transactional functions and set the callback.
+ *
+ * @param base SPIFI peripheral base address
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param callback SPIFI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMA handle for DMA transfer
+ */
+void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the SPIFI handle for receive which is used in transactional functions and set the callback.
+ *
+ * @param base SPIFI peripheral base address
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param callback SPIFI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMA handle for DMA transfer
+ */
+void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Transfers SPIFI data using an DMA non-blocking method.
+ *
+ * This function writes data to the SPIFI transmit FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param xfer SPIFI transfer structure.
+ */
+status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using an DMA non-blocking method.
+ *
+ * This function receive data from the SPIFI receive buffer/FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param xfer SPIFI transfer structure.
+ */
+status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts the sent data using DMA.
+ *
+ * @param base SPIFI peripheral base address.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ */
+void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data using DMA.
+ *
+ * This function abort receive data which using DMA.
+ *
+ * @param base SPIFI peripheral base address.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ */
+void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the transferred counts of send.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure.
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the status of the receive transfer.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* _FSL_SPIFI_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,708 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if ((uint32_t)base == s_usartBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* setup baudrate */
+    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;
+    return kStatus_Success;
+}
+
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Set always all members ! */
+    config->baudRate_Bps = 115200U;
+    config->parityMode = kUSART_ParityDisabled;
+    config->stopBitCount = kUSART_OneStopBit;
+    config->bitCountPerChar = kUSART_8BitsPerChar;
+    config->loopback = false;
+    config->enableRx = false;
+    config->enableTx = false;
+    config->txWatermark = kUSART_TxFifo0;
+    config->rxWatermark = kUSART_RxFifo1;
+}
+
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /*
+     * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+     * potentially cause more noise errors or incorrect data.
+     */
+    for (osrval = best_osrval; osrval >= 8; osrval--)
+    {
+        brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;
+        if (brgval > 0xFFFF)
+        {
+            continue;
+        }
+        baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));
+        diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+        if (diff < best_diff)
+        {
+            best_diff = diff;
+            best_osrval = osrval;
+            best_brgval = brgval;
+        }
+    }
+
+    /* value over range */
+    if (best_brgval > 0xFFFF)
+    {
+        return kStatus_USART_BaudrateNotSupport;
+    }
+
+    base->OSR = best_osrval;
+    base->BRG = best_brgval;
+    return kStatus_Success;
+}
+
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return;
+    }
+    /* Check whether txFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return;
+    }
+    for (; length > 0; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+        }
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+}
+
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t status;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+        }
+        /* check receive status */
+        status = base->STAT;
+        if (status & USART_STAT_FRAMERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_FRAMERRINT_MASK;
+            return kStatus_USART_FramingError;
+        }
+        if (status & USART_STAT_PARITYERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_PARITYERRINT_MASK;
+            return kStatus_USART_ParityError;
+        }
+        if (status & USART_STAT_RXNOISEINT_MASK)
+        {
+            base->STAT |= USART_STAT_RXNOISEINT_MASK;
+            return kStatus_USART_NoiseError;
+        }
+        /* check rxFIFO status */
+        if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            return kStatus_USART_RxError;
+        }
+
+        *data = base->FIFORD;
+        data++;
+    }
+    return kStatus_Success;
+}
+
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    int32_t instance = 0;
+
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle);
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState = kUSART_TxBusy;
+        /* Enable transmiter interrupt. */
+        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK;
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0;
+    handle->txState = kUSART_TxIdle;
+}
+
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState = kUSART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState = kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK;
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);
+    bool sendEnabled = handle->txDataSize;
+
+    /* If RX overrun. */
+    if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
+           (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
+    {
+        /* Receive data */
+        if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize)
+            {
+                *handle->rxData = base->FIFORD;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));
+                if (!handle->rxDataSize)
+                {
+                    if (!handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = kUSART_RxIdle;
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;
+                    /* Increase handle->rxRingBufferHead. */
+                    if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                handle->txState = kUSART_TxIdle;
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum _usart_status
+{
+    kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0),              /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1),              /*!< Receiver is busy. */
+    kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2),              /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3),              /*!< USART receiver is idle. */
+    kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7),             /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9),             /*!< Error happens on rxFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10),         /*!< USART noise error. */
+    kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11),       /*!< USART framing error. */
+    kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12),        /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK),                 /*!< TEERR bit, sets if TX buffer is error */
+    kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK),                 /*!< RXERR bit, sets if RX buffer is error */
+    kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK),       /*!< TXEMPTY bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXNOTFULL bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK),         /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;                /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                        /*!< Enable peripheral loopback */
+    bool enableRx;                        /*!< Enable RX */
+    bool enableTx;                        /*!< Enable TX */
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source freqency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ *      kUSART_TxError
+ *      kUSART_RxError
+ * For example:
+ * @code
+ *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = mask & 0xF;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = ~(mask & 0xF);
+}
+
+/*!
+* @brief Enable DMA for Tx
+*/
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+* @brief Enable DMA for Rx
+*/
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_dma.h"
+#include "fsl_flexcomm.h"
+#include "fsl_usart_dma.h"
+
+/*<! Structure definition for uart_dma_handle_t. The structure is private. */
+typedef struct _usart_dma_private_handle
+{
+    USART_Type *base;
+    usart_dma_handle_t *handle;
+} usart_dma_private_handle_t;
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*<! Private handle only used for internally. */
+static usart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_USART_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART TX DMA. */
+    USART_EnableTxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->txState = kUSART_TxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART RX DMA. */
+    USART_EnableRxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->rxState = kUSART_RxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* set tx/rx 'idle' state */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Configure TX. */
+    if (txDmaHandle)
+    {
+        DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->txDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        status = kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txState = kUSART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from txFIFO */
+        USART_EnableTxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_MemoryToPeripheral, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->txDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        status = kStatus_USART_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kUSART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from rxFIFO */
+        USART_EnableRxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->txDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->txDmaHandle);
+    handle->txState = kUSART_TxIdle;
+}
+
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_DMA_H_
+#define _FSL_USART_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+#include "fsl_usart.h"
+
+/*!
+ * @addtogroup usart_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_dma_handle usart_dma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*usart_dma_transfer_callback_t)(USART_Type *base,
+                                              usart_dma_handle_t *handle,
+                                              status_t status,
+                                              void *userData);
+
+/*!
+* @brief UART DMA handle
+*/
+struct _usart_dma_handle
+{
+    USART_Type *base; /*!< UART peripheral base address. */
+
+    usart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                         /*!< UART callback function parameter.*/
+    size_t rxDataSizeAll;                   /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                   /*!< Size of the data to send out. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle which is used in transactional functions.
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param txDmaHandle User-requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_TxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts send data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_utick.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Typedef for interrupt handler. */
+typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base UTICK peripheral base address
+ *
+ * @return The UTICK instance
+ */
+static uint32_t UTICK_GetInstance(UTICK_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UTICK handle. */
+static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT];
+/* Array of UTICK peripheral base address. */
+static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS;
+/* Array of UTICK IRQ number. */
+static const IRQn_Type s_utickIRQ[] = UTICK_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of UTICK clock name. */
+static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/* UTICK ISR for transactional APIs. */
+static utick_isr_t s_utickIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t UTICK_GetInstance(UTICK_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++)
+    {
+        if (s_utickBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_utickBases));
+
+    return instance;
+}
+
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)
+{
+    uint32_t instance;
+
+    /* Get instance from peripheral base address. */
+    instance = UTICK_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_utickHandle[instance] = cb;
+    EnableDeepSleepIRQ(s_utickIRQ[instance]);
+    base->CTRL = count | UTICK_CTRL_REPEAT(mode);
+}
+
+void UTICK_Init(UTICK_Type *base)
+{
+    /* Enable utick clock */
+    CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]);
+    /* Power up Watchdog oscillator*/
+    POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
+    s_utickIsr = UTICK_HandleIRQ;
+}
+
+void UTICK_Deinit(UTICK_Type *base)
+{
+    /* Turn off utick */
+    base->CTRL = 0;
+    /* Disable utick clock */
+    CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]);
+}
+
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base)
+{
+    return (base->STAT);
+}
+
+void UTICK_ClearStatusFlags(UTICK_Type *base)
+{
+    base->STAT = UTICK_STAT_INTR_MASK;
+}
+
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)
+{
+    UTICK_ClearStatusFlags(base);
+    if (cb)
+    {
+        cb();
+    }
+}
+
+#if defined(UTICK0)
+void UTICK0_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK0, s_utickHandle[0]);
+}
+#endif
+#if defined(UTICK1)
+void UTICK1_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK1, s_utickHandle[1]);
+}
+#endif
+#if defined(UTICK2)
+void UTICK2_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK2, s_utickHandle[2]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_UTICK_H_
+#define _FSL_UTICK_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup utick
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UTICK driver version 2.0.0. */
+#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief UTICK timer operational mode. */
+typedef enum _utick_mode
+{
+    kUTICK_Onetime = 0x0U, /*!< Trigger once*/
+    kUTICK_Repeat = 0x1U,  /*!< Trigger repeatedly */
+} utick_mode_t;
+
+/*! @brief UTICK callback function. */
+typedef void (*utick_callback_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+* @brief Initializes an UTICK by turning its bus clock on
+*
+*/
+void UTICK_Init(UTICK_Type *base);
+
+/*!
+ * @brief Deinitializes a UTICK instance.
+ *
+ * This function shuts down Utick bus clock
+ *
+ * @param base UTICK peripheral base address.
+ */
+void UTICK_Deinit(UTICK_Type *base);
+/*!
+ * @brief Get Status Flags.
+ *
+ * This returns the status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return status register value
+ */
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base);
+/*!
+ * @brief Clear Status Interrupt Flags.
+ *
+ * This clears intr status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return none
+ */
+void UTICK_ClearStatusFlags(UTICK_Type *base);
+
+/*!
+ * @brief Starts UTICK.
+ *
+ * This function starts a repeat/onetime countdown with an optional callback
+ *
+ * @param base   UTICK peripheral base address.
+ * @param mode  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param count  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param cb  UTICK callback (can be left as NULL if none, otherwise should be a void func(void))
+ * @return none
+ */
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb);
+/*!
+ * @brief UTICK Interrupt Service Handler.
+ *
+ * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
+ * in UTICK_SetTick()).
+ * if no user callback is scheduled, the interrupt will simply be cleared.
+ *
+ * @param base   UTICK peripheral base address.
+ * @param cb  callback scheduled for this instance of UTICK
+ * @return none
+ */
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UTICK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wwdt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base WWDT peripheral base address
+ *
+ * @return The WWDT instance
+ */
+static uint32_t WWDT_GetInstance(WWDT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to WWDT bases for each instance. */
+static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to WWDT clocks for each instance. */
+static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to WWDT resets for each instance. */
+static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t WWDT_GetInstance(WWDT_Type *base)
+{
+    uint32_t instance;
+    uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < wwdtArrayCount; instance++)
+    {
+        if (s_wwdtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < wwdtArrayCount);
+
+    return instance;
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void WWDT_GetDefaultConfig(wwdt_config_t *config)
+{
+    assert(config);
+
+    /* Enable the watch dog */
+    config->enableWwdt = true;
+    /* Disable the watchdog timeout reset */
+    config->enableWatchdogReset = false;
+    /* Disable the watchdog protection for updating the timeout value */
+    config->enableWatchdogProtect = false;
+    /* Do not lock the watchdog oscillator */
+    config->enableLockOscillator = false;
+    /* Windowing is not in effect */
+    config->windowValue = 0xFFFFFFU;
+    /* Set the timeout value to the max */
+    config->timeoutValue = 0xFFFFFFU;
+    /* No warning is provided */
+    config->warningValue = 0;
+}
+
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the WWDT clock */
+    CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the WWDT module */
+    RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]);
+
+    value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
+            WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator);
+    /* Set configruation */
+    base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);
+    base->TC = WWDT_TC_COUNT(config->timeoutValue);
+    base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue);
+    base->MOD = value;
+}
+
+void WWDT_Deinit(WWDT_Type *base)
+{
+    WWDT_Disable(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the WWDT clock */
+    CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void WWDT_Refresh(WWDT_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->FEED = WWDT_FIRST_WORD_OF_REFRESH;
+    base->FEED = WWDT_SECOND_WORD_OF_REFRESH;
+    EnableGlobalIRQ(primaskValue);
+}
+
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)
+{
+    /* Clear the WDINT bit so that we don't accidentally clear it */
+    uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK));
+
+    /* Clear timeout by writing a zero */
+    if (mask & kWWDT_TimeoutFlag)
+    {
+        reg &= ~WWDT_MOD_WDTOF_MASK;
+    }
+
+    /* Clear warning interrupt flag by writing a one */
+    if (mask & kWWDT_WarningFlag)
+    {
+        reg |= WWDT_MOD_WDINT_MASK;
+    }
+
+    base->MOD = reg;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h	Wed Oct 11 12:45:49 2017 +0100
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_WWDT_H_
+#define _FSL_WWDT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wwdt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines WWDT driver version 2.0.0. */
+#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @name Refresh sequence */
+/*@{*/
+#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU)  /*!< First word of refresh sequence */
+#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
+/*@}*/
+
+/*! @brief Describes WWDT configuration structure. */
+typedef struct _wwdt_config
+{
+    bool enableWwdt;            /*!< Enables or disables WWDT */
+    bool enableWatchdogReset;   /*!< true: Watchdog timeout will cause a chip reset
+                                     false: Watchdog timeout will not cause a chip reset */
+    bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be
+                                           changed after counter is below warning & window values
+                                     false: Disable watchdog protect; timeout value can be changed
+                                            at any time */
+    bool enableLockOscillator;  /*!< true: Disabling or powering down the watchdog oscillator is prevented
+                                           Once set, this bit can only be cleared by a reset
+                                     false: Do not lock oscillator */
+    uint32_t windowValue;       /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
+    uint32_t timeoutValue;      /*!< Timeout value */
+    uint32_t warningValue;      /*!< Watchdog time counter value that will generate a
+                                     warning interrupt. Set this to 0 for no warning */
+
+} wwdt_config_t;
+
+/*!
+ * @brief WWDT status flags.
+ *
+ * This structure contains the WWDT status flags for use in the WWDT functions.
+ */
+enum _wwdt_status_flags_t
+{
+    kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */
+    kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK  /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name WWDT Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes WWDT configure sturcture.
+ *
+ * This function initializes the WWDT configure structure to default value. The default
+ * value are:
+ * @code
+ *  config->enableWwdt = true;
+ *  config->enableWatchdogReset = false;
+ *  config->enableWatchdogProtect = false;
+ *  config->enableLockOscillator = false;
+ *  config->windowValue = 0xFFFFFFU;
+ *  config->timeoutValue = 0xFFFFFFU;
+ *  config->warningValue = 0;
+ * @endcode
+ *
+ * @param config Pointer to WWDT config structure.
+ * @see wwdt_config_t
+ */
+void WWDT_GetDefaultConfig(wwdt_config_t *config);
+
+/*!
+ * @brief Initializes the WWDT.
+ *
+ * This function initializes the WWDT. When called, the WWDT runs according to the configuration.
+ *
+ * Example:
+ * @code
+ *   wwdt_config_t config;
+ *   WWDT_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   WWDT_Init(wwdt_base,&config);
+ * @endcode
+ *
+ * @param base   WWDT peripheral base address
+ * @param config The configuration of WWDT
+ */
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
+
+/*!
+ * @brief Shuts down the WWDT.
+ *
+ * This function shuts down the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Deinit(WWDT_Type *base);
+
+/* @} */
+
+/*!
+ * @name WWDT Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit;
+ * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run
+ * permanently.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Enable(WWDT_Type *base)
+{
+    base->MOD |= WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Disables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to disable the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Disable(WWDT_Type *base)
+{
+    base->MOD &= ~WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Gets all WWDT status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Timeout Flag:
+ * @code
+ *   uint32_t status;
+ *   status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;
+ * @endcode
+ * @param base        WWDT peripheral base address
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::_wwdt_status_flags_t
+ */
+static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)
+{
+    return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK));
+}
+
+/*!
+ * @brief Clear WWDT flag.
+ *
+ * This function clears WWDT status flag.
+ *
+ * Example for clearing warning flag:
+ * @code
+ *   WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);
+ * @endcode
+ * @param base WWDT peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::_wwdt_status_flags_t
+ */
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask);
+
+/*!
+ * @brief Set the WWDT warning value.
+ *
+ * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog
+ * interrupt. When the watchdog timer counter is no longer greater than the value defined by
+ * WARNINT, an interrupt will be generated after the subsequent WDCLK.
+ *
+ * @param base         WWDT peripheral base address
+ * @param warningValue WWDT warning value.
+ */
+static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)
+{
+    base->WARNINT = WWDT_WARNINT_WARNINT(warningValue);
+}
+
+/*!
+ * @brief Set the WWDT timeout value.
+ *
+ * This function sets the timeout value. Every time a feed sequence occurs the value in the TC
+ * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be
+ * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4.
+ * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change
+ * the timeout value before the watchdog counter is below the warning and window values
+ * will cause a watchdog reset and set the WDTOF flag.
+ *
+ * @param base WWDT peripheral base address
+ * @param timeoutCount WWDT timeout value, count of WWDT clock tick.
+ */
+static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)
+{
+    base->TC = WWDT_TC_COUNT(timeoutCount);
+}
+
+/*!
+ * @brief Sets the WWDT window value.
+ *
+ * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed.
+ * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog
+ * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer
+ * value) so windowing is not in effect.
+ *
+ * @param base        WWDT peripheral base address
+ * @param windowValue WWDT window value.
+ */
+static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
+{
+    base->WINDOW = WWDT_WINDOW_WINDOW(windowValue);
+}
+
+/*!
+ * @brief Refreshes the WWDT timer.
+ *
+ * This function feeds the WWDT.
+ * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Refresh(WWDT_Type *base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WWDT_H_ */

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -54,9 +54,6 @@
 
 void rtc_write(time_t t)
 {
-    if (t == 0) {
-        t = 1;
-    }
     RTC_StopTimer(RTC);
     RTC->COUNT = t;
     RTC_StartTimer(RTC);

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -68,7 +68,7 @@
     if (slave) {
         /* Slave config */
         SPI_SlaveGetDefaultConfig(&slave_config);
-        slave_config.dataWidth = (uint32_t)bits - 1;
+        slave_config.dataWidth = (spi_data_width_t)(bits - 1);
         slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
         slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
 
@@ -76,7 +76,7 @@
     } else {
         /* Master config */
         SPI_MasterGetDefaultConfig(&master_config);
-        master_config.dataWidth = (uint32_t)bits - 1;
+        master_config.dataWidth = (spi_data_width_t)(bits - 1);
         master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
         master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
         master_config.direction = kSPI_MsbFirst;
@@ -154,7 +154,7 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, 
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/cmsis_nvic.h	Mon Oct 02 15:33:19 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-extern uint32_t Image$$VECTOR_RAM$$Base[];
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#else
-extern uint32_t __VECTOR_RAM[];
-#endif
-
-/* Symbols defined by the linker script */
-#define NVIC_NUM_VECTORS        (16 + 57)         // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
-
-#endif

--- a/targets/TARGET_NXP/mbed_rtx.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_NXP/mbed_rtx.h	Wed Oct 11 12:45:49 2017 +0100
@@ -86,7 +86,7 @@
 #define INITIAL_SP              (0x20010000UL)
 #endif
 
-#elif defined(TARGET_LPC54608)
+#elif defined(TARGET_LPC546XX)
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20028000UL)

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -637,17 +637,17 @@
         __NOP();
     }
     
-    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
         /* send/receive FIFO buffer isn't full */
         dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
         if ((*dmy_cfsts & 0x02) != 0x02) {
-            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
             dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
             *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
             if (msg.format == CANStandard) {
                 *dmy_cfid |= (msg.id & 0x07FF);
             } else {
-                *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+                *dmy_cfid |= (msg.id & 0x1FFFFFFF);
             }
             /* set length */
             dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
@@ -686,14 +686,14 @@
     /* send/receive FIFO buffer isn't empty */
     dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
     while ((*dmy_cfsts & 0x01) != 0x01) {
-        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
         dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
         msg->format = (CANFormat)(*dmy_cfid >> 31);
-        msg->type = (CANType)(*dmy_cfid >> 30);
+        msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
         if (msg->format == CANStandard) {
             msg->id = (*dmy_cfid & 0x07FF);
         } else {
-            msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+            msg->id = (*dmy_cfid & 0x1FFFFFFF);
         }
         /* get length */
         dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
@@ -813,7 +813,7 @@
     int retval = 0;
     
     if ((format == CANStandard) || (format == CANExtended)) {
-        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
             /* set Global Reset mode and Channel Reset mode */
             can_set_global_mode(GL_RESET);
             can_set_channel_mode(obj->ch, CH_RESET);
@@ -824,11 +824,11 @@
             /* set IDE format */
             *dmy_gaflid = (format << 31);
             if (format == CANExtended) {
-                /* set receive rule ID for bit28-11 */
-                *dmy_gaflid |= (id << 11);
+                /* set receive rule ID for bit28-0 */
+                *dmy_gaflid |= (id & 0x1FFFFFFF);
             } else {
                 /* set receive rule ID for bit10-0 */
-                *dmy_gaflid |= id;
+                *dmy_gaflid |= (id & 0x07FF);
             }
             /* set ID mask bit */
             *dmy_gaflm = (0xC0000000 | mask);
@@ -971,6 +971,7 @@
     uint8_t brp = 0;
     uint8_t tseg1 = 0;
     uint8_t tseg2 = 0;
+    uint8_t sjw = 0;
     
     /* set clkc */
     if (RZ_A1_IsClockMode0() == false) {
@@ -993,9 +994,10 @@
     /* calculate TSEG1 bit and TSEG2 bit */
     tseg1 = (tq - 1) * 0.666666667;
     tseg2 = (tq - 1) - tseg1;
+    sjw = (tseg2 > 4)? 4 : tseg2;
     /* set RSCAN0CmCFG register */
     dmy_cfg = CFG_MATCH[obj->ch];
-    *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+    *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
 }
 
 static void can_set_global_mode(int mode) {

--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -654,17 +654,17 @@
         __NOP();
     }
     
-    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
         /* send/receive FIFO buffer isn't full */
         dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
         if ((*dmy_cfsts & 0x02) != 0x02) {
-            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
             dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
             *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
             if (msg.format == CANStandard) {
                 *dmy_cfid |= (msg.id & 0x07FF);
             } else {
-                *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+                *dmy_cfid |= (msg.id & 0x1FFFFFFF);
             }
             /* set length */
             dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
@@ -703,14 +703,14 @@
     /* send/receive FIFO buffer isn't empty */
     dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
     while ((*dmy_cfsts & 0x01) != 0x01) {
-        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
         dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
         msg->format = (CANFormat)(*dmy_cfid >> 31);
-        msg->type = (CANType)(*dmy_cfid >> 30);
+        msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
         if (msg->format == CANStandard) {
             msg->id = (*dmy_cfid & 0x07FF);
         } else {
-            msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+            msg->id = (*dmy_cfid & 0x1FFFFFFF);
         }
         /* get length */
         dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
@@ -830,7 +830,7 @@
     int retval = 0;
     
     if ((format == CANStandard) || (format == CANExtended)) {
-        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
             /* set Global Reset mode and Channel Reset mode */
             can_set_global_mode(GL_RESET);
             can_set_channel_mode(obj->ch, CH_RESET);
@@ -841,11 +841,11 @@
             /* set IDE format */
             *dmy_gaflid = (format << 31);
             if (format == CANExtended) {
-                /* set receive rule ID for bit28-11 */
-                *dmy_gaflid |= (id << 11);
+                /* set receive rule ID for bit28-0 */
+                *dmy_gaflid |= (id & 0x1FFFFFFF);
             } else {
                 /* set receive rule ID for bit10-0 */
-                *dmy_gaflid |= id;
+                *dmy_gaflid |= (id & 0x07FF);
             }
             /* set ID mask bit */
             *dmy_gaflm = (0xC0000000 | mask);
@@ -988,6 +988,7 @@
     uint8_t brp = 0;
     uint8_t tseg1 = 0;
     uint8_t tseg2 = 0;
+    uint8_t sjw = 0;
     
     /* set clkc */
     if (RZ_A1_IsClockMode0() == false) {
@@ -1010,9 +1011,10 @@
     /* calculate TSEG1 bit and TSEG2 bit */
     tseg1 = (tq - 1) * 0.666666667;
     tseg2 = (tq - 1) - tseg1;
+    sjw = (tseg2 > 4)? 4 : tseg2;
     /* set RSCAN0CmCFG register */
     dmy_cfg = CFG_MATCH[obj->ch];
-    *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+    *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
 }
 
 static void can_set_global_mode(int mode) {

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c	Wed Oct 11 12:45:49 2017 +0100
@@ -35,6 +35,7 @@
 **/
 
 #include "stm32f4xx.h"
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -240,8 +241,6 @@
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c	Wed Oct 11 12:45:49 2017 +0100
@@ -35,7 +35,7 @@
 **/
 
 #include "stm32f4xx.h"
-
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -243,8 +243,6 @@
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h	Wed Oct 11 12:45:49 2017 +0100
@@ -57,7 +57,7 @@
     PD_4  = 0x34, PD_5  = 0x35, PD_6  = 0x36, PD_7  = 0x37,
     PD_8  = 0x38, PD_9  = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
     PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
-    
+
     PE_0  = 0x40, PE_1  = 0x41, PE_2  = 0x42, PE_3  = 0x43,
     PE_4  = 0x44, PE_5  = 0x45, PE_6  = 0x46, PE_7  = 0x47,
     PE_8  = 0x48, PE_9  = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
@@ -80,100 +80,100 @@
 
     // Module Pins
     // A
-    P_A5    = PC_2,   // UART-DTR
-    P_A6    = PF_2,   // Switch-0
-    P_A7    = PE_0,   // Red, Mode
-    P_A8    = PB_6,   // Green, Switch-1
-    P_A9    = PB_8,   // Blue
-    P_A10   = PA_11,  // UART-CTS
-    P_A11   = PA_9,   // UART-TXD
-    P_A12   = PA_12,  // UART-RTS
-    P_A13   = PA_10,  // UART-RXD
-    P_A14   = PD_9,   // GPIO-0
-    P_A15   = PD_8,   // GPIO-1
-    P_A16   = PD_11,  // GPIO-2
-    P_A17   = PD_12,  // GPIO-3
-    P_A18   = PA_3,   // UART-DSR
+    P_A5       = PC_2,   // UART-DTR
+    P_A6       = PF_2,   // Switch-0
+    P_A7       = PE_0,   // Red, Mode
+    P_A8       = PB_6,   // Green, Switch-1
+    P_A9       = PB_8,   // Blue
+    P_A10      = PA_11,  // UART-CTS
+    P_A11      = PA_9,   // UART-TXD
+    P_A12      = PA_12,  // UART-RTS
+    P_A13      = PA_10,  // UART-RXD
+    P_A14      = PD_9,   // GPIO-0
+    P_A15      = PD_8,   // GPIO-1
+    P_A16      = PD_11,  // GPIO-2
+    P_A17      = PD_12,  // GPIO-3
+    P_A18      = PA_3,   // UART-DSR
     // B
     // C
-    P_C5    = PG_4,   // SPI-IRQ
-    P_C6    = PE_13,  // SPI-MISO
-    P_C8    = PE_12,  // Res
-    P_C10   = PE_14,  // SPI-MOSI
-    P_C11   = PE_11,  // SPI-CS0
-    P_C12   = PE_9,   // Res
-    P_C13   = PF_6,   // GPIO-4
-    P_C14   = PC_1,   // RMII-MDC
-    P_C15   = PA_2,   // RMII-MDIO
-    P_C16   = PF_7,   // GPIO-7
-    P_C17   = PF_1,   // I2C-SCL
-    P_C18   = PF_0,   // I2C-SDA
+    P_C5       = PG_4,   // SPI-IRQ
+    P_C6       = PE_13,  // SPI-MISO
+    P_C8       = PE_12,  // Res
+    P_C10      = PE_14,  // SPI-MOSI
+    P_C11      = PE_11,  // SPI-CS0
+    P_C12      = PE_9,   // Res
+    P_C13      = PF_6,   // GPIO-4
+    P_C14      = PC_1,   // RMII-MDC
+    P_C15      = PA_2,   // RMII-MDIO
+    P_C16      = PF_7,   // GPIO-7
+    P_C17      = PF_1,   // I2C-SCL
+    P_C18      = PF_0,   // I2C-SDA
 	  // D
-    P_D1    = PB_12,  // RMII-TXD0
-    P_D2    = PB_13,  // RMII-TXD1
-    P_D3    = PB_11,  // RMII-TXEN
-    P_D4    = PA_7,   // RMII-CRSDV
-    P_D5    = PC_4,   // RMII-RXD0
-    P_D6    = PC_5,   // RMII-RXD1
-    P_D8    = PA_1,   // RMII-REFCLK
+    P_D1       = PB_12,  // RMII-TXD0
+    P_D2       = PB_13,  // RMII-TXD1
+    P_D3       = PB_11,  // RMII-TXEN
+    P_D4       = PA_7,   // RMII-CRSDV
+    P_D5       = PC_4,   // RMII-RXD0
+    P_D6       = PC_5,   // RMII-RXD1
+    P_D8       = PA_1,   // RMII-REFCLK
     // TP
-    P_TP5   = PB_4,   // NTRST
-    P_TP7   = PA_13,  // TMS  SWDIO
-    P_TP8   = PA_15,  // TDI
-    P_TP9   = PA_14,  // TCK  SWCLK
-    P_TP10  = PB_3,   // TDO 
-    //P_TP11,         // BOOT0 		
+    P_TP5      = PB_4,   // NTRST
+    P_TP7      = PA_13,  // TMS  SWDIO
+    P_TP8      = PA_15,  // TDI
+    P_TP9      = PA_14,  // TCK  SWCLK
+    P_TP10     = PB_3,   // TDO
+    //P_TP11,         // BOOT0
 
     // Board Pins
     // A0-A5
-    A0      = PF_6,  // AI4
-    A1      = PA_3,  // AI3
-    A2      = PC_2,  // AI12
-    A3      = PF_7,  // LPOCLK, not AI
-    A4      = PG_4,  // not AI
-    A5      = PE_0,  // not AI
+    A0         = PF_6,  // AI4
+    A1         = PA_3,  // AI3
+    A2         = PC_2,  // AI12
+    A3         = PF_7,  // LPOCLK, not AI
+    A4         = PG_4,  // not AI
+    A5         = PE_0,  // not AI
     // D0-D15
-    D0      = PD_9,   // UART3-RX
-    D1      = PD_8,   // UART3-TX
-    D2      = PA_10,  // UART1-RX
-    D3      = PA_11,  // CAN1-RX
-    D4      = PA_12,  // CAN1-TX
-    D5      = PB_8,
-    D6      = PD_11,  // UART3-CTS
-    D7      = PD_12,  // UART3-RTS
-    D8      = PA_9,   // UART1-TX
-    D9      = PE_9,   // SDCard-CS
-    D10     = PE_11,  // SSEL
-    D11     = PE_14,  // MOSI
-    D12     = PE_13,  // MISO
-    D13     = PE_12,  // SCK
-    D14     = PF_0,   // SDA
-    D15     = PF_1,   // SCL
+    D0         = PD_9,   // UART3-RX
+    D1         = PD_8,   // UART3-TX
+    D2         = PA_10,  // UART1-RX
+    D3         = PA_11,  // CAN1-RX
+    D4         = PA_12,  // CAN1-TX
+    D5         = PB_8,
+    D6         = PD_11,  // UART3-CTS
+    D7         = PD_12,  // UART3-RTS
+    D8         = PA_9,   // UART1-TX
+    D9         = PE_9,   // SDCard-CS
+    D10        = PE_11,  // SSEL
+    D11        = PE_14,  // MOSI
+    D12        = PE_13,  // MISO
+    D13        = PE_12,  // SCK
+    D14        = PF_0,   // SDA
+    D15        = PF_1,   // SCL
     // Internal
-    LED1    = PE_0,   // Red / Mode
-    LED2    = PB_6,   // Green / Switch-1
-    LED3    = PB_8,   // Blue
-    LED4    = D10,
-    SW0     = PF_2,   // Switch-0
-    SW1     = PB_6,   // Green / Switch-1
+    LED1       = PE_0,   // Red / Mode
+    LED2       = PB_6,   // Green / Switch-1
+    LED3       = PB_8,   // Blue
+    LED4       = D10,
+    LED_RED    = LED1,
+    LED_GREEN  = LED2,
+    LED_BLUE   = LED3,
+    SW0        = PF_2,   // Switch-0
+    SW1        = PB_6,   // Green / Switch-1
 
-    LED_RED   = LED1,
-    LED_GREEN = LED2,
-    LED_BLUE  = LED3,
 
     // Standardized button names
-    BUTTON1 = SW0,
-    BUTTON2 = SW1,
+    BUTTON1    = SW0,
+    BUTTON2    = SW1,
 
     // ST-Link
-    USBRX   = PA_10,
-    USBTX   = PA_9,
-    SWDIO   = PA_15, 
-    SWCLK   = PA_14, 
-    NTRST   = PB_4,  
+    USBRX      = PA_10,
+    USBTX      = PA_9,
+    SWDIO      = PA_15,
+    SWCLK      = PA_14,
+    NTRST      = PB_4,
 
     // Not connected
-    NC = (int)0xFFFFFFFF
+    NC    = (int)0xFFFFFFFF
 } PinName;
 
 #ifdef __cplusplus

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -41,6 +41,16 @@
 
 int32_t flash_init(flash_t *obj)
 {
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+static int32_t flash_unlock(void)
+{
     /* Allow Access to Flash control registers and user Falsh */
     if (HAL_FLASH_Unlock()) {
         return -1;
@@ -48,9 +58,10 @@
         return 0;
     }
 }
-int32_t flash_free(flash_t *obj)
+
+static int32_t flash_lock(void)
 {
-    /* Disable the Flash option control register access (recommended to protect 
+    /* Disable the Flash option control register access (recommended to protect
     the option Bytes against possible unwanted operations) */
     if (HAL_FLASH_Lock()) {
         return -1;
@@ -58,18 +69,23 @@
         return 0;
     }
 }
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     /*Variable used for Erase procedure*/
     static FLASH_EraseInitTypeDef EraseInitStruct;
     uint32_t FirstSector;
     uint32_t SectorError = 0;
- 
+    int32_t status = 0;
+
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
-
         return -1;
     }
-   
+
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Get the 1st sector to erase */
     FirstSector = GetSector(address);
 
@@ -79,19 +95,26 @@
     EraseInitStruct.Sector = FirstSector;
     EraseInitStruct.NbSectors = 1;
     if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
 {
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -105,16 +128,19 @@
     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
     __HAL_FLASH_DATA_CACHE_ENABLE();
 
-    while (size > 0) {
+    while ((size > 0) && (status == 0)) {
         if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
-            return -1;
+            status = -1;
         } else {
             size--;
             address++;
             data++;
         }
     }
-    return 0;
+
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c	Wed Oct 11 12:45:49 2017 +0100
@@ -1063,33 +1063,54 @@
   
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
 
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-    /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
   {
-    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
     {
       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-        /* Process Unlocked */ 
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-      
+
         return HAL_TIMEOUT;
       }  
     }
   }
-  
+  /* Disable the Wake-Up timer */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+  /* Clear flag Wake-Up */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
   /* Configure the Wakeup Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
 
@@ -1098,15 +1119,12 @@
 
   /* Configure the clock source */
   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
+
   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-  
-  /* Clear RTC Wake Up timer Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
+
+  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
   /* Configure the Interrupt in the RTC_CR register */
   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
   

--- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -38,14 +38,24 @@
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Allow Access to Flash control registers and user Flash */
+    return 0;
+}
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
     if (HAL_FLASH_Unlock()) {
         return -1;
     } else {
         return 0;
     }
 }
-int32_t flash_free(flash_t *obj)
+
+static int32_t flash_lock(void)
 {
     /* Disable the Flash option control register access (recommended to protect
     the option Bytes against possible unwanted operations) */
@@ -55,6 +65,7 @@
         return 0;
     }
 }
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     /* Variable used for Erase procedure */
@@ -62,11 +73,16 @@
     FLASH_OBProgramInitTypeDef OBInit;
     uint32_t SectorId;
     uint32_t SectorError = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -102,19 +118,27 @@
     EraseInitStruct.NbSectors = 1;
 
     if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
         uint32_t size)
 {
+    int32_t status = 0;
+
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -123,17 +147,20 @@
     __HAL_FLASH_ART_RESET();
     __HAL_FLASH_ART_ENABLE();
 
-    while (size > 0) {
+    while ((size > 0) && (status == 0)) {
         if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE,
                     address, (uint64_t)*data) != HAL_OK) {
-            return -1;
+            status = -1;
         } else {
             size--;
             address++;
             data++;
         }
     }
-    return 0;
+
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -26,30 +26,51 @@
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     uint32_t FirstPage = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Clear OPTVERR bit set on virgin samples */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
 
@@ -65,16 +86,20 @@
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
+
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address,
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -85,6 +110,10 @@
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -92,7 +121,7 @@
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint32_t data32;
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             for (uint8_t i =0; i < 4; i++) {
                 *(((uint8_t *) &data32) + i) = *(data + i);
             }
@@ -101,21 +130,23 @@
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c	Wed Oct 11 12:45:49 2017 +0100
@@ -37,6 +37,7 @@
 
 #include "stm32l1xx.h"
 #include "stdio.h"
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -253,9 +254,7 @@
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }
 

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c	Wed Oct 11 12:45:49 2017 +0100
@@ -30,12 +30,7 @@
 
 #include "xdot_low_power.h"
 #include "stdio.h"
-
-#if defined(NDEBUG) && NDEBUG == 1
-#define xdot_lp_debug(...) do {} while(0)
-#else
-#define xdot_lp_debug(...) printf(__VA_ARGS__)
-#endif
+#include "mbed_debug.h"
 
 static uint32_t portA[6];
 static uint32_t portB[6];
@@ -236,7 +231,7 @@
     HSERCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
     HSERCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
     if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
-        xdot_lp_debug("OSC initialization failed - initiating soft reset\r\n");
+        debug("OSC initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -247,7 +242,7 @@
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        xdot_lp_debug("PLL initialization failed - initiating soft reset\r\n");
+        debug("PLL initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -260,7 +255,7 @@
         HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
         HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
         if ( ret != HAL_OK ) {
-            xdot_lp_debug("HSI initialization failed - ADC will not function properly\r\n");
+            debug("HSI initialization failed - ADC will not function properly\r\n");
         }
     }
 

--- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -26,30 +26,51 @@
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     uint32_t FirstPage = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR | FLASH_FLAG_EOP | FLASH_FLAG_PGAERR | FLASH_FLAG_WRPERR);
     /* MBED HAL erases 1 sector at a time */
     /* Fill EraseInit structure*/
@@ -63,16 +84,20 @@
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
+
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address,
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -83,6 +108,10 @@
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -90,7 +119,7 @@
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint32_t data32;
-        while (address < (StartAddress + size)) {
+        while (address < (StartAddress + size) && (status == 0)) {
             for (uint8_t i =0; i < 4; i++) {
                 *(((uint8_t *) &data32) + i) = *(data + i);
             }
@@ -99,21 +128,23 @@
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) 

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S	Wed Oct 11 12:45:49 2017 +0100
@@ -42,13 +42,13 @@
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
                 EXPORT  __initial_sp
 
-__initial_sp    EQU     0x2000C000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+__initial_sp    EQU     0x20010000 ; Top of RAM
 
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Heap_Size       EQU     0x0BA00 ; 46KB (48KB, -2*1KB for main thread and scheduler)
+Heap_Size       EQU     0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler)
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
                 EXPORT  __heap_base

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct	Wed Oct 11 12:45:49 2017 +0100
@@ -36,12 +36,8 @@
    .ANY (+RO)
   }
 
-  RW_IRAM1 0x20000000 0x0000C000  { ; RW data 48k L4-SRAM1
-   .ANY (+RW +ZI)
-  }
-
   ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
-  RW_IRAM2 (0x10000000+0x188) (0x04000-0x188)  {  ; RW data 16k L4-ECC-SRAM2 retained in standby
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
   .ANY (+RW +ZI)
   }
 

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S	Wed Oct 11 12:45:49 2017 +0100
@@ -39,7 +39,7 @@
 ;*
 ;*******************************************************************************
 
-__initial_sp    EQU     0x2000C000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+__initial_sp    EQU     0x20010000 ; Top of RAM
 
                 PRESERVE8
                 THUMB

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct	Wed Oct 11 12:45:49 2017 +0100
@@ -36,13 +36,9 @@
    .ANY (+RO)
   }
 
-  RW_IRAM1 0x20000000 0x0000C000  { ; RW data 48k L4-SRAM1
+  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
   .ANY (+RW +ZI)
   }
 
-  ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
-  RW_IRAM2 (0x10000000+0x188) (0x04000-0x188)  {  ; RW data 16k L4-ECC-SRAM2 retained in standby
-   .ANY (+RW +ZI)
-  }
-
 }

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld	Wed Oct 11 12:45:49 2017 +0100
@@ -2,8 +2,7 @@
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 16k - 0x188
-  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 48k
+  SRAM1 (rwx)  : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
 }
 
 /* Linker script to place sections and symbol values. Should be used together

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf	Wed Oct 11 12:45:49 2017 +0100
@@ -5,20 +5,16 @@
 
 /* [RAM = 48kb + 16kb = 0xC000] */
 /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x10000000;
-define symbol __NVIC_end__            = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
-define symbol __region_SRAM2_start__  = 0x10000188;
-define symbol __region_SRAM2_end__    = 0x10003FFF;
-define symbol __region_SRAM1_start__  = 0x20000000;
-define symbol __region_SRAM1_end__    = 0x2000BFFF;
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM1_start__  = 0x20000188;
+define symbol __region_SRAM1_end__    = 0x2000FFFF;
 
 /* Memory regions */
 define memory mem with size = 4G;
 define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
 define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
 
-/* Stack 1/8 and Heap 1/4 of RAM */
 define symbol __size_cstack__ = 0x2000;
 define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
@@ -32,4 +28,3 @@
 
 place in ROM_region   { readonly };
 place in SRAM1_region   { readwrite, block STACKHEAP };
-place in SRAM2_region { };

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h	Wed Oct 11 12:45:49 2017 +0100
@@ -35,6 +35,6 @@
 // MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
 // Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
 #define NVIC_NUM_VECTORS        98
-#define NVIC_RAM_VECTOR_ADDRESS 0x10000000    // Vectors positioned at start of SRAM2
+#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE    // Vectors positioned at start of SRAM1
 
 #endif

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h	Wed Oct 11 12:45:49 2017 +0100
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()

--- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c	Wed Oct 11 12:45:49 2017 +0100
@@ -80,8 +80,6 @@
  */
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
@@ -92,12 +90,30 @@
  */
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 /** Erase one sector starting at defined address
  *
  * The address should be at sector boundary. This function does not do any check for address alignments
@@ -110,12 +126,17 @@
     uint32_t FirstPage = 0, BankNumber = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
       /* Clear OPTVERR bit set on virgin samples */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
     /* Get the 1st page to erase */
@@ -135,10 +156,12 @@
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 /** Program one page starting at defined address
@@ -156,6 +179,7 @@
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -166,6 +190,10 @@
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -173,34 +201,39 @@
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint64_t data64;
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             for (uint8_t i =0; i < 8; i++) {
                 *(((uint8_t *) &data64) + i) = *(data + i);
             }
 
-            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data64) == HAL_OK) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data64)
+                    == HAL_OK) {
                 address = address + 8;
                 data = data + 8;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
-            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, *((uint64_t*) data)) == HAL_OK) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address,
+                        *((uint64_t*) data))
+                    == HAL_OK) {
                 address = address + 8;
                 data = data + 8;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 /** Get sector size
- * 
+ *
  * @param obj The flash object
  * @param address The sector starting address
  * @return The size of a sector

--- a/targets/TARGET_STM/hal_tick_16b.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_16b.c	Wed Oct 11 12:45:49 2017 +0100
@@ -148,12 +148,11 @@
     // Enable timer
     HAL_TIM_Base_Start(&TimMasterHandle);
 
-#ifndef NDEBUG
-#ifdef TIM_MST_DBGMCU_FREEZE
     // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
     TIM_MST_DBGMCU_FREEZE;
 #endif
-#endif
 
 #if DEBUG_TICK > 0
     __HAL_RCC_GPIOB_CLK_ENABLE();

--- a/targets/TARGET_STM/hal_tick_32b.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/hal_tick_32b.c	Wed Oct 11 12:45:49 2017 +0100
@@ -118,12 +118,11 @@
     __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
     __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
 
-#ifndef NDEBUG
-#ifdef TIM_MST_DBGMCU_FREEZE
     // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
     TIM_MST_DBGMCU_FREEZE;
 #endif
-#endif
 
 #if DEBUG_TICK > 0
     __HAL_RCC_GPIOB_CLK_ENABLE();

--- a/targets/TARGET_STM/mbed_rtx.h	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_STM/mbed_rtx.h	Wed Oct 11 12:45:49 2017 +0100
@@ -53,7 +53,7 @@
 #define INITIAL_SP              (0x2000A000UL)
 
 #elif defined(TARGET_STM32L432KC)
-#define INITIAL_SP              (0x2000C000UL)
+#define INITIAL_SP              (0x20010000UL)
 
 #elif (defined(TARGET_STM32F303RE) ||\
        defined(TARGET_STM32F303ZE) ||\

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c	Wed Oct 11 12:45:49 2017 +0100
@@ -213,6 +213,8 @@
 
 void us_ticker_fire_interrupt(void)
 {
+    ticker_int_cnt = 0;
+    TIMER_IntSet(US_TICKER_TIMER, TIMER_IF_CC0);
     NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQ);
 }
 

--- a/targets/targets.json	Mon Oct 02 15:33:19 2017 +0100
+++ b/targets/targets.json	Wed Oct 11 12:45:49 2017 +0100
@@ -690,18 +690,18 @@
         "release_versions": ["2", "5"],
         "device_name" : "LPC54114J256BD64"
     },
-    "LPC54608": {
+    "LPC546XX": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
-        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54608", "LPCXpresso"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso"],
         "is_disk_virtual": true,
-        "macros": ["CPU_LPC54608J512ET180", "FSL_RTOS_MBED"],
+        "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["1056"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
-        "device_name" : "LPC54608J512ET180"
+        "device_name" : "LPC54618J512ET180"
     },
     "NUCLEO_F030R8": {
         "inherits": ["FAMILY_STM32"],
@@ -711,7 +711,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -770,7 +770,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -788,7 +788,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -806,7 +806,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -824,7 +824,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -851,7 +851,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -870,7 +870,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -907,7 +907,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -924,7 +924,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -941,7 +941,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -959,7 +959,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -977,7 +977,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -995,7 +995,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1017,7 +1017,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1036,7 +1036,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1071,7 +1071,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1101,7 +1101,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1127,7 +1127,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1145,7 +1145,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1177,7 +1177,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1201,7 +1201,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1225,7 +1225,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1247,7 +1247,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1284,7 +1284,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1302,7 +1302,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1319,7 +1319,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1401,7 +1401,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1434,7 +1434,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1459,7 +1459,7 @@
         "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xI", "STM32F429xx"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
@@ -1481,12 +1481,13 @@
         "extra_labels_add": ["STM32F4", "STM32F469", "STM32F469NI", "STM32F469xI", "STM32F469xx"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
         "detect_code": ["0788"],
+        "macros_add": ["USB_STM_HAL"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F469NI"
@@ -1499,7 +1500,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },